Eli Hughes
V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
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core_cm0plus.h
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00001 /**************************************************************************//** 00002 * @file core_cm0plus.h 00003 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 00004 * @version V3.30 00005 * @date 06. May 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM0PLUS_H_GENERIC 00043 #define __CORE_CM0PLUS_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex-M0+ 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0P definitions */ 00071 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0PLUS_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) /* Cosmic */ 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00112 */ 00113 #define __FPU_USED 0 00114 00115 #if defined ( __CC_ARM ) 00116 #if defined __TARGET_FPU_VFP 00117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #endif 00119 00120 #elif defined ( __GNUC__ ) 00121 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00123 #endif 00124 00125 #elif defined ( __ICCARM__ ) 00126 #if defined __ARMVFP__ 00127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #endif 00129 00130 #elif defined ( __TMS470__ ) 00131 #if defined __TI__VFP_SUPPORT____ 00132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00133 #endif 00134 00135 #elif defined ( __TASKING__ ) 00136 #if defined __FPU_VFP__ 00137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00138 #endif 00139 00140 #elif defined ( __CSMC__ ) /* Cosmic */ 00141 #if ( __CSMC__ & 0x400) // FPU present for parser 00142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00143 #endif 00144 #endif 00145 00146 #include <stdint.h> /* standard types definitions */ 00147 #include <core_cmInstr.h> /* Core Instruction Access */ 00148 #include <core_cmFunc.h> /* Core Function Access */ 00149 00150 #endif /* __CORE_CM0PLUS_H_GENERIC */ 00151 00152 #ifndef __CMSIS_GENERIC 00153 00154 #ifndef __CORE_CM0PLUS_H_DEPENDANT 00155 #define __CORE_CM0PLUS_H_DEPENDANT 00156 00157 /* check device defines and use defaults */ 00158 #if defined __CHECK_DEVICE_DEFINES 00159 #ifndef __CM0PLUS_REV 00160 #define __CM0PLUS_REV 0x0000 00161 #warning "__CM0PLUS_REV not defined in device header file; using default!" 00162 #endif 00163 00164 #ifndef __MPU_PRESENT 00165 #define __MPU_PRESENT 0 00166 #warning "__MPU_PRESENT not defined in device header file; using default!" 00167 #endif 00168 00169 #ifndef __VTOR_PRESENT 00170 #define __VTOR_PRESENT 0 00171 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00172 #endif 00173 00174 #ifndef __NVIC_PRIO_BITS 00175 #define __NVIC_PRIO_BITS 2 00176 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00177 #endif 00178 00179 #ifndef __Vendor_SysTickConfig 00180 #define __Vendor_SysTickConfig 0 00181 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00182 #endif 00183 #endif 00184 00185 /* IO definitions (access restrictions to peripheral registers) */ 00186 /** 00187 \defgroup CMSIS_glob_defs CMSIS Global Defines 00188 00189 <strong>IO Type Qualifiers</strong> are used 00190 \li to specify the access to peripheral variables. 00191 \li for automatic generation of peripheral register debug information. 00192 */ 00193 #ifdef __cplusplus 00194 #define __I volatile /*!< Defines 'read only' permissions */ 00195 #else 00196 #define __I volatile const /*!< Defines 'read only' permissions */ 00197 #endif 00198 #define __O volatile /*!< Defines 'write only' permissions */ 00199 #define __IO volatile /*!< Defines 'read / write' permissions */ 00200 00201 /*@} end of group Cortex-M0+ */ 00202 00203 00204 00205 /******************************************************************************* 00206 * Register Abstraction 00207 Core Register contain: 00208 - Core Register 00209 - Core NVIC Register 00210 - Core SCB Register 00211 - Core SysTick Register 00212 - Core MPU Register 00213 ******************************************************************************/ 00214 /** \defgroup CMSIS_core_register Defines and Type Definitions 00215 \brief Type definitions and defines for Cortex-M processor based devices. 00216 */ 00217 00218 /** \ingroup CMSIS_core_register 00219 \defgroup CMSIS_CORE Status and Control Registers 00220 \brief Core Register type definitions. 00221 @{ 00222 */ 00223 00224 /** \brief Union type to access the Application Program Status Register (APSR). 00225 */ 00226 typedef union 00227 { 00228 struct 00229 { 00230 #if (__CORTEX_M != 0x04) 00231 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00232 #else 00233 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00234 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00235 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00236 #endif 00237 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00242 } b; /*!< Structure used for bit access */ 00243 uint32_t w; /*!< Type used for word access */ 00244 } APSR_Type; 00245 00246 00247 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00248 */ 00249 typedef union 00250 { 00251 struct 00252 { 00253 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00254 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00255 } b; /*!< Structure used for bit access */ 00256 uint32_t w; /*!< Type used for word access */ 00257 } IPSR_Type; 00258 00259 00260 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00261 */ 00262 typedef union 00263 { 00264 struct 00265 { 00266 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00267 #if (__CORTEX_M != 0x04) 00268 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00269 #else 00270 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00271 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00272 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00273 #endif 00274 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00275 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00276 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00277 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00278 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00279 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00280 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00281 } b; /*!< Structure used for bit access */ 00282 uint32_t w; /*!< Type used for word access */ 00283 } xPSR_Type; 00284 00285 00286 /** \brief Union type to access the Control Registers (CONTROL). 00287 */ 00288 typedef union 00289 { 00290 struct 00291 { 00292 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00293 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00294 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00295 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00296 } b; /*!< Structure used for bit access */ 00297 uint32_t w; /*!< Type used for word access */ 00298 } CONTROL_Type; 00299 00300 /*@} end of group CMSIS_CORE */ 00301 00302 00303 /** \ingroup CMSIS_core_register 00304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00305 \brief Type definitions for the NVIC Registers 00306 @{ 00307 */ 00308 00309 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00310 */ 00311 typedef struct 00312 { 00313 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00314 uint32_t RESERVED0[31]; 00315 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00316 uint32_t RSERVED1[31]; 00317 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00318 uint32_t RESERVED2[31]; 00319 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00320 uint32_t RESERVED3[31]; 00321 uint32_t RESERVED4[64]; 00322 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00323 } NVIC_Type; 00324 00325 /*@} end of group CMSIS_NVIC */ 00326 00327 00328 /** \ingroup CMSIS_core_register 00329 \defgroup CMSIS_SCB System Control Block (SCB) 00330 \brief Type definitions for the System Control Block Registers 00331 @{ 00332 */ 00333 00334 /** \brief Structure type to access the System Control Block (SCB). 00335 */ 00336 typedef struct 00337 { 00338 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00339 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00340 #if (__VTOR_PRESENT == 1) 00341 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00342 #else 00343 uint32_t RESERVED0; 00344 #endif 00345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00348 uint32_t RESERVED1; 00349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00351 } SCB_Type; 00352 00353 /* SCB CPUID Register Definitions */ 00354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00356 00357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00359 00360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00362 00363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00365 00366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00368 00369 /* SCB Interrupt Control State Register Definitions */ 00370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00372 00373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00375 00376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00378 00379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00381 00382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00384 00385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00387 00388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00390 00391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00393 00394 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00395 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00396 00397 #if (__VTOR_PRESENT == 1) 00398 /* SCB Interrupt Control State Register Definitions */ 00399 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ 00400 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00401 #endif 00402 00403 /* SCB Application Interrupt and Reset Control Register Definitions */ 00404 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00406 00407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00409 00410 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00412 00413 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00415 00416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00418 00419 /* SCB System Control Register Definitions */ 00420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00422 00423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00425 00426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00428 00429 /* SCB Configuration Control Register Definitions */ 00430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00432 00433 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00435 00436 /* SCB System Handler Control and State Register Definitions */ 00437 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00439 00440 /*@} end of group CMSIS_SCB */ 00441 00442 00443 /** \ingroup CMSIS_core_register 00444 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00445 \brief Type definitions for the System Timer Registers. 00446 @{ 00447 */ 00448 00449 /** \brief Structure type to access the System Timer (SysTick). 00450 */ 00451 typedef struct 00452 { 00453 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00454 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00455 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00456 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00457 } SysTick_Type; 00458 00459 /* SysTick Control / Status Register Definitions */ 00460 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00461 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00462 00463 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00464 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00465 00466 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00467 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00468 00469 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00470 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00471 00472 /* SysTick Reload Register Definitions */ 00473 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00474 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00475 00476 /* SysTick Current Register Definitions */ 00477 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00478 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00479 00480 /* SysTick Calibration Register Definitions */ 00481 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00482 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00483 00484 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00485 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00486 00487 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00488 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00489 00490 /*@} end of group CMSIS_SysTick */ 00491 00492 #if (__MPU_PRESENT == 1) 00493 /** \ingroup CMSIS_core_register 00494 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00495 \brief Type definitions for the Memory Protection Unit (MPU) 00496 @{ 00497 */ 00498 00499 /** \brief Structure type to access the Memory Protection Unit (MPU). 00500 */ 00501 typedef struct 00502 { 00503 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00504 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00505 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00506 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00507 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00508 } MPU_Type; 00509 00510 /* MPU Type Register */ 00511 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00512 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00513 00514 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00515 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00516 00517 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00518 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 00519 00520 /* MPU Control Register */ 00521 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00522 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00523 00524 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00525 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00526 00527 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00528 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 00529 00530 /* MPU Region Number Register */ 00531 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00532 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 00533 00534 /* MPU Region Base Address Register */ 00535 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00536 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00537 00538 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00539 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00540 00541 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00542 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 00543 00544 /* MPU Region Attribute and Size Register */ 00545 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00546 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00547 00548 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00549 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00550 00551 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00552 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00553 00554 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00555 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00556 00557 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00558 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00559 00560 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00561 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00562 00563 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00564 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00565 00566 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00567 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00568 00569 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00570 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00571 00572 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00573 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 00574 00575 /*@} end of group CMSIS_MPU */ 00576 #endif 00577 00578 00579 /** \ingroup CMSIS_core_register 00580 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00581 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) 00582 are only accessible over DAP and not via processor. Therefore 00583 they are not covered by the Cortex-M0 header file. 00584 @{ 00585 */ 00586 /*@} end of group CMSIS_CoreDebug */ 00587 00588 00589 /** \ingroup CMSIS_core_register 00590 \defgroup CMSIS_core_base Core Definitions 00591 \brief Definitions for base addresses, unions, and structures. 00592 @{ 00593 */ 00594 00595 /* Memory mapping of Cortex-M0+ Hardware */ 00596 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00597 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00598 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00599 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00600 00601 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00602 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00603 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00604 00605 #if (__MPU_PRESENT == 1) 00606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00608 #endif 00609 00610 /*@} */ 00611 00612 00613 00614 /******************************************************************************* 00615 * Hardware Abstraction Layer 00616 Core Function Interface contains: 00617 - Core NVIC Functions 00618 - Core SysTick Functions 00619 - Core Register Access Functions 00620 ******************************************************************************/ 00621 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00622 */ 00623 00624 00625 00626 /* ########################## NVIC functions #################################### */ 00627 /** \ingroup CMSIS_Core_FunctionInterface 00628 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00629 \brief Functions that manage interrupts and exceptions via the NVIC. 00630 @{ 00631 */ 00632 00633 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00634 /* The following MACROS handle generation of the register offset and byte masks */ 00635 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00636 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00637 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00638 00639 00640 /** \brief Enable External Interrupt 00641 00642 The function enables a device-specific interrupt in the NVIC interrupt controller. 00643 00644 \param [in] IRQn External interrupt number. Value cannot be negative. 00645 */ 00646 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00647 { 00648 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00649 } 00650 00651 00652 /** \brief Disable External Interrupt 00653 00654 The function disables a device-specific interrupt in the NVIC interrupt controller. 00655 00656 \param [in] IRQn External interrupt number. Value cannot be negative. 00657 */ 00658 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00659 { 00660 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00661 } 00662 00663 00664 /** \brief Get Pending Interrupt 00665 00666 The function reads the pending register in the NVIC and returns the pending bit 00667 for the specified interrupt. 00668 00669 \param [in] IRQn Interrupt number. 00670 00671 \return 0 Interrupt status is not pending. 00672 \return 1 Interrupt status is pending. 00673 */ 00674 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00675 { 00676 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00677 } 00678 00679 00680 /** \brief Set Pending Interrupt 00681 00682 The function sets the pending bit of an external interrupt. 00683 00684 \param [in] IRQn Interrupt number. Value cannot be negative. 00685 */ 00686 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00687 { 00688 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00689 } 00690 00691 00692 /** \brief Clear Pending Interrupt 00693 00694 The function clears the pending bit of an external interrupt. 00695 00696 \param [in] IRQn External interrupt number. Value cannot be negative. 00697 */ 00698 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00699 { 00700 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00701 } 00702 00703 00704 /** \brief Set Interrupt Priority 00705 00706 The function sets the priority of an interrupt. 00707 00708 \note The priority cannot be set for every core interrupt. 00709 00710 \param [in] IRQn Interrupt number. 00711 \param [in] priority Priority to set. 00712 */ 00713 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00714 { 00715 if(IRQn < 0) { 00716 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00717 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00718 else { 00719 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00720 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00721 } 00722 00723 00724 /** \brief Get Interrupt Priority 00725 00726 The function reads the priority of an interrupt. The interrupt 00727 number can be positive to specify an external (device specific) 00728 interrupt, or negative to specify an internal (core) interrupt. 00729 00730 00731 \param [in] IRQn Interrupt number. 00732 \return Interrupt Priority. Value is aligned automatically to the implemented 00733 priority bits of the microcontroller. 00734 */ 00735 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00736 { 00737 00738 if(IRQn < 0) { 00739 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00740 else { 00741 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00742 } 00743 00744 00745 /** \brief System Reset 00746 00747 The function initiates a system reset request to reset the MCU. 00748 */ 00749 __STATIC_INLINE void NVIC_SystemReset(void) 00750 { 00751 __DSB(); /* Ensure all outstanding memory accesses included 00752 buffered write are completed before reset */ 00753 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00754 SCB_AIRCR_SYSRESETREQ_Msk); 00755 __DSB(); /* Ensure completion of memory access */ 00756 while(1); /* wait until reset */ 00757 } 00758 00759 /*@} end of CMSIS_Core_NVICFunctions */ 00760 00761 00762 00763 /* ################################## SysTick function ############################################ */ 00764 /** \ingroup CMSIS_Core_FunctionInterface 00765 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00766 \brief Functions that configure the System. 00767 @{ 00768 */ 00769 00770 #if (__Vendor_SysTickConfig == 0) 00771 00772 /** \brief System Tick Configuration 00773 00774 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00775 Counter is in free running mode to generate periodic interrupts. 00776 00777 \param [in] ticks Number of ticks between two interrupts. 00778 00779 \return 0 Function succeeded. 00780 \return 1 Function failed. 00781 00782 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00783 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00784 must contain a vendor-specific implementation of this function. 00785 00786 */ 00787 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00788 { 00789 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00790 00791 SysTick->LOAD = ticks - 1; /* set reload register */ 00792 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00793 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00794 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00795 SysTick_CTRL_TICKINT_Msk | 00796 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00797 return (0); /* Function successful */ 00798 } 00799 00800 #endif 00801 00802 /*@} end of CMSIS_Core_SysTickFunctions */ 00803 00804 00805 00806 00807 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 00808 00809 #ifdef __cplusplus 00810 } 00811 #endif 00812 00813 #endif /* __CMSIS_GENERIC */
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