Eli Hughes
V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
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core_cm0.h
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00001 /**************************************************************************//** 00002 * @file core_cm0.h 00003 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 00004 * @version V3.30 00005 * @date 06. May 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM0_H_GENERIC 00043 #define __CORE_CM0_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M0 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0 definitions */ 00071 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) /* Cosmic */ 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00112 */ 00113 #define __FPU_USED 0 00114 00115 #if defined ( __CC_ARM ) 00116 #if defined __TARGET_FPU_VFP 00117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #endif 00119 00120 #elif defined ( __GNUC__ ) 00121 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00123 #endif 00124 00125 #elif defined ( __ICCARM__ ) 00126 #if defined __ARMVFP__ 00127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #endif 00129 00130 #elif defined ( __TMS470__ ) 00131 #if defined __TI__VFP_SUPPORT____ 00132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00133 #endif 00134 00135 #elif defined ( __TASKING__ ) 00136 #if defined __FPU_VFP__ 00137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00138 #endif 00139 00140 #elif defined ( __CSMC__ ) /* Cosmic */ 00141 #if ( __CSMC__ & 0x400) // FPU present for parser 00142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00143 #endif 00144 #endif 00145 00146 #include <stdint.h> /* standard types definitions */ 00147 #include <core_cmInstr.h> /* Core Instruction Access */ 00148 #include <core_cmFunc.h> /* Core Function Access */ 00149 00150 #endif /* __CORE_CM0_H_GENERIC */ 00151 00152 #ifndef __CMSIS_GENERIC 00153 00154 #ifndef __CORE_CM0_H_DEPENDANT 00155 #define __CORE_CM0_H_DEPENDANT 00156 00157 /* check device defines and use defaults */ 00158 #if defined __CHECK_DEVICE_DEFINES 00159 #ifndef __CM0_REV 00160 #define __CM0_REV 0x0000 00161 #warning "__CM0_REV not defined in device header file; using default!" 00162 #endif 00163 00164 #ifndef __NVIC_PRIO_BITS 00165 #define __NVIC_PRIO_BITS 2 00166 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00167 #endif 00168 00169 #ifndef __Vendor_SysTickConfig 00170 #define __Vendor_SysTickConfig 0 00171 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00172 #endif 00173 #endif 00174 00175 /* IO definitions (access restrictions to peripheral registers) */ 00176 /** 00177 \defgroup CMSIS_glob_defs CMSIS Global Defines 00178 00179 <strong>IO Type Qualifiers</strong> are used 00180 \li to specify the access to peripheral variables. 00181 \li for automatic generation of peripheral register debug information. 00182 */ 00183 #ifdef __cplusplus 00184 #define __I volatile /*!< Defines 'read only' permissions */ 00185 #else 00186 #define __I volatile const /*!< Defines 'read only' permissions */ 00187 #endif 00188 #define __O volatile /*!< Defines 'write only' permissions */ 00189 #define __IO volatile /*!< Defines 'read / write' permissions */ 00190 00191 /*@} end of group Cortex_M0 */ 00192 00193 00194 00195 /******************************************************************************* 00196 * Register Abstraction 00197 Core Register contain: 00198 - Core Register 00199 - Core NVIC Register 00200 - Core SCB Register 00201 - Core SysTick Register 00202 ******************************************************************************/ 00203 /** \defgroup CMSIS_core_register Defines and Type Definitions 00204 \brief Type definitions and defines for Cortex-M processor based devices. 00205 */ 00206 00207 /** \ingroup CMSIS_core_register 00208 \defgroup CMSIS_CORE Status and Control Registers 00209 \brief Core Register type definitions. 00210 @{ 00211 */ 00212 00213 /** \brief Union type to access the Application Program Status Register (APSR). 00214 */ 00215 typedef union 00216 { 00217 struct 00218 { 00219 #if (__CORTEX_M != 0x04) 00220 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00221 #else 00222 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00224 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00225 #endif 00226 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00227 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00228 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00229 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00230 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00231 } b; /*!< Structure used for bit access */ 00232 uint32_t w ; /*!< Type used for word access */ 00233 } APSR_Type; 00234 00235 00236 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00237 */ 00238 typedef union 00239 { 00240 struct 00241 { 00242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00244 } b; /*!< Structure used for bit access */ 00245 uint32_t w ; /*!< Type used for word access */ 00246 } IPSR_Type; 00247 00248 00249 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00250 */ 00251 typedef union 00252 { 00253 struct 00254 { 00255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00256 #if (__CORTEX_M != 0x04) 00257 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00258 #else 00259 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00260 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00261 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00262 #endif 00263 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00264 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00265 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00270 } b; /*!< Structure used for bit access */ 00271 uint32_t w ; /*!< Type used for word access */ 00272 } xPSR_Type; 00273 00274 00275 /** \brief Union type to access the Control Registers (CONTROL). 00276 */ 00277 typedef union 00278 { 00279 struct 00280 { 00281 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00282 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00283 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00284 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00285 } b; /*!< Structure used for bit access */ 00286 uint32_t w ; /*!< Type used for word access */ 00287 } CONTROL_Type; 00288 00289 /*@} end of group CMSIS_CORE */ 00290 00291 00292 /** \ingroup CMSIS_core_register 00293 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00294 \brief Type definitions for the NVIC Registers 00295 @{ 00296 */ 00297 00298 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00299 */ 00300 typedef struct 00301 { 00302 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00303 uint32_t RESERVED0[31]; 00304 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00305 uint32_t RSERVED1[31]; 00306 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00307 uint32_t RESERVED2[31]; 00308 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00309 uint32_t RESERVED3[31]; 00310 uint32_t RESERVED4[64]; 00311 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00312 } NVIC_Type; 00313 00314 /*@} end of group CMSIS_NVIC */ 00315 00316 00317 /** \ingroup CMSIS_core_register 00318 \defgroup CMSIS_SCB System Control Block (SCB) 00319 \brief Type definitions for the System Control Block Registers 00320 @{ 00321 */ 00322 00323 /** \brief Structure type to access the System Control Block (SCB). 00324 */ 00325 typedef struct 00326 { 00327 __I uint32_t CPUID ; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00328 __IO uint32_t ICSR ; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00329 uint32_t RESERVED0; 00330 __IO uint32_t AIRCR ; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00331 __IO uint32_t SCR ; /*!< Offset: 0x010 (R/W) System Control Register */ 00332 __IO uint32_t CCR ; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00333 uint32_t RESERVED1; 00334 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00335 __IO uint32_t SHCSR ; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00336 } SCB_Type; 00337 00338 /* SCB CPUID Register Definitions */ 00339 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00340 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00341 00342 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00343 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00344 00345 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00347 00348 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00349 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00350 00351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00353 00354 /* SCB Interrupt Control State Register Definitions */ 00355 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00356 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00357 00358 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00359 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00360 00361 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00362 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00363 00364 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00365 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00366 00367 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00368 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00369 00370 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00371 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00372 00373 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00374 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00375 00376 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00377 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00378 00379 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00380 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00381 00382 /* SCB Application Interrupt and Reset Control Register Definitions */ 00383 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00384 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00385 00386 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00387 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00388 00389 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00390 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00391 00392 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00393 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00394 00395 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00396 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00397 00398 /* SCB System Control Register Definitions */ 00399 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00400 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00401 00402 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00403 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00404 00405 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00406 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00407 00408 /* SCB Configuration Control Register Definitions */ 00409 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00410 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00411 00412 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00413 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00414 00415 /* SCB System Handler Control and State Register Definitions */ 00416 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00417 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00418 00419 /*@} end of group CMSIS_SCB */ 00420 00421 00422 /** \ingroup CMSIS_core_register 00423 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00424 \brief Type definitions for the System Timer Registers. 00425 @{ 00426 */ 00427 00428 /** \brief Structure type to access the System Timer (SysTick). 00429 */ 00430 typedef struct 00431 { 00432 __IO uint32_t CTRL ; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00433 __IO uint32_t LOAD ; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00434 __IO uint32_t VAL ; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00435 __I uint32_t CALIB ; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00436 } SysTick_Type; 00437 00438 /* SysTick Control / Status Register Definitions */ 00439 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00440 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00441 00442 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00443 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00444 00445 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00446 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00447 00448 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00449 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00450 00451 /* SysTick Reload Register Definitions */ 00452 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00453 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00454 00455 /* SysTick Current Register Definitions */ 00456 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00457 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00458 00459 /* SysTick Calibration Register Definitions */ 00460 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00461 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00462 00463 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00464 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00465 00466 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00467 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00468 00469 /*@} end of group CMSIS_SysTick */ 00470 00471 00472 /** \ingroup CMSIS_core_register 00473 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00474 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00475 are only accessible over DAP and not via processor. Therefore 00476 they are not covered by the Cortex-M0 header file. 00477 @{ 00478 */ 00479 /*@} end of group CMSIS_CoreDebug */ 00480 00481 00482 /** \ingroup CMSIS_core_register 00483 \defgroup CMSIS_core_base Core Definitions 00484 \brief Definitions for base addresses, unions, and structures. 00485 @{ 00486 */ 00487 00488 /* Memory mapping of Cortex-M0 Hardware */ 00489 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00490 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00491 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00492 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00493 00494 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00495 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00496 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00497 00498 00499 /*@} */ 00500 00501 00502 00503 /******************************************************************************* 00504 * Hardware Abstraction Layer 00505 Core Function Interface contains: 00506 - Core NVIC Functions 00507 - Core SysTick Functions 00508 - Core Register Access Functions 00509 ******************************************************************************/ 00510 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00511 */ 00512 00513 00514 00515 /* ########################## NVIC functions #################################### */ 00516 /** \ingroup CMSIS_Core_FunctionInterface 00517 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00518 \brief Functions that manage interrupts and exceptions via the NVIC. 00519 @{ 00520 */ 00521 00522 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00523 /* The following MACROS handle generation of the register offset and byte masks */ 00524 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00525 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00526 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00527 00528 00529 /** \brief Enable External Interrupt 00530 00531 The function enables a device-specific interrupt in the NVIC interrupt controller. 00532 00533 \param [in] IRQn External interrupt number. Value cannot be negative. 00534 */ 00535 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00536 { 00537 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00538 } 00539 00540 00541 /** \brief Disable External Interrupt 00542 00543 The function disables a device-specific interrupt in the NVIC interrupt controller. 00544 00545 \param [in] IRQn External interrupt number. Value cannot be negative. 00546 */ 00547 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00548 { 00549 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00550 } 00551 00552 00553 /** \brief Get Pending Interrupt 00554 00555 The function reads the pending register in the NVIC and returns the pending bit 00556 for the specified interrupt. 00557 00558 \param [in] IRQn Interrupt number. 00559 00560 \return 0 Interrupt status is not pending. 00561 \return 1 Interrupt status is pending. 00562 */ 00563 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00564 { 00565 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00566 } 00567 00568 00569 /** \brief Set Pending Interrupt 00570 00571 The function sets the pending bit of an external interrupt. 00572 00573 \param [in] IRQn Interrupt number. Value cannot be negative. 00574 */ 00575 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00576 { 00577 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00578 } 00579 00580 00581 /** \brief Clear Pending Interrupt 00582 00583 The function clears the pending bit of an external interrupt. 00584 00585 \param [in] IRQn External interrupt number. Value cannot be negative. 00586 */ 00587 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00588 { 00589 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00590 } 00591 00592 00593 /** \brief Set Interrupt Priority 00594 00595 The function sets the priority of an interrupt. 00596 00597 \note The priority cannot be set for every core interrupt. 00598 00599 \param [in] IRQn Interrupt number. 00600 \param [in] priority Priority to set. 00601 */ 00602 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00603 { 00604 if(IRQn < 0) { 00605 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00606 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00607 else { 00608 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00609 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00610 } 00611 00612 00613 /** \brief Get Interrupt Priority 00614 00615 The function reads the priority of an interrupt. The interrupt 00616 number can be positive to specify an external (device specific) 00617 interrupt, or negative to specify an internal (core) interrupt. 00618 00619 00620 \param [in] IRQn Interrupt number. 00621 \return Interrupt Priority. Value is aligned automatically to the implemented 00622 priority bits of the microcontroller. 00623 */ 00624 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00625 { 00626 00627 if(IRQn < 0) { 00628 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00629 else { 00630 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00631 } 00632 00633 00634 /** \brief System Reset 00635 00636 The function initiates a system reset request to reset the MCU. 00637 */ 00638 __STATIC_INLINE void NVIC_SystemReset(void) 00639 { 00640 __DSB(); /* Ensure all outstanding memory accesses included 00641 buffered write are completed before reset */ 00642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00643 SCB_AIRCR_SYSRESETREQ_Msk); 00644 __DSB(); /* Ensure completion of memory access */ 00645 while(1); /* wait until reset */ 00646 } 00647 00648 /*@} end of CMSIS_Core_NVICFunctions */ 00649 00650 00651 00652 /* ################################## SysTick function ############################################ */ 00653 /** \ingroup CMSIS_Core_FunctionInterface 00654 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00655 \brief Functions that configure the System. 00656 @{ 00657 */ 00658 00659 #if (__Vendor_SysTickConfig == 0) 00660 00661 /** \brief System Tick Configuration 00662 00663 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00664 Counter is in free running mode to generate periodic interrupts. 00665 00666 \param [in] ticks Number of ticks between two interrupts. 00667 00668 \return 0 Function succeeded. 00669 \return 1 Function failed. 00670 00671 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00672 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00673 must contain a vendor-specific implementation of this function. 00674 00675 */ 00676 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00677 { 00678 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00679 00680 SysTick->LOAD = ticks - 1; /* set reload register */ 00681 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00682 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00683 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00684 SysTick_CTRL_TICKINT_Msk | 00685 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00686 return (0); /* Function successful */ 00687 } 00688 00689 #endif 00690 00691 /*@} end of CMSIS_Core_SysTickFunctions */ 00692 00693 00694 00695 00696 #endif /* __CORE_CM0_H_DEPENDANT */ 00697 00698 #ifdef __cplusplus 00699 } 00700 #endif 00701 00702 #endif /* __CMSIS_GENERIC */
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