V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

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Show/hide line numbers arm_cmplx_dot_prod_q15.c Source File

arm_cmplx_dot_prod_q15.c

00001 /* ----------------------------------------------------------------------    
00002 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
00003 *    
00004 * $Date:        12. March 2014
00005 * $Revision:    V1.4.3
00006 *    
00007 * Project:      CMSIS DSP Library    
00008 * Title:        arm_cmplx_dot_prod_q15.c    
00009 *    
00010 * Description:  Processing function for the Q15 Complex Dot product    
00011 *    
00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
00013 *  
00014 * Redistribution and use in source and binary forms, with or without 
00015 * modification, are permitted provided that the following conditions
00016 * are met:
00017 *   - Redistributions of source code must retain the above copyright
00018 *     notice, this list of conditions and the following disclaimer.
00019 *   - Redistributions in binary form must reproduce the above copyright
00020 *     notice, this list of conditions and the following disclaimer in
00021 *     the documentation and/or other materials provided with the 
00022 *     distribution.
00023 *   - Neither the name of ARM LIMITED nor the names of its contributors
00024 *     may be used to endorse or promote products derived from this
00025 *     software without specific prior written permission.
00026 *
00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00038 * POSSIBILITY OF SUCH DAMAGE.  
00039 * -------------------------------------------------------------------- */
00040 
00041 #include "arm_math.h"
00042 
00043 /**    
00044  * @ingroup groupCmplxMath    
00045  */
00046 
00047 /**    
00048  * @addtogroup cmplx_dot_prod    
00049  * @{    
00050  */
00051 
00052 /**    
00053  * @brief  Q15 complex dot product    
00054  * @param  *pSrcA points to the first input vector    
00055  * @param  *pSrcB points to the second input vector    
00056  * @param  numSamples number of complex samples in each vector    
00057  * @param  *realResult real part of the result returned here    
00058  * @param  *imagResult imaginary part of the result returned here    
00059  * @return none.    
00060  *    
00061  * <b>Scaling and Overflow Behavior:</b>    
00062  * \par    
00063  * The function is implemented using an internal 64-bit accumulator.    
00064  * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    
00065  * These are accumulated in a 64-bit accumulator with 34.30 precision.    
00066  * As a final step, the accumulators are converted to 8.24 format.    
00067  * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.    
00068  */
00069 
00070 void arm_cmplx_dot_prod_q15(
00071   q15_t * pSrcA,
00072   q15_t * pSrcB,
00073   uint32_t numSamples,
00074   q31_t * realResult,
00075   q31_t * imagResult)
00076 {
00077   q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
00078   q15_t a0,b0,c0,d0;
00079 
00080 #ifndef ARM_MATH_CM0_FAMILY
00081 
00082   /* Run the below code for Cortex-M4 and Cortex-M3 */
00083   uint32_t blkCnt;                               /* loop counter */
00084 
00085 
00086   /*loop Unrolling */
00087   blkCnt = numSamples >> 2u;
00088 
00089   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00090    ** a second loop below computes the remaining 1 to 3 samples. */
00091   while(blkCnt > 0u)
00092   {
00093       a0 = *pSrcA++;
00094       b0 = *pSrcA++;
00095       c0 = *pSrcB++;
00096       d0 = *pSrcB++;  
00097   
00098       real_sum += (q31_t)a0 * c0;
00099       imag_sum += (q31_t)a0 * d0;
00100       real_sum -= (q31_t)b0 * d0;
00101       imag_sum += (q31_t)b0 * c0;
00102       
00103       a0 = *pSrcA++;
00104       b0 = *pSrcA++;
00105       c0 = *pSrcB++;
00106       d0 = *pSrcB++;  
00107   
00108       real_sum += (q31_t)a0 * c0;
00109       imag_sum += (q31_t)a0 * d0;
00110       real_sum -= (q31_t)b0 * d0;
00111       imag_sum += (q31_t)b0 * c0;
00112       
00113       a0 = *pSrcA++;
00114       b0 = *pSrcA++;
00115       c0 = *pSrcB++;
00116       d0 = *pSrcB++;  
00117   
00118       real_sum += (q31_t)a0 * c0;
00119       imag_sum += (q31_t)a0 * d0;
00120       real_sum -= (q31_t)b0 * d0;
00121       imag_sum += (q31_t)b0 * c0;
00122       
00123       a0 = *pSrcA++;
00124       b0 = *pSrcA++;
00125       c0 = *pSrcB++;
00126       d0 = *pSrcB++;  
00127   
00128       real_sum += (q31_t)a0 * c0;
00129       imag_sum += (q31_t)a0 * d0;
00130       real_sum -= (q31_t)b0 * d0;
00131       imag_sum += (q31_t)b0 * c0;
00132 
00133       /* Decrement the loop counter */
00134       blkCnt--;
00135   }
00136 
00137   /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
00138    ** No loop unrolling is used. */
00139   blkCnt = numSamples % 0x4u;
00140 
00141   while(blkCnt > 0u)
00142   {
00143       a0 = *pSrcA++;
00144       b0 = *pSrcA++;
00145       c0 = *pSrcB++;
00146       d0 = *pSrcB++;  
00147   
00148       real_sum += (q31_t)a0 * c0;
00149       imag_sum += (q31_t)a0 * d0;
00150       real_sum -= (q31_t)b0 * d0;
00151       imag_sum += (q31_t)b0 * c0;
00152 
00153       /* Decrement the loop counter */
00154       blkCnt--;
00155   }
00156 
00157 #else
00158 
00159   /* Run the below code for Cortex-M0 */
00160 
00161   while(numSamples > 0u)
00162   {
00163       a0 = *pSrcA++;
00164       b0 = *pSrcA++;
00165       c0 = *pSrcB++;
00166       d0 = *pSrcB++;  
00167   
00168       real_sum += a0 * c0;
00169       imag_sum += a0 * d0;
00170       real_sum -= b0 * d0;
00171       imag_sum += b0 * c0;
00172 
00173 
00174       /* Decrement the loop counter */
00175       numSamples--;
00176   }
00177 
00178 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
00179 
00180   /* Store the real and imaginary results in 8.24 format  */
00181   /* Convert real data in 34.30 to 8.24 by 6 right shifts */
00182   *realResult = (q31_t) (real_sum >> 6);
00183   /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
00184   *imagResult = (q31_t) (imag_sum >> 6);
00185 }
00186 
00187 /**    
00188  * @} end of cmplx_dot_prod group    
00189  */