V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
arm_biquad_cascade_df1_init_q15.c
00001 /*----------------------------------------------------------------------------- 00002 * Copyright (C) 2010-2014 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 12. March 2014 00005 * $Revision: V1.4.3 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_biquad_cascade_df1_init_q15.c 00009 * 00010 * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function. 00011 * 00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 00013 * 00014 * Redistribution and use in source and binary forms, with or without 00015 * modification, are permitted provided that the following conditions 00016 * are met: 00017 * - Redistributions of source code must retain the above copyright 00018 * notice, this list of conditions and the following disclaimer. 00019 * - Redistributions in binary form must reproduce the above copyright 00020 * notice, this list of conditions and the following disclaimer in 00021 * the documentation and/or other materials provided with the 00022 * distribution. 00023 * - Neither the name of ARM LIMITED nor the names of its contributors 00024 * may be used to endorse or promote products derived from this 00025 * software without specific prior written permission. 00026 * 00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00038 * POSSIBILITY OF SUCH DAMAGE. 00039 * ---------------------------------------------------------------------------*/ 00040 00041 #include "arm_math.h" 00042 00043 /** 00044 * @ingroup groupFilters 00045 */ 00046 00047 /** 00048 * @addtogroup BiquadCascadeDF1 00049 * @{ 00050 */ 00051 00052 /** 00053 * @details 00054 * 00055 * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. 00056 * @param[in] numStages number of 2nd order stages in the filter. 00057 * @param[in] *pCoeffs points to the filter coefficients. 00058 * @param[in] *pState points to the state buffer. 00059 * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format 00060 * @return none 00061 * 00062 * <b>Coefficient and State Ordering:</b> 00063 * 00064 * \par 00065 * The coefficients are stored in the array <code>pCoeffs</code> in the following order: 00066 * <pre> 00067 * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...} 00068 * </pre> 00069 * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage, 00070 * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage, 00071 * and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values. 00072 * The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4. 00073 * 00074 * \par 00075 * The state variables are stored in the array <code>pState</code>. 00076 * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>. 00077 * The state variables are arranged in the <code>pState</code> array as: 00078 * <pre> 00079 * {x[n-1], x[n-2], y[n-1], y[n-2]} 00080 * </pre> 00081 * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. 00082 * The state array has a total length of <code>4*numStages</code> values. 00083 * The state variables are updated after each block of data is processed; the coefficients are untouched. 00084 */ 00085 00086 void arm_biquad_cascade_df1_init_q15( 00087 arm_biquad_casd_df1_inst_q15 * S, 00088 uint8_t numStages, 00089 q15_t * pCoeffs, 00090 q15_t * pState, 00091 int8_t postShift) 00092 { 00093 /* Assign filter stages */ 00094 S->numStages = numStages; 00095 00096 /* Assign postShift to be applied to the output */ 00097 S->postShift = postShift; 00098 00099 /* Assign coefficient pointer */ 00100 S->pCoeffs = pCoeffs; 00101 00102 /* Clear state buffer and size is always 4 * numStages */ 00103 memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t)); 00104 00105 /* Assign state pointer */ 00106 S->pState = pState; 00107 } 00108 00109 /** 00110 * @} end of BiquadCascadeDF1 group 00111 */
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