Eli Hughes / CMSIS_DSP_401

V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

ComplexMathFunctions/arm_cmplx_mult_real_q15.c@0:3d9c67d97d6f, 2014-07-28 (annotated)

Committer:
emh203
Date:
Mon Jul 28 15:03:15 2014 +0000
Revision:
0:3d9c67d97d6f
1st working commit.   Had to remove arm_bitreversal2.s     arm_cfft_f32.c and arm_rfft_fast_f32.c.    The .s will not assemble.      For now I removed these functions so we could at least have a library for the other functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 0:3d9c67d97d6f 1 /* ----------------------------------------------------------------------
emh203 0:3d9c67d97d6f 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emh203 0:3d9c67d97d6f 3 *
emh203 0:3d9c67d97d6f 4 * $Date: 12. March 2014
emh203 0:3d9c67d97d6f 5 * $Revision: V1.4.3
emh203 0:3d9c67d97d6f 6 *
emh203 0:3d9c67d97d6f 7 * Project: CMSIS DSP Library
emh203 0:3d9c67d97d6f 8 * Title: arm_cmplx_mult_real_q15.c
emh203 0:3d9c67d97d6f 9 *
emh203 0:3d9c67d97d6f 10 * Description: Q15 complex by real multiplication
emh203 0:3d9c67d97d6f 11 *
emh203 0:3d9c67d97d6f 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emh203 0:3d9c67d97d6f 13 *
emh203 0:3d9c67d97d6f 14 * Redistribution and use in source and binary forms, with or without
emh203 0:3d9c67d97d6f 15 * modification, are permitted provided that the following conditions
emh203 0:3d9c67d97d6f 16 * are met:
emh203 0:3d9c67d97d6f 17 * - Redistributions of source code must retain the above copyright
emh203 0:3d9c67d97d6f 18 * notice, this list of conditions and the following disclaimer.
emh203 0:3d9c67d97d6f 19 * - Redistributions in binary form must reproduce the above copyright
emh203 0:3d9c67d97d6f 20 * notice, this list of conditions and the following disclaimer in
emh203 0:3d9c67d97d6f 21 * the documentation and/or other materials provided with the
emh203 0:3d9c67d97d6f 22 * distribution.
emh203 0:3d9c67d97d6f 23 * - Neither the name of ARM LIMITED nor the names of its contributors
emh203 0:3d9c67d97d6f 24 * may be used to endorse or promote products derived from this
emh203 0:3d9c67d97d6f 25 * software without specific prior written permission.
emh203 0:3d9c67d97d6f 26 *
emh203 0:3d9c67d97d6f 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
emh203 0:3d9c67d97d6f 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
emh203 0:3d9c67d97d6f 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
emh203 0:3d9c67d97d6f 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
emh203 0:3d9c67d97d6f 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
emh203 0:3d9c67d97d6f 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
emh203 0:3d9c67d97d6f 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
emh203 0:3d9c67d97d6f 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emh203 0:3d9c67d97d6f 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
emh203 0:3d9c67d97d6f 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
emh203 0:3d9c67d97d6f 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emh203 0:3d9c67d97d6f 38 * POSSIBILITY OF SUCH DAMAGE.
emh203 0:3d9c67d97d6f 39 * -------------------------------------------------------------------- */
emh203 0:3d9c67d97d6f 40
emh203 0:3d9c67d97d6f 41 #include "arm_math.h"
emh203 0:3d9c67d97d6f 42
emh203 0:3d9c67d97d6f 43 /**
emh203 0:3d9c67d97d6f 44 * @ingroup groupCmplxMath
emh203 0:3d9c67d97d6f 45 */
emh203 0:3d9c67d97d6f 46
emh203 0:3d9c67d97d6f 47 /**
emh203 0:3d9c67d97d6f 48 * @addtogroup CmplxByRealMult
emh203 0:3d9c67d97d6f 49 * @{
emh203 0:3d9c67d97d6f 50 */
emh203 0:3d9c67d97d6f 51
emh203 0:3d9c67d97d6f 52
emh203 0:3d9c67d97d6f 53 /**
emh203 0:3d9c67d97d6f 54 * @brief Q15 complex-by-real multiplication
emh203 0:3d9c67d97d6f 55 * @param[in] *pSrcCmplx points to the complex input vector
emh203 0:3d9c67d97d6f 56 * @param[in] *pSrcReal points to the real input vector
emh203 0:3d9c67d97d6f 57 * @param[out] *pCmplxDst points to the complex output vector
emh203 0:3d9c67d97d6f 58 * @param[in] numSamples number of samples in each vector
emh203 0:3d9c67d97d6f 59 * @return none.
emh203 0:3d9c67d97d6f 60 *
emh203 0:3d9c67d97d6f 61 * <b>Scaling and Overflow Behavior:</b>
emh203 0:3d9c67d97d6f 62 * \par
emh203 0:3d9c67d97d6f 63 * The function uses saturating arithmetic.
emh203 0:3d9c67d97d6f 64 * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
emh203 0:3d9c67d97d6f 65 */
emh203 0:3d9c67d97d6f 66
emh203 0:3d9c67d97d6f 67 void arm_cmplx_mult_real_q15(
emh203 0:3d9c67d97d6f 68 q15_t * pSrcCmplx,
emh203 0:3d9c67d97d6f 69 q15_t * pSrcReal,
emh203 0:3d9c67d97d6f 70 q15_t * pCmplxDst,
emh203 0:3d9c67d97d6f 71 uint32_t numSamples)
emh203 0:3d9c67d97d6f 72 {
emh203 0:3d9c67d97d6f 73 q15_t in; /* Temporary variable to store input value */
emh203 0:3d9c67d97d6f 74
emh203 0:3d9c67d97d6f 75 #ifndef ARM_MATH_CM0_FAMILY
emh203 0:3d9c67d97d6f 76
emh203 0:3d9c67d97d6f 77 /* Run the below code for Cortex-M4 and Cortex-M3 */
emh203 0:3d9c67d97d6f 78 uint32_t blkCnt; /* loop counters */
emh203 0:3d9c67d97d6f 79 q31_t inA1, inA2; /* Temporary variables to hold input data */
emh203 0:3d9c67d97d6f 80 q31_t inB1; /* Temporary variables to hold input data */
emh203 0:3d9c67d97d6f 81 q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
emh203 0:3d9c67d97d6f 82 q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
emh203 0:3d9c67d97d6f 83
emh203 0:3d9c67d97d6f 84 /* loop Unrolling */
emh203 0:3d9c67d97d6f 85 blkCnt = numSamples >> 2u;
emh203 0:3d9c67d97d6f 86
emh203 0:3d9c67d97d6f 87 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emh203 0:3d9c67d97d6f 88 ** a second loop below computes the remaining 1 to 3 samples. */
emh203 0:3d9c67d97d6f 89 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 90 {
emh203 0:3d9c67d97d6f 91 /* C[2 * i] = A[2 * i] * B[i]. */
emh203 0:3d9c67d97d6f 92 /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
emh203 0:3d9c67d97d6f 93 /* read complex number both real and imaginary from complex input buffer */
emh203 0:3d9c67d97d6f 94 inA1 = *__SIMD32(pSrcCmplx)++;
emh203 0:3d9c67d97d6f 95 /* read two real values at a time from real input buffer */
emh203 0:3d9c67d97d6f 96 inB1 = *__SIMD32(pSrcReal)++;
emh203 0:3d9c67d97d6f 97 /* read complex number both real and imaginary from complex input buffer */
emh203 0:3d9c67d97d6f 98 inA2 = *__SIMD32(pSrcCmplx)++;
emh203 0:3d9c67d97d6f 99
emh203 0:3d9c67d97d6f 100 /* multiply complex number with real numbers */
emh203 0:3d9c67d97d6f 101 #ifndef ARM_MATH_BIG_ENDIAN
emh203 0:3d9c67d97d6f 102
emh203 0:3d9c67d97d6f 103 mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
emh203 0:3d9c67d97d6f 104 mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
emh203 0:3d9c67d97d6f 105 mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 106 mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 107
emh203 0:3d9c67d97d6f 108 #else
emh203 0:3d9c67d97d6f 109
emh203 0:3d9c67d97d6f 110 mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 111 mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 112 mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
emh203 0:3d9c67d97d6f 113 mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
emh203 0:3d9c67d97d6f 114
emh203 0:3d9c67d97d6f 115 #endif // #ifndef ARM_MATH_BIG_ENDIAN
emh203 0:3d9c67d97d6f 116
emh203 0:3d9c67d97d6f 117 /* saturate the result */
emh203 0:3d9c67d97d6f 118 out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
emh203 0:3d9c67d97d6f 119 out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
emh203 0:3d9c67d97d6f 120 out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
emh203 0:3d9c67d97d6f 121 out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
emh203 0:3d9c67d97d6f 122
emh203 0:3d9c67d97d6f 123 /* pack real and imaginary outputs and store them to destination */
emh203 0:3d9c67d97d6f 124 *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
emh203 0:3d9c67d97d6f 125 *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
emh203 0:3d9c67d97d6f 126
emh203 0:3d9c67d97d6f 127 inA1 = *__SIMD32(pSrcCmplx)++;
emh203 0:3d9c67d97d6f 128 inB1 = *__SIMD32(pSrcReal)++;
emh203 0:3d9c67d97d6f 129 inA2 = *__SIMD32(pSrcCmplx)++;
emh203 0:3d9c67d97d6f 130
emh203 0:3d9c67d97d6f 131 #ifndef ARM_MATH_BIG_ENDIAN
emh203 0:3d9c67d97d6f 132
emh203 0:3d9c67d97d6f 133 mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
emh203 0:3d9c67d97d6f 134 mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
emh203 0:3d9c67d97d6f 135 mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 136 mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 137
emh203 0:3d9c67d97d6f 138 #else
emh203 0:3d9c67d97d6f 139
emh203 0:3d9c67d97d6f 140 mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 141 mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
emh203 0:3d9c67d97d6f 142 mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
emh203 0:3d9c67d97d6f 143 mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
emh203 0:3d9c67d97d6f 144
emh203 0:3d9c67d97d6f 145 #endif // #ifndef ARM_MATH_BIG_ENDIAN
emh203 0:3d9c67d97d6f 146
emh203 0:3d9c67d97d6f 147 out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
emh203 0:3d9c67d97d6f 148 out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
emh203 0:3d9c67d97d6f 149 out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
emh203 0:3d9c67d97d6f 150 out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
emh203 0:3d9c67d97d6f 151
emh203 0:3d9c67d97d6f 152 *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
emh203 0:3d9c67d97d6f 153 *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
emh203 0:3d9c67d97d6f 154
emh203 0:3d9c67d97d6f 155 /* Decrement the numSamples loop counter */
emh203 0:3d9c67d97d6f 156 blkCnt--;
emh203 0:3d9c67d97d6f 157 }
emh203 0:3d9c67d97d6f 158
emh203 0:3d9c67d97d6f 159 /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
emh203 0:3d9c67d97d6f 160 ** No loop unrolling is used. */
emh203 0:3d9c67d97d6f 161 blkCnt = numSamples % 0x4u;
emh203 0:3d9c67d97d6f 162
emh203 0:3d9c67d97d6f 163 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 164 {
emh203 0:3d9c67d97d6f 165 /* C[2 * i] = A[2 * i] * B[i]. */
emh203 0:3d9c67d97d6f 166 /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
emh203 0:3d9c67d97d6f 167 in = *pSrcReal++;
emh203 0:3d9c67d97d6f 168 /* store the result in the destination buffer. */
emh203 0:3d9c67d97d6f 169 *pCmplxDst++ =
emh203 0:3d9c67d97d6f 170 (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
emh203 0:3d9c67d97d6f 171 *pCmplxDst++ =
emh203 0:3d9c67d97d6f 172 (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
emh203 0:3d9c67d97d6f 173
emh203 0:3d9c67d97d6f 174 /* Decrement the numSamples loop counter */
emh203 0:3d9c67d97d6f 175 blkCnt--;
emh203 0:3d9c67d97d6f 176 }
emh203 0:3d9c67d97d6f 177
emh203 0:3d9c67d97d6f 178 #else
emh203 0:3d9c67d97d6f 179
emh203 0:3d9c67d97d6f 180 /* Run the below code for Cortex-M0 */
emh203 0:3d9c67d97d6f 181
emh203 0:3d9c67d97d6f 182 while(numSamples > 0u)
emh203 0:3d9c67d97d6f 183 {
emh203 0:3d9c67d97d6f 184 /* realOut = realA * realB. */
emh203 0:3d9c67d97d6f 185 /* imagOut = imagA * realB. */
emh203 0:3d9c67d97d6f 186 in = *pSrcReal++;
emh203 0:3d9c67d97d6f 187 /* store the result in the destination buffer. */
emh203 0:3d9c67d97d6f 188 *pCmplxDst++ =
emh203 0:3d9c67d97d6f 189 (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
emh203 0:3d9c67d97d6f 190 *pCmplxDst++ =
emh203 0:3d9c67d97d6f 191 (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
emh203 0:3d9c67d97d6f 192
emh203 0:3d9c67d97d6f 193 /* Decrement the numSamples loop counter */
emh203 0:3d9c67d97d6f 194 numSamples--;
emh203 0:3d9c67d97d6f 195 }
emh203 0:3d9c67d97d6f 196
emh203 0:3d9c67d97d6f 197 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emh203 0:3d9c67d97d6f 198
emh203 0:3d9c67d97d6f 199 }
emh203 0:3d9c67d97d6f 200
emh203 0:3d9c67d97d6f 201 /**
emh203 0:3d9c67d97d6f 202 * @} end of CmplxByRealMult group
emh203 0:3d9c67d97d6f 203 */