V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

Committer:
emh203
Date:
Mon Jul 28 15:03:15 2014 +0000
Revision:
0:3d9c67d97d6f
1st working commit.   Had to remove arm_bitreversal2.s     arm_cfft_f32.c and arm_rfft_fast_f32.c.    The .s will not assemble.      For now I removed these functions so we could at least have a library for the other functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 0:3d9c67d97d6f 1 /* ----------------------------------------------------------------------
emh203 0:3d9c67d97d6f 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emh203 0:3d9c67d97d6f 3 *
emh203 0:3d9c67d97d6f 4 * $Date: 12. March 2014
emh203 0:3d9c67d97d6f 5 * $Revision: V1.4.3
emh203 0:3d9c67d97d6f 6 *
emh203 0:3d9c67d97d6f 7 * Project: CMSIS DSP Library
emh203 0:3d9c67d97d6f 8 * Title: arm_cmplx_dot_prod_q31.c
emh203 0:3d9c67d97d6f 9 *
emh203 0:3d9c67d97d6f 10 * Description: Q31 complex dot product
emh203 0:3d9c67d97d6f 11 *
emh203 0:3d9c67d97d6f 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emh203 0:3d9c67d97d6f 13 *
emh203 0:3d9c67d97d6f 14 * Redistribution and use in source and binary forms, with or without
emh203 0:3d9c67d97d6f 15 * modification, are permitted provided that the following conditions
emh203 0:3d9c67d97d6f 16 * are met:
emh203 0:3d9c67d97d6f 17 * - Redistributions of source code must retain the above copyright
emh203 0:3d9c67d97d6f 18 * notice, this list of conditions and the following disclaimer.
emh203 0:3d9c67d97d6f 19 * - Redistributions in binary form must reproduce the above copyright
emh203 0:3d9c67d97d6f 20 * notice, this list of conditions and the following disclaimer in
emh203 0:3d9c67d97d6f 21 * the documentation and/or other materials provided with the
emh203 0:3d9c67d97d6f 22 * distribution.
emh203 0:3d9c67d97d6f 23 * - Neither the name of ARM LIMITED nor the names of its contributors
emh203 0:3d9c67d97d6f 24 * may be used to endorse or promote products derived from this
emh203 0:3d9c67d97d6f 25 * software without specific prior written permission.
emh203 0:3d9c67d97d6f 26 *
emh203 0:3d9c67d97d6f 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
emh203 0:3d9c67d97d6f 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
emh203 0:3d9c67d97d6f 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
emh203 0:3d9c67d97d6f 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
emh203 0:3d9c67d97d6f 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
emh203 0:3d9c67d97d6f 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
emh203 0:3d9c67d97d6f 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
emh203 0:3d9c67d97d6f 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emh203 0:3d9c67d97d6f 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
emh203 0:3d9c67d97d6f 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
emh203 0:3d9c67d97d6f 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emh203 0:3d9c67d97d6f 38 * POSSIBILITY OF SUCH DAMAGE.
emh203 0:3d9c67d97d6f 39 * -------------------------------------------------------------------- */
emh203 0:3d9c67d97d6f 40
emh203 0:3d9c67d97d6f 41 #include "arm_math.h"
emh203 0:3d9c67d97d6f 42
emh203 0:3d9c67d97d6f 43 /**
emh203 0:3d9c67d97d6f 44 * @ingroup groupCmplxMath
emh203 0:3d9c67d97d6f 45 */
emh203 0:3d9c67d97d6f 46
emh203 0:3d9c67d97d6f 47 /**
emh203 0:3d9c67d97d6f 48 * @addtogroup cmplx_dot_prod
emh203 0:3d9c67d97d6f 49 * @{
emh203 0:3d9c67d97d6f 50 */
emh203 0:3d9c67d97d6f 51
emh203 0:3d9c67d97d6f 52 /**
emh203 0:3d9c67d97d6f 53 * @brief Q31 complex dot product
emh203 0:3d9c67d97d6f 54 * @param *pSrcA points to the first input vector
emh203 0:3d9c67d97d6f 55 * @param *pSrcB points to the second input vector
emh203 0:3d9c67d97d6f 56 * @param numSamples number of complex samples in each vector
emh203 0:3d9c67d97d6f 57 * @param *realResult real part of the result returned here
emh203 0:3d9c67d97d6f 58 * @param *imagResult imaginary part of the result returned here
emh203 0:3d9c67d97d6f 59 * @return none.
emh203 0:3d9c67d97d6f 60 *
emh203 0:3d9c67d97d6f 61 * <b>Scaling and Overflow Behavior:</b>
emh203 0:3d9c67d97d6f 62 * \par
emh203 0:3d9c67d97d6f 63 * The function is implemented using an internal 64-bit accumulator.
emh203 0:3d9c67d97d6f 64 * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
emh203 0:3d9c67d97d6f 65 * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
emh203 0:3d9c67d97d6f 66 * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
emh203 0:3d9c67d97d6f 67 * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
emh203 0:3d9c67d97d6f 68 * Input down scaling is not required.
emh203 0:3d9c67d97d6f 69 */
emh203 0:3d9c67d97d6f 70
emh203 0:3d9c67d97d6f 71 void arm_cmplx_dot_prod_q31(
emh203 0:3d9c67d97d6f 72 q31_t * pSrcA,
emh203 0:3d9c67d97d6f 73 q31_t * pSrcB,
emh203 0:3d9c67d97d6f 74 uint32_t numSamples,
emh203 0:3d9c67d97d6f 75 q63_t * realResult,
emh203 0:3d9c67d97d6f 76 q63_t * imagResult)
emh203 0:3d9c67d97d6f 77 {
emh203 0:3d9c67d97d6f 78 q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
emh203 0:3d9c67d97d6f 79 q31_t a0,b0,c0,d0;
emh203 0:3d9c67d97d6f 80
emh203 0:3d9c67d97d6f 81 #ifndef ARM_MATH_CM0_FAMILY
emh203 0:3d9c67d97d6f 82
emh203 0:3d9c67d97d6f 83 /* Run the below code for Cortex-M4 and Cortex-M3 */
emh203 0:3d9c67d97d6f 84 uint32_t blkCnt; /* loop counter */
emh203 0:3d9c67d97d6f 85
emh203 0:3d9c67d97d6f 86
emh203 0:3d9c67d97d6f 87 /*loop Unrolling */
emh203 0:3d9c67d97d6f 88 blkCnt = numSamples >> 2u;
emh203 0:3d9c67d97d6f 89
emh203 0:3d9c67d97d6f 90 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emh203 0:3d9c67d97d6f 91 ** a second loop below computes the remaining 1 to 3 samples. */
emh203 0:3d9c67d97d6f 92 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 93 {
emh203 0:3d9c67d97d6f 94 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 95 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 96 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 97 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 98
emh203 0:3d9c67d97d6f 99 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 100 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 101 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 102 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 103
emh203 0:3d9c67d97d6f 104 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 105 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 106 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 107 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 108
emh203 0:3d9c67d97d6f 109 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 110 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 111 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 112 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 113
emh203 0:3d9c67d97d6f 114 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 115 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 116 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 117 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 118
emh203 0:3d9c67d97d6f 119 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 120 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 121 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 122 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 123
emh203 0:3d9c67d97d6f 124 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 125 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 126 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 127 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 128
emh203 0:3d9c67d97d6f 129 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 130 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 131 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 132 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 133
emh203 0:3d9c67d97d6f 134 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 135 blkCnt--;
emh203 0:3d9c67d97d6f 136 }
emh203 0:3d9c67d97d6f 137
emh203 0:3d9c67d97d6f 138 /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
emh203 0:3d9c67d97d6f 139 ** No loop unrolling is used. */
emh203 0:3d9c67d97d6f 140 blkCnt = numSamples % 0x4u;
emh203 0:3d9c67d97d6f 141
emh203 0:3d9c67d97d6f 142 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 143 {
emh203 0:3d9c67d97d6f 144 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 145 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 146 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 147 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 148
emh203 0:3d9c67d97d6f 149 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 150 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 151 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 152 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 153
emh203 0:3d9c67d97d6f 154 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 155 blkCnt--;
emh203 0:3d9c67d97d6f 156 }
emh203 0:3d9c67d97d6f 157
emh203 0:3d9c67d97d6f 158 #else
emh203 0:3d9c67d97d6f 159
emh203 0:3d9c67d97d6f 160 /* Run the below code for Cortex-M0 */
emh203 0:3d9c67d97d6f 161
emh203 0:3d9c67d97d6f 162 while(numSamples > 0u)
emh203 0:3d9c67d97d6f 163 {
emh203 0:3d9c67d97d6f 164 a0 = *pSrcA++;
emh203 0:3d9c67d97d6f 165 b0 = *pSrcA++;
emh203 0:3d9c67d97d6f 166 c0 = *pSrcB++;
emh203 0:3d9c67d97d6f 167 d0 = *pSrcB++;
emh203 0:3d9c67d97d6f 168
emh203 0:3d9c67d97d6f 169 real_sum += ((q63_t)a0 * c0) >> 14;
emh203 0:3d9c67d97d6f 170 imag_sum += ((q63_t)a0 * d0) >> 14;
emh203 0:3d9c67d97d6f 171 real_sum -= ((q63_t)b0 * d0) >> 14;
emh203 0:3d9c67d97d6f 172 imag_sum += ((q63_t)b0 * c0) >> 14;
emh203 0:3d9c67d97d6f 173
emh203 0:3d9c67d97d6f 174 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 175 numSamples--;
emh203 0:3d9c67d97d6f 176 }
emh203 0:3d9c67d97d6f 177
emh203 0:3d9c67d97d6f 178 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emh203 0:3d9c67d97d6f 179
emh203 0:3d9c67d97d6f 180 /* Store the real and imaginary results in 16.48 format */
emh203 0:3d9c67d97d6f 181 *realResult = real_sum;
emh203 0:3d9c67d97d6f 182 *imagResult = imag_sum;
emh203 0:3d9c67d97d6f 183 }
emh203 0:3d9c67d97d6f 184
emh203 0:3d9c67d97d6f 185 /**
emh203 0:3d9c67d97d6f 186 * @} end of cmplx_dot_prod group
emh203 0:3d9c67d97d6f 187 */