Eli Hughes / CMSIS_DSP_401

V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

core_cm0plus.h@0:3d9c67d97d6f, 2014-07-28 (annotated)

Committer:
emh203
Date:
Mon Jul 28 15:03:15 2014 +0000
Revision:
0:3d9c67d97d6f
1st working commit.   Had to remove arm_bitreversal2.s     arm_cfft_f32.c and arm_rfft_fast_f32.c.    The .s will not assemble.      For now I removed these functions so we could at least have a library for the other functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 0:3d9c67d97d6f 1 /**************************************************************************//**
emh203 0:3d9c67d97d6f 2 * @file core_cm0plus.h
emh203 0:3d9c67d97d6f 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
emh203 0:3d9c67d97d6f 4 * @version V3.30
emh203 0:3d9c67d97d6f 5 * @date 06. May 2014
emh203 0:3d9c67d97d6f 6 *
emh203 0:3d9c67d97d6f 7 * @note
emh203 0:3d9c67d97d6f 8 *
emh203 0:3d9c67d97d6f 9 ******************************************************************************/
emh203 0:3d9c67d97d6f 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
emh203 0:3d9c67d97d6f 11
emh203 0:3d9c67d97d6f 12 All rights reserved.
emh203 0:3d9c67d97d6f 13 Redistribution and use in source and binary forms, with or without
emh203 0:3d9c67d97d6f 14 modification, are permitted provided that the following conditions are met:
emh203 0:3d9c67d97d6f 15 - Redistributions of source code must retain the above copyright
emh203 0:3d9c67d97d6f 16 notice, this list of conditions and the following disclaimer.
emh203 0:3d9c67d97d6f 17 - Redistributions in binary form must reproduce the above copyright
emh203 0:3d9c67d97d6f 18 notice, this list of conditions and the following disclaimer in the
emh203 0:3d9c67d97d6f 19 documentation and/or other materials provided with the distribution.
emh203 0:3d9c67d97d6f 20 - Neither the name of ARM nor the names of its contributors may be used
emh203 0:3d9c67d97d6f 21 to endorse or promote products derived from this software without
emh203 0:3d9c67d97d6f 22 specific prior written permission.
emh203 0:3d9c67d97d6f 23 *
emh203 0:3d9c67d97d6f 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emh203 0:3d9c67d97d6f 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emh203 0:3d9c67d97d6f 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emh203 0:3d9c67d97d6f 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emh203 0:3d9c67d97d6f 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emh203 0:3d9c67d97d6f 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emh203 0:3d9c67d97d6f 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emh203 0:3d9c67d97d6f 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emh203 0:3d9c67d97d6f 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emh203 0:3d9c67d97d6f 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emh203 0:3d9c67d97d6f 34 POSSIBILITY OF SUCH DAMAGE.
emh203 0:3d9c67d97d6f 35 ---------------------------------------------------------------------------*/
emh203 0:3d9c67d97d6f 36
emh203 0:3d9c67d97d6f 37
emh203 0:3d9c67d97d6f 38 #if defined ( __ICCARM__ )
emh203 0:3d9c67d97d6f 39 #pragma system_include /* treat file as system include file for MISRA check */
emh203 0:3d9c67d97d6f 40 #endif
emh203 0:3d9c67d97d6f 41
emh203 0:3d9c67d97d6f 42 #ifndef __CORE_CM0PLUS_H_GENERIC
emh203 0:3d9c67d97d6f 43 #define __CORE_CM0PLUS_H_GENERIC
emh203 0:3d9c67d97d6f 44
emh203 0:3d9c67d97d6f 45 #ifdef __cplusplus
emh203 0:3d9c67d97d6f 46 extern "C" {
emh203 0:3d9c67d97d6f 47 #endif
emh203 0:3d9c67d97d6f 48
emh203 0:3d9c67d97d6f 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emh203 0:3d9c67d97d6f 50 CMSIS violates the following MISRA-C:2004 rules:
emh203 0:3d9c67d97d6f 51
emh203 0:3d9c67d97d6f 52 \li Required Rule 8.5, object/function definition in header file.<br>
emh203 0:3d9c67d97d6f 53 Function definitions in header files are used to allow 'inlining'.
emh203 0:3d9c67d97d6f 54
emh203 0:3d9c67d97d6f 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emh203 0:3d9c67d97d6f 56 Unions are used for effective representation of core registers.
emh203 0:3d9c67d97d6f 57
emh203 0:3d9c67d97d6f 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emh203 0:3d9c67d97d6f 59 Function-like macros are used to allow more efficient code.
emh203 0:3d9c67d97d6f 60 */
emh203 0:3d9c67d97d6f 61
emh203 0:3d9c67d97d6f 62
emh203 0:3d9c67d97d6f 63 /*******************************************************************************
emh203 0:3d9c67d97d6f 64 * CMSIS definitions
emh203 0:3d9c67d97d6f 65 ******************************************************************************/
emh203 0:3d9c67d97d6f 66 /** \ingroup Cortex-M0+
emh203 0:3d9c67d97d6f 67 @{
emh203 0:3d9c67d97d6f 68 */
emh203 0:3d9c67d97d6f 69
emh203 0:3d9c67d97d6f 70 /* CMSIS CM0P definitions */
emh203 0:3d9c67d97d6f 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emh203 0:3d9c67d97d6f 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
emh203 0:3d9c67d97d6f 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emh203 0:3d9c67d97d6f 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emh203 0:3d9c67d97d6f 75
emh203 0:3d9c67d97d6f 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emh203 0:3d9c67d97d6f 77
emh203 0:3d9c67d97d6f 78
emh203 0:3d9c67d97d6f 79 #if defined ( __CC_ARM )
emh203 0:3d9c67d97d6f 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emh203 0:3d9c67d97d6f 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emh203 0:3d9c67d97d6f 82 #define __STATIC_INLINE static __inline
emh203 0:3d9c67d97d6f 83
emh203 0:3d9c67d97d6f 84 #elif defined ( __GNUC__ )
emh203 0:3d9c67d97d6f 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emh203 0:3d9c67d97d6f 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emh203 0:3d9c67d97d6f 87 #define __STATIC_INLINE static inline
emh203 0:3d9c67d97d6f 88
emh203 0:3d9c67d97d6f 89 #elif defined ( __ICCARM__ )
emh203 0:3d9c67d97d6f 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emh203 0:3d9c67d97d6f 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emh203 0:3d9c67d97d6f 92 #define __STATIC_INLINE static inline
emh203 0:3d9c67d97d6f 93
emh203 0:3d9c67d97d6f 94 #elif defined ( __TMS470__ )
emh203 0:3d9c67d97d6f 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emh203 0:3d9c67d97d6f 96 #define __STATIC_INLINE static inline
emh203 0:3d9c67d97d6f 97
emh203 0:3d9c67d97d6f 98 #elif defined ( __TASKING__ )
emh203 0:3d9c67d97d6f 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emh203 0:3d9c67d97d6f 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emh203 0:3d9c67d97d6f 101 #define __STATIC_INLINE static inline
emh203 0:3d9c67d97d6f 102
emh203 0:3d9c67d97d6f 103 #elif defined ( __CSMC__ ) /* Cosmic */
emh203 0:3d9c67d97d6f 104 #define __packed
emh203 0:3d9c67d97d6f 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
emh203 0:3d9c67d97d6f 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
emh203 0:3d9c67d97d6f 107 #define __STATIC_INLINE static inline
emh203 0:3d9c67d97d6f 108
emh203 0:3d9c67d97d6f 109 #endif
emh203 0:3d9c67d97d6f 110
emh203 0:3d9c67d97d6f 111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emh203 0:3d9c67d97d6f 112 */
emh203 0:3d9c67d97d6f 113 #define __FPU_USED 0
emh203 0:3d9c67d97d6f 114
emh203 0:3d9c67d97d6f 115 #if defined ( __CC_ARM )
emh203 0:3d9c67d97d6f 116 #if defined __TARGET_FPU_VFP
emh203 0:3d9c67d97d6f 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 118 #endif
emh203 0:3d9c67d97d6f 119
emh203 0:3d9c67d97d6f 120 #elif defined ( __GNUC__ )
emh203 0:3d9c67d97d6f 121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emh203 0:3d9c67d97d6f 122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 123 #endif
emh203 0:3d9c67d97d6f 124
emh203 0:3d9c67d97d6f 125 #elif defined ( __ICCARM__ )
emh203 0:3d9c67d97d6f 126 #if defined __ARMVFP__
emh203 0:3d9c67d97d6f 127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 128 #endif
emh203 0:3d9c67d97d6f 129
emh203 0:3d9c67d97d6f 130 #elif defined ( __TMS470__ )
emh203 0:3d9c67d97d6f 131 #if defined __TI__VFP_SUPPORT____
emh203 0:3d9c67d97d6f 132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 133 #endif
emh203 0:3d9c67d97d6f 134
emh203 0:3d9c67d97d6f 135 #elif defined ( __TASKING__ )
emh203 0:3d9c67d97d6f 136 #if defined __FPU_VFP__
emh203 0:3d9c67d97d6f 137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 138 #endif
emh203 0:3d9c67d97d6f 139
emh203 0:3d9c67d97d6f 140 #elif defined ( __CSMC__ ) /* Cosmic */
emh203 0:3d9c67d97d6f 141 #if ( __CSMC__ & 0x400) // FPU present for parser
emh203 0:3d9c67d97d6f 142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emh203 0:3d9c67d97d6f 143 #endif
emh203 0:3d9c67d97d6f 144 #endif
emh203 0:3d9c67d97d6f 145
emh203 0:3d9c67d97d6f 146 #include <stdint.h> /* standard types definitions */
emh203 0:3d9c67d97d6f 147 #include <core_cmInstr.h> /* Core Instruction Access */
emh203 0:3d9c67d97d6f 148 #include <core_cmFunc.h> /* Core Function Access */
emh203 0:3d9c67d97d6f 149
emh203 0:3d9c67d97d6f 150 #endif /* __CORE_CM0PLUS_H_GENERIC */
emh203 0:3d9c67d97d6f 151
emh203 0:3d9c67d97d6f 152 #ifndef __CMSIS_GENERIC
emh203 0:3d9c67d97d6f 153
emh203 0:3d9c67d97d6f 154 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emh203 0:3d9c67d97d6f 155 #define __CORE_CM0PLUS_H_DEPENDANT
emh203 0:3d9c67d97d6f 156
emh203 0:3d9c67d97d6f 157 /* check device defines and use defaults */
emh203 0:3d9c67d97d6f 158 #if defined __CHECK_DEVICE_DEFINES
emh203 0:3d9c67d97d6f 159 #ifndef __CM0PLUS_REV
emh203 0:3d9c67d97d6f 160 #define __CM0PLUS_REV 0x0000
emh203 0:3d9c67d97d6f 161 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emh203 0:3d9c67d97d6f 162 #endif
emh203 0:3d9c67d97d6f 163
emh203 0:3d9c67d97d6f 164 #ifndef __MPU_PRESENT
emh203 0:3d9c67d97d6f 165 #define __MPU_PRESENT 0
emh203 0:3d9c67d97d6f 166 #warning "__MPU_PRESENT not defined in device header file; using default!"
emh203 0:3d9c67d97d6f 167 #endif
emh203 0:3d9c67d97d6f 168
emh203 0:3d9c67d97d6f 169 #ifndef __VTOR_PRESENT
emh203 0:3d9c67d97d6f 170 #define __VTOR_PRESENT 0
emh203 0:3d9c67d97d6f 171 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emh203 0:3d9c67d97d6f 172 #endif
emh203 0:3d9c67d97d6f 173
emh203 0:3d9c67d97d6f 174 #ifndef __NVIC_PRIO_BITS
emh203 0:3d9c67d97d6f 175 #define __NVIC_PRIO_BITS 2
emh203 0:3d9c67d97d6f 176 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emh203 0:3d9c67d97d6f 177 #endif
emh203 0:3d9c67d97d6f 178
emh203 0:3d9c67d97d6f 179 #ifndef __Vendor_SysTickConfig
emh203 0:3d9c67d97d6f 180 #define __Vendor_SysTickConfig 0
emh203 0:3d9c67d97d6f 181 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emh203 0:3d9c67d97d6f 182 #endif
emh203 0:3d9c67d97d6f 183 #endif
emh203 0:3d9c67d97d6f 184
emh203 0:3d9c67d97d6f 185 /* IO definitions (access restrictions to peripheral registers) */
emh203 0:3d9c67d97d6f 186 /**
emh203 0:3d9c67d97d6f 187 \defgroup CMSIS_glob_defs CMSIS Global Defines
emh203 0:3d9c67d97d6f 188
emh203 0:3d9c67d97d6f 189 <strong>IO Type Qualifiers</strong> are used
emh203 0:3d9c67d97d6f 190 \li to specify the access to peripheral variables.
emh203 0:3d9c67d97d6f 191 \li for automatic generation of peripheral register debug information.
emh203 0:3d9c67d97d6f 192 */
emh203 0:3d9c67d97d6f 193 #ifdef __cplusplus
emh203 0:3d9c67d97d6f 194 #define __I volatile /*!< Defines 'read only' permissions */
emh203 0:3d9c67d97d6f 195 #else
emh203 0:3d9c67d97d6f 196 #define __I volatile const /*!< Defines 'read only' permissions */
emh203 0:3d9c67d97d6f 197 #endif
emh203 0:3d9c67d97d6f 198 #define __O volatile /*!< Defines 'write only' permissions */
emh203 0:3d9c67d97d6f 199 #define __IO volatile /*!< Defines 'read / write' permissions */
emh203 0:3d9c67d97d6f 200
emh203 0:3d9c67d97d6f 201 /*@} end of group Cortex-M0+ */
emh203 0:3d9c67d97d6f 202
emh203 0:3d9c67d97d6f 203
emh203 0:3d9c67d97d6f 204
emh203 0:3d9c67d97d6f 205 /*******************************************************************************
emh203 0:3d9c67d97d6f 206 * Register Abstraction
emh203 0:3d9c67d97d6f 207 Core Register contain:
emh203 0:3d9c67d97d6f 208 - Core Register
emh203 0:3d9c67d97d6f 209 - Core NVIC Register
emh203 0:3d9c67d97d6f 210 - Core SCB Register
emh203 0:3d9c67d97d6f 211 - Core SysTick Register
emh203 0:3d9c67d97d6f 212 - Core MPU Register
emh203 0:3d9c67d97d6f 213 ******************************************************************************/
emh203 0:3d9c67d97d6f 214 /** \defgroup CMSIS_core_register Defines and Type Definitions
emh203 0:3d9c67d97d6f 215 \brief Type definitions and defines for Cortex-M processor based devices.
emh203 0:3d9c67d97d6f 216 */
emh203 0:3d9c67d97d6f 217
emh203 0:3d9c67d97d6f 218 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 219 \defgroup CMSIS_CORE Status and Control Registers
emh203 0:3d9c67d97d6f 220 \brief Core Register type definitions.
emh203 0:3d9c67d97d6f 221 @{
emh203 0:3d9c67d97d6f 222 */
emh203 0:3d9c67d97d6f 223
emh203 0:3d9c67d97d6f 224 /** \brief Union type to access the Application Program Status Register (APSR).
emh203 0:3d9c67d97d6f 225 */
emh203 0:3d9c67d97d6f 226 typedef union
emh203 0:3d9c67d97d6f 227 {
emh203 0:3d9c67d97d6f 228 struct
emh203 0:3d9c67d97d6f 229 {
emh203 0:3d9c67d97d6f 230 #if (__CORTEX_M != 0x04)
emh203 0:3d9c67d97d6f 231 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emh203 0:3d9c67d97d6f 232 #else
emh203 0:3d9c67d97d6f 233 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emh203 0:3d9c67d97d6f 234 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emh203 0:3d9c67d97d6f 235 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emh203 0:3d9c67d97d6f 236 #endif
emh203 0:3d9c67d97d6f 237 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emh203 0:3d9c67d97d6f 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emh203 0:3d9c67d97d6f 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emh203 0:3d9c67d97d6f 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emh203 0:3d9c67d97d6f 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emh203 0:3d9c67d97d6f 242 } b; /*!< Structure used for bit access */
emh203 0:3d9c67d97d6f 243 uint32_t w; /*!< Type used for word access */
emh203 0:3d9c67d97d6f 244 } APSR_Type;
emh203 0:3d9c67d97d6f 245
emh203 0:3d9c67d97d6f 246
emh203 0:3d9c67d97d6f 247 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emh203 0:3d9c67d97d6f 248 */
emh203 0:3d9c67d97d6f 249 typedef union
emh203 0:3d9c67d97d6f 250 {
emh203 0:3d9c67d97d6f 251 struct
emh203 0:3d9c67d97d6f 252 {
emh203 0:3d9c67d97d6f 253 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emh203 0:3d9c67d97d6f 254 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emh203 0:3d9c67d97d6f 255 } b; /*!< Structure used for bit access */
emh203 0:3d9c67d97d6f 256 uint32_t w; /*!< Type used for word access */
emh203 0:3d9c67d97d6f 257 } IPSR_Type;
emh203 0:3d9c67d97d6f 258
emh203 0:3d9c67d97d6f 259
emh203 0:3d9c67d97d6f 260 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emh203 0:3d9c67d97d6f 261 */
emh203 0:3d9c67d97d6f 262 typedef union
emh203 0:3d9c67d97d6f 263 {
emh203 0:3d9c67d97d6f 264 struct
emh203 0:3d9c67d97d6f 265 {
emh203 0:3d9c67d97d6f 266 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emh203 0:3d9c67d97d6f 267 #if (__CORTEX_M != 0x04)
emh203 0:3d9c67d97d6f 268 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emh203 0:3d9c67d97d6f 269 #else
emh203 0:3d9c67d97d6f 270 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emh203 0:3d9c67d97d6f 271 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emh203 0:3d9c67d97d6f 272 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emh203 0:3d9c67d97d6f 273 #endif
emh203 0:3d9c67d97d6f 274 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emh203 0:3d9c67d97d6f 275 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emh203 0:3d9c67d97d6f 276 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emh203 0:3d9c67d97d6f 277 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emh203 0:3d9c67d97d6f 278 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emh203 0:3d9c67d97d6f 279 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emh203 0:3d9c67d97d6f 280 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emh203 0:3d9c67d97d6f 281 } b; /*!< Structure used for bit access */
emh203 0:3d9c67d97d6f 282 uint32_t w; /*!< Type used for word access */
emh203 0:3d9c67d97d6f 283 } xPSR_Type;
emh203 0:3d9c67d97d6f 284
emh203 0:3d9c67d97d6f 285
emh203 0:3d9c67d97d6f 286 /** \brief Union type to access the Control Registers (CONTROL).
emh203 0:3d9c67d97d6f 287 */
emh203 0:3d9c67d97d6f 288 typedef union
emh203 0:3d9c67d97d6f 289 {
emh203 0:3d9c67d97d6f 290 struct
emh203 0:3d9c67d97d6f 291 {
emh203 0:3d9c67d97d6f 292 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emh203 0:3d9c67d97d6f 293 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emh203 0:3d9c67d97d6f 294 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emh203 0:3d9c67d97d6f 295 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emh203 0:3d9c67d97d6f 296 } b; /*!< Structure used for bit access */
emh203 0:3d9c67d97d6f 297 uint32_t w; /*!< Type used for word access */
emh203 0:3d9c67d97d6f 298 } CONTROL_Type;
emh203 0:3d9c67d97d6f 299
emh203 0:3d9c67d97d6f 300 /*@} end of group CMSIS_CORE */
emh203 0:3d9c67d97d6f 301
emh203 0:3d9c67d97d6f 302
emh203 0:3d9c67d97d6f 303 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emh203 0:3d9c67d97d6f 305 \brief Type definitions for the NVIC Registers
emh203 0:3d9c67d97d6f 306 @{
emh203 0:3d9c67d97d6f 307 */
emh203 0:3d9c67d97d6f 308
emh203 0:3d9c67d97d6f 309 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emh203 0:3d9c67d97d6f 310 */
emh203 0:3d9c67d97d6f 311 typedef struct
emh203 0:3d9c67d97d6f 312 {
emh203 0:3d9c67d97d6f 313 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emh203 0:3d9c67d97d6f 314 uint32_t RESERVED0[31];
emh203 0:3d9c67d97d6f 315 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emh203 0:3d9c67d97d6f 316 uint32_t RSERVED1[31];
emh203 0:3d9c67d97d6f 317 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emh203 0:3d9c67d97d6f 318 uint32_t RESERVED2[31];
emh203 0:3d9c67d97d6f 319 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emh203 0:3d9c67d97d6f 320 uint32_t RESERVED3[31];
emh203 0:3d9c67d97d6f 321 uint32_t RESERVED4[64];
emh203 0:3d9c67d97d6f 322 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emh203 0:3d9c67d97d6f 323 } NVIC_Type;
emh203 0:3d9c67d97d6f 324
emh203 0:3d9c67d97d6f 325 /*@} end of group CMSIS_NVIC */
emh203 0:3d9c67d97d6f 326
emh203 0:3d9c67d97d6f 327
emh203 0:3d9c67d97d6f 328 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 329 \defgroup CMSIS_SCB System Control Block (SCB)
emh203 0:3d9c67d97d6f 330 \brief Type definitions for the System Control Block Registers
emh203 0:3d9c67d97d6f 331 @{
emh203 0:3d9c67d97d6f 332 */
emh203 0:3d9c67d97d6f 333
emh203 0:3d9c67d97d6f 334 /** \brief Structure type to access the System Control Block (SCB).
emh203 0:3d9c67d97d6f 335 */
emh203 0:3d9c67d97d6f 336 typedef struct
emh203 0:3d9c67d97d6f 337 {
emh203 0:3d9c67d97d6f 338 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emh203 0:3d9c67d97d6f 339 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emh203 0:3d9c67d97d6f 340 #if (__VTOR_PRESENT == 1)
emh203 0:3d9c67d97d6f 341 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emh203 0:3d9c67d97d6f 342 #else
emh203 0:3d9c67d97d6f 343 uint32_t RESERVED0;
emh203 0:3d9c67d97d6f 344 #endif
emh203 0:3d9c67d97d6f 345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emh203 0:3d9c67d97d6f 346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emh203 0:3d9c67d97d6f 347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emh203 0:3d9c67d97d6f 348 uint32_t RESERVED1;
emh203 0:3d9c67d97d6f 349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emh203 0:3d9c67d97d6f 350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emh203 0:3d9c67d97d6f 351 } SCB_Type;
emh203 0:3d9c67d97d6f 352
emh203 0:3d9c67d97d6f 353 /* SCB CPUID Register Definitions */
emh203 0:3d9c67d97d6f 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emh203 0:3d9c67d97d6f 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emh203 0:3d9c67d97d6f 356
emh203 0:3d9c67d97d6f 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emh203 0:3d9c67d97d6f 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emh203 0:3d9c67d97d6f 359
emh203 0:3d9c67d97d6f 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emh203 0:3d9c67d97d6f 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emh203 0:3d9c67d97d6f 362
emh203 0:3d9c67d97d6f 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emh203 0:3d9c67d97d6f 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emh203 0:3d9c67d97d6f 365
emh203 0:3d9c67d97d6f 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emh203 0:3d9c67d97d6f 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emh203 0:3d9c67d97d6f 368
emh203 0:3d9c67d97d6f 369 /* SCB Interrupt Control State Register Definitions */
emh203 0:3d9c67d97d6f 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emh203 0:3d9c67d97d6f 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emh203 0:3d9c67d97d6f 372
emh203 0:3d9c67d97d6f 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emh203 0:3d9c67d97d6f 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emh203 0:3d9c67d97d6f 375
emh203 0:3d9c67d97d6f 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emh203 0:3d9c67d97d6f 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emh203 0:3d9c67d97d6f 378
emh203 0:3d9c67d97d6f 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emh203 0:3d9c67d97d6f 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emh203 0:3d9c67d97d6f 381
emh203 0:3d9c67d97d6f 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emh203 0:3d9c67d97d6f 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emh203 0:3d9c67d97d6f 384
emh203 0:3d9c67d97d6f 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emh203 0:3d9c67d97d6f 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emh203 0:3d9c67d97d6f 387
emh203 0:3d9c67d97d6f 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emh203 0:3d9c67d97d6f 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emh203 0:3d9c67d97d6f 390
emh203 0:3d9c67d97d6f 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emh203 0:3d9c67d97d6f 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emh203 0:3d9c67d97d6f 393
emh203 0:3d9c67d97d6f 394 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emh203 0:3d9c67d97d6f 395 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emh203 0:3d9c67d97d6f 396
emh203 0:3d9c67d97d6f 397 #if (__VTOR_PRESENT == 1)
emh203 0:3d9c67d97d6f 398 /* SCB Interrupt Control State Register Definitions */
emh203 0:3d9c67d97d6f 399 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
emh203 0:3d9c67d97d6f 400 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emh203 0:3d9c67d97d6f 401 #endif
emh203 0:3d9c67d97d6f 402
emh203 0:3d9c67d97d6f 403 /* SCB Application Interrupt and Reset Control Register Definitions */
emh203 0:3d9c67d97d6f 404 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emh203 0:3d9c67d97d6f 405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emh203 0:3d9c67d97d6f 406
emh203 0:3d9c67d97d6f 407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emh203 0:3d9c67d97d6f 408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emh203 0:3d9c67d97d6f 409
emh203 0:3d9c67d97d6f 410 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emh203 0:3d9c67d97d6f 411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emh203 0:3d9c67d97d6f 412
emh203 0:3d9c67d97d6f 413 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emh203 0:3d9c67d97d6f 414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emh203 0:3d9c67d97d6f 415
emh203 0:3d9c67d97d6f 416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emh203 0:3d9c67d97d6f 417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emh203 0:3d9c67d97d6f 418
emh203 0:3d9c67d97d6f 419 /* SCB System Control Register Definitions */
emh203 0:3d9c67d97d6f 420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emh203 0:3d9c67d97d6f 421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emh203 0:3d9c67d97d6f 422
emh203 0:3d9c67d97d6f 423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emh203 0:3d9c67d97d6f 424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emh203 0:3d9c67d97d6f 425
emh203 0:3d9c67d97d6f 426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emh203 0:3d9c67d97d6f 427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emh203 0:3d9c67d97d6f 428
emh203 0:3d9c67d97d6f 429 /* SCB Configuration Control Register Definitions */
emh203 0:3d9c67d97d6f 430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emh203 0:3d9c67d97d6f 431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emh203 0:3d9c67d97d6f 432
emh203 0:3d9c67d97d6f 433 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emh203 0:3d9c67d97d6f 434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emh203 0:3d9c67d97d6f 435
emh203 0:3d9c67d97d6f 436 /* SCB System Handler Control and State Register Definitions */
emh203 0:3d9c67d97d6f 437 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emh203 0:3d9c67d97d6f 438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emh203 0:3d9c67d97d6f 439
emh203 0:3d9c67d97d6f 440 /*@} end of group CMSIS_SCB */
emh203 0:3d9c67d97d6f 441
emh203 0:3d9c67d97d6f 442
emh203 0:3d9c67d97d6f 443 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 444 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emh203 0:3d9c67d97d6f 445 \brief Type definitions for the System Timer Registers.
emh203 0:3d9c67d97d6f 446 @{
emh203 0:3d9c67d97d6f 447 */
emh203 0:3d9c67d97d6f 448
emh203 0:3d9c67d97d6f 449 /** \brief Structure type to access the System Timer (SysTick).
emh203 0:3d9c67d97d6f 450 */
emh203 0:3d9c67d97d6f 451 typedef struct
emh203 0:3d9c67d97d6f 452 {
emh203 0:3d9c67d97d6f 453 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emh203 0:3d9c67d97d6f 454 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emh203 0:3d9c67d97d6f 455 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emh203 0:3d9c67d97d6f 456 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emh203 0:3d9c67d97d6f 457 } SysTick_Type;
emh203 0:3d9c67d97d6f 458
emh203 0:3d9c67d97d6f 459 /* SysTick Control / Status Register Definitions */
emh203 0:3d9c67d97d6f 460 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emh203 0:3d9c67d97d6f 461 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emh203 0:3d9c67d97d6f 462
emh203 0:3d9c67d97d6f 463 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emh203 0:3d9c67d97d6f 464 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emh203 0:3d9c67d97d6f 465
emh203 0:3d9c67d97d6f 466 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emh203 0:3d9c67d97d6f 467 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emh203 0:3d9c67d97d6f 468
emh203 0:3d9c67d97d6f 469 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emh203 0:3d9c67d97d6f 470 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emh203 0:3d9c67d97d6f 471
emh203 0:3d9c67d97d6f 472 /* SysTick Reload Register Definitions */
emh203 0:3d9c67d97d6f 473 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emh203 0:3d9c67d97d6f 474 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emh203 0:3d9c67d97d6f 475
emh203 0:3d9c67d97d6f 476 /* SysTick Current Register Definitions */
emh203 0:3d9c67d97d6f 477 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emh203 0:3d9c67d97d6f 478 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emh203 0:3d9c67d97d6f 479
emh203 0:3d9c67d97d6f 480 /* SysTick Calibration Register Definitions */
emh203 0:3d9c67d97d6f 481 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emh203 0:3d9c67d97d6f 482 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emh203 0:3d9c67d97d6f 483
emh203 0:3d9c67d97d6f 484 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emh203 0:3d9c67d97d6f 485 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emh203 0:3d9c67d97d6f 486
emh203 0:3d9c67d97d6f 487 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emh203 0:3d9c67d97d6f 488 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
emh203 0:3d9c67d97d6f 489
emh203 0:3d9c67d97d6f 490 /*@} end of group CMSIS_SysTick */
emh203 0:3d9c67d97d6f 491
emh203 0:3d9c67d97d6f 492 #if (__MPU_PRESENT == 1)
emh203 0:3d9c67d97d6f 493 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 494 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emh203 0:3d9c67d97d6f 495 \brief Type definitions for the Memory Protection Unit (MPU)
emh203 0:3d9c67d97d6f 496 @{
emh203 0:3d9c67d97d6f 497 */
emh203 0:3d9c67d97d6f 498
emh203 0:3d9c67d97d6f 499 /** \brief Structure type to access the Memory Protection Unit (MPU).
emh203 0:3d9c67d97d6f 500 */
emh203 0:3d9c67d97d6f 501 typedef struct
emh203 0:3d9c67d97d6f 502 {
emh203 0:3d9c67d97d6f 503 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emh203 0:3d9c67d97d6f 504 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emh203 0:3d9c67d97d6f 505 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emh203 0:3d9c67d97d6f 506 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emh203 0:3d9c67d97d6f 507 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emh203 0:3d9c67d97d6f 508 } MPU_Type;
emh203 0:3d9c67d97d6f 509
emh203 0:3d9c67d97d6f 510 /* MPU Type Register */
emh203 0:3d9c67d97d6f 511 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emh203 0:3d9c67d97d6f 512 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emh203 0:3d9c67d97d6f 513
emh203 0:3d9c67d97d6f 514 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emh203 0:3d9c67d97d6f 515 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emh203 0:3d9c67d97d6f 516
emh203 0:3d9c67d97d6f 517 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emh203 0:3d9c67d97d6f 518 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emh203 0:3d9c67d97d6f 519
emh203 0:3d9c67d97d6f 520 /* MPU Control Register */
emh203 0:3d9c67d97d6f 521 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emh203 0:3d9c67d97d6f 522 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emh203 0:3d9c67d97d6f 523
emh203 0:3d9c67d97d6f 524 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emh203 0:3d9c67d97d6f 525 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emh203 0:3d9c67d97d6f 526
emh203 0:3d9c67d97d6f 527 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emh203 0:3d9c67d97d6f 528 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emh203 0:3d9c67d97d6f 529
emh203 0:3d9c67d97d6f 530 /* MPU Region Number Register */
emh203 0:3d9c67d97d6f 531 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emh203 0:3d9c67d97d6f 532 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emh203 0:3d9c67d97d6f 533
emh203 0:3d9c67d97d6f 534 /* MPU Region Base Address Register */
emh203 0:3d9c67d97d6f 535 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emh203 0:3d9c67d97d6f 536 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emh203 0:3d9c67d97d6f 537
emh203 0:3d9c67d97d6f 538 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emh203 0:3d9c67d97d6f 539 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emh203 0:3d9c67d97d6f 540
emh203 0:3d9c67d97d6f 541 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emh203 0:3d9c67d97d6f 542 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emh203 0:3d9c67d97d6f 543
emh203 0:3d9c67d97d6f 544 /* MPU Region Attribute and Size Register */
emh203 0:3d9c67d97d6f 545 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emh203 0:3d9c67d97d6f 546 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emh203 0:3d9c67d97d6f 547
emh203 0:3d9c67d97d6f 548 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emh203 0:3d9c67d97d6f 549 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emh203 0:3d9c67d97d6f 550
emh203 0:3d9c67d97d6f 551 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emh203 0:3d9c67d97d6f 552 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emh203 0:3d9c67d97d6f 553
emh203 0:3d9c67d97d6f 554 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emh203 0:3d9c67d97d6f 555 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emh203 0:3d9c67d97d6f 556
emh203 0:3d9c67d97d6f 557 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emh203 0:3d9c67d97d6f 558 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emh203 0:3d9c67d97d6f 559
emh203 0:3d9c67d97d6f 560 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emh203 0:3d9c67d97d6f 561 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emh203 0:3d9c67d97d6f 562
emh203 0:3d9c67d97d6f 563 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emh203 0:3d9c67d97d6f 564 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emh203 0:3d9c67d97d6f 565
emh203 0:3d9c67d97d6f 566 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emh203 0:3d9c67d97d6f 567 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emh203 0:3d9c67d97d6f 568
emh203 0:3d9c67d97d6f 569 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emh203 0:3d9c67d97d6f 570 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emh203 0:3d9c67d97d6f 571
emh203 0:3d9c67d97d6f 572 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emh203 0:3d9c67d97d6f 573 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emh203 0:3d9c67d97d6f 574
emh203 0:3d9c67d97d6f 575 /*@} end of group CMSIS_MPU */
emh203 0:3d9c67d97d6f 576 #endif
emh203 0:3d9c67d97d6f 577
emh203 0:3d9c67d97d6f 578
emh203 0:3d9c67d97d6f 579 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 580 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emh203 0:3d9c67d97d6f 581 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emh203 0:3d9c67d97d6f 582 are only accessible over DAP and not via processor. Therefore
emh203 0:3d9c67d97d6f 583 they are not covered by the Cortex-M0 header file.
emh203 0:3d9c67d97d6f 584 @{
emh203 0:3d9c67d97d6f 585 */
emh203 0:3d9c67d97d6f 586 /*@} end of group CMSIS_CoreDebug */
emh203 0:3d9c67d97d6f 587
emh203 0:3d9c67d97d6f 588
emh203 0:3d9c67d97d6f 589 /** \ingroup CMSIS_core_register
emh203 0:3d9c67d97d6f 590 \defgroup CMSIS_core_base Core Definitions
emh203 0:3d9c67d97d6f 591 \brief Definitions for base addresses, unions, and structures.
emh203 0:3d9c67d97d6f 592 @{
emh203 0:3d9c67d97d6f 593 */
emh203 0:3d9c67d97d6f 594
emh203 0:3d9c67d97d6f 595 /* Memory mapping of Cortex-M0+ Hardware */
emh203 0:3d9c67d97d6f 596 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emh203 0:3d9c67d97d6f 597 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emh203 0:3d9c67d97d6f 598 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emh203 0:3d9c67d97d6f 599 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emh203 0:3d9c67d97d6f 600
emh203 0:3d9c67d97d6f 601 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emh203 0:3d9c67d97d6f 602 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emh203 0:3d9c67d97d6f 603 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emh203 0:3d9c67d97d6f 604
emh203 0:3d9c67d97d6f 605 #if (__MPU_PRESENT == 1)
emh203 0:3d9c67d97d6f 606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emh203 0:3d9c67d97d6f 607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emh203 0:3d9c67d97d6f 608 #endif
emh203 0:3d9c67d97d6f 609
emh203 0:3d9c67d97d6f 610 /*@} */
emh203 0:3d9c67d97d6f 611
emh203 0:3d9c67d97d6f 612
emh203 0:3d9c67d97d6f 613
emh203 0:3d9c67d97d6f 614 /*******************************************************************************
emh203 0:3d9c67d97d6f 615 * Hardware Abstraction Layer
emh203 0:3d9c67d97d6f 616 Core Function Interface contains:
emh203 0:3d9c67d97d6f 617 - Core NVIC Functions
emh203 0:3d9c67d97d6f 618 - Core SysTick Functions
emh203 0:3d9c67d97d6f 619 - Core Register Access Functions
emh203 0:3d9c67d97d6f 620 ******************************************************************************/
emh203 0:3d9c67d97d6f 621 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emh203 0:3d9c67d97d6f 622 */
emh203 0:3d9c67d97d6f 623
emh203 0:3d9c67d97d6f 624
emh203 0:3d9c67d97d6f 625
emh203 0:3d9c67d97d6f 626 /* ########################## NVIC functions #################################### */
emh203 0:3d9c67d97d6f 627 /** \ingroup CMSIS_Core_FunctionInterface
emh203 0:3d9c67d97d6f 628 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emh203 0:3d9c67d97d6f 629 \brief Functions that manage interrupts and exceptions via the NVIC.
emh203 0:3d9c67d97d6f 630 @{
emh203 0:3d9c67d97d6f 631 */
emh203 0:3d9c67d97d6f 632
emh203 0:3d9c67d97d6f 633 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emh203 0:3d9c67d97d6f 634 /* The following MACROS handle generation of the register offset and byte masks */
emh203 0:3d9c67d97d6f 635 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emh203 0:3d9c67d97d6f 636 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emh203 0:3d9c67d97d6f 637 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emh203 0:3d9c67d97d6f 638
emh203 0:3d9c67d97d6f 639
emh203 0:3d9c67d97d6f 640 /** \brief Enable External Interrupt
emh203 0:3d9c67d97d6f 641
emh203 0:3d9c67d97d6f 642 The function enables a device-specific interrupt in the NVIC interrupt controller.
emh203 0:3d9c67d97d6f 643
emh203 0:3d9c67d97d6f 644 \param [in] IRQn External interrupt number. Value cannot be negative.
emh203 0:3d9c67d97d6f 645 */
emh203 0:3d9c67d97d6f 646 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 647 {
emh203 0:3d9c67d97d6f 648 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emh203 0:3d9c67d97d6f 649 }
emh203 0:3d9c67d97d6f 650
emh203 0:3d9c67d97d6f 651
emh203 0:3d9c67d97d6f 652 /** \brief Disable External Interrupt
emh203 0:3d9c67d97d6f 653
emh203 0:3d9c67d97d6f 654 The function disables a device-specific interrupt in the NVIC interrupt controller.
emh203 0:3d9c67d97d6f 655
emh203 0:3d9c67d97d6f 656 \param [in] IRQn External interrupt number. Value cannot be negative.
emh203 0:3d9c67d97d6f 657 */
emh203 0:3d9c67d97d6f 658 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 659 {
emh203 0:3d9c67d97d6f 660 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emh203 0:3d9c67d97d6f 661 }
emh203 0:3d9c67d97d6f 662
emh203 0:3d9c67d97d6f 663
emh203 0:3d9c67d97d6f 664 /** \brief Get Pending Interrupt
emh203 0:3d9c67d97d6f 665
emh203 0:3d9c67d97d6f 666 The function reads the pending register in the NVIC and returns the pending bit
emh203 0:3d9c67d97d6f 667 for the specified interrupt.
emh203 0:3d9c67d97d6f 668
emh203 0:3d9c67d97d6f 669 \param [in] IRQn Interrupt number.
emh203 0:3d9c67d97d6f 670
emh203 0:3d9c67d97d6f 671 \return 0 Interrupt status is not pending.
emh203 0:3d9c67d97d6f 672 \return 1 Interrupt status is pending.
emh203 0:3d9c67d97d6f 673 */
emh203 0:3d9c67d97d6f 674 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 675 {
emh203 0:3d9c67d97d6f 676 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emh203 0:3d9c67d97d6f 677 }
emh203 0:3d9c67d97d6f 678
emh203 0:3d9c67d97d6f 679
emh203 0:3d9c67d97d6f 680 /** \brief Set Pending Interrupt
emh203 0:3d9c67d97d6f 681
emh203 0:3d9c67d97d6f 682 The function sets the pending bit of an external interrupt.
emh203 0:3d9c67d97d6f 683
emh203 0:3d9c67d97d6f 684 \param [in] IRQn Interrupt number. Value cannot be negative.
emh203 0:3d9c67d97d6f 685 */
emh203 0:3d9c67d97d6f 686 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 687 {
emh203 0:3d9c67d97d6f 688 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emh203 0:3d9c67d97d6f 689 }
emh203 0:3d9c67d97d6f 690
emh203 0:3d9c67d97d6f 691
emh203 0:3d9c67d97d6f 692 /** \brief Clear Pending Interrupt
emh203 0:3d9c67d97d6f 693
emh203 0:3d9c67d97d6f 694 The function clears the pending bit of an external interrupt.
emh203 0:3d9c67d97d6f 695
emh203 0:3d9c67d97d6f 696 \param [in] IRQn External interrupt number. Value cannot be negative.
emh203 0:3d9c67d97d6f 697 */
emh203 0:3d9c67d97d6f 698 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 699 {
emh203 0:3d9c67d97d6f 700 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emh203 0:3d9c67d97d6f 701 }
emh203 0:3d9c67d97d6f 702
emh203 0:3d9c67d97d6f 703
emh203 0:3d9c67d97d6f 704 /** \brief Set Interrupt Priority
emh203 0:3d9c67d97d6f 705
emh203 0:3d9c67d97d6f 706 The function sets the priority of an interrupt.
emh203 0:3d9c67d97d6f 707
emh203 0:3d9c67d97d6f 708 \note The priority cannot be set for every core interrupt.
emh203 0:3d9c67d97d6f 709
emh203 0:3d9c67d97d6f 710 \param [in] IRQn Interrupt number.
emh203 0:3d9c67d97d6f 711 \param [in] priority Priority to set.
emh203 0:3d9c67d97d6f 712 */
emh203 0:3d9c67d97d6f 713 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emh203 0:3d9c67d97d6f 714 {
emh203 0:3d9c67d97d6f 715 if(IRQn < 0) {
emh203 0:3d9c67d97d6f 716 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emh203 0:3d9c67d97d6f 717 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emh203 0:3d9c67d97d6f 718 else {
emh203 0:3d9c67d97d6f 719 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emh203 0:3d9c67d97d6f 720 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emh203 0:3d9c67d97d6f 721 }
emh203 0:3d9c67d97d6f 722
emh203 0:3d9c67d97d6f 723
emh203 0:3d9c67d97d6f 724 /** \brief Get Interrupt Priority
emh203 0:3d9c67d97d6f 725
emh203 0:3d9c67d97d6f 726 The function reads the priority of an interrupt. The interrupt
emh203 0:3d9c67d97d6f 727 number can be positive to specify an external (device specific)
emh203 0:3d9c67d97d6f 728 interrupt, or negative to specify an internal (core) interrupt.
emh203 0:3d9c67d97d6f 729
emh203 0:3d9c67d97d6f 730
emh203 0:3d9c67d97d6f 731 \param [in] IRQn Interrupt number.
emh203 0:3d9c67d97d6f 732 \return Interrupt Priority. Value is aligned automatically to the implemented
emh203 0:3d9c67d97d6f 733 priority bits of the microcontroller.
emh203 0:3d9c67d97d6f 734 */
emh203 0:3d9c67d97d6f 735 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emh203 0:3d9c67d97d6f 736 {
emh203 0:3d9c67d97d6f 737
emh203 0:3d9c67d97d6f 738 if(IRQn < 0) {
emh203 0:3d9c67d97d6f 739 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emh203 0:3d9c67d97d6f 740 else {
emh203 0:3d9c67d97d6f 741 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emh203 0:3d9c67d97d6f 742 }
emh203 0:3d9c67d97d6f 743
emh203 0:3d9c67d97d6f 744
emh203 0:3d9c67d97d6f 745 /** \brief System Reset
emh203 0:3d9c67d97d6f 746
emh203 0:3d9c67d97d6f 747 The function initiates a system reset request to reset the MCU.
emh203 0:3d9c67d97d6f 748 */
emh203 0:3d9c67d97d6f 749 __STATIC_INLINE void NVIC_SystemReset(void)
emh203 0:3d9c67d97d6f 750 {
emh203 0:3d9c67d97d6f 751 __DSB(); /* Ensure all outstanding memory accesses included
emh203 0:3d9c67d97d6f 752 buffered write are completed before reset */
emh203 0:3d9c67d97d6f 753 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emh203 0:3d9c67d97d6f 754 SCB_AIRCR_SYSRESETREQ_Msk);
emh203 0:3d9c67d97d6f 755 __DSB(); /* Ensure completion of memory access */
emh203 0:3d9c67d97d6f 756 while(1); /* wait until reset */
emh203 0:3d9c67d97d6f 757 }
emh203 0:3d9c67d97d6f 758
emh203 0:3d9c67d97d6f 759 /*@} end of CMSIS_Core_NVICFunctions */
emh203 0:3d9c67d97d6f 760
emh203 0:3d9c67d97d6f 761
emh203 0:3d9c67d97d6f 762
emh203 0:3d9c67d97d6f 763 /* ################################## SysTick function ############################################ */
emh203 0:3d9c67d97d6f 764 /** \ingroup CMSIS_Core_FunctionInterface
emh203 0:3d9c67d97d6f 765 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emh203 0:3d9c67d97d6f 766 \brief Functions that configure the System.
emh203 0:3d9c67d97d6f 767 @{
emh203 0:3d9c67d97d6f 768 */
emh203 0:3d9c67d97d6f 769
emh203 0:3d9c67d97d6f 770 #if (__Vendor_SysTickConfig == 0)
emh203 0:3d9c67d97d6f 771
emh203 0:3d9c67d97d6f 772 /** \brief System Tick Configuration
emh203 0:3d9c67d97d6f 773
emh203 0:3d9c67d97d6f 774 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emh203 0:3d9c67d97d6f 775 Counter is in free running mode to generate periodic interrupts.
emh203 0:3d9c67d97d6f 776
emh203 0:3d9c67d97d6f 777 \param [in] ticks Number of ticks between two interrupts.
emh203 0:3d9c67d97d6f 778
emh203 0:3d9c67d97d6f 779 \return 0 Function succeeded.
emh203 0:3d9c67d97d6f 780 \return 1 Function failed.
emh203 0:3d9c67d97d6f 781
emh203 0:3d9c67d97d6f 782 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emh203 0:3d9c67d97d6f 783 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emh203 0:3d9c67d97d6f 784 must contain a vendor-specific implementation of this function.
emh203 0:3d9c67d97d6f 785
emh203 0:3d9c67d97d6f 786 */
emh203 0:3d9c67d97d6f 787 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emh203 0:3d9c67d97d6f 788 {
emh203 0:3d9c67d97d6f 789 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emh203 0:3d9c67d97d6f 790
emh203 0:3d9c67d97d6f 791 SysTick->LOAD = ticks - 1; /* set reload register */
emh203 0:3d9c67d97d6f 792 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emh203 0:3d9c67d97d6f 793 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emh203 0:3d9c67d97d6f 794 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emh203 0:3d9c67d97d6f 795 SysTick_CTRL_TICKINT_Msk |
emh203 0:3d9c67d97d6f 796 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emh203 0:3d9c67d97d6f 797 return (0); /* Function successful */
emh203 0:3d9c67d97d6f 798 }
emh203 0:3d9c67d97d6f 799
emh203 0:3d9c67d97d6f 800 #endif
emh203 0:3d9c67d97d6f 801
emh203 0:3d9c67d97d6f 802 /*@} end of CMSIS_Core_SysTickFunctions */
emh203 0:3d9c67d97d6f 803
emh203 0:3d9c67d97d6f 804
emh203 0:3d9c67d97d6f 805
emh203 0:3d9c67d97d6f 806
emh203 0:3d9c67d97d6f 807 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emh203 0:3d9c67d97d6f 808
emh203 0:3d9c67d97d6f 809 #ifdef __cplusplus
emh203 0:3d9c67d97d6f 810 }
emh203 0:3d9c67d97d6f 811 #endif
emh203 0:3d9c67d97d6f 812
emh203 0:3d9c67d97d6f 813 #endif /* __CMSIS_GENERIC */