Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAXWSNENV/adc_regs.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /*******************************************************************************
Kojto 99:dbbf35b96557 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 99:dbbf35b96557 3 *
Kojto 99:dbbf35b96557 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 99:dbbf35b96557 5 * copy of this software and associated documentation files (the "Software"),
Kojto 99:dbbf35b96557 6 * to deal in the Software without restriction, including without limitation
Kojto 99:dbbf35b96557 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 99:dbbf35b96557 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 99:dbbf35b96557 9 * Software is furnished to do so, subject to the following conditions:
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * The above copyright notice and this permission notice shall be included
Kojto 99:dbbf35b96557 12 * in all copies or substantial portions of the Software.
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 99:dbbf35b96557 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 99:dbbf35b96557 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 99:dbbf35b96557 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 99:dbbf35b96557 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 99:dbbf35b96557 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 99:dbbf35b96557 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 99:dbbf35b96557 21 *
Kojto 99:dbbf35b96557 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 99:dbbf35b96557 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 99:dbbf35b96557 24 * Products, Inc. Branding Policy.
Kojto 99:dbbf35b96557 25 *
Kojto 99:dbbf35b96557 26 * The mere transfer of this software does not imply any licenses
Kojto 99:dbbf35b96557 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 99:dbbf35b96557 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 99:dbbf35b96557 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 99:dbbf35b96557 30 * ownership rights.
Kojto 99:dbbf35b96557 31 *******************************************************************************
Kojto 99:dbbf35b96557 32 */
Kojto 99:dbbf35b96557 33
Kojto 99:dbbf35b96557 34 #ifndef _MXC_ADC_REGS_H
Kojto 99:dbbf35b96557 35 #define _MXC_ADC_REGS_H
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37 #ifdef __cplusplus
Kojto 99:dbbf35b96557 38 extern "C" {
Kojto 99:dbbf35b96557 39 #endif
Kojto 99:dbbf35b96557 40
Kojto 99:dbbf35b96557 41 #include <stdint.h>
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 /**
Kojto 99:dbbf35b96557 44 * @file adc_regs.h
Kojto 99:dbbf35b96557 45 * @addtogroup adc ADC
Kojto 99:dbbf35b96557 46 * @{
Kojto 99:dbbf35b96557 47 */
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 /**
Kojto 99:dbbf35b96557 50 * @brief Defines ADC Modes.
Kojto 99:dbbf35b96557 51 */
Kojto 99:dbbf35b96557 52 typedef enum {
Kojto 99:dbbf35b96557 53 /** Single Mode Full Rate */
Kojto 99:dbbf35b96557 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
Kojto 99:dbbf35b96557 55 /** Single Mode Low Power */
Kojto 99:dbbf35b96557 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
Kojto 99:dbbf35b96557 57 /** Continuous Mode Full Rate */
Kojto 99:dbbf35b96557 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
Kojto 99:dbbf35b96557 59 /** Continuous Mode Low Power */
Kojto 99:dbbf35b96557 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
Kojto 99:dbbf35b96557 61 /** Single Mode Full Rate with Scan Enabled */
Kojto 99:dbbf35b96557 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
Kojto 99:dbbf35b96557 63 /** Single Mode Low Power with Scan Enabled */
Kojto 99:dbbf35b96557 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
Kojto 99:dbbf35b96557 65 /** Continuous Mode Full Rate with Scan Enabled */
Kojto 99:dbbf35b96557 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
Kojto 99:dbbf35b96557 67 /** Continuous Mode Low Power with Scan Enabled */
Kojto 99:dbbf35b96557 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
Kojto 99:dbbf35b96557 69 } mxc_adc_mode_t;
Kojto 99:dbbf35b96557 70
Kojto 99:dbbf35b96557 71 /**
Kojto 99:dbbf35b96557 72 * @brief Defines ADC Range Control.
Kojto 99:dbbf35b96557 73 */
Kojto 99:dbbf35b96557 74 typedef enum {
Kojto 99:dbbf35b96557 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
Kojto 99:dbbf35b96557 76 MXC_E_ADC_RANGE_HALF = 0,
Kojto 99:dbbf35b96557 77 /** Bi-polar Operation (-Vref -> Vref) */
Kojto 99:dbbf35b96557 78 MXC_E_ADC_RANGE_FULL
Kojto 99:dbbf35b96557 79 } mxc_adc_range_t;
Kojto 99:dbbf35b96557 80
Kojto 99:dbbf35b96557 81 /**
Kojto 99:dbbf35b96557 82 * @brief Defines ADC Bipolar operation.
Kojto 99:dbbf35b96557 83 */
Kojto 99:dbbf35b96557 84 typedef enum {
Kojto 99:dbbf35b96557 85 /** Uni-polar operation (0 -> Vref) */
Kojto 99:dbbf35b96557 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
Kojto 99:dbbf35b96557 87 /** Bi-polar operation see ADC Range Control */
Kojto 99:dbbf35b96557 88 MXC_E_ADC_BI_POL_BIPOLAR
Kojto 99:dbbf35b96557 89 } mxc_adc_bi_pol_t;
Kojto 99:dbbf35b96557 90
Kojto 99:dbbf35b96557 91 /**
Kojto 99:dbbf35b96557 92 * @brief Defines Decimation Filter Modes.
Kojto 99:dbbf35b96557 93 */
Kojto 99:dbbf35b96557 94 typedef enum {
Kojto 99:dbbf35b96557 95 /** Decimation Filter ByPassed */
Kojto 99:dbbf35b96557 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
Kojto 99:dbbf35b96557 97 /** Output Average Only*/
Kojto 99:dbbf35b96557 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
Kojto 99:dbbf35b96557 99 /** Output Average and Raw Data (Test Mode Only) */
Kojto 99:dbbf35b96557 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
Kojto 99:dbbf35b96557 101 } mxc_adc_avg_mode_t;
Kojto 99:dbbf35b96557 102
Kojto 99:dbbf35b96557 103 /**
Kojto 99:dbbf35b96557 104 * @brief Defines ADC StartMode Modes.
Kojto 99:dbbf35b96557 105 */
Kojto 99:dbbf35b96557 106 typedef enum {
Kojto 99:dbbf35b96557 107 /** StarMode via Software */
Kojto 99:dbbf35b96557 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
Kojto 99:dbbf35b96557 109 /** StarMode via PulseTrain */
Kojto 99:dbbf35b96557 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
Kojto 99:dbbf35b96557 111 } mxc_adc_strt_mode_t;
Kojto 99:dbbf35b96557 112
Kojto 99:dbbf35b96557 113 /**
Kojto 99:dbbf35b96557 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
Kojto 99:dbbf35b96557 115 */
Kojto 99:dbbf35b96557 116 typedef enum {
Kojto 99:dbbf35b96557 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
Kojto 99:dbbf35b96557 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
Kojto 99:dbbf35b96557 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
Kojto 99:dbbf35b96557 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
Kojto 99:dbbf35b96557 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
Kojto 99:dbbf35b96557 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
Kojto 99:dbbf35b96557 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
Kojto 99:dbbf35b96557 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
Kojto 99:dbbf35b96557 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
Kojto 99:dbbf35b96557 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
Kojto 99:dbbf35b96557 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
Kojto 99:dbbf35b96557 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
Kojto 99:dbbf35b96557 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
Kojto 99:dbbf35b96557 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
Kojto 99:dbbf35b96557 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
Kojto 99:dbbf35b96557 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
Kojto 99:dbbf35b96557 133 /** Single Mode Input AIN8+ */
Kojto 99:dbbf35b96557 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
Kojto 99:dbbf35b96557 135 /** Single Mode Input AIN9+ */
Kojto 99:dbbf35b96557 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
Kojto 99:dbbf35b96557 137 /** Single Mode Input AIN10+ */
Kojto 99:dbbf35b96557 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
Kojto 99:dbbf35b96557 139 /** Single Mode Input AIN11+ */
Kojto 99:dbbf35b96557 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
Kojto 99:dbbf35b96557 141 /** Single Mode Input AIN12+ */
Kojto 99:dbbf35b96557 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
Kojto 99:dbbf35b96557 143 /** Single Mode Input AIN13+ */
Kojto 99:dbbf35b96557 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
Kojto 99:dbbf35b96557 145 /** Single Mode Input AIN14+ */
Kojto 99:dbbf35b96557 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
Kojto 99:dbbf35b96557 147 /** Single Mode Input AIN15+ */
Kojto 99:dbbf35b96557 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
Kojto 99:dbbf35b96557 149 /** Positive Input VSSADC */
Kojto 99:dbbf35b96557 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
Kojto 99:dbbf35b96557 151 /** Positive Input TMON_R */
Kojto 99:dbbf35b96557 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
Kojto 99:dbbf35b96557 153 /** Positive Input VDDA/4 */
Kojto 99:dbbf35b96557 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
Kojto 99:dbbf35b96557 155 /** Positive Input PWRMAN_TST */
Kojto 99:dbbf35b96557 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
Kojto 99:dbbf35b96557 157 /** Positive Input Ain0Div */
Kojto 99:dbbf35b96557 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
Kojto 99:dbbf35b96557 159 /** Positive Input OpAmp OUTA */
Kojto 99:dbbf35b96557 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
Kojto 99:dbbf35b96557 161 /** Positive Input OpAmp OUTB */
Kojto 99:dbbf35b96557 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
Kojto 99:dbbf35b96557 163 /** Positive Input OpAmp OUTC */
Kojto 99:dbbf35b96557 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
Kojto 99:dbbf35b96557 165 /** Positive Input OpAmp OUTD */
Kojto 99:dbbf35b96557 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
Kojto 99:dbbf35b96557 167 /** Positive INA+ */
Kojto 99:dbbf35b96557 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
Kojto 99:dbbf35b96557 169 /** Positive SNO_or */
Kojto 99:dbbf35b96557 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
Kojto 99:dbbf35b96557 171 /** Positive SCM_or */
Kojto 99:dbbf35b96557 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
Kojto 99:dbbf35b96557 173 /** Positive TPROBE_sense */
Kojto 99:dbbf35b96557 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
Kojto 99:dbbf35b96557 175 /** Positive VREFDAC */
Kojto 99:dbbf35b96557 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
Kojto 99:dbbf35b96557 177 /** Positive VREFADJ */
Kojto 99:dbbf35b96557 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
Kojto 99:dbbf35b96557 179 /** Positive Vdd3xtal */
Kojto 99:dbbf35b96557 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
Kojto 99:dbbf35b96557 181 } mxc_adc_pga_mux_ch_sel_t;
Kojto 99:dbbf35b96557 182
Kojto 99:dbbf35b96557 183 /**
Kojto 99:dbbf35b96557 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
Kojto 99:dbbf35b96557 185 */
Kojto 99:dbbf35b96557 186 typedef enum {
Kojto 99:dbbf35b96557 187 /** Differential Mode Disabled */
Kojto 99:dbbf35b96557 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
Kojto 99:dbbf35b96557 189 /** Differential Mode Enabled */
Kojto 99:dbbf35b96557 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
Kojto 99:dbbf35b96557 191 } mxc_adc_pga_mux_diff_t;
Kojto 99:dbbf35b96557 192
Kojto 99:dbbf35b96557 193 /**
Kojto 99:dbbf35b96557 194 * @brief Defines the PGA Gain Options.
Kojto 99:dbbf35b96557 195 */
Kojto 99:dbbf35b96557 196 typedef enum {
Kojto 99:dbbf35b96557 197 /** PGA Gain = 1 */
Kojto 99:dbbf35b96557 198 MXC_E_ADC_PGA_GAIN_1 = 0,
Kojto 99:dbbf35b96557 199 /** PGA Gain = 2 */
Kojto 99:dbbf35b96557 200 MXC_E_ADC_PGA_GAIN_2,
Kojto 99:dbbf35b96557 201 /** PGA Gain = 4 */
Kojto 99:dbbf35b96557 202 MXC_E_ADC_PGA_GAIN_4,
Kojto 99:dbbf35b96557 203 /** PGA Gain = 8 */
Kojto 99:dbbf35b96557 204 MXC_E_ADC_PGA_GAIN_8,
Kojto 99:dbbf35b96557 205 } mxc_adc_pga_gain_t;
Kojto 99:dbbf35b96557 206
Kojto 99:dbbf35b96557 207 /**
Kojto 99:dbbf35b96557 208 * @brief Defines the Switch Control Mode.
Kojto 99:dbbf35b96557 209 */
Kojto 99:dbbf35b96557 210 typedef enum {
Kojto 99:dbbf35b96557 211 /** Switch Control Mode = Software */
Kojto 99:dbbf35b96557 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
Kojto 99:dbbf35b96557 213 /** Switch Control Mode = Pulse Train */
Kojto 99:dbbf35b96557 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
Kojto 99:dbbf35b96557 215 } mxc_adc_spst_sw_ctrl_t;
Kojto 99:dbbf35b96557 216
Kojto 99:dbbf35b96557 217 /**
Kojto 99:dbbf35b96557 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
Kojto 99:dbbf35b96557 219 */
Kojto 99:dbbf35b96557 220 typedef enum {
Kojto 99:dbbf35b96557 221 /** Number of Channels to Scan = 1 */
Kojto 99:dbbf35b96557 222 MXC_E_ADC_SCAN_CNT_1 = 0,
Kojto 99:dbbf35b96557 223 /** Number of Channels to Scan = 2 */
Kojto 99:dbbf35b96557 224 MXC_E_ADC_SCAN_CNT_2,
Kojto 99:dbbf35b96557 225 /** Number of Channels to Scan = 3 */
Kojto 99:dbbf35b96557 226 MXC_E_ADC_SCAN_CNT_3,
Kojto 99:dbbf35b96557 227 /** Number of Channels to Scan = 4 */
Kojto 99:dbbf35b96557 228 MXC_E_ADC_SCAN_CNT_4,
Kojto 99:dbbf35b96557 229 /** Number of Channels to Scan = 5 */
Kojto 99:dbbf35b96557 230 MXC_E_ADC_SCAN_CNT_5,
Kojto 99:dbbf35b96557 231 /** Number of Channels to Scan = 6 */
Kojto 99:dbbf35b96557 232 MXC_E_ADC_SCAN_CNT_6,
Kojto 99:dbbf35b96557 233 /** Number of Channels to Scan = 7 */
Kojto 99:dbbf35b96557 234 MXC_E_ADC_SCAN_CNT_7,
Kojto 99:dbbf35b96557 235 /** Number of Channels to Scan = 8 */
Kojto 99:dbbf35b96557 236 MXC_E_ADC_SCAN_CNT_8,
Kojto 99:dbbf35b96557 237 } mxc_adc_scan_cnt_t;
Kojto 99:dbbf35b96557 238
Kojto 99:dbbf35b96557 239 /* Offset Register Description
Kojto 99:dbbf35b96557 240 ====== =================================================== */
Kojto 99:dbbf35b96557 241 typedef struct {
Kojto 99:dbbf35b96557 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
Kojto 99:dbbf35b96557 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
Kojto 99:dbbf35b96557 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
Kojto 99:dbbf35b96557 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
Kojto 99:dbbf35b96557 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
Kojto 99:dbbf35b96557 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
Kojto 99:dbbf35b96557 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
Kojto 99:dbbf35b96557 249 } mxc_adc_regs_t;
Kojto 99:dbbf35b96557 250
Kojto 99:dbbf35b96557 251 /* Offset Register Description
Kojto 99:dbbf35b96557 252 ====== =================================================== */
Kojto 99:dbbf35b96557 253 typedef struct {
Kojto 99:dbbf35b96557 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
Kojto 99:dbbf35b96557 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
Kojto 99:dbbf35b96557 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
Kojto 99:dbbf35b96557 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
Kojto 99:dbbf35b96557 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
Kojto 99:dbbf35b96557 259 } mxc_adccfg_regs_t;
Kojto 99:dbbf35b96557 260
Kojto 99:dbbf35b96557 261 typedef struct {
Kojto 99:dbbf35b96557 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
Kojto 99:dbbf35b96557 263 } mxc_adc_fifo_regs_t;
Kojto 99:dbbf35b96557 264
Kojto 99:dbbf35b96557 265 /*
Kojto 99:dbbf35b96557 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
Kojto 99:dbbf35b96557 267 */
Kojto 99:dbbf35b96557 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
Kojto 99:dbbf35b96557 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
Kojto 99:dbbf35b96557 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
Kojto 99:dbbf35b96557 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
Kojto 99:dbbf35b96557 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
Kojto 99:dbbf35b96557 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
Kojto 99:dbbf35b96557 275
Kojto 99:dbbf35b96557 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
Kojto 99:dbbf35b96557 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
Kojto 99:dbbf35b96557 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
Kojto 99:dbbf35b96557 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
Kojto 99:dbbf35b96557 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 282
Kojto 99:dbbf35b96557 283 /*
Kojto 99:dbbf35b96557 284 Field positions and masks for module ADC.
Kojto 99:dbbf35b96557 285 */
Kojto 99:dbbf35b96557 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
Kojto 99:dbbf35b96557 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
Kojto 99:dbbf35b96557 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
Kojto 99:dbbf35b96557 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
Kojto 99:dbbf35b96557 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
Kojto 99:dbbf35b96557 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
Kojto 99:dbbf35b96557 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
Kojto 99:dbbf35b96557 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
Kojto 99:dbbf35b96557 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
Kojto 99:dbbf35b96557 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
Kojto 99:dbbf35b96557 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
Kojto 99:dbbf35b96557 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
Kojto 99:dbbf35b96557 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
Kojto 99:dbbf35b96557 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
Kojto 99:dbbf35b96557 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
Kojto 99:dbbf35b96557 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
Kojto 99:dbbf35b96557 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
Kojto 99:dbbf35b96557 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
Kojto 99:dbbf35b96557 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
Kojto 99:dbbf35b96557 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
Kojto 99:dbbf35b96557 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
Kojto 99:dbbf35b96557 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
Kojto 99:dbbf35b96557 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
Kojto 99:dbbf35b96557 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
Kojto 99:dbbf35b96557 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
Kojto 99:dbbf35b96557 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
Kojto 99:dbbf35b96557 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
Kojto 99:dbbf35b96557 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
Kojto 99:dbbf35b96557 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
Kojto 99:dbbf35b96557 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
Kojto 99:dbbf35b96557 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
Kojto 99:dbbf35b96557 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
Kojto 99:dbbf35b96557 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
Kojto 99:dbbf35b96557 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
Kojto 99:dbbf35b96557 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
Kojto 99:dbbf35b96557 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
Kojto 99:dbbf35b96557 322
Kojto 99:dbbf35b96557 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
Kojto 99:dbbf35b96557 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
Kojto 99:dbbf35b96557 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
Kojto 99:dbbf35b96557 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
Kojto 99:dbbf35b96557 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
Kojto 99:dbbf35b96557 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
Kojto 99:dbbf35b96557 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
Kojto 99:dbbf35b96557 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
Kojto 99:dbbf35b96557 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
Kojto 99:dbbf35b96557 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
Kojto 99:dbbf35b96557 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
Kojto 99:dbbf35b96557 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
Kojto 99:dbbf35b96557 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
Kojto 99:dbbf35b96557 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
Kojto 99:dbbf35b96557 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
Kojto 99:dbbf35b96557 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
Kojto 99:dbbf35b96557 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
Kojto 99:dbbf35b96557 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
Kojto 99:dbbf35b96557 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
Kojto 99:dbbf35b96557 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
Kojto 99:dbbf35b96557 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
Kojto 99:dbbf35b96557 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
Kojto 99:dbbf35b96557 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
Kojto 99:dbbf35b96557 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
Kojto 99:dbbf35b96557 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
Kojto 99:dbbf35b96557 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
Kojto 99:dbbf35b96557 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
Kojto 99:dbbf35b96557 352
Kojto 99:dbbf35b96557 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
Kojto 99:dbbf35b96557 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
Kojto 99:dbbf35b96557 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
Kojto 99:dbbf35b96557 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
Kojto 99:dbbf35b96557 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
Kojto 99:dbbf35b96557 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
Kojto 99:dbbf35b96557 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
Kojto 99:dbbf35b96557 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
Kojto 99:dbbf35b96557 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
Kojto 99:dbbf35b96557 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
Kojto 99:dbbf35b96557 363
Kojto 99:dbbf35b96557 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
Kojto 99:dbbf35b96557 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
Kojto 99:dbbf35b96557 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
Kojto 99:dbbf35b96557 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
Kojto 99:dbbf35b96557 368
Kojto 99:dbbf35b96557 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
Kojto 99:dbbf35b96557 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
Kojto 99:dbbf35b96557 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
Kojto 99:dbbf35b96557 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
Kojto 99:dbbf35b96557 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
Kojto 99:dbbf35b96557 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
Kojto 99:dbbf35b96557 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
Kojto 99:dbbf35b96557 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
Kojto 99:dbbf35b96557 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
Kojto 99:dbbf35b96557 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
Kojto 99:dbbf35b96557 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
Kojto 99:dbbf35b96557 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
Kojto 99:dbbf35b96557 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
Kojto 99:dbbf35b96557 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
Kojto 99:dbbf35b96557 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
Kojto 99:dbbf35b96557 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
Kojto 99:dbbf35b96557 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
Kojto 99:dbbf35b96557 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
Kojto 99:dbbf35b96557 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
Kojto 99:dbbf35b96557 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
Kojto 99:dbbf35b96557 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
Kojto 99:dbbf35b96557 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
Kojto 99:dbbf35b96557 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
Kojto 99:dbbf35b96557 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
Kojto 99:dbbf35b96557 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
Kojto 99:dbbf35b96557 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
Kojto 99:dbbf35b96557 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
Kojto 99:dbbf35b96557 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
Kojto 99:dbbf35b96557 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
Kojto 99:dbbf35b96557 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
Kojto 99:dbbf35b96557 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
Kojto 99:dbbf35b96557 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
Kojto 99:dbbf35b96557 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
Kojto 99:dbbf35b96557 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
Kojto 99:dbbf35b96557 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
Kojto 99:dbbf35b96557 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
Kojto 99:dbbf35b96557 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
Kojto 99:dbbf35b96557 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
Kojto 99:dbbf35b96557 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
Kojto 99:dbbf35b96557 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
Kojto 99:dbbf35b96557 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
Kojto 99:dbbf35b96557 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
Kojto 99:dbbf35b96557 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
Kojto 99:dbbf35b96557 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
Kojto 99:dbbf35b96557 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
Kojto 99:dbbf35b96557 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
Kojto 99:dbbf35b96557 415
Kojto 99:dbbf35b96557 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
Kojto 99:dbbf35b96557 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
Kojto 99:dbbf35b96557 418
Kojto 99:dbbf35b96557 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
Kojto 99:dbbf35b96557 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
Kojto 99:dbbf35b96557 421
Kojto 99:dbbf35b96557 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
Kojto 99:dbbf35b96557 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
Kojto 99:dbbf35b96557 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
Kojto 99:dbbf35b96557 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
Kojto 99:dbbf35b96557 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
Kojto 99:dbbf35b96557 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
Kojto 99:dbbf35b96557 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
Kojto 99:dbbf35b96557 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
Kojto 99:dbbf35b96557 430
Kojto 99:dbbf35b96557 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
Kojto 99:dbbf35b96557 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
Kojto 99:dbbf35b96557 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
Kojto 99:dbbf35b96557 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
Kojto 99:dbbf35b96557 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
Kojto 99:dbbf35b96557 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
Kojto 99:dbbf35b96557 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
Kojto 99:dbbf35b96557 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
Kojto 99:dbbf35b96557 439
Kojto 99:dbbf35b96557 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
Kojto 99:dbbf35b96557 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
Kojto 99:dbbf35b96557 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
Kojto 99:dbbf35b96557 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
Kojto 99:dbbf35b96557 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
Kojto 99:dbbf35b96557 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
Kojto 99:dbbf35b96557 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
Kojto 99:dbbf35b96557 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
Kojto 99:dbbf35b96557 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
Kojto 99:dbbf35b96557 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
Kojto 99:dbbf35b96557 450
Kojto 99:dbbf35b96557 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
Kojto 99:dbbf35b96557 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
Kojto 99:dbbf35b96557 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
Kojto 99:dbbf35b96557 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
Kojto 99:dbbf35b96557 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
Kojto 99:dbbf35b96557 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
Kojto 99:dbbf35b96557 457
Kojto 99:dbbf35b96557 458 #ifdef __cplusplus
Kojto 99:dbbf35b96557 459 }
Kojto 99:dbbf35b96557 460 #endif
Kojto 99:dbbf35b96557 461
Kojto 99:dbbf35b96557 462 /**
Kojto 99:dbbf35b96557 463 * @}
Kojto 99:dbbf35b96557 464 */
Kojto 99:dbbf35b96557 465
Kojto 99:dbbf35b96557 466 #endif /* _MXC_ADC_REGS_H */