STM32746G-Discovery board drivers V1.0.0
Dependents: F746_SD_GraphicEqualizer_ren0620
Fork of BSP_DISCO_F746NG by
stm32746g_discovery_sdram.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32746g_discovery_sdram.c 00004 * @author MCD Application Team 00005 * @version V1.0.0 00006 * @date 25-June-2015 00007 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory 00008 * device mounted on STM32746G-Discovery board. 00009 @verbatim 00010 1. How To use this driver: 00011 -------------------------- 00012 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted 00013 on STM32746G-Discovery board. 00014 - This driver does not need a specific component driver for the SDRAM device 00015 to be included with. 00016 00017 2. Driver description: 00018 --------------------- 00019 + Initialization steps: 00020 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 00021 function includes the MSP layer hardware resources initialization and the 00022 FMC controller configuration to interface with the external SDRAM memory. 00023 o It contains the SDRAM initialization sequence to program the SDRAM external 00024 device using the function BSP_SDRAM_Initialization_sequence(). Note that this 00025 sequence is standard for all SDRAM devices, but can include some differences 00026 from a device to another. If it is the case, the right sequence should be 00027 implemented separately. 00028 00029 + SDRAM read/write operations 00030 o SDRAM external memory can be accessed with read/write operations once it is 00031 initialized. 00032 Read/write operation can be performed with AHB access using the functions 00033 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions 00034 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). 00035 o The AHB access is performed with 32-bit width transaction, the DMA transfer 00036 configuration is fixed at single (no burst) word transfer (see the 00037 SDRAM_MspInit() static function). 00038 o User can implement his own functions for read/write access with his desired 00039 configurations. 00040 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() 00041 is called in IRQ handler file, to serve the generated interrupt once the DMA 00042 transfer is complete. 00043 o You can send a command to the SDRAM device in runtime using the function 00044 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 00045 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 00046 00047 @endverbatim 00048 ****************************************************************************** 00049 * @attention 00050 * 00051 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00052 * 00053 * Redistribution and use in source and binary forms, with or without modification, 00054 * are permitted provided that the following conditions are met: 00055 * 1. Redistributions of source code must retain the above copyright notice, 00056 * this list of conditions and the following disclaimer. 00057 * 2. Redistributions in binary form must reproduce the above copyright notice, 00058 * this list of conditions and the following disclaimer in the documentation 00059 * and/or other materials provided with the distribution. 00060 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00061 * may be used to endorse or promote products derived from this software 00062 * without specific prior written permission. 00063 * 00064 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00065 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00066 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00067 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00068 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00069 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00070 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00071 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00072 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00073 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00074 * 00075 ****************************************************************************** 00076 */ 00077 00078 /* Includes ------------------------------------------------------------------*/ 00079 #include "stm32746g_discovery_sdram.h" 00080 00081 // mbed function to replace HAL_Delay function 00082 void wait_ms(int ms); 00083 00084 /** @addtogroup BSP 00085 * @{ 00086 */ 00087 00088 /** @addtogroup STM32746G_DISCOVERY 00089 * @{ 00090 */ 00091 00092 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM 00093 * @{ 00094 */ 00095 00096 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions 00097 * @{ 00098 */ 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines 00104 * @{ 00105 */ 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros 00111 * @{ 00112 */ 00113 /** 00114 * @} 00115 */ 00116 00117 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables 00118 * @{ 00119 */ 00120 static SDRAM_HandleTypeDef sdramHandle; 00121 static FMC_SDRAM_TimingTypeDef Timing; 00122 static FMC_SDRAM_CommandTypeDef Command; 00123 /** 00124 * @} 00125 */ 00126 00127 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes 00128 * @{ 00129 */ 00130 /** 00131 * @} 00132 */ 00133 00134 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions 00135 * @{ 00136 */ 00137 00138 /** 00139 * @brief Initializes the SDRAM device. 00140 * @retval SDRAM status 00141 */ 00142 uint8_t BSP_SDRAM_Init(void) 00143 { 00144 static uint8_t sdramstatus = SDRAM_ERROR; 00145 /* SDRAM device configuration */ 00146 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00147 00148 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ 00149 Timing.LoadToActiveDelay = 2; 00150 Timing.ExitSelfRefreshDelay = 7; 00151 Timing.SelfRefreshTime = 4; 00152 Timing.RowCycleDelay = 7; 00153 Timing.WriteRecoveryTime = 2; 00154 Timing.RPDelay = 2; 00155 Timing.RCDDelay = 2; 00156 00157 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; 00158 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; 00159 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; 00160 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; 00161 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 00162 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; 00163 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 00164 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; 00165 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; 00166 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; 00167 00168 /* SDRAM controller initialization */ 00169 00170 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ 00171 00172 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) 00173 { 00174 sdramstatus = SDRAM_ERROR; 00175 } 00176 else 00177 { 00178 sdramstatus = SDRAM_OK; 00179 } 00180 00181 /* SDRAM initialization sequence */ 00182 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); 00183 00184 return sdramstatus; 00185 } 00186 00187 /** 00188 * @brief DeInitializes the SDRAM device. 00189 * @retval SDRAM status 00190 */ 00191 uint8_t BSP_SDRAM_DeInit(void) 00192 { 00193 static uint8_t sdramstatus = SDRAM_ERROR; 00194 /* SDRAM device de-initialization */ 00195 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00196 00197 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) 00198 { 00199 sdramstatus = SDRAM_ERROR; 00200 } 00201 else 00202 { 00203 sdramstatus = SDRAM_OK; 00204 } 00205 00206 /* SDRAM controller de-initialization */ 00207 BSP_SDRAM_MspDeInit(&sdramHandle, NULL); 00208 00209 return sdramstatus; 00210 } 00211 00212 /** 00213 * @brief Programs the SDRAM device. 00214 * @param RefreshCount: SDRAM refresh counter value 00215 * @retval None 00216 */ 00217 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) 00218 { 00219 __IO uint32_t tmpmrd = 0; 00220 00221 /* Step 1: Configure a clock configuration enable command */ 00222 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; 00223 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00224 Command.AutoRefreshNumber = 1; 00225 Command.ModeRegisterDefinition = 0; 00226 00227 /* Send the command */ 00228 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00229 00230 /* Step 2: Insert 100 us minimum delay */ 00231 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ 00232 //HAL_Delay(1); 00233 wait_ms(1); 00234 00235 /* Step 3: Configure a PALL (precharge all) command */ 00236 Command.CommandMode = FMC_SDRAM_CMD_PALL; 00237 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00238 Command.AutoRefreshNumber = 1; 00239 Command.ModeRegisterDefinition = 0; 00240 00241 /* Send the command */ 00242 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00243 00244 /* Step 4: Configure an Auto Refresh command */ 00245 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; 00246 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00247 Command.AutoRefreshNumber = 8; 00248 Command.ModeRegisterDefinition = 0; 00249 00250 /* Send the command */ 00251 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00252 00253 /* Step 5: Program the external memory mode register */ 00254 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ 00255 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ 00256 SDRAM_MODEREG_CAS_LATENCY_2 |\ 00257 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ 00258 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; 00259 00260 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; 00261 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00262 Command.AutoRefreshNumber = 1; 00263 Command.ModeRegisterDefinition = tmpmrd; 00264 00265 /* Send the command */ 00266 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00267 00268 /* Step 6: Set the refresh rate counter */ 00269 /* Set the device refresh rate */ 00270 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); 00271 } 00272 00273 /** 00274 * @brief Reads an amount of data from the SDRAM memory in polling mode. 00275 * @param uwStartAddress: Read start address 00276 * @param pData: Pointer to data to be read 00277 * @param uwDataSize: Size of read data from the memory 00278 * @retval SDRAM status 00279 */ 00280 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00281 { 00282 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00283 { 00284 return SDRAM_ERROR; 00285 } 00286 else 00287 { 00288 return SDRAM_OK; 00289 } 00290 } 00291 00292 /** 00293 * @brief Reads an amount of data from the SDRAM memory in DMA mode. 00294 * @param uwStartAddress: Read start address 00295 * @param pData: Pointer to data to be read 00296 * @param uwDataSize: Size of read data from the memory 00297 * @retval SDRAM status 00298 */ 00299 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00300 { 00301 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00302 { 00303 return SDRAM_ERROR; 00304 } 00305 else 00306 { 00307 return SDRAM_OK; 00308 } 00309 } 00310 00311 /** 00312 * @brief Writes an amount of data to the SDRAM memory in polling mode. 00313 * @param uwStartAddress: Write start address 00314 * @param pData: Pointer to data to be written 00315 * @param uwDataSize: Size of written data from the memory 00316 * @retval SDRAM status 00317 */ 00318 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00319 { 00320 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00321 { 00322 return SDRAM_ERROR; 00323 } 00324 else 00325 { 00326 return SDRAM_OK; 00327 } 00328 } 00329 00330 /** 00331 * @brief Writes an amount of data to the SDRAM memory in DMA mode. 00332 * @param uwStartAddress: Write start address 00333 * @param pData: Pointer to data to be written 00334 * @param uwDataSize: Size of written data from the memory 00335 * @retval SDRAM status 00336 */ 00337 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00338 { 00339 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00340 { 00341 return SDRAM_ERROR; 00342 } 00343 else 00344 { 00345 return SDRAM_OK; 00346 } 00347 } 00348 00349 /** 00350 * @brief Sends command to the SDRAM bank. 00351 * @param SdramCmd: Pointer to SDRAM command structure 00352 * @retval SDRAM status 00353 */ 00354 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) 00355 { 00356 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) 00357 { 00358 return SDRAM_ERROR; 00359 } 00360 else 00361 { 00362 return SDRAM_OK; 00363 } 00364 } 00365 00366 /** 00367 * @brief Handles SDRAM DMA transfer interrupt request. 00368 * @retval None 00369 */ 00370 void BSP_SDRAM_DMA_IRQHandler(void) 00371 { 00372 HAL_DMA_IRQHandler(sdramHandle.hdma); 00373 } 00374 00375 /** 00376 * @brief Initializes SDRAM MSP. 00377 * @param hsdram: SDRAM handle 00378 * @param Params 00379 * @retval None 00380 */ 00381 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00382 { 00383 static DMA_HandleTypeDef dma_handle; 00384 GPIO_InitTypeDef gpio_init_structure; 00385 00386 /* Enable FMC clock */ 00387 __HAL_RCC_FMC_CLK_ENABLE(); 00388 00389 /* Enable chosen DMAx clock */ 00390 __DMAx_CLK_ENABLE(); 00391 00392 /* Enable GPIOs clock */ 00393 __HAL_RCC_GPIOC_CLK_ENABLE(); 00394 __HAL_RCC_GPIOD_CLK_ENABLE(); 00395 __HAL_RCC_GPIOE_CLK_ENABLE(); 00396 __HAL_RCC_GPIOF_CLK_ENABLE(); 00397 __HAL_RCC_GPIOG_CLK_ENABLE(); 00398 __HAL_RCC_GPIOH_CLK_ENABLE(); 00399 00400 /* Common GPIO configuration */ 00401 gpio_init_structure.Mode = GPIO_MODE_AF_PP; 00402 gpio_init_structure.Pull = GPIO_PULLUP; 00403 gpio_init_structure.Speed = GPIO_SPEED_FAST; 00404 gpio_init_structure.Alternate = GPIO_AF12_FMC; 00405 00406 /* GPIOC configuration */ 00407 gpio_init_structure.Pin = GPIO_PIN_3; 00408 HAL_GPIO_Init(GPIOC, &gpio_init_structure); 00409 00410 /* GPIOD configuration */ 00411 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 | 00412 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; 00413 HAL_GPIO_Init(GPIOD, &gpio_init_structure); 00414 00415 /* GPIOE configuration */ 00416 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ 00417 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00418 GPIO_PIN_15; 00419 HAL_GPIO_Init(GPIOE, &gpio_init_structure); 00420 00421 /* GPIOF configuration */ 00422 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ 00423 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00424 GPIO_PIN_15; 00425 HAL_GPIO_Init(GPIOF, &gpio_init_structure); 00426 00427 /* GPIOG configuration */ 00428 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ 00429 GPIO_PIN_15; 00430 HAL_GPIO_Init(GPIOG, &gpio_init_structure); 00431 00432 /* GPIOH configuration */ 00433 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; 00434 HAL_GPIO_Init(GPIOH, &gpio_init_structure); 00435 00436 /* Configure common DMA parameters */ 00437 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; 00438 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; 00439 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; 00440 dma_handle.Init.MemInc = DMA_MINC_ENABLE; 00441 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 00442 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 00443 dma_handle.Init.Mode = DMA_NORMAL; 00444 dma_handle.Init.Priority = DMA_PRIORITY_HIGH; 00445 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 00446 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; 00447 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; 00448 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; 00449 00450 dma_handle.Instance = SDRAM_DMAx_STREAM; 00451 00452 /* Associate the DMA handle */ 00453 __HAL_LINKDMA(hsdram, hdma, dma_handle); 00454 00455 /* Deinitialize the stream for new transfer */ 00456 HAL_DMA_DeInit(&dma_handle); 00457 00458 /* Configure the DMA stream */ 00459 HAL_DMA_Init(&dma_handle); 00460 00461 /* NVIC configuration for DMA transfer complete interrupt */ 00462 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); 00463 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); 00464 } 00465 00466 /** 00467 * @brief DeInitializes SDRAM MSP. 00468 * @param hsdram: SDRAM handle 00469 * @param Params 00470 * @retval None 00471 */ 00472 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00473 { 00474 static DMA_HandleTypeDef dma_handle; 00475 00476 /* Disable NVIC configuration for DMA interrupt */ 00477 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); 00478 00479 /* Deinitialize the stream for new transfer */ 00480 dma_handle.Instance = SDRAM_DMAx_STREAM; 00481 HAL_DMA_DeInit(&dma_handle); 00482 00483 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications 00484 by surcharging this __weak function */ 00485 } 00486 00487 /** 00488 * @} 00489 */ 00490 00491 /** 00492 * @} 00493 */ 00494 00495 /** 00496 * @} 00497 */ 00498 00499 /** 00500 * @} 00501 */ 00502 00503 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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