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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_adc.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
ebrus 0:0a673c671a56 9 * + Initialization and Configuration
ebrus 0:0a673c671a56 10 * + Analog Watchdog configuration
ebrus 0:0a673c671a56 11 * + Temperature Sensor, Vbat & Vrefint (Internal Reference Voltage) management
ebrus 0:0a673c671a56 12 * + Regular Channels Configuration
ebrus 0:0a673c671a56 13 * + Regular Channels DMA Configuration
ebrus 0:0a673c671a56 14 * + Injected channels Configuration
ebrus 0:0a673c671a56 15 * + Interrupts and flags management
ebrus 0:0a673c671a56 16 * + Dual mode configuration
ebrus 0:0a673c671a56 17 *
ebrus 0:0a673c671a56 18 @verbatim
ebrus 0:0a673c671a56 19 ==============================================================================
ebrus 0:0a673c671a56 20 ##### How to use this driver #####
ebrus 0:0a673c671a56 21 ==============================================================================
ebrus 0:0a673c671a56 22 [..]
ebrus 0:0a673c671a56 23 (#) select the ADC clock using the function RCC_ADCCLKConfig()
ebrus 0:0a673c671a56 24 (#) Enable the ADC interface clock using RCC_AHBPeriphClockCmd();
ebrus 0:0a673c671a56 25 (#) ADC pins configuration
ebrus 0:0a673c671a56 26 (++) Enable the clock for the ADC GPIOs using the following function:
ebrus 0:0a673c671a56 27 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
ebrus 0:0a673c671a56 28 (++) Configure these ADC pins in analog mode using GPIO_Init();
ebrus 0:0a673c671a56 29 (#) Configure the ADC conversion resolution, data alignment, external
ebrus 0:0a673c671a56 30 trigger and edge, sequencer lenght and Enable/Disable the continuous mode
ebrus 0:0a673c671a56 31 using the ADC_Init() function.
ebrus 0:0a673c671a56 32 (#) Activate the ADC peripheral using ADC_Cmd() function.
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 *** ADC channels group configuration ***
ebrus 0:0a673c671a56 35 ========================================
ebrus 0:0a673c671a56 36 [..]
ebrus 0:0a673c671a56 37 (+) To configure the ADC channels features, use ADC_Init(), ADC_InjectedInit()
ebrus 0:0a673c671a56 38 and/or ADC_RegularChannelConfig() functions.
ebrus 0:0a673c671a56 39 (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
ebrus 0:0a673c671a56 40 function.
ebrus 0:0a673c671a56 41 (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions.
ebrus 0:0a673c671a56 42 (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
ebrus 0:0a673c671a56 43 (+) To activate the calibration mode, use the ADC_StartCalibration() functions.
ebrus 0:0a673c671a56 44 (+) To read the ADC converted values, use the ADC_GetConversionValue()
ebrus 0:0a673c671a56 45 function.
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47 *** DMA for ADC channels features configuration ***
ebrus 0:0a673c671a56 48 ===================================================
ebrus 0:0a673c671a56 49 [..]
ebrus 0:0a673c671a56 50 (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
ebrus 0:0a673c671a56 51 (+) To configure the DMA transfer request, use ADC_DMAConfig() function.
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 @endverbatim
ebrus 0:0a673c671a56 54 *
ebrus 0:0a673c671a56 55 ******************************************************************************
ebrus 0:0a673c671a56 56 * @attention
ebrus 0:0a673c671a56 57 *
ebrus 0:0a673c671a56 58 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 59 *
ebrus 0:0a673c671a56 60 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 61 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 62 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 63 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 65 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 66 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 68 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 69 * without specific prior written permission.
ebrus 0:0a673c671a56 70 *
ebrus 0:0a673c671a56 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 81 *
ebrus 0:0a673c671a56 82 ******************************************************************************
ebrus 0:0a673c671a56 83 */
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 86 #include "stm32f30x_adc.h"
ebrus 0:0a673c671a56 87 #include "stm32f30x_rcc.h"
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 90 * @{
ebrus 0:0a673c671a56 91 */
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 /** @defgroup ADC
ebrus 0:0a673c671a56 94 * @brief ADC driver modules
ebrus 0:0a673c671a56 95 * @{
ebrus 0:0a673c671a56 96 */
ebrus 0:0a673c671a56 97
ebrus 0:0a673c671a56 98 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 99 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 /* CFGR register Mask */
ebrus 0:0a673c671a56 102 #define CFGR_CLEAR_Mask ((uint32_t)0xFDFFC007)
ebrus 0:0a673c671a56 103
ebrus 0:0a673c671a56 104 /* JSQR register Mask */
ebrus 0:0a673c671a56 105 #define JSQR_CLEAR_Mask ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 106
ebrus 0:0a673c671a56 107 /* ADC ADON mask */
ebrus 0:0a673c671a56 108 #define CCR_CLEAR_MASK ((uint32_t)0xFFFC10E0)
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 /* ADC JDRx registers offset */
ebrus 0:0a673c671a56 111 #define JDR_Offset ((uint8_t)0x80)
ebrus 0:0a673c671a56 112
ebrus 0:0a673c671a56 113 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 114 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 115 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 116 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 117
ebrus 0:0a673c671a56 118 /** @defgroup ADC_Private_Functions
ebrus 0:0a673c671a56 119 * @{
ebrus 0:0a673c671a56 120 */
ebrus 0:0a673c671a56 121
ebrus 0:0a673c671a56 122 /** @defgroup ADC_Group1 Initialization and Configuration functions
ebrus 0:0a673c671a56 123 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 124 *
ebrus 0:0a673c671a56 125 @verbatim
ebrus 0:0a673c671a56 126 ===============================================================================
ebrus 0:0a673c671a56 127 ##### Initialization and Configuration functions #####
ebrus 0:0a673c671a56 128 ===============================================================================
ebrus 0:0a673c671a56 129 [..]
ebrus 0:0a673c671a56 130 This section provides functions allowing to:
ebrus 0:0a673c671a56 131 (#) Initialize and configure the ADC injected and/or regular channels and dual mode.
ebrus 0:0a673c671a56 132 (#) Management of the calibration process
ebrus 0:0a673c671a56 133 (#) ADC Power-on Power-off
ebrus 0:0a673c671a56 134 (#) Single ended or differential mode
ebrus 0:0a673c671a56 135 (#) Enabling the queue of context and the auto delay mode
ebrus 0:0a673c671a56 136 (#) The number of ADC conversions that will be done using the sequencer for regular
ebrus 0:0a673c671a56 137 channel group
ebrus 0:0a673c671a56 138 (#) Enable or disable the ADC peripheral
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 @endverbatim
ebrus 0:0a673c671a56 141 * @{
ebrus 0:0a673c671a56 142 */
ebrus 0:0a673c671a56 143
ebrus 0:0a673c671a56 144 /**
ebrus 0:0a673c671a56 145 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
ebrus 0:0a673c671a56 146 * @param ADCx: where x can be 1, 2,3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 147 * @retval None
ebrus 0:0a673c671a56 148 */
ebrus 0:0a673c671a56 149 void ADC_DeInit(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 150 {
ebrus 0:0a673c671a56 151 /* Check the parameters */
ebrus 0:0a673c671a56 152 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 153
ebrus 0:0a673c671a56 154
ebrus 0:0a673c671a56 155 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 156 {
ebrus 0:0a673c671a56 157 /* Enable ADC1/ADC2 reset state */
ebrus 0:0a673c671a56 158 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, ENABLE);
ebrus 0:0a673c671a56 159 /* Release ADC1/ADC2 from reset state */
ebrus 0:0a673c671a56 160 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, DISABLE);
ebrus 0:0a673c671a56 161 }
ebrus 0:0a673c671a56 162 else if((ADCx == ADC3) || (ADCx == ADC4))
ebrus 0:0a673c671a56 163 {
ebrus 0:0a673c671a56 164 /* Enable ADC3/ADC4 reset state */
ebrus 0:0a673c671a56 165 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, ENABLE);
ebrus 0:0a673c671a56 166 /* Release ADC3/ADC4 from reset state */
ebrus 0:0a673c671a56 167 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, DISABLE);
ebrus 0:0a673c671a56 168 }
ebrus 0:0a673c671a56 169 }
ebrus 0:0a673c671a56 170 /**
ebrus 0:0a673c671a56 171 * @brief Initializes the ADCx peripheral according to the specified parameters
ebrus 0:0a673c671a56 172 * in the ADC_InitStruct.
ebrus 0:0a673c671a56 173 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 174 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
ebrus 0:0a673c671a56 175 * the configuration information for the specified ADC peripheral.
ebrus 0:0a673c671a56 176 * @retval None
ebrus 0:0a673c671a56 177 */
ebrus 0:0a673c671a56 178 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
ebrus 0:0a673c671a56 179 {
ebrus 0:0a673c671a56 180 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 181 /* Check the parameters */
ebrus 0:0a673c671a56 182 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 183 assert_param(IS_ADC_CONVMODE(ADC_InitStruct->ADC_ContinuousConvMode));
ebrus 0:0a673c671a56 184 assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
ebrus 0:0a673c671a56 185 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConvEvent));
ebrus 0:0a673c671a56 186 assert_param(IS_EXTERNALTRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigEventEdge));
ebrus 0:0a673c671a56 187 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
ebrus 0:0a673c671a56 188 assert_param(IS_ADC_OVRUNMODE(ADC_InitStruct->ADC_OverrunMode));
ebrus 0:0a673c671a56 189 assert_param(IS_ADC_AUTOINJECMODE(ADC_InitStruct->ADC_AutoInjMode));
ebrus 0:0a673c671a56 190 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfRegChannel));
ebrus 0:0a673c671a56 191
ebrus 0:0a673c671a56 192 /*---------------------------- ADCx CFGR Configuration -----------------*/
ebrus 0:0a673c671a56 193 /* Get the ADCx CFGR value */
ebrus 0:0a673c671a56 194 tmpreg1 = ADCx->CFGR;
ebrus 0:0a673c671a56 195 /* Clear SCAN bit */
ebrus 0:0a673c671a56 196 tmpreg1 &= CFGR_CLEAR_Mask;
ebrus 0:0a673c671a56 197 /* Configure ADCx: scan conversion mode */
ebrus 0:0a673c671a56 198 /* Set SCAN bit according to ADC_ScanConvMode value */
ebrus 0:0a673c671a56 199 tmpreg1 |= (uint32_t)ADC_InitStruct->ADC_ContinuousConvMode |
ebrus 0:0a673c671a56 200 ADC_InitStruct->ADC_Resolution|
ebrus 0:0a673c671a56 201 ADC_InitStruct->ADC_ExternalTrigConvEvent|
ebrus 0:0a673c671a56 202 ADC_InitStruct->ADC_ExternalTrigEventEdge|
ebrus 0:0a673c671a56 203 ADC_InitStruct->ADC_DataAlign|
ebrus 0:0a673c671a56 204 ADC_InitStruct->ADC_OverrunMode|
ebrus 0:0a673c671a56 205 ADC_InitStruct->ADC_AutoInjMode;
ebrus 0:0a673c671a56 206
ebrus 0:0a673c671a56 207 /* Write to ADCx CFGR */
ebrus 0:0a673c671a56 208 ADCx->CFGR = tmpreg1;
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 /*---------------------------- ADCx SQR1 Configuration -----------------*/
ebrus 0:0a673c671a56 211 /* Get the ADCx SQR1 value */
ebrus 0:0a673c671a56 212 tmpreg1 = ADCx->SQR1;
ebrus 0:0a673c671a56 213 /* Clear L bits */
ebrus 0:0a673c671a56 214 tmpreg1 &= ~(uint32_t)(ADC_SQR1_L);
ebrus 0:0a673c671a56 215 /* Configure ADCx: regular channel sequence length */
ebrus 0:0a673c671a56 216 /* Set L bits according to ADC_NbrOfRegChannel value */
ebrus 0:0a673c671a56 217 tmpreg1 |= (uint32_t) (ADC_InitStruct->ADC_NbrOfRegChannel - 1);
ebrus 0:0a673c671a56 218 /* Write to ADCx SQR1 */
ebrus 0:0a673c671a56 219 ADCx->SQR1 = tmpreg1;
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 }
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 /**
ebrus 0:0a673c671a56 224 * @brief Fills each ADC_InitStruct member with its default value.
ebrus 0:0a673c671a56 225 * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
ebrus 0:0a673c671a56 226 * @retval None
ebrus 0:0a673c671a56 227 */
ebrus 0:0a673c671a56 228 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
ebrus 0:0a673c671a56 229 {
ebrus 0:0a673c671a56 230 /* Reset ADC init structure parameters values */
ebrus 0:0a673c671a56 231 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
ebrus 0:0a673c671a56 232 ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
ebrus 0:0a673c671a56 233 ADC_InitStruct->ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0;
ebrus 0:0a673c671a56 234 ADC_InitStruct->ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None;
ebrus 0:0a673c671a56 235 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
ebrus 0:0a673c671a56 236 ADC_InitStruct->ADC_OverrunMode = DISABLE;
ebrus 0:0a673c671a56 237 ADC_InitStruct->ADC_AutoInjMode = DISABLE;
ebrus 0:0a673c671a56 238 ADC_InitStruct->ADC_NbrOfRegChannel = 1;
ebrus 0:0a673c671a56 239 }
ebrus 0:0a673c671a56 240
ebrus 0:0a673c671a56 241 /**
ebrus 0:0a673c671a56 242 * @brief Initializes the ADCx peripheral according to the specified parameters
ebrus 0:0a673c671a56 243 * in the ADC_InitStruct.
ebrus 0:0a673c671a56 244 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 245 * @param ADC_InjectInitStruct: pointer to an ADC_InjecInitTypeDef structure that contains
ebrus 0:0a673c671a56 246 * the configuration information for the specified ADC injected channel.
ebrus 0:0a673c671a56 247 * @retval None
ebrus 0:0a673c671a56 248 */
ebrus 0:0a673c671a56 249 void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
ebrus 0:0a673c671a56 250 {
ebrus 0:0a673c671a56 251 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 252 /* Check the parameters */
ebrus 0:0a673c671a56 253 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 254 assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent));
ebrus 0:0a673c671a56 255 assert_param(IS_EXTERNALTRIGINJ_EDGE(ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge));
ebrus 0:0a673c671a56 256 assert_param(IS_ADC_INJECTED_LENGTH(ADC_InjectedInitStruct->ADC_NbrOfInjecChannel));
ebrus 0:0a673c671a56 257 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence1));
ebrus 0:0a673c671a56 258 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence2));
ebrus 0:0a673c671a56 259 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence3));
ebrus 0:0a673c671a56 260 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence4));
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 /*---------------------------- ADCx JSQR Configuration -----------------*/
ebrus 0:0a673c671a56 263 /* Get the ADCx JSQR value */
ebrus 0:0a673c671a56 264 tmpreg1 = ADCx->JSQR;
ebrus 0:0a673c671a56 265 /* Clear L bits */
ebrus 0:0a673c671a56 266 tmpreg1 &= JSQR_CLEAR_Mask;
ebrus 0:0a673c671a56 267 /* Configure ADCx: Injected channel sequence length, external trigger,
ebrus 0:0a673c671a56 268 external trigger edge and sequences
ebrus 0:0a673c671a56 269 */
ebrus 0:0a673c671a56 270 tmpreg1 = (uint32_t) ((ADC_InjectedInitStruct->ADC_NbrOfInjecChannel - (uint8_t)1) |
ebrus 0:0a673c671a56 271 ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent |
ebrus 0:0a673c671a56 272 ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge |
ebrus 0:0a673c671a56 273 (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence1) << 8) |
ebrus 0:0a673c671a56 274 (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence2) << 14) |
ebrus 0:0a673c671a56 275 (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence3) << 20) |
ebrus 0:0a673c671a56 276 (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence4) << 26));
ebrus 0:0a673c671a56 277 /* Write to ADCx SQR1 */
ebrus 0:0a673c671a56 278 ADCx->JSQR = tmpreg1;
ebrus 0:0a673c671a56 279 }
ebrus 0:0a673c671a56 280
ebrus 0:0a673c671a56 281 /**
ebrus 0:0a673c671a56 282 * @brief Fills each ADC_InjectedInitStruct member with its default value.
ebrus 0:0a673c671a56 283 * @param ADC_InjectedInitStruct : pointer to an ADC_InjectedInitTypeDef structure which will be initialized.
ebrus 0:0a673c671a56 284 * @retval None
ebrus 0:0a673c671a56 285 */
ebrus 0:0a673c671a56 286 void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
ebrus 0:0a673c671a56 287 {
ebrus 0:0a673c671a56 288 ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent = ADC_ExternalTrigInjecConvEvent_0;
ebrus 0:0a673c671a56 289 ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge = ADC_ExternalTrigInjecEventEdge_None;
ebrus 0:0a673c671a56 290 ADC_InjectedInitStruct->ADC_NbrOfInjecChannel = 1;
ebrus 0:0a673c671a56 291 ADC_InjectedInitStruct->ADC_InjecSequence1 = ADC_InjectedChannel_1;
ebrus 0:0a673c671a56 292 ADC_InjectedInitStruct->ADC_InjecSequence2 = ADC_InjectedChannel_1;
ebrus 0:0a673c671a56 293 ADC_InjectedInitStruct->ADC_InjecSequence3 = ADC_InjectedChannel_1;
ebrus 0:0a673c671a56 294 ADC_InjectedInitStruct->ADC_InjecSequence4 = ADC_InjectedChannel_1;
ebrus 0:0a673c671a56 295 }
ebrus 0:0a673c671a56 296
ebrus 0:0a673c671a56 297 /**
ebrus 0:0a673c671a56 298 * @brief Initializes the ADCs peripherals according to the specified parameters
ebrus 0:0a673c671a56 299 * in the ADC_CommonInitStruct.
ebrus 0:0a673c671a56 300 * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 301 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
ebrus 0:0a673c671a56 302 * that contains the configuration information for All ADCs peripherals.
ebrus 0:0a673c671a56 303 * @retval None
ebrus 0:0a673c671a56 304 */
ebrus 0:0a673c671a56 305 void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct)
ebrus 0:0a673c671a56 306 {
ebrus 0:0a673c671a56 307 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 308 /* Check the parameters */
ebrus 0:0a673c671a56 309 assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
ebrus 0:0a673c671a56 310 assert_param(IS_ADC_CLOCKMODE(ADC_CommonInitStruct->ADC_Clock));
ebrus 0:0a673c671a56 311 assert_param(IS_ADC_DMA_MODE(ADC_CommonInitStruct->ADC_DMAMode));
ebrus 0:0a673c671a56 312 assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
ebrus 0:0a673c671a56 313 assert_param(IS_ADC_TWOSAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 316 {
ebrus 0:0a673c671a56 317 /* Get the ADC CCR value */
ebrus 0:0a673c671a56 318 tmpreg1 = ADC1_2->CCR;
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320 /* Clear MULTI, DELAY, DMA and ADCPRE bits */
ebrus 0:0a673c671a56 321 tmpreg1 &= CCR_CLEAR_MASK;
ebrus 0:0a673c671a56 322 }
ebrus 0:0a673c671a56 323 else
ebrus 0:0a673c671a56 324 {
ebrus 0:0a673c671a56 325 /* Get the ADC CCR value */
ebrus 0:0a673c671a56 326 tmpreg1 = ADC3_4->CCR;
ebrus 0:0a673c671a56 327
ebrus 0:0a673c671a56 328 /* Clear MULTI, DELAY, DMA and ADCPRE bits */
ebrus 0:0a673c671a56 329 tmpreg1 &= CCR_CLEAR_MASK;
ebrus 0:0a673c671a56 330 }
ebrus 0:0a673c671a56 331 /*---------------------------- ADC CCR Configuration -----------------*/
ebrus 0:0a673c671a56 332 /* Configure ADCx: Multi mode, Delay between two sampling time, ADC clock, DMA mode
ebrus 0:0a673c671a56 333 and DMA access mode for dual mode */
ebrus 0:0a673c671a56 334 /* Set MULTI bits according to ADC_Mode value */
ebrus 0:0a673c671a56 335 /* Set CKMODE bits according to ADC_Clock value */
ebrus 0:0a673c671a56 336 /* Set MDMA bits according to ADC_DMAAccessMode value */
ebrus 0:0a673c671a56 337 /* Set DMACFG bits according to ADC_DMAMode value */
ebrus 0:0a673c671a56 338 /* Set DELAY bits according to ADC_TwoSamplingDelay value */
ebrus 0:0a673c671a56 339 tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
ebrus 0:0a673c671a56 340 ADC_CommonInitStruct->ADC_Clock |
ebrus 0:0a673c671a56 341 ADC_CommonInitStruct->ADC_DMAAccessMode |
ebrus 0:0a673c671a56 342 (uint32_t)(ADC_CommonInitStruct->ADC_DMAMode << 12) |
ebrus 0:0a673c671a56 343 (uint32_t)((uint32_t)ADC_CommonInitStruct->ADC_TwoSamplingDelay << 8));
ebrus 0:0a673c671a56 344
ebrus 0:0a673c671a56 345 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 346 {
ebrus 0:0a673c671a56 347 /* Write to ADC CCR */
ebrus 0:0a673c671a56 348 ADC1_2->CCR = tmpreg1;
ebrus 0:0a673c671a56 349 }
ebrus 0:0a673c671a56 350 else
ebrus 0:0a673c671a56 351 {
ebrus 0:0a673c671a56 352 /* Write to ADC CCR */
ebrus 0:0a673c671a56 353 ADC3_4->CCR = tmpreg1;
ebrus 0:0a673c671a56 354 }
ebrus 0:0a673c671a56 355 }
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 /**
ebrus 0:0a673c671a56 358 * @brief Fills each ADC_CommonInitStruct member with its default value.
ebrus 0:0a673c671a56 359 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
ebrus 0:0a673c671a56 360 * which will be initialized.
ebrus 0:0a673c671a56 361 * @retval None
ebrus 0:0a673c671a56 362 */
ebrus 0:0a673c671a56 363 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
ebrus 0:0a673c671a56 364 {
ebrus 0:0a673c671a56 365 /* Initialize the ADC_Mode member */
ebrus 0:0a673c671a56 366 ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
ebrus 0:0a673c671a56 367
ebrus 0:0a673c671a56 368 /* initialize the ADC_Clock member */
ebrus 0:0a673c671a56 369 ADC_CommonInitStruct->ADC_Clock = ADC_Clock_AsynClkMode;
ebrus 0:0a673c671a56 370
ebrus 0:0a673c671a56 371 /* Initialize the ADC_DMAAccessMode member */
ebrus 0:0a673c671a56 372 ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ebrus 0:0a673c671a56 373
ebrus 0:0a673c671a56 374 /* Initialize the ADC_DMAMode member */
ebrus 0:0a673c671a56 375 ADC_CommonInitStruct->ADC_DMAMode = ADC_DMAMode_OneShot;
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 /* Initialize the ADC_TwoSamplingDelay member */
ebrus 0:0a673c671a56 378 ADC_CommonInitStruct->ADC_TwoSamplingDelay = 0;
ebrus 0:0a673c671a56 379
ebrus 0:0a673c671a56 380 }
ebrus 0:0a673c671a56 381
ebrus 0:0a673c671a56 382 /**
ebrus 0:0a673c671a56 383 * @brief Enables or disables the specified ADC peripheral.
ebrus 0:0a673c671a56 384 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 385 * @param NewState: new state of the ADCx peripheral.
ebrus 0:0a673c671a56 386 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 387 * @retval None
ebrus 0:0a673c671a56 388 */
ebrus 0:0a673c671a56 389 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 390 {
ebrus 0:0a673c671a56 391 /* Check the parameters */
ebrus 0:0a673c671a56 392 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 393 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 394
ebrus 0:0a673c671a56 395 if (NewState != DISABLE)
ebrus 0:0a673c671a56 396 {
ebrus 0:0a673c671a56 397 /* Set the ADEN bit */
ebrus 0:0a673c671a56 398 ADCx->CR |= ADC_CR_ADEN;
ebrus 0:0a673c671a56 399 }
ebrus 0:0a673c671a56 400 else
ebrus 0:0a673c671a56 401 {
ebrus 0:0a673c671a56 402 /* Disable the selected ADC peripheral: Set the ADDIS bit */
ebrus 0:0a673c671a56 403 ADCx->CR |= ADC_CR_ADDIS;
ebrus 0:0a673c671a56 404 }
ebrus 0:0a673c671a56 405 }
ebrus 0:0a673c671a56 406
ebrus 0:0a673c671a56 407 /**
ebrus 0:0a673c671a56 408 * @brief Starts the selected ADC calibration process.
ebrus 0:0a673c671a56 409 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 410 * @retval None
ebrus 0:0a673c671a56 411 */
ebrus 0:0a673c671a56 412 void ADC_StartCalibration(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 413 {
ebrus 0:0a673c671a56 414 /* Check the parameters */
ebrus 0:0a673c671a56 415 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 416
ebrus 0:0a673c671a56 417 /* Set the ADCAL bit */
ebrus 0:0a673c671a56 418 ADCx->CR |= ADC_CR_ADCAL;
ebrus 0:0a673c671a56 419 }
ebrus 0:0a673c671a56 420
ebrus 0:0a673c671a56 421 /**
ebrus 0:0a673c671a56 422 * @brief Returns the ADCx calibration value.
ebrus 0:0a673c671a56 423 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 424 * @retval None
ebrus 0:0a673c671a56 425 */
ebrus 0:0a673c671a56 426 uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 427 {
ebrus 0:0a673c671a56 428 /* Check the parameters */
ebrus 0:0a673c671a56 429 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 430
ebrus 0:0a673c671a56 431 /* Return the selected ADC calibration value */
ebrus 0:0a673c671a56 432 return (uint32_t)ADCx->CALFACT;
ebrus 0:0a673c671a56 433 }
ebrus 0:0a673c671a56 434
ebrus 0:0a673c671a56 435 /**
ebrus 0:0a673c671a56 436 * @brief Sets the ADCx calibration register.
ebrus 0:0a673c671a56 437 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 438 * @retval None
ebrus 0:0a673c671a56 439 */
ebrus 0:0a673c671a56 440 void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration)
ebrus 0:0a673c671a56 441 {
ebrus 0:0a673c671a56 442 /* Check the parameters */
ebrus 0:0a673c671a56 443 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 444
ebrus 0:0a673c671a56 445 /* Set the ADC calibration register value */
ebrus 0:0a673c671a56 446 ADCx->CALFACT = ADC_Calibration;
ebrus 0:0a673c671a56 447 }
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 /**
ebrus 0:0a673c671a56 450 * @brief Select the ADC calibration mode.
ebrus 0:0a673c671a56 451 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 452 * @param ADC_CalibrationMode: the ADC calibration mode.
ebrus 0:0a673c671a56 453 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 454 * @arg ADC_CalibrationMode_Single: to select the calibration for single channel
ebrus 0:0a673c671a56 455 * @arg ADC_CalibrationMode_Differential: to select the calibration for differential channel
ebrus 0:0a673c671a56 456 * @retval None
ebrus 0:0a673c671a56 457 */
ebrus 0:0a673c671a56 458 void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode)
ebrus 0:0a673c671a56 459 {
ebrus 0:0a673c671a56 460 /* Check the parameters */
ebrus 0:0a673c671a56 461 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 462 assert_param(IS_ADC_CALIBRATION_MODE(ADC_CalibrationMode));
ebrus 0:0a673c671a56 463 /* Set or Reset the ADCALDIF bit */
ebrus 0:0a673c671a56 464 ADCx->CR &= (~ADC_CR_ADCALDIF);
ebrus 0:0a673c671a56 465 ADCx->CR |= ADC_CalibrationMode;
ebrus 0:0a673c671a56 466
ebrus 0:0a673c671a56 467 }
ebrus 0:0a673c671a56 468
ebrus 0:0a673c671a56 469 /**
ebrus 0:0a673c671a56 470 * @brief Gets the selected ADC calibration status.
ebrus 0:0a673c671a56 471 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 472 * @retval The new state of ADC calibration (SET or RESET).
ebrus 0:0a673c671a56 473 */
ebrus 0:0a673c671a56 474 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 475 {
ebrus 0:0a673c671a56 476 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 477 /* Check the parameters */
ebrus 0:0a673c671a56 478 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 479 /* Check the status of CAL bit */
ebrus 0:0a673c671a56 480 if ((ADCx->CR & ADC_CR_ADCAL) != (uint32_t)RESET)
ebrus 0:0a673c671a56 481 {
ebrus 0:0a673c671a56 482 /* CAL bit is set: calibration on going */
ebrus 0:0a673c671a56 483 bitstatus = SET;
ebrus 0:0a673c671a56 484 }
ebrus 0:0a673c671a56 485 else
ebrus 0:0a673c671a56 486 {
ebrus 0:0a673c671a56 487 /* CAL bit is reset: end of calibration */
ebrus 0:0a673c671a56 488 bitstatus = RESET;
ebrus 0:0a673c671a56 489 }
ebrus 0:0a673c671a56 490 /* Return the CAL bit status */
ebrus 0:0a673c671a56 491 return bitstatus;
ebrus 0:0a673c671a56 492 }
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 /**
ebrus 0:0a673c671a56 495 * @brief ADC Disable Command.
ebrus 0:0a673c671a56 496 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 497 * @retval None
ebrus 0:0a673c671a56 498 */
ebrus 0:0a673c671a56 499 void ADC_DisableCmd(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 500 {
ebrus 0:0a673c671a56 501 /* Check the parameters */
ebrus 0:0a673c671a56 502 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 503
ebrus 0:0a673c671a56 504 /* Set the ADDIS bit */
ebrus 0:0a673c671a56 505 ADCx->CR |= ADC_CR_ADDIS;
ebrus 0:0a673c671a56 506 }
ebrus 0:0a673c671a56 507
ebrus 0:0a673c671a56 508
ebrus 0:0a673c671a56 509 /**
ebrus 0:0a673c671a56 510 * @brief Gets the selected ADC disable command Status.
ebrus 0:0a673c671a56 511 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 512 * @retval The new state of ADC ADC disable command (SET or RESET).
ebrus 0:0a673c671a56 513 */
ebrus 0:0a673c671a56 514 FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 515 {
ebrus 0:0a673c671a56 516 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 517 /* Check the parameters */
ebrus 0:0a673c671a56 518 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 519
ebrus 0:0a673c671a56 520 /* Check the status of ADDIS bit */
ebrus 0:0a673c671a56 521 if ((ADCx->CR & ADC_CR_ADDIS) != (uint32_t)RESET)
ebrus 0:0a673c671a56 522 {
ebrus 0:0a673c671a56 523 /* ADDIS bit is set */
ebrus 0:0a673c671a56 524 bitstatus = SET;
ebrus 0:0a673c671a56 525 }
ebrus 0:0a673c671a56 526 else
ebrus 0:0a673c671a56 527 {
ebrus 0:0a673c671a56 528 /* ADDIS bit is reset */
ebrus 0:0a673c671a56 529 bitstatus = RESET;
ebrus 0:0a673c671a56 530 }
ebrus 0:0a673c671a56 531 /* Return the ADDIS bit status */
ebrus 0:0a673c671a56 532 return bitstatus;
ebrus 0:0a673c671a56 533 }
ebrus 0:0a673c671a56 534
ebrus 0:0a673c671a56 535 /**
ebrus 0:0a673c671a56 536 * @brief Enables or disables the specified ADC Voltage Regulator.
ebrus 0:0a673c671a56 537 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 538 * @param NewState: new state of the ADCx Voltage Regulator.
ebrus 0:0a673c671a56 539 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 540 * @retval None
ebrus 0:0a673c671a56 541 */
ebrus 0:0a673c671a56 542 void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 543 {
ebrus 0:0a673c671a56 544 /* Check the parameters */
ebrus 0:0a673c671a56 545 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 546 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 547
ebrus 0:0a673c671a56 548 /* set the intermediate state before moving the ADC voltage regulator
ebrus 0:0a673c671a56 549 from enable state to disable state or from disable state to enable state */
ebrus 0:0a673c671a56 550 ADCx->CR &= ~(ADC_CR_ADVREGEN);
ebrus 0:0a673c671a56 551
ebrus 0:0a673c671a56 552 if (NewState != DISABLE)
ebrus 0:0a673c671a56 553 {
ebrus 0:0a673c671a56 554 /* Set the ADVREGEN bit 0 */
ebrus 0:0a673c671a56 555 ADCx->CR |= ADC_CR_ADVREGEN_0;
ebrus 0:0a673c671a56 556 }
ebrus 0:0a673c671a56 557 else
ebrus 0:0a673c671a56 558 {
ebrus 0:0a673c671a56 559 /* Set the ADVREGEN bit 1 */
ebrus 0:0a673c671a56 560 ADCx->CR |=ADC_CR_ADVREGEN_1;
ebrus 0:0a673c671a56 561 }
ebrus 0:0a673c671a56 562 }
ebrus 0:0a673c671a56 563
ebrus 0:0a673c671a56 564 /**
ebrus 0:0a673c671a56 565 * @brief Selectes the differential mode for a specific channel
ebrus 0:0a673c671a56 566 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 567 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
ebrus 0:0a673c671a56 568 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 569 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 570 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 571 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 572 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 573 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 574 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 575 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 576 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 577 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 578 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 579 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 580 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 581 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 582 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 583 * @note : Channel 15, 16 and 17 are fixed to single-ended inputs mode.
ebrus 0:0a673c671a56 584 * @retval None
ebrus 0:0a673c671a56 585 */
ebrus 0:0a673c671a56 586 void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState)
ebrus 0:0a673c671a56 587 {
ebrus 0:0a673c671a56 588 /* Check the parameters */
ebrus 0:0a673c671a56 589 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 590 assert_param(IS_ADC_DIFFCHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 591 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593 if (NewState != DISABLE)
ebrus 0:0a673c671a56 594 {
ebrus 0:0a673c671a56 595 /* Set the DIFSEL bit */
ebrus 0:0a673c671a56 596 ADCx->DIFSEL |= (uint32_t)(1 << ADC_Channel );
ebrus 0:0a673c671a56 597 }
ebrus 0:0a673c671a56 598 else
ebrus 0:0a673c671a56 599 {
ebrus 0:0a673c671a56 600 /* Reset the DIFSEL bit */
ebrus 0:0a673c671a56 601 ADCx->DIFSEL &= ~(uint32_t)(1 << ADC_Channel);
ebrus 0:0a673c671a56 602 }
ebrus 0:0a673c671a56 603 }
ebrus 0:0a673c671a56 604
ebrus 0:0a673c671a56 605 /**
ebrus 0:0a673c671a56 606 * @brief Selects the Queue Of Context Mode for injected channels.
ebrus 0:0a673c671a56 607 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 608 * @param NewState: new state of the Queue Of Context Mode.
ebrus 0:0a673c671a56 609 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 610 * @retval None
ebrus 0:0a673c671a56 611 */
ebrus 0:0a673c671a56 612 void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 613 {
ebrus 0:0a673c671a56 614 /* Check the parameters */
ebrus 0:0a673c671a56 615 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 616 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 617
ebrus 0:0a673c671a56 618 if (NewState != DISABLE)
ebrus 0:0a673c671a56 619 {
ebrus 0:0a673c671a56 620 /* Set the JQM bit */
ebrus 0:0a673c671a56 621 ADCx->CFGR |= (uint32_t)(ADC_CFGR_JQM );
ebrus 0:0a673c671a56 622 }
ebrus 0:0a673c671a56 623 else
ebrus 0:0a673c671a56 624 {
ebrus 0:0a673c671a56 625 /* Reset the JQM bit */
ebrus 0:0a673c671a56 626 ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_JQM);
ebrus 0:0a673c671a56 627 }
ebrus 0:0a673c671a56 628 }
ebrus 0:0a673c671a56 629
ebrus 0:0a673c671a56 630 /**
ebrus 0:0a673c671a56 631 * @brief Selects the ADC Delayed Conversion Mode.
ebrus 0:0a673c671a56 632 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 633 * @param NewState: new state of the ADC Delayed Conversion Mode.
ebrus 0:0a673c671a56 634 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 635 * @retval None
ebrus 0:0a673c671a56 636 */
ebrus 0:0a673c671a56 637 void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 638 {
ebrus 0:0a673c671a56 639 /* Check the parameters */
ebrus 0:0a673c671a56 640 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 641 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 642
ebrus 0:0a673c671a56 643 if (NewState != DISABLE)
ebrus 0:0a673c671a56 644 {
ebrus 0:0a673c671a56 645 /* Set the AUTDLY bit */
ebrus 0:0a673c671a56 646 ADCx->CFGR |= (uint32_t)(ADC_CFGR_AUTDLY );
ebrus 0:0a673c671a56 647 }
ebrus 0:0a673c671a56 648 else
ebrus 0:0a673c671a56 649 {
ebrus 0:0a673c671a56 650 /* Reset the AUTDLY bit */
ebrus 0:0a673c671a56 651 ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_AUTDLY);
ebrus 0:0a673c671a56 652 }
ebrus 0:0a673c671a56 653 }
ebrus 0:0a673c671a56 654
ebrus 0:0a673c671a56 655 /**
ebrus 0:0a673c671a56 656 * @}
ebrus 0:0a673c671a56 657 */
ebrus 0:0a673c671a56 658
ebrus 0:0a673c671a56 659 /** @defgroup ADC_Group2 Analog Watchdog configuration functions
ebrus 0:0a673c671a56 660 * @brief Analog Watchdog configuration functions
ebrus 0:0a673c671a56 661 *
ebrus 0:0a673c671a56 662 @verbatim
ebrus 0:0a673c671a56 663 ===============================================================================
ebrus 0:0a673c671a56 664 ##### Analog Watchdog configuration functions #####
ebrus 0:0a673c671a56 665 ===============================================================================
ebrus 0:0a673c671a56 666
ebrus 0:0a673c671a56 667 [..] This section provides functions allowing to configure the 3 Analog Watchdogs
ebrus 0:0a673c671a56 668 (AWDG1, AWDG2 and AWDG3) in the ADC.
ebrus 0:0a673c671a56 669
ebrus 0:0a673c671a56 670 [..] A typical configuration Analog Watchdog is done following these steps :
ebrus 0:0a673c671a56 671 (#) The ADC guarded channel(s) is (are) selected using the functions:
ebrus 0:0a673c671a56 672 (++) ADC_AnalogWatchdog1SingleChannelConfig().
ebrus 0:0a673c671a56 673 (++) ADC_AnalogWatchdog2SingleChannelConfig().
ebrus 0:0a673c671a56 674 (++) ADC_AnalogWatchdog3SingleChannelConfig().
ebrus 0:0a673c671a56 675
ebrus 0:0a673c671a56 676 (#) The Analog watchdog lower and higher threshold are configured using the functions:
ebrus 0:0a673c671a56 677 (++) ADC_AnalogWatchdog1ThresholdsConfig().
ebrus 0:0a673c671a56 678 (++) ADC_AnalogWatchdog2ThresholdsConfig().
ebrus 0:0a673c671a56 679 (++) ADC_AnalogWatchdog3ThresholdsConfig().
ebrus 0:0a673c671a56 680
ebrus 0:0a673c671a56 681 (#) The Analog watchdog is enabled and configured to enable the check, on one
ebrus 0:0a673c671a56 682 or more channels, using the function:
ebrus 0:0a673c671a56 683 (++) ADC_AnalogWatchdogCmd().
ebrus 0:0a673c671a56 684
ebrus 0:0a673c671a56 685 @endverbatim
ebrus 0:0a673c671a56 686 * @{
ebrus 0:0a673c671a56 687 */
ebrus 0:0a673c671a56 688
ebrus 0:0a673c671a56 689 /**
ebrus 0:0a673c671a56 690 * @brief Enables or disables the analog watchdog on single/all regular
ebrus 0:0a673c671a56 691 * or injected channels
ebrus 0:0a673c671a56 692 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 693 * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
ebrus 0:0a673c671a56 694 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 695 * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
ebrus 0:0a673c671a56 696 * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
ebrus 0:0a673c671a56 697 * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
ebrus 0:0a673c671a56 698 * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
ebrus 0:0a673c671a56 699 * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
ebrus 0:0a673c671a56 700 * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
ebrus 0:0a673c671a56 701 * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
ebrus 0:0a673c671a56 702 * @retval None
ebrus 0:0a673c671a56 703 */
ebrus 0:0a673c671a56 704 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
ebrus 0:0a673c671a56 705 {
ebrus 0:0a673c671a56 706 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 707 /* Check the parameters */
ebrus 0:0a673c671a56 708 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 709 assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
ebrus 0:0a673c671a56 710 /* Get the old register value */
ebrus 0:0a673c671a56 711 tmpreg = ADCx->CFGR;
ebrus 0:0a673c671a56 712 /* Clear AWDEN, AWDENJ and AWDSGL bits */
ebrus 0:0a673c671a56 713 tmpreg &= ~(uint32_t)(ADC_CFGR_AWD1SGL|ADC_CFGR_AWD1EN|ADC_CFGR_JAWD1EN);
ebrus 0:0a673c671a56 714 /* Set the analog watchdog enable mode */
ebrus 0:0a673c671a56 715 tmpreg |= ADC_AnalogWatchdog;
ebrus 0:0a673c671a56 716 /* Store the new register value */
ebrus 0:0a673c671a56 717 ADCx->CFGR = tmpreg;
ebrus 0:0a673c671a56 718 }
ebrus 0:0a673c671a56 719
ebrus 0:0a673c671a56 720 /**
ebrus 0:0a673c671a56 721 * @brief Configures the high and low thresholds of the analog watchdog1.
ebrus 0:0a673c671a56 722 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 723 * @param HighThreshold: the ADC analog watchdog High threshold value.
ebrus 0:0a673c671a56 724 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 725 * @param LowThreshold: the ADC analog watchdog Low threshold value.
ebrus 0:0a673c671a56 726 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 727 * @retval None
ebrus 0:0a673c671a56 728 */
ebrus 0:0a673c671a56 729 void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
ebrus 0:0a673c671a56 730 uint16_t LowThreshold)
ebrus 0:0a673c671a56 731 {
ebrus 0:0a673c671a56 732 /* Check the parameters */
ebrus 0:0a673c671a56 733 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 734 assert_param(IS_ADC_THRESHOLD(HighThreshold));
ebrus 0:0a673c671a56 735 assert_param(IS_ADC_THRESHOLD(LowThreshold));
ebrus 0:0a673c671a56 736 /* Set the ADCx high threshold */
ebrus 0:0a673c671a56 737 ADCx->TR1 &= ~(uint32_t)ADC_TR1_HT1;
ebrus 0:0a673c671a56 738 ADCx->TR1 |= (uint32_t)((uint32_t)HighThreshold << 16);
ebrus 0:0a673c671a56 739
ebrus 0:0a673c671a56 740 /* Set the ADCx low threshold */
ebrus 0:0a673c671a56 741 ADCx->TR1 &= ~(uint32_t)ADC_TR1_LT1;
ebrus 0:0a673c671a56 742 ADCx->TR1 |= LowThreshold;
ebrus 0:0a673c671a56 743 }
ebrus 0:0a673c671a56 744
ebrus 0:0a673c671a56 745 /**
ebrus 0:0a673c671a56 746 * @brief Configures the high and low thresholds of the analog watchdog2.
ebrus 0:0a673c671a56 747 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 748 * @param HighThreshold: the ADC analog watchdog High threshold value.
ebrus 0:0a673c671a56 749 * This parameter must be a 8bit value.
ebrus 0:0a673c671a56 750 * @param LowThreshold: the ADC analog watchdog Low threshold value.
ebrus 0:0a673c671a56 751 * This parameter must be a 8bit value.
ebrus 0:0a673c671a56 752 * @retval None
ebrus 0:0a673c671a56 753 */
ebrus 0:0a673c671a56 754 void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
ebrus 0:0a673c671a56 755 uint8_t LowThreshold)
ebrus 0:0a673c671a56 756 {
ebrus 0:0a673c671a56 757 /* Check the parameters */
ebrus 0:0a673c671a56 758 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 759
ebrus 0:0a673c671a56 760 /* Set the ADCx high threshold */
ebrus 0:0a673c671a56 761 ADCx->TR2 &= ~(uint32_t)ADC_TR2_HT2;
ebrus 0:0a673c671a56 762 ADCx->TR2 |= (uint32_t)((uint32_t)HighThreshold << 16);
ebrus 0:0a673c671a56 763
ebrus 0:0a673c671a56 764 /* Set the ADCx low threshold */
ebrus 0:0a673c671a56 765 ADCx->TR2 &= ~(uint32_t)ADC_TR2_LT2;
ebrus 0:0a673c671a56 766 ADCx->TR2 |= LowThreshold;
ebrus 0:0a673c671a56 767 }
ebrus 0:0a673c671a56 768
ebrus 0:0a673c671a56 769 /**
ebrus 0:0a673c671a56 770 * @brief Configures the high and low thresholds of the analog watchdog3.
ebrus 0:0a673c671a56 771 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 772 * @param HighThreshold: the ADC analog watchdog High threshold value.
ebrus 0:0a673c671a56 773 * This parameter must be a 8bit value.
ebrus 0:0a673c671a56 774 * @param LowThreshold: the ADC analog watchdog Low threshold value.
ebrus 0:0a673c671a56 775 * This parameter must be a 8bit value.
ebrus 0:0a673c671a56 776 * @retval None
ebrus 0:0a673c671a56 777 */
ebrus 0:0a673c671a56 778 void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
ebrus 0:0a673c671a56 779 uint8_t LowThreshold)
ebrus 0:0a673c671a56 780 {
ebrus 0:0a673c671a56 781 /* Check the parameters */
ebrus 0:0a673c671a56 782 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 783
ebrus 0:0a673c671a56 784 /* Set the ADCx high threshold */
ebrus 0:0a673c671a56 785 ADCx->TR3 &= ~(uint32_t)ADC_TR3_HT3;
ebrus 0:0a673c671a56 786 ADCx->TR3 |= (uint32_t)((uint32_t)HighThreshold << 16);
ebrus 0:0a673c671a56 787
ebrus 0:0a673c671a56 788 /* Set the ADCx low threshold */
ebrus 0:0a673c671a56 789 ADCx->TR3 &= ~(uint32_t)ADC_TR3_LT3;
ebrus 0:0a673c671a56 790 ADCx->TR3 |= LowThreshold;
ebrus 0:0a673c671a56 791 }
ebrus 0:0a673c671a56 792
ebrus 0:0a673c671a56 793 /**
ebrus 0:0a673c671a56 794 * @brief Configures the analog watchdog 2 guarded single channel
ebrus 0:0a673c671a56 795 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 796 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
ebrus 0:0a673c671a56 797 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 798 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 799 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 800 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 801 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 802 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 803 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 804 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 805 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 806 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 807 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 808 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 809 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 810 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 811 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 812 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 813 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 814 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 815 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 816 * @retval None
ebrus 0:0a673c671a56 817 */
ebrus 0:0a673c671a56 818 void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
ebrus 0:0a673c671a56 819 {
ebrus 0:0a673c671a56 820 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 821 /* Check the parameters */
ebrus 0:0a673c671a56 822 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 823 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 824 /* Get the old register value */
ebrus 0:0a673c671a56 825 tmpreg = ADCx->CFGR;
ebrus 0:0a673c671a56 826 /* Clear the Analog watchdog channel select bits */
ebrus 0:0a673c671a56 827 tmpreg &= ~(uint32_t)ADC_CFGR_AWD1CH;
ebrus 0:0a673c671a56 828 /* Set the Analog watchdog channel */
ebrus 0:0a673c671a56 829 tmpreg |= (uint32_t)((uint32_t)ADC_Channel << 26);
ebrus 0:0a673c671a56 830 /* Store the new register value */
ebrus 0:0a673c671a56 831 ADCx->CFGR = tmpreg;
ebrus 0:0a673c671a56 832 }
ebrus 0:0a673c671a56 833
ebrus 0:0a673c671a56 834 /**
ebrus 0:0a673c671a56 835 * @brief Configures the analog watchdog 2 guarded single channel
ebrus 0:0a673c671a56 836 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 837 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
ebrus 0:0a673c671a56 838 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 839 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 840 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 841 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 842 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 843 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 844 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 845 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 846 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 847 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 848 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 849 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 850 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 851 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 852 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 853 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 854 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 855 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 856 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 857 * @retval None
ebrus 0:0a673c671a56 858 */
ebrus 0:0a673c671a56 859 void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
ebrus 0:0a673c671a56 860 {
ebrus 0:0a673c671a56 861 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 862 /* Check the parameters */
ebrus 0:0a673c671a56 863 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 864 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 865 /* Get the old register value */
ebrus 0:0a673c671a56 866 tmpreg = ADCx->AWD2CR;
ebrus 0:0a673c671a56 867 /* Clear the Analog watchdog channel select bits */
ebrus 0:0a673c671a56 868 tmpreg &= ~(uint32_t)ADC_AWD2CR_AWD2CH;
ebrus 0:0a673c671a56 869 /* Set the Analog watchdog channel */
ebrus 0:0a673c671a56 870 tmpreg |= (uint32_t)1 << (ADC_Channel);
ebrus 0:0a673c671a56 871 /* Store the new register value */
ebrus 0:0a673c671a56 872 ADCx->AWD2CR |= tmpreg;
ebrus 0:0a673c671a56 873 }
ebrus 0:0a673c671a56 874
ebrus 0:0a673c671a56 875 /**
ebrus 0:0a673c671a56 876 * @brief Configures the analog watchdog 3 guarded single channel
ebrus 0:0a673c671a56 877 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 878 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
ebrus 0:0a673c671a56 879 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 880 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 881 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 882 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 883 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 884 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 885 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 886 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 887 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 888 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 889 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 890 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 891 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 892 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 893 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 894 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 895 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 896 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 897 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 898 * @retval None
ebrus 0:0a673c671a56 899 */
ebrus 0:0a673c671a56 900 void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
ebrus 0:0a673c671a56 901 {
ebrus 0:0a673c671a56 902 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 903 /* Check the parameters */
ebrus 0:0a673c671a56 904 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 905 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 906 /* Get the old register value */
ebrus 0:0a673c671a56 907 tmpreg = ADCx->AWD3CR;
ebrus 0:0a673c671a56 908 /* Clear the Analog watchdog channel select bits */
ebrus 0:0a673c671a56 909 tmpreg &= ~(uint32_t)ADC_AWD3CR_AWD3CH;
ebrus 0:0a673c671a56 910 /* Set the Analog watchdog channel */
ebrus 0:0a673c671a56 911 tmpreg |= (uint32_t)1 << (ADC_Channel);
ebrus 0:0a673c671a56 912 /* Store the new register value */
ebrus 0:0a673c671a56 913 ADCx->AWD3CR |= tmpreg;
ebrus 0:0a673c671a56 914 }
ebrus 0:0a673c671a56 915
ebrus 0:0a673c671a56 916 /**
ebrus 0:0a673c671a56 917 * @}
ebrus 0:0a673c671a56 918 */
ebrus 0:0a673c671a56 919
ebrus 0:0a673c671a56 920 /** @defgroup ADC_Group3 Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions
ebrus 0:0a673c671a56 921 * @brief Vbat, Temperature Sensor & Vrefint (Internal Reference Voltage) management function
ebrus 0:0a673c671a56 922 *
ebrus 0:0a673c671a56 923 @verbatim
ebrus 0:0a673c671a56 924 ====================================================================================================
ebrus 0:0a673c671a56 925 ##### Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions #####
ebrus 0:0a673c671a56 926 ====================================================================================================
ebrus 0:0a673c671a56 927
ebrus 0:0a673c671a56 928 [..] This section provides a function allowing to enable/ disable the internal
ebrus 0:0a673c671a56 929 connections between the ADC and the Vbat/2, Temperature Sensor and the Vrefint source.
ebrus 0:0a673c671a56 930
ebrus 0:0a673c671a56 931 [..] A typical configuration to get the Temperature sensor and Vrefint channels
ebrus 0:0a673c671a56 932 voltages is done following these steps :
ebrus 0:0a673c671a56 933 (#) Enable the internal connection of Vbat/2, Temperature sensor and Vrefint sources
ebrus 0:0a673c671a56 934 with the ADC channels using:
ebrus 0:0a673c671a56 935 (++) ADC_TempSensorCmd()
ebrus 0:0a673c671a56 936 (++) ADC_VrefintCmd()
ebrus 0:0a673c671a56 937 (++) ADC_VbatCmd()
ebrus 0:0a673c671a56 938
ebrus 0:0a673c671a56 939 (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint and/or ADC_Channel_Vbat using
ebrus 0:0a673c671a56 940 (++) ADC_RegularChannelConfig() or
ebrus 0:0a673c671a56 941 (++) ADC_InjectedInit() functions
ebrus 0:0a673c671a56 942
ebrus 0:0a673c671a56 943 (#) Get the voltage values, using:
ebrus 0:0a673c671a56 944 (++) ADC_GetConversionValue() or
ebrus 0:0a673c671a56 945 (++) ADC_GetInjectedConversionValue().
ebrus 0:0a673c671a56 946
ebrus 0:0a673c671a56 947 @endverbatim
ebrus 0:0a673c671a56 948 * @{
ebrus 0:0a673c671a56 949 */
ebrus 0:0a673c671a56 950
ebrus 0:0a673c671a56 951 /**
ebrus 0:0a673c671a56 952 * @brief Enables or disables the temperature sensor channel.
ebrus 0:0a673c671a56 953 * @param ADCx: where x can be 1 to select the ADC peripheral.
ebrus 0:0a673c671a56 954 * @param NewState: new state of the temperature sensor.
ebrus 0:0a673c671a56 955 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 956 * @retval None
ebrus 0:0a673c671a56 957 */
ebrus 0:0a673c671a56 958 void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 959 {
ebrus 0:0a673c671a56 960 /* Check the parameters */
ebrus 0:0a673c671a56 961 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 962
ebrus 0:0a673c671a56 963 if (NewState != DISABLE)
ebrus 0:0a673c671a56 964 {
ebrus 0:0a673c671a56 965 /* Enable the temperature sensor channel*/
ebrus 0:0a673c671a56 966 ADC1_2->CCR |= ADC12_CCR_TSEN;
ebrus 0:0a673c671a56 967 }
ebrus 0:0a673c671a56 968 else
ebrus 0:0a673c671a56 969 {
ebrus 0:0a673c671a56 970 /* Disable the temperature sensor channel*/
ebrus 0:0a673c671a56 971 ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_TSEN;
ebrus 0:0a673c671a56 972 }
ebrus 0:0a673c671a56 973 }
ebrus 0:0a673c671a56 974
ebrus 0:0a673c671a56 975 /**
ebrus 0:0a673c671a56 976 * @brief Enables or disables the Vrefint channel.
ebrus 0:0a673c671a56 977 * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 978 * @param NewState: new state of the Vrefint.
ebrus 0:0a673c671a56 979 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 980 * @retval None
ebrus 0:0a673c671a56 981 */
ebrus 0:0a673c671a56 982 void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 983 {
ebrus 0:0a673c671a56 984 /* Check the parameters */
ebrus 0:0a673c671a56 985 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 986 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 987
ebrus 0:0a673c671a56 988 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 989 {
ebrus 0:0a673c671a56 990 if (NewState != DISABLE)
ebrus 0:0a673c671a56 991 {
ebrus 0:0a673c671a56 992 /* Enable the Vrefint channel*/
ebrus 0:0a673c671a56 993 ADC1_2->CCR |= ADC12_CCR_VREFEN;
ebrus 0:0a673c671a56 994 }
ebrus 0:0a673c671a56 995 else
ebrus 0:0a673c671a56 996 {
ebrus 0:0a673c671a56 997 /* Disable the Vrefint channel*/
ebrus 0:0a673c671a56 998 ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VREFEN;
ebrus 0:0a673c671a56 999 }
ebrus 0:0a673c671a56 1000 }
ebrus 0:0a673c671a56 1001 else
ebrus 0:0a673c671a56 1002 {
ebrus 0:0a673c671a56 1003 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1004 {
ebrus 0:0a673c671a56 1005 /* Enable the Vrefint channel*/
ebrus 0:0a673c671a56 1006 ADC3_4->CCR |= ADC34_CCR_VREFEN;
ebrus 0:0a673c671a56 1007 }
ebrus 0:0a673c671a56 1008 else
ebrus 0:0a673c671a56 1009 {
ebrus 0:0a673c671a56 1010 /* Disable the Vrefint channel*/
ebrus 0:0a673c671a56 1011 ADC3_4->CCR &= ~(uint32_t)ADC34_CCR_VREFEN;
ebrus 0:0a673c671a56 1012 }
ebrus 0:0a673c671a56 1013 }
ebrus 0:0a673c671a56 1014 }
ebrus 0:0a673c671a56 1015
ebrus 0:0a673c671a56 1016 /**
ebrus 0:0a673c671a56 1017 * @brief Enables or disables the Vbat channel.
ebrus 0:0a673c671a56 1018 * @param ADCx: where x can be 1 to select the ADC peripheral.
ebrus 0:0a673c671a56 1019 * @param NewState: new state of the Vbat.
ebrus 0:0a673c671a56 1020 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1021 * @retval None
ebrus 0:0a673c671a56 1022 */
ebrus 0:0a673c671a56 1023 void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1024 {
ebrus 0:0a673c671a56 1025 /* Check the parameters */
ebrus 0:0a673c671a56 1026 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1027
ebrus 0:0a673c671a56 1028 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1029 {
ebrus 0:0a673c671a56 1030 /* Enable the Vbat channel*/
ebrus 0:0a673c671a56 1031 ADC1_2->CCR |= ADC12_CCR_VBATEN;
ebrus 0:0a673c671a56 1032 }
ebrus 0:0a673c671a56 1033 else
ebrus 0:0a673c671a56 1034 {
ebrus 0:0a673c671a56 1035 /* Disable the Vbat channel*/
ebrus 0:0a673c671a56 1036 ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VBATEN;
ebrus 0:0a673c671a56 1037 }
ebrus 0:0a673c671a56 1038 }
ebrus 0:0a673c671a56 1039
ebrus 0:0a673c671a56 1040 /**
ebrus 0:0a673c671a56 1041 * @}
ebrus 0:0a673c671a56 1042 */
ebrus 0:0a673c671a56 1043
ebrus 0:0a673c671a56 1044 /** @defgroup ADC_Group4 Regular Channels Configuration functions
ebrus 0:0a673c671a56 1045 * @brief Regular Channels Configuration functions
ebrus 0:0a673c671a56 1046 *
ebrus 0:0a673c671a56 1047 @verbatim
ebrus 0:0a673c671a56 1048 ===============================================================================
ebrus 0:0a673c671a56 1049 ##### Channels Configuration functions #####
ebrus 0:0a673c671a56 1050 ===============================================================================
ebrus 0:0a673c671a56 1051
ebrus 0:0a673c671a56 1052 [..] This section provides functions allowing to manage the ADC regular channels.
ebrus 0:0a673c671a56 1053
ebrus 0:0a673c671a56 1054 [..] To configure a regular sequence of channels use:
ebrus 0:0a673c671a56 1055 (#) ADC_RegularChannelConfig()
ebrus 0:0a673c671a56 1056 this fuction allows:
ebrus 0:0a673c671a56 1057 (++) Configure the rank in the regular group sequencer for each channel
ebrus 0:0a673c671a56 1058 (++) Configure the sampling time for each channel
ebrus 0:0a673c671a56 1059
ebrus 0:0a673c671a56 1060 (#) ADC_RegularChannelSequencerLengthConfig() to set the length of the regular sequencer
ebrus 0:0a673c671a56 1061
ebrus 0:0a673c671a56 1062 [..] The regular trigger is configured using the following functions:
ebrus 0:0a673c671a56 1063 (#) ADC_SelectExternalTrigger()
ebrus 0:0a673c671a56 1064 (#) ADC_ExternalTriggerPolarityConfig()
ebrus 0:0a673c671a56 1065
ebrus 0:0a673c671a56 1066 [..] The start and the stop conversion are controlled by:
ebrus 0:0a673c671a56 1067 (#) ADC_StartConversion()
ebrus 0:0a673c671a56 1068 (#) ADC_StopConversion()
ebrus 0:0a673c671a56 1069
ebrus 0:0a673c671a56 1070 [..]
ebrus 0:0a673c671a56 1071 (@)Please Note that the following features for regular channels are configurated
ebrus 0:0a673c671a56 1072 using the ADC_Init() function :
ebrus 0:0a673c671a56 1073 (++) continuous mode activation
ebrus 0:0a673c671a56 1074 (++) Resolution
ebrus 0:0a673c671a56 1075 (++) Data Alignement
ebrus 0:0a673c671a56 1076 (++) Overrun Mode.
ebrus 0:0a673c671a56 1077
ebrus 0:0a673c671a56 1078 [..] Get the conversion data: This subsection provides an important function in
ebrus 0:0a673c671a56 1079 the ADC peripheral since it returns the converted data of the current
ebrus 0:0a673c671a56 1080 regular channel. When the Conversion value is read, the EOC Flag is
ebrus 0:0a673c671a56 1081 automatically cleared.
ebrus 0:0a673c671a56 1082
ebrus 0:0a673c671a56 1083 [..] To configure the discontinous mode, the following functions should be used:
ebrus 0:0a673c671a56 1084 (#) ADC_DiscModeChannelCountConfig() to configure the number of discontinuous channel to be converted.
ebrus 0:0a673c671a56 1085 (#) ADC_DiscModeCmd() to enable the discontinuous mode.
ebrus 0:0a673c671a56 1086
ebrus 0:0a673c671a56 1087 [..] To configure and enable/disable the Channel offset use the functions:
ebrus 0:0a673c671a56 1088 (++) ADC_SetChannelOffset1()
ebrus 0:0a673c671a56 1089 (++) ADC_SetChannelOffset2()
ebrus 0:0a673c671a56 1090 (++) ADC_SetChannelOffset3()
ebrus 0:0a673c671a56 1091 (++) ADC_SetChannelOffset4()
ebrus 0:0a673c671a56 1092 (++) ADC_ChannelOffset1Cmd()
ebrus 0:0a673c671a56 1093 (++) ADC_ChannelOffset2Cmd()
ebrus 0:0a673c671a56 1094 (++) ADC_ChannelOffset3Cmd()
ebrus 0:0a673c671a56 1095 (++) ADC_ChannelOffset4Cmd()
ebrus 0:0a673c671a56 1096
ebrus 0:0a673c671a56 1097 @endverbatim
ebrus 0:0a673c671a56 1098 * @{
ebrus 0:0a673c671a56 1099 */
ebrus 0:0a673c671a56 1100
ebrus 0:0a673c671a56 1101 /**
ebrus 0:0a673c671a56 1102 * @brief Configures for the selected ADC regular channel its corresponding
ebrus 0:0a673c671a56 1103 * rank in the sequencer and its sample time.
ebrus 0:0a673c671a56 1104 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1105 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1106 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1107 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1108 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1109 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1110 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1111 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1112 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1113 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1114 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1115 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1116 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1117 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1118 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1119 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1120 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1121 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1122 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1123 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1124 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1125 * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
ebrus 0:0a673c671a56 1126 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
ebrus 0:0a673c671a56 1127 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1128 * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
ebrus 0:0a673c671a56 1129 * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
ebrus 0:0a673c671a56 1130 * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
ebrus 0:0a673c671a56 1131 * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
ebrus 0:0a673c671a56 1132 * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
ebrus 0:0a673c671a56 1133 * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
ebrus 0:0a673c671a56 1134 * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
ebrus 0:0a673c671a56 1135 * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
ebrus 0:0a673c671a56 1136 * @retval None
ebrus 0:0a673c671a56 1137 */
ebrus 0:0a673c671a56 1138 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
ebrus 0:0a673c671a56 1139 {
ebrus 0:0a673c671a56 1140 uint32_t tmpreg1 = 0, tmpreg2 = 0;
ebrus 0:0a673c671a56 1141 /* Check the parameters */
ebrus 0:0a673c671a56 1142 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1143 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 1144 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
ebrus 0:0a673c671a56 1145
ebrus 0:0a673c671a56 1146 /* Regular sequence configuration */
ebrus 0:0a673c671a56 1147 /* For Rank 1 to 4 */
ebrus 0:0a673c671a56 1148 if (Rank < 5)
ebrus 0:0a673c671a56 1149 {
ebrus 0:0a673c671a56 1150 /* Get the old register value */
ebrus 0:0a673c671a56 1151 tmpreg1 = ADCx->SQR1;
ebrus 0:0a673c671a56 1152 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1153 tmpreg2 = 0x1F << (6 * (Rank ));
ebrus 0:0a673c671a56 1154 /* Clear the old SQx bits for the selected rank */
ebrus 0:0a673c671a56 1155 tmpreg1 &= ~tmpreg2;
ebrus 0:0a673c671a56 1156 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1157 tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank));
ebrus 0:0a673c671a56 1158 /* Set the SQx bits for the selected rank */
ebrus 0:0a673c671a56 1159 tmpreg1 |= tmpreg2;
ebrus 0:0a673c671a56 1160 /* Store the new register value */
ebrus 0:0a673c671a56 1161 ADCx->SQR1 = tmpreg1;
ebrus 0:0a673c671a56 1162 }
ebrus 0:0a673c671a56 1163 /* For Rank 5 to 9 */
ebrus 0:0a673c671a56 1164 else if (Rank < 10)
ebrus 0:0a673c671a56 1165 {
ebrus 0:0a673c671a56 1166 /* Get the old register value */
ebrus 0:0a673c671a56 1167 tmpreg1 = ADCx->SQR2;
ebrus 0:0a673c671a56 1168 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1169 tmpreg2 = ADC_SQR2_SQ5 << (6 * (Rank - 5));
ebrus 0:0a673c671a56 1170 /* Clear the old SQx bits for the selected rank */
ebrus 0:0a673c671a56 1171 tmpreg1 &= ~tmpreg2;
ebrus 0:0a673c671a56 1172 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1173 tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 5));
ebrus 0:0a673c671a56 1174 /* Set the SQx bits for the selected rank */
ebrus 0:0a673c671a56 1175 tmpreg1 |= tmpreg2;
ebrus 0:0a673c671a56 1176 /* Store the new register value */
ebrus 0:0a673c671a56 1177 ADCx->SQR2 = tmpreg1;
ebrus 0:0a673c671a56 1178 }
ebrus 0:0a673c671a56 1179 /* For Rank 10 to 14 */
ebrus 0:0a673c671a56 1180 else if (Rank < 15)
ebrus 0:0a673c671a56 1181 {
ebrus 0:0a673c671a56 1182 /* Get the old register value */
ebrus 0:0a673c671a56 1183 tmpreg1 = ADCx->SQR3;
ebrus 0:0a673c671a56 1184 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1185 tmpreg2 = ADC_SQR3_SQ10 << (6 * (Rank - 10));
ebrus 0:0a673c671a56 1186 /* Clear the old SQx bits for the selected rank */
ebrus 0:0a673c671a56 1187 tmpreg1 &= ~tmpreg2;
ebrus 0:0a673c671a56 1188 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1189 tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 10));
ebrus 0:0a673c671a56 1190 /* Set the SQx bits for the selected rank */
ebrus 0:0a673c671a56 1191 tmpreg1 |= tmpreg2;
ebrus 0:0a673c671a56 1192 /* Store the new register value */
ebrus 0:0a673c671a56 1193 ADCx->SQR3 = tmpreg1;
ebrus 0:0a673c671a56 1194 }
ebrus 0:0a673c671a56 1195 else
ebrus 0:0a673c671a56 1196 {
ebrus 0:0a673c671a56 1197 /* Get the old register value */
ebrus 0:0a673c671a56 1198 tmpreg1 = ADCx->SQR4;
ebrus 0:0a673c671a56 1199 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1200 tmpreg2 = ADC_SQR3_SQ15 << (6 * (Rank - 15));
ebrus 0:0a673c671a56 1201 /* Clear the old SQx bits for the selected rank */
ebrus 0:0a673c671a56 1202 tmpreg1 &= ~tmpreg2;
ebrus 0:0a673c671a56 1203 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1204 tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 15));
ebrus 0:0a673c671a56 1205 /* Set the SQx bits for the selected rank */
ebrus 0:0a673c671a56 1206 tmpreg1 |= tmpreg2;
ebrus 0:0a673c671a56 1207 /* Store the new register value */
ebrus 0:0a673c671a56 1208 ADCx->SQR4 = tmpreg1;
ebrus 0:0a673c671a56 1209 }
ebrus 0:0a673c671a56 1210
ebrus 0:0a673c671a56 1211 /* Channel sampling configuration */
ebrus 0:0a673c671a56 1212 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
ebrus 0:0a673c671a56 1213 if (ADC_Channel > ADC_Channel_9)
ebrus 0:0a673c671a56 1214 {
ebrus 0:0a673c671a56 1215 /* Get the old register value */
ebrus 0:0a673c671a56 1216 tmpreg1 = ADCx->SMPR2;
ebrus 0:0a673c671a56 1217 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1218 tmpreg2 = ADC_SMPR2_SMP10 << (3 * (ADC_Channel - 10));
ebrus 0:0a673c671a56 1219 /* Clear the old channel sample time */
ebrus 0:0a673c671a56 1220 ADCx->SMPR2 &= ~tmpreg2;
ebrus 0:0a673c671a56 1221 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1222 ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
ebrus 0:0a673c671a56 1223
ebrus 0:0a673c671a56 1224 }
ebrus 0:0a673c671a56 1225 else /* ADC_Channel include in ADC_Channel_[0..9] */
ebrus 0:0a673c671a56 1226 {
ebrus 0:0a673c671a56 1227 /* Get the old register value */
ebrus 0:0a673c671a56 1228 tmpreg1 = ADCx->SMPR1;
ebrus 0:0a673c671a56 1229 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1230 tmpreg2 = ADC_SMPR1_SMP1 << (3 * (ADC_Channel - 1));
ebrus 0:0a673c671a56 1231 /* Clear the old channel sample time */
ebrus 0:0a673c671a56 1232 ADCx->SMPR1 &= ~tmpreg2;
ebrus 0:0a673c671a56 1233 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1234 ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel));
ebrus 0:0a673c671a56 1235 }
ebrus 0:0a673c671a56 1236 }
ebrus 0:0a673c671a56 1237
ebrus 0:0a673c671a56 1238 /**
ebrus 0:0a673c671a56 1239 * @brief Sets the ADC regular channel sequence lenght.
ebrus 0:0a673c671a56 1240 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
ebrus 0:0a673c671a56 1241 * @param SequenceLength: The Regular sequence length. This parameter must be between 1 to 16.
ebrus 0:0a673c671a56 1242 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1243 * @retval None
ebrus 0:0a673c671a56 1244 */
ebrus 0:0a673c671a56 1245 void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength)
ebrus 0:0a673c671a56 1246 {
ebrus 0:0a673c671a56 1247 /* Check the parameters */
ebrus 0:0a673c671a56 1248 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1249
ebrus 0:0a673c671a56 1250 /* Configure the ADC sequence lenght */
ebrus 0:0a673c671a56 1251 ADCx->SQR1 &= ~(uint32_t)ADC_SQR1_L;
ebrus 0:0a673c671a56 1252 ADCx->SQR1 |= (uint32_t)(SequencerLength - 1);
ebrus 0:0a673c671a56 1253 }
ebrus 0:0a673c671a56 1254
ebrus 0:0a673c671a56 1255 /**
ebrus 0:0a673c671a56 1256 * @brief External Trigger Enable and Polarity Selection for regular channels.
ebrus 0:0a673c671a56 1257 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1258 * @param ADC_ExternalTrigConvEvent: ADC external Trigger source.
ebrus 0:0a673c671a56 1259 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1260 * @arg ADC_ExternalTrigger_Event0: External trigger event 0
ebrus 0:0a673c671a56 1261 * @arg ADC_ExternalTrigger_Event1: External trigger event 1
ebrus 0:0a673c671a56 1262 * @arg ADC_ExternalTrigger_Event2: External trigger event 2
ebrus 0:0a673c671a56 1263 * @arg ADC_ExternalTrigger_Event3: External trigger event 3
ebrus 0:0a673c671a56 1264 * @arg ADC_ExternalTrigger_Event4: External trigger event 4
ebrus 0:0a673c671a56 1265 * @arg ADC_ExternalTrigger_Event5: External trigger event 5
ebrus 0:0a673c671a56 1266 * @arg ADC_ExternalTrigger_Event6: External trigger event 6
ebrus 0:0a673c671a56 1267 * @arg ADC_ExternalTrigger_Event7: External trigger event 7
ebrus 0:0a673c671a56 1268 * @arg ADC_ExternalTrigger_Event8: External trigger event 8
ebrus 0:0a673c671a56 1269 * @arg ADC_ExternalTrigger_Event9: External trigger event 9
ebrus 0:0a673c671a56 1270 * @arg ADC_ExternalTrigger_Event10: External trigger event 10
ebrus 0:0a673c671a56 1271 * @arg ADC_ExternalTrigger_Event11: External trigger event 11
ebrus 0:0a673c671a56 1272 * @arg ADC_ExternalTrigger_Event12: External trigger event 12
ebrus 0:0a673c671a56 1273 * @arg ADC_ExternalTrigger_Event13: External trigger event 13
ebrus 0:0a673c671a56 1274 * @arg ADC_ExternalTrigger_Event14: External trigger event 14
ebrus 0:0a673c671a56 1275 * @arg ADC_ExternalTrigger_Event15: External trigger event 15
ebrus 0:0a673c671a56 1276 * @param ADC_ExternalTrigEventEdge: ADC external Trigger Polarity.
ebrus 0:0a673c671a56 1277 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1278 * @arg ADC_ExternalTrigEventEdge_OFF: Hardware trigger detection disabled
ebrus 0:0a673c671a56 1279 * (conversions can be launched by software)
ebrus 0:0a673c671a56 1280 * @arg ADC_ExternalTrigEventEdge_RisingEdge: Hardware trigger detection on the rising edge
ebrus 0:0a673c671a56 1281 * @arg ADC_ExternalTrigEventEdge_FallingEdge: Hardware trigger detection on the falling edge
ebrus 0:0a673c671a56 1282 * @arg ADC_ExternalTrigEventEdge_BothEdge: Hardware trigger detection on both the rising and falling edges
ebrus 0:0a673c671a56 1283 * @retval None
ebrus 0:0a673c671a56 1284 */
ebrus 0:0a673c671a56 1285 void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge)
ebrus 0:0a673c671a56 1286 {
ebrus 0:0a673c671a56 1287 /* Check the parameters */
ebrus 0:0a673c671a56 1288 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1289 assert_param(IS_ADC_EXT_TRIG(ADC_ExternalTrigConvEvent));
ebrus 0:0a673c671a56 1290 assert_param(IS_EXTERNALTRIG_EDGE(ADC_ExternalTrigEventEdge));
ebrus 0:0a673c671a56 1291
ebrus 0:0a673c671a56 1292 /* Disable the selected ADC conversion on external event */
ebrus 0:0a673c671a56 1293 ADCx->CFGR &= ~(ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
ebrus 0:0a673c671a56 1294 ADCx->CFGR |= (uint32_t)(ADC_ExternalTrigEventEdge | ADC_ExternalTrigConvEvent);
ebrus 0:0a673c671a56 1295 }
ebrus 0:0a673c671a56 1296
ebrus 0:0a673c671a56 1297 /**
ebrus 0:0a673c671a56 1298 * @brief Enables or disables the selected ADC start conversion .
ebrus 0:0a673c671a56 1299 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1300 * @retval None
ebrus 0:0a673c671a56 1301 */
ebrus 0:0a673c671a56 1302 void ADC_StartConversion(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1303 {
ebrus 0:0a673c671a56 1304 /* Check the parameters */
ebrus 0:0a673c671a56 1305 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1306
ebrus 0:0a673c671a56 1307 /* Set the ADSTART bit */
ebrus 0:0a673c671a56 1308 ADCx->CR |= ADC_CR_ADSTART;
ebrus 0:0a673c671a56 1309 }
ebrus 0:0a673c671a56 1310
ebrus 0:0a673c671a56 1311 /**
ebrus 0:0a673c671a56 1312 * @brief Gets the selected ADC start conversion Status.
ebrus 0:0a673c671a56 1313 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1314 * @retval The new state of ADC start conversion (SET or RESET).
ebrus 0:0a673c671a56 1315 */
ebrus 0:0a673c671a56 1316 FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1317 {
ebrus 0:0a673c671a56 1318 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 1319 /* Check the parameters */
ebrus 0:0a673c671a56 1320 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1321 /* Check the status of ADSTART bit */
ebrus 0:0a673c671a56 1322 if ((ADCx->CR & ADC_CR_ADSTART) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1323 {
ebrus 0:0a673c671a56 1324 /* ADSTART bit is set */
ebrus 0:0a673c671a56 1325 bitstatus = SET;
ebrus 0:0a673c671a56 1326 }
ebrus 0:0a673c671a56 1327 else
ebrus 0:0a673c671a56 1328 {
ebrus 0:0a673c671a56 1329 /* ADSTART bit is reset */
ebrus 0:0a673c671a56 1330 bitstatus = RESET;
ebrus 0:0a673c671a56 1331 }
ebrus 0:0a673c671a56 1332 /* Return the ADSTART bit status */
ebrus 0:0a673c671a56 1333 return bitstatus;
ebrus 0:0a673c671a56 1334 }
ebrus 0:0a673c671a56 1335
ebrus 0:0a673c671a56 1336 /**
ebrus 0:0a673c671a56 1337 * @brief Stops the selected ADC ongoing conversion.
ebrus 0:0a673c671a56 1338 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1339 * @retval None
ebrus 0:0a673c671a56 1340 */
ebrus 0:0a673c671a56 1341 void ADC_StopConversion(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1342 {
ebrus 0:0a673c671a56 1343 /* Check the parameters */
ebrus 0:0a673c671a56 1344 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1345
ebrus 0:0a673c671a56 1346 /* Set the ADSTP bit */
ebrus 0:0a673c671a56 1347 ADCx->CR |= ADC_CR_ADSTP;
ebrus 0:0a673c671a56 1348 }
ebrus 0:0a673c671a56 1349
ebrus 0:0a673c671a56 1350
ebrus 0:0a673c671a56 1351 /**
ebrus 0:0a673c671a56 1352 * @brief Configures the discontinuous mode for the selected ADC regular
ebrus 0:0a673c671a56 1353 * group channel.
ebrus 0:0a673c671a56 1354 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1355 * @param Number: specifies the discontinuous mode regular channel
ebrus 0:0a673c671a56 1356 * count value. This number must be between 1 and 8.
ebrus 0:0a673c671a56 1357 * @retval None
ebrus 0:0a673c671a56 1358 */
ebrus 0:0a673c671a56 1359 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
ebrus 0:0a673c671a56 1360 {
ebrus 0:0a673c671a56 1361 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 1362 uint32_t tmpreg2 = 0;
ebrus 0:0a673c671a56 1363 /* Check the parameters */
ebrus 0:0a673c671a56 1364 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1365 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
ebrus 0:0a673c671a56 1366 /* Get the old register value */
ebrus 0:0a673c671a56 1367 tmpreg1 = ADCx->CFGR;
ebrus 0:0a673c671a56 1368 /* Clear the old discontinuous mode channel count */
ebrus 0:0a673c671a56 1369 tmpreg1 &= ~(uint32_t)(ADC_CFGR_DISCNUM);
ebrus 0:0a673c671a56 1370 /* Set the discontinuous mode channel count */
ebrus 0:0a673c671a56 1371 tmpreg2 = Number - 1;
ebrus 0:0a673c671a56 1372 tmpreg1 |= tmpreg2 << 17;
ebrus 0:0a673c671a56 1373 /* Store the new register value */
ebrus 0:0a673c671a56 1374 ADCx->CFGR = tmpreg1;
ebrus 0:0a673c671a56 1375 }
ebrus 0:0a673c671a56 1376
ebrus 0:0a673c671a56 1377 /**
ebrus 0:0a673c671a56 1378 * @brief Enables or disables the discontinuous mode on regular group
ebrus 0:0a673c671a56 1379 * channel for the specified ADC
ebrus 0:0a673c671a56 1380 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1381 * @param NewState: new state of the selected ADC discontinuous mode
ebrus 0:0a673c671a56 1382 * on regular group channel.
ebrus 0:0a673c671a56 1383 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1384 * @retval None
ebrus 0:0a673c671a56 1385 */
ebrus 0:0a673c671a56 1386 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1387 {
ebrus 0:0a673c671a56 1388 /* Check the parameters */
ebrus 0:0a673c671a56 1389 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1390 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1391 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1392 {
ebrus 0:0a673c671a56 1393 /* Enable the selected ADC regular discontinuous mode */
ebrus 0:0a673c671a56 1394 ADCx->CFGR |= ADC_CFGR_DISCEN;
ebrus 0:0a673c671a56 1395 }
ebrus 0:0a673c671a56 1396 else
ebrus 0:0a673c671a56 1397 {
ebrus 0:0a673c671a56 1398 /* Disable the selected ADC regular discontinuous mode */
ebrus 0:0a673c671a56 1399 ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_DISCEN);
ebrus 0:0a673c671a56 1400 }
ebrus 0:0a673c671a56 1401 }
ebrus 0:0a673c671a56 1402
ebrus 0:0a673c671a56 1403 /**
ebrus 0:0a673c671a56 1404 * @brief Returns the last ADCx conversion result data for regular channel.
ebrus 0:0a673c671a56 1405 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1406 * @retval The Data conversion value.
ebrus 0:0a673c671a56 1407 */
ebrus 0:0a673c671a56 1408 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1409 {
ebrus 0:0a673c671a56 1410 /* Check the parameters */
ebrus 0:0a673c671a56 1411 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1412 /* Return the selected ADC conversion value */
ebrus 0:0a673c671a56 1413 return (uint16_t) ADCx->DR;
ebrus 0:0a673c671a56 1414 }
ebrus 0:0a673c671a56 1415
ebrus 0:0a673c671a56 1416 /**
ebrus 0:0a673c671a56 1417 * @brief Returns the last ADC1, ADC2, ADC3 and ADC4 regular conversions results
ebrus 0:0a673c671a56 1418 * data in the selected dual mode.
ebrus 0:0a673c671a56 1419 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1420 * @retval The Data conversion value.
ebrus 0:0a673c671a56 1421 * @note In dual mode, the value returned by this function is as following
ebrus 0:0a673c671a56 1422 * Data[15:0] : these bits contain the regular data of the Master ADC.
ebrus 0:0a673c671a56 1423 * Data[31:16]: these bits contain the regular data of the Slave ADC.
ebrus 0:0a673c671a56 1424 */
ebrus 0:0a673c671a56 1425 uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1426 {
ebrus 0:0a673c671a56 1427 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 1428
ebrus 0:0a673c671a56 1429 /* Check the parameters */
ebrus 0:0a673c671a56 1430 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1431
ebrus 0:0a673c671a56 1432 if((ADCx == ADC1) || (ADCx== ADC2))
ebrus 0:0a673c671a56 1433 {
ebrus 0:0a673c671a56 1434 /* Get the dual mode conversion value */
ebrus 0:0a673c671a56 1435 tmpreg1 = ADC1_2->CDR;
ebrus 0:0a673c671a56 1436 }
ebrus 0:0a673c671a56 1437 else
ebrus 0:0a673c671a56 1438 {
ebrus 0:0a673c671a56 1439 /* Get the dual mode conversion value */
ebrus 0:0a673c671a56 1440 tmpreg1 = ADC3_4->CDR;
ebrus 0:0a673c671a56 1441 }
ebrus 0:0a673c671a56 1442 /* Return the dual mode conversion value */
ebrus 0:0a673c671a56 1443 return (uint32_t) tmpreg1;
ebrus 0:0a673c671a56 1444 }
ebrus 0:0a673c671a56 1445
ebrus 0:0a673c671a56 1446 /**
ebrus 0:0a673c671a56 1447 * @brief Set the ADC channels conversion value offset1
ebrus 0:0a673c671a56 1448 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1449 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1450 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1451 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1452 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1453 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1454 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1455 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1456 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1457 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1458 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1459 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1460 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1461 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1462 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1463 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1464 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1465 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1466 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1467 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1468 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1469 * @param Offset: the offset value for the selected ADC Channel
ebrus 0:0a673c671a56 1470 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 1471 * @retval None
ebrus 0:0a673c671a56 1472 */
ebrus 0:0a673c671a56 1473 void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
ebrus 0:0a673c671a56 1474 {
ebrus 0:0a673c671a56 1475 /* Check the parameters */
ebrus 0:0a673c671a56 1476 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1477 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 1478 assert_param(IS_ADC_OFFSET(Offset));
ebrus 0:0a673c671a56 1479
ebrus 0:0a673c671a56 1480 /* Select the Channel */
ebrus 0:0a673c671a56 1481 ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1_CH;
ebrus 0:0a673c671a56 1482 ADCx->OFR1 |= (uint32_t)((uint32_t)ADC_Channel << 26);
ebrus 0:0a673c671a56 1483
ebrus 0:0a673c671a56 1484 /* Set the data offset */
ebrus 0:0a673c671a56 1485 ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1;
ebrus 0:0a673c671a56 1486 ADCx->OFR1 |= (uint32_t)Offset;
ebrus 0:0a673c671a56 1487 }
ebrus 0:0a673c671a56 1488
ebrus 0:0a673c671a56 1489 /**
ebrus 0:0a673c671a56 1490 * @brief Set the ADC channels conversion value offset2
ebrus 0:0a673c671a56 1491 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1492 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1493 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1494 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1495 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1496 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1497 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1498 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1499 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1500 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1501 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1502 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1503 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1504 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1505 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1506 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1507 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1508 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1509 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1510 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1511 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1512 * @param Offset: the offset value for the selected ADC Channel
ebrus 0:0a673c671a56 1513 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 1514 * @retval None
ebrus 0:0a673c671a56 1515 */
ebrus 0:0a673c671a56 1516 void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
ebrus 0:0a673c671a56 1517 {
ebrus 0:0a673c671a56 1518 /* Check the parameters */
ebrus 0:0a673c671a56 1519 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1520 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 1521 assert_param(IS_ADC_OFFSET(Offset));
ebrus 0:0a673c671a56 1522
ebrus 0:0a673c671a56 1523 /* Select the Channel */
ebrus 0:0a673c671a56 1524 ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2_CH;
ebrus 0:0a673c671a56 1525 ADCx->OFR2 |= (uint32_t)((uint32_t)ADC_Channel << 26);
ebrus 0:0a673c671a56 1526
ebrus 0:0a673c671a56 1527 /* Set the data offset */
ebrus 0:0a673c671a56 1528 ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2;
ebrus 0:0a673c671a56 1529 ADCx->OFR2 |= (uint32_t)Offset;
ebrus 0:0a673c671a56 1530 }
ebrus 0:0a673c671a56 1531
ebrus 0:0a673c671a56 1532 /**
ebrus 0:0a673c671a56 1533 * @brief Set the ADC channels conversion value offset3
ebrus 0:0a673c671a56 1534 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1535 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1536 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1537 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1538 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1539 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1540 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1541 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1542 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1543 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1544 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1545 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1546 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1547 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1548 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1549 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1550 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1551 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1552 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1553 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1554 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1555 * @param Offset: the offset value for the selected ADC Channel
ebrus 0:0a673c671a56 1556 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 1557 * @retval None
ebrus 0:0a673c671a56 1558 */
ebrus 0:0a673c671a56 1559 void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
ebrus 0:0a673c671a56 1560 {
ebrus 0:0a673c671a56 1561 /* Check the parameters */
ebrus 0:0a673c671a56 1562 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1563 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 1564 assert_param(IS_ADC_OFFSET(Offset));
ebrus 0:0a673c671a56 1565
ebrus 0:0a673c671a56 1566 /* Select the Channel */
ebrus 0:0a673c671a56 1567 ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3_CH;
ebrus 0:0a673c671a56 1568 ADCx->OFR3 |= (uint32_t)((uint32_t)ADC_Channel << 26);
ebrus 0:0a673c671a56 1569
ebrus 0:0a673c671a56 1570 /* Set the data offset */
ebrus 0:0a673c671a56 1571 ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3;
ebrus 0:0a673c671a56 1572 ADCx->OFR3 |= (uint32_t)Offset;
ebrus 0:0a673c671a56 1573 }
ebrus 0:0a673c671a56 1574
ebrus 0:0a673c671a56 1575 /**
ebrus 0:0a673c671a56 1576 * @brief Set the ADC channels conversion value offset4
ebrus 0:0a673c671a56 1577 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1578 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1579 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1580 * @arg ADC_Channel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1581 * @arg ADC_Channel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1582 * @arg ADC_Channel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1583 * @arg ADC_Channel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1584 * @arg ADC_Channel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1585 * @arg ADC_Channel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1586 * @arg ADC_Channel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1587 * @arg ADC_Channel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1588 * @arg ADC_Channel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1589 * @arg ADC_Channel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1590 * @arg ADC_Channel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1591 * @arg ADC_Channel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1592 * @arg ADC_Channel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1593 * @arg ADC_Channel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1594 * @arg ADC_Channel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1595 * @arg ADC_Channel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1596 * @arg ADC_Channel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1597 * @arg ADC_Channel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1598 * @param Offset: the offset value for the selected ADC Channel
ebrus 0:0a673c671a56 1599 * This parameter must be a 12bit value.
ebrus 0:0a673c671a56 1600 * @retval None
ebrus 0:0a673c671a56 1601 */
ebrus 0:0a673c671a56 1602 void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
ebrus 0:0a673c671a56 1603 {
ebrus 0:0a673c671a56 1604 /* Check the parameters */
ebrus 0:0a673c671a56 1605 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1606 assert_param(IS_ADC_CHANNEL(ADC_Channel));
ebrus 0:0a673c671a56 1607 assert_param(IS_ADC_OFFSET(Offset));
ebrus 0:0a673c671a56 1608
ebrus 0:0a673c671a56 1609 /* Select the Channel */
ebrus 0:0a673c671a56 1610 ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4_CH;
ebrus 0:0a673c671a56 1611 ADCx->OFR4 |= (uint32_t)((uint32_t)ADC_Channel << 26);
ebrus 0:0a673c671a56 1612
ebrus 0:0a673c671a56 1613 /* Set the data offset */
ebrus 0:0a673c671a56 1614 ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4;
ebrus 0:0a673c671a56 1615 ADCx->OFR4 |= (uint32_t)Offset;
ebrus 0:0a673c671a56 1616 }
ebrus 0:0a673c671a56 1617
ebrus 0:0a673c671a56 1618 /**
ebrus 0:0a673c671a56 1619 * @brief Enables or disables the Offset1.
ebrus 0:0a673c671a56 1620 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1621 * @param NewState: new state of the ADCx offset1.
ebrus 0:0a673c671a56 1622 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1623 * @retval None
ebrus 0:0a673c671a56 1624 */
ebrus 0:0a673c671a56 1625 void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1626 {
ebrus 0:0a673c671a56 1627 /* Check the parameters */
ebrus 0:0a673c671a56 1628 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1629 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1630
ebrus 0:0a673c671a56 1631 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1632 {
ebrus 0:0a673c671a56 1633 /* Set the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1634 ADCx->OFR1 |= ADC_OFR1_OFFSET1_EN;
ebrus 0:0a673c671a56 1635 }
ebrus 0:0a673c671a56 1636 else
ebrus 0:0a673c671a56 1637 {
ebrus 0:0a673c671a56 1638 /* Reset the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1639 ADCx->OFR1 &= ~(ADC_OFR1_OFFSET1_EN);
ebrus 0:0a673c671a56 1640 }
ebrus 0:0a673c671a56 1641 }
ebrus 0:0a673c671a56 1642
ebrus 0:0a673c671a56 1643 /**
ebrus 0:0a673c671a56 1644 * @brief Enables or disables the Offset2.
ebrus 0:0a673c671a56 1645 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1646 * @param NewState: new state of the ADCx offset2.
ebrus 0:0a673c671a56 1647 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1648 * @retval None
ebrus 0:0a673c671a56 1649 */
ebrus 0:0a673c671a56 1650 void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1651 {
ebrus 0:0a673c671a56 1652 /* Check the parameters */
ebrus 0:0a673c671a56 1653 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1654 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1655
ebrus 0:0a673c671a56 1656 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1657 {
ebrus 0:0a673c671a56 1658 /* Set the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1659 ADCx->OFR2 |= ADC_OFR2_OFFSET2_EN;
ebrus 0:0a673c671a56 1660 }
ebrus 0:0a673c671a56 1661 else
ebrus 0:0a673c671a56 1662 {
ebrus 0:0a673c671a56 1663 /* Reset the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1664 ADCx->OFR2 &= ~(ADC_OFR2_OFFSET2_EN);
ebrus 0:0a673c671a56 1665 }
ebrus 0:0a673c671a56 1666 }
ebrus 0:0a673c671a56 1667
ebrus 0:0a673c671a56 1668 /**
ebrus 0:0a673c671a56 1669 * @brief Enables or disables the Offset3.
ebrus 0:0a673c671a56 1670 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1671 * @param NewState: new state of the ADCx offset3.
ebrus 0:0a673c671a56 1672 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1673 * @retval None
ebrus 0:0a673c671a56 1674 */
ebrus 0:0a673c671a56 1675 void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1676 {
ebrus 0:0a673c671a56 1677 /* Check the parameters */
ebrus 0:0a673c671a56 1678 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1679 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1680
ebrus 0:0a673c671a56 1681 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1682 {
ebrus 0:0a673c671a56 1683 /* Set the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1684 ADCx->OFR3 |= ADC_OFR3_OFFSET3_EN;
ebrus 0:0a673c671a56 1685 }
ebrus 0:0a673c671a56 1686 else
ebrus 0:0a673c671a56 1687 {
ebrus 0:0a673c671a56 1688 /* Reset the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1689 ADCx->OFR3 &= ~(ADC_OFR3_OFFSET3_EN);
ebrus 0:0a673c671a56 1690 }
ebrus 0:0a673c671a56 1691 }
ebrus 0:0a673c671a56 1692
ebrus 0:0a673c671a56 1693 /**
ebrus 0:0a673c671a56 1694 * @brief Enables or disables the Offset4.
ebrus 0:0a673c671a56 1695 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1696 * @param NewState: new state of the ADCx offset4.
ebrus 0:0a673c671a56 1697 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1698 * @retval None
ebrus 0:0a673c671a56 1699 */
ebrus 0:0a673c671a56 1700 void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1701 {
ebrus 0:0a673c671a56 1702 /* Check the parameters */
ebrus 0:0a673c671a56 1703 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1704 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1705
ebrus 0:0a673c671a56 1706 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1707 {
ebrus 0:0a673c671a56 1708 /* Set the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1709 ADCx->OFR4 |= ADC_OFR4_OFFSET4_EN;
ebrus 0:0a673c671a56 1710 }
ebrus 0:0a673c671a56 1711 else
ebrus 0:0a673c671a56 1712 {
ebrus 0:0a673c671a56 1713 /* Reset the OFFSET1_EN bit */
ebrus 0:0a673c671a56 1714 ADCx->OFR4 &= ~(ADC_OFR4_OFFSET4_EN);
ebrus 0:0a673c671a56 1715 }
ebrus 0:0a673c671a56 1716 }
ebrus 0:0a673c671a56 1717
ebrus 0:0a673c671a56 1718 /**
ebrus 0:0a673c671a56 1719 * @}
ebrus 0:0a673c671a56 1720 */
ebrus 0:0a673c671a56 1721
ebrus 0:0a673c671a56 1722 /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
ebrus 0:0a673c671a56 1723 * @brief Regular Channels DMA Configuration functions
ebrus 0:0a673c671a56 1724 *
ebrus 0:0a673c671a56 1725 @verbatim
ebrus 0:0a673c671a56 1726 ===============================================================================
ebrus 0:0a673c671a56 1727 ##### Regular Channels DMA Configuration functions #####
ebrus 0:0a673c671a56 1728 ===============================================================================
ebrus 0:0a673c671a56 1729
ebrus 0:0a673c671a56 1730 [..] This section provides functions allowing to configure the DMA for ADC regular
ebrus 0:0a673c671a56 1731 channels. Since converted regular channel values are stored into a unique data register,
ebrus 0:0a673c671a56 1732 it is useful to use DMA for conversion of more than one regular channel. This
ebrus 0:0a673c671a56 1733 avoids the loss of the data already stored in the ADC Data register.
ebrus 0:0a673c671a56 1734
ebrus 0:0a673c671a56 1735 (#) ADC_DMACmd() function is used to enable the ADC DMA mode, after each
ebrus 0:0a673c671a56 1736 conversion of a regular channel, a DMA request is generated.
ebrus 0:0a673c671a56 1737 (#) ADC_DMAConfig() function is used to select between the one shot DMA mode
ebrus 0:0a673c671a56 1738 or the circular DMA mode
ebrus 0:0a673c671a56 1739
ebrus 0:0a673c671a56 1740 @endverbatim
ebrus 0:0a673c671a56 1741 * @{
ebrus 0:0a673c671a56 1742 */
ebrus 0:0a673c671a56 1743
ebrus 0:0a673c671a56 1744 /**
ebrus 0:0a673c671a56 1745 * @brief Enables or disables the specified ADC DMA request.
ebrus 0:0a673c671a56 1746 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1747 * @param NewState: new state of the selected ADC DMA transfer.
ebrus 0:0a673c671a56 1748 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1749 * @retval None
ebrus 0:0a673c671a56 1750 */
ebrus 0:0a673c671a56 1751 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1752 {
ebrus 0:0a673c671a56 1753 /* Check the parameters */
ebrus 0:0a673c671a56 1754 assert_param(IS_ADC_DMA_PERIPH(ADCx));
ebrus 0:0a673c671a56 1755 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1756 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1757 {
ebrus 0:0a673c671a56 1758 /* Enable the selected ADC DMA request */
ebrus 0:0a673c671a56 1759 ADCx->CFGR |= ADC_CFGR_DMAEN;
ebrus 0:0a673c671a56 1760 }
ebrus 0:0a673c671a56 1761 else
ebrus 0:0a673c671a56 1762 {
ebrus 0:0a673c671a56 1763 /* Disable the selected ADC DMA request */
ebrus 0:0a673c671a56 1764 ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMAEN;
ebrus 0:0a673c671a56 1765 }
ebrus 0:0a673c671a56 1766 }
ebrus 0:0a673c671a56 1767
ebrus 0:0a673c671a56 1768 /**
ebrus 0:0a673c671a56 1769 * @brief Configure ADC DMA mode.
ebrus 0:0a673c671a56 1770 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1771 * @param ADC_DMAMode: select the ADC DMA mode.
ebrus 0:0a673c671a56 1772 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1773 * @arg ADC_DMAMode_OneShot: ADC DMA Oneshot mode
ebrus 0:0a673c671a56 1774 * @arg ADC_DMAMode_Circular: ADC DMA circular mode
ebrus 0:0a673c671a56 1775 * @retval None
ebrus 0:0a673c671a56 1776 */
ebrus 0:0a673c671a56 1777 void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode)
ebrus 0:0a673c671a56 1778 {
ebrus 0:0a673c671a56 1779 /* Check the parameters */
ebrus 0:0a673c671a56 1780 assert_param(IS_ADC_DMA_PERIPH(ADCx));
ebrus 0:0a673c671a56 1781 assert_param(IS_ADC_DMA_MODE(ADC_DMAMode));
ebrus 0:0a673c671a56 1782
ebrus 0:0a673c671a56 1783 /* Set or reset the DMACFG bit */
ebrus 0:0a673c671a56 1784 ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMACFG;
ebrus 0:0a673c671a56 1785 ADCx->CFGR |= ADC_DMAMode;
ebrus 0:0a673c671a56 1786 }
ebrus 0:0a673c671a56 1787
ebrus 0:0a673c671a56 1788 /**
ebrus 0:0a673c671a56 1789 * @}
ebrus 0:0a673c671a56 1790 */
ebrus 0:0a673c671a56 1791
ebrus 0:0a673c671a56 1792 /** @defgroup ADC_Group6 Injected channels Configuration functions
ebrus 0:0a673c671a56 1793 * @brief Injected channels Configuration functions
ebrus 0:0a673c671a56 1794 *
ebrus 0:0a673c671a56 1795 @verbatim
ebrus 0:0a673c671a56 1796 ===============================================================================
ebrus 0:0a673c671a56 1797 ##### Injected channels Configuration functions #####
ebrus 0:0a673c671a56 1798 ===============================================================================
ebrus 0:0a673c671a56 1799
ebrus 0:0a673c671a56 1800 [..] This section provide functions allowing to manage the ADC Injected channels,
ebrus 0:0a673c671a56 1801 it is composed of :
ebrus 0:0a673c671a56 1802
ebrus 0:0a673c671a56 1803 (#) Configuration functions for Injected channels sample time
ebrus 0:0a673c671a56 1804 (#) Functions to start and stop the injected conversion
ebrus 0:0a673c671a56 1805 (#) unction to select the discontinuous mode
ebrus 0:0a673c671a56 1806 (#) Function to get the Specified Injected channel conversion data: This subsection
ebrus 0:0a673c671a56 1807 provides an important function in the ADC peripheral since it returns the
ebrus 0:0a673c671a56 1808 converted data of the specific injected channel.
ebrus 0:0a673c671a56 1809
ebrus 0:0a673c671a56 1810 @endverbatim
ebrus 0:0a673c671a56 1811 * @{
ebrus 0:0a673c671a56 1812 */
ebrus 0:0a673c671a56 1813
ebrus 0:0a673c671a56 1814 /**
ebrus 0:0a673c671a56 1815 * @brief Configures for the selected ADC injected channel its corresponding
ebrus 0:0a673c671a56 1816 * sample time.
ebrus 0:0a673c671a56 1817 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1818 * @param ADC_Channel: the ADC channel to configure.
ebrus 0:0a673c671a56 1819 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1820 * @arg ADC_InjectedChannel_1: ADC Channel1 selected
ebrus 0:0a673c671a56 1821 * @arg ADC_InjectedChannel_2: ADC Channel2 selected
ebrus 0:0a673c671a56 1822 * @arg ADC_InjectedChannel_3: ADC Channel3 selected
ebrus 0:0a673c671a56 1823 * @arg ADC_InjectedChannel_4: ADC Channel4 selected
ebrus 0:0a673c671a56 1824 * @arg ADC_InjectedChannel_5: ADC Channel5 selected
ebrus 0:0a673c671a56 1825 * @arg ADC_InjectedChannel_6: ADC Channel6 selected
ebrus 0:0a673c671a56 1826 * @arg ADC_InjectedChannel_7: ADC Channel7 selected
ebrus 0:0a673c671a56 1827 * @arg ADC_InjectedChannel_8: ADC Channel8 selected
ebrus 0:0a673c671a56 1828 * @arg ADC_InjectedChannel_9: ADC Channel9 selected
ebrus 0:0a673c671a56 1829 * @arg ADC_InjectedChannel_10: ADC Channel10 selected
ebrus 0:0a673c671a56 1830 * @arg ADC_InjectedChannel_11: ADC Channel11 selected
ebrus 0:0a673c671a56 1831 * @arg ADC_InjectedChannel_12: ADC Channel12 selected
ebrus 0:0a673c671a56 1832 * @arg ADC_InjectedChannel_13: ADC Channel13 selected
ebrus 0:0a673c671a56 1833 * @arg ADC_InjectedChannel_14: ADC Channel14 selected
ebrus 0:0a673c671a56 1834 * @arg ADC_InjectedChannel_15: ADC Channel15 selected
ebrus 0:0a673c671a56 1835 * @arg ADC_InjectedChannel_16: ADC Channel16 selected
ebrus 0:0a673c671a56 1836 * @arg ADC_InjectedChannel_17: ADC Channel17 selected
ebrus 0:0a673c671a56 1837 * @arg ADC_InjectedChannel_18: ADC Channel18 selected
ebrus 0:0a673c671a56 1838 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
ebrus 0:0a673c671a56 1839 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1840 * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
ebrus 0:0a673c671a56 1841 * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
ebrus 0:0a673c671a56 1842 * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
ebrus 0:0a673c671a56 1843 * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
ebrus 0:0a673c671a56 1844 * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
ebrus 0:0a673c671a56 1845 * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
ebrus 0:0a673c671a56 1846 * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
ebrus 0:0a673c671a56 1847 * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
ebrus 0:0a673c671a56 1848 * @retval None
ebrus 0:0a673c671a56 1849 */
ebrus 0:0a673c671a56 1850 void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime)
ebrus 0:0a673c671a56 1851 {
ebrus 0:0a673c671a56 1852 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 1853 /* Check the parameters */
ebrus 0:0a673c671a56 1854 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1855 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
ebrus 0:0a673c671a56 1856 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
ebrus 0:0a673c671a56 1857
ebrus 0:0a673c671a56 1858 /* Channel sampling configuration */
ebrus 0:0a673c671a56 1859 /* if ADC_InjectedChannel_10 ... ADC_InjectedChannel_18 is selected */
ebrus 0:0a673c671a56 1860 if (ADC_InjectedChannel > ADC_InjectedChannel_9)
ebrus 0:0a673c671a56 1861 {
ebrus 0:0a673c671a56 1862 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1863 tmpreg1 = ADC_SMPR2_SMP10 << (3 * (ADC_InjectedChannel - 10));
ebrus 0:0a673c671a56 1864 /* Clear the old channel sample time */
ebrus 0:0a673c671a56 1865 ADCx->SMPR2 &= ~tmpreg1;
ebrus 0:0a673c671a56 1866 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1867 ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel - 10));
ebrus 0:0a673c671a56 1868
ebrus 0:0a673c671a56 1869 }
ebrus 0:0a673c671a56 1870 else /* ADC_InjectedChannel include in ADC_InjectedChannel_[0..9] */
ebrus 0:0a673c671a56 1871 {
ebrus 0:0a673c671a56 1872 /* Calculate the mask to clear */
ebrus 0:0a673c671a56 1873 tmpreg1 = ADC_SMPR1_SMP1 << (3 * (ADC_InjectedChannel - 1));
ebrus 0:0a673c671a56 1874 /* Clear the old channel sample time */
ebrus 0:0a673c671a56 1875 ADCx->SMPR1 &= ~tmpreg1;
ebrus 0:0a673c671a56 1876 /* Calculate the mask to set */
ebrus 0:0a673c671a56 1877 ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel));
ebrus 0:0a673c671a56 1878 }
ebrus 0:0a673c671a56 1879 }
ebrus 0:0a673c671a56 1880
ebrus 0:0a673c671a56 1881 /**
ebrus 0:0a673c671a56 1882 * @brief Enables or disables the selected ADC start of the injected
ebrus 0:0a673c671a56 1883 * channels conversion.
ebrus 0:0a673c671a56 1884 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1885 * @param NewState: new state of the selected ADC software start injected conversion.
ebrus 0:0a673c671a56 1886 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1887 * @retval None
ebrus 0:0a673c671a56 1888 */
ebrus 0:0a673c671a56 1889 void ADC_StartInjectedConversion(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1890 {
ebrus 0:0a673c671a56 1891 /* Check the parameters */
ebrus 0:0a673c671a56 1892 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1893
ebrus 0:0a673c671a56 1894 /* Enable the selected ADC conversion for injected group on external event and start the selected
ebrus 0:0a673c671a56 1895 ADC injected conversion */
ebrus 0:0a673c671a56 1896 ADCx->CR |= ADC_CR_JADSTART;
ebrus 0:0a673c671a56 1897 }
ebrus 0:0a673c671a56 1898
ebrus 0:0a673c671a56 1899 /**
ebrus 0:0a673c671a56 1900 * @brief Stops the selected ADC ongoing injected conversion.
ebrus 0:0a673c671a56 1901 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1902 * @retval None
ebrus 0:0a673c671a56 1903 */
ebrus 0:0a673c671a56 1904 void ADC_StopInjectedConversion(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1905 {
ebrus 0:0a673c671a56 1906 /* Check the parameters */
ebrus 0:0a673c671a56 1907 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1908
ebrus 0:0a673c671a56 1909 /* Set the JADSTP bit */
ebrus 0:0a673c671a56 1910 ADCx->CR |= ADC_CR_JADSTP;
ebrus 0:0a673c671a56 1911 }
ebrus 0:0a673c671a56 1912
ebrus 0:0a673c671a56 1913 /**
ebrus 0:0a673c671a56 1914 * @brief Gets the selected ADC Software start injected conversion Status.
ebrus 0:0a673c671a56 1915 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1916 * @retval The new state of ADC start injected conversion (SET or RESET).
ebrus 0:0a673c671a56 1917 */
ebrus 0:0a673c671a56 1918 FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx)
ebrus 0:0a673c671a56 1919 {
ebrus 0:0a673c671a56 1920 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 1921 /* Check the parameters */
ebrus 0:0a673c671a56 1922 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1923
ebrus 0:0a673c671a56 1924 /* Check the status of JADSTART bit */
ebrus 0:0a673c671a56 1925 if ((ADCx->CR & ADC_CR_JADSTART) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1926 {
ebrus 0:0a673c671a56 1927 /* JADSTART bit is set */
ebrus 0:0a673c671a56 1928 bitstatus = SET;
ebrus 0:0a673c671a56 1929 }
ebrus 0:0a673c671a56 1930 else
ebrus 0:0a673c671a56 1931 {
ebrus 0:0a673c671a56 1932 /* JADSTART bit is reset */
ebrus 0:0a673c671a56 1933 bitstatus = RESET;
ebrus 0:0a673c671a56 1934 }
ebrus 0:0a673c671a56 1935 /* Return the JADSTART bit status */
ebrus 0:0a673c671a56 1936 return bitstatus;
ebrus 0:0a673c671a56 1937 }
ebrus 0:0a673c671a56 1938
ebrus 0:0a673c671a56 1939 /**
ebrus 0:0a673c671a56 1940 * @brief Enables or disables the selected ADC automatic injected group
ebrus 0:0a673c671a56 1941 * conversion after regular one.
ebrus 0:0a673c671a56 1942 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1943 * @param NewState: new state of the selected ADC auto injected conversion
ebrus 0:0a673c671a56 1944 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1945 * @retval None
ebrus 0:0a673c671a56 1946 */
ebrus 0:0a673c671a56 1947 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1948 {
ebrus 0:0a673c671a56 1949 /* Check the parameters */
ebrus 0:0a673c671a56 1950 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1951 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1952 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1953 {
ebrus 0:0a673c671a56 1954 /* Enable the selected ADC automatic injected group conversion */
ebrus 0:0a673c671a56 1955 ADCx->CFGR |= ADC_CFGR_JAUTO;
ebrus 0:0a673c671a56 1956 }
ebrus 0:0a673c671a56 1957 else
ebrus 0:0a673c671a56 1958 {
ebrus 0:0a673c671a56 1959 /* Disable the selected ADC automatic injected group conversion */
ebrus 0:0a673c671a56 1960 ADCx->CFGR &= ~ADC_CFGR_JAUTO;
ebrus 0:0a673c671a56 1961 }
ebrus 0:0a673c671a56 1962 }
ebrus 0:0a673c671a56 1963
ebrus 0:0a673c671a56 1964 /**
ebrus 0:0a673c671a56 1965 * @brief Enables or disables the discontinuous mode for injected group
ebrus 0:0a673c671a56 1966 * channel for the specified ADC
ebrus 0:0a673c671a56 1967 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1968 * @param NewState: new state of the selected ADC discontinuous mode
ebrus 0:0a673c671a56 1969 * on injected group channel.
ebrus 0:0a673c671a56 1970 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1971 * @retval None
ebrus 0:0a673c671a56 1972 */
ebrus 0:0a673c671a56 1973 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
ebrus 0:0a673c671a56 1974 {
ebrus 0:0a673c671a56 1975 /* Check the parameters */
ebrus 0:0a673c671a56 1976 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 1977 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1978 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1979 {
ebrus 0:0a673c671a56 1980 /* Enable the selected ADC injected discontinuous mode */
ebrus 0:0a673c671a56 1981 ADCx->CFGR |= ADC_CFGR_JDISCEN;
ebrus 0:0a673c671a56 1982 }
ebrus 0:0a673c671a56 1983 else
ebrus 0:0a673c671a56 1984 {
ebrus 0:0a673c671a56 1985 /* Disable the selected ADC injected discontinuous mode */
ebrus 0:0a673c671a56 1986 ADCx->CFGR &= ~ADC_CFGR_JDISCEN;
ebrus 0:0a673c671a56 1987 }
ebrus 0:0a673c671a56 1988 }
ebrus 0:0a673c671a56 1989
ebrus 0:0a673c671a56 1990 /**
ebrus 0:0a673c671a56 1991 * @brief Returns the ADC injected channel conversion result
ebrus 0:0a673c671a56 1992 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 1993 * @param ADC_InjectedSequence: the converted ADC injected sequence.
ebrus 0:0a673c671a56 1994 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1995 * @arg ADC_InjectedSequence_1: Injected Sequence1 selected
ebrus 0:0a673c671a56 1996 * @arg ADC_InjectedSequence_2: Injected Sequence2 selected
ebrus 0:0a673c671a56 1997 * @arg ADC_InjectedSequence_3: Injected Sequence3 selected
ebrus 0:0a673c671a56 1998 * @arg ADC_InjectedSequence_4: Injected Sequence4 selected
ebrus 0:0a673c671a56 1999 * @retval The Data conversion value.
ebrus 0:0a673c671a56 2000 */
ebrus 0:0a673c671a56 2001 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedSequence)
ebrus 0:0a673c671a56 2002 {
ebrus 0:0a673c671a56 2003 __IO uint32_t tmp = 0;
ebrus 0:0a673c671a56 2004
ebrus 0:0a673c671a56 2005 /* Check the parameters */
ebrus 0:0a673c671a56 2006 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2007 assert_param(IS_ADC_INJECTED_SEQUENCE(ADC_InjectedSequence));
ebrus 0:0a673c671a56 2008
ebrus 0:0a673c671a56 2009 tmp = (uint32_t)ADCx;
ebrus 0:0a673c671a56 2010 tmp += ((ADC_InjectedSequence - 1 )<< 2) + JDR_Offset;
ebrus 0:0a673c671a56 2011
ebrus 0:0a673c671a56 2012 /* Returns the selected injected channel conversion data value */
ebrus 0:0a673c671a56 2013 return (uint16_t) (*(__IO uint32_t*) tmp);
ebrus 0:0a673c671a56 2014 }
ebrus 0:0a673c671a56 2015
ebrus 0:0a673c671a56 2016 /**
ebrus 0:0a673c671a56 2017 * @}
ebrus 0:0a673c671a56 2018 */
ebrus 0:0a673c671a56 2019
ebrus 0:0a673c671a56 2020 /** @defgroup ADC_Group7 Interrupts and flags management functions
ebrus 0:0a673c671a56 2021 * @brief Interrupts and flags management functions
ebrus 0:0a673c671a56 2022 *
ebrus 0:0a673c671a56 2023 @verbatim
ebrus 0:0a673c671a56 2024 ===============================================================================
ebrus 0:0a673c671a56 2025 ##### Interrupts and flags management functions #####
ebrus 0:0a673c671a56 2026 ===============================================================================
ebrus 0:0a673c671a56 2027
ebrus 0:0a673c671a56 2028 [..] This section provides functions allowing to configure the ADC Interrupts, get
ebrus 0:0a673c671a56 2029 the status and clear flags and Interrupts pending bits.
ebrus 0:0a673c671a56 2030
ebrus 0:0a673c671a56 2031 [..] The ADC provide 11 Interrupts sources and 11 Flags which can be divided into 3 groups:
ebrus 0:0a673c671a56 2032
ebrus 0:0a673c671a56 2033 (#) Flags and Interrupts for ADC regular channels
ebrus 0:0a673c671a56 2034 (##)Flags
ebrus 0:0a673c671a56 2035 (+) ADC_FLAG_RDY: ADC Ready flag
ebrus 0:0a673c671a56 2036 (+) ADC_FLAG_EOSMP: ADC End of Sampling flag
ebrus 0:0a673c671a56 2037 (+) ADC_FLAG_EOC: ADC End of Regular Conversion flag.
ebrus 0:0a673c671a56 2038 (+) ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2039 (+) ADC_FLAG_OVR: ADC overrun flag
ebrus 0:0a673c671a56 2040
ebrus 0:0a673c671a56 2041 (##) Interrupts
ebrus 0:0a673c671a56 2042 (+) ADC_IT_RDY: ADC Ready interrupt source
ebrus 0:0a673c671a56 2043 (+) ADC_IT_EOSMP: ADC End of Sampling interrupt source
ebrus 0:0a673c671a56 2044 (+) ADC_IT_EOC: ADC End of Regular Conversion interrupt source
ebrus 0:0a673c671a56 2045 (+) ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt
ebrus 0:0a673c671a56 2046 (+) ADC_IT_OVR: ADC overrun interrupt source
ebrus 0:0a673c671a56 2047
ebrus 0:0a673c671a56 2048
ebrus 0:0a673c671a56 2049 (#) Flags and Interrupts for ADC regular channels
ebrus 0:0a673c671a56 2050 (##)Flags
ebrus 0:0a673c671a56 2051 (+) ADC_FLAG_JEOC: ADC Ready flag
ebrus 0:0a673c671a56 2052 (+) ADC_FLAG_JEOS: ADC End of Sampling flag
ebrus 0:0a673c671a56 2053 (+) ADC_FLAG_JQOVF: ADC End of Regular Conversion flag.
ebrus 0:0a673c671a56 2054
ebrus 0:0a673c671a56 2055 (##) Interrupts
ebrus 0:0a673c671a56 2056 (+) ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
ebrus 0:0a673c671a56 2057 (+) ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2058 (+) ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
ebrus 0:0a673c671a56 2059
ebrus 0:0a673c671a56 2060 (#) General Flags and Interrupts for the ADC
ebrus 0:0a673c671a56 2061 (##)Flags
ebrus 0:0a673c671a56 2062 (+) ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
ebrus 0:0a673c671a56 2063 (+) ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
ebrus 0:0a673c671a56 2064 (+) ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
ebrus 0:0a673c671a56 2065
ebrus 0:0a673c671a56 2066 (##)Flags
ebrus 0:0a673c671a56 2067 (+) ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
ebrus 0:0a673c671a56 2068 (+) ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
ebrus 0:0a673c671a56 2069 (+) ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
ebrus 0:0a673c671a56 2070
ebrus 0:0a673c671a56 2071 (#) Flags for ADC dual mode
ebrus 0:0a673c671a56 2072 (##)Flags for Master
ebrus 0:0a673c671a56 2073 (+) ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
ebrus 0:0a673c671a56 2074 (+) ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
ebrus 0:0a673c671a56 2075 (+) ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
ebrus 0:0a673c671a56 2076 (+) ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2077 (+) ADC_FLAG_MSTOVR: ADC master overrun flag
ebrus 0:0a673c671a56 2078 (+) ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
ebrus 0:0a673c671a56 2079 (+) ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2080 (+) ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
ebrus 0:0a673c671a56 2081 (+) ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
ebrus 0:0a673c671a56 2082 (+) ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
ebrus 0:0a673c671a56 2083 (+) ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2084
ebrus 0:0a673c671a56 2085 (##) Flags for Slave
ebrus 0:0a673c671a56 2086 (+) ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
ebrus 0:0a673c671a56 2087 (+) ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
ebrus 0:0a673c671a56 2088 (+) ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
ebrus 0:0a673c671a56 2089 (+) ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2090 (+) ADC_FLAG_SLVOVR: ADC slave overrun flag
ebrus 0:0a673c671a56 2091 (+) ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
ebrus 0:0a673c671a56 2092 (+) ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2093 (+) ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
ebrus 0:0a673c671a56 2094 (+) ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
ebrus 0:0a673c671a56 2095 (+) ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
ebrus 0:0a673c671a56 2096 (+) ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2097
ebrus 0:0a673c671a56 2098 The user should identify which mode will be used in his application to manage
ebrus 0:0a673c671a56 2099 the ADC controller events: Polling mode or Interrupt mode.
ebrus 0:0a673c671a56 2100
ebrus 0:0a673c671a56 2101 In the Polling Mode it is advised to use the following functions:
ebrus 0:0a673c671a56 2102 - ADC_GetFlagStatus() : to check if flags events occur.
ebrus 0:0a673c671a56 2103 - ADC_ClearFlag() : to clear the flags events.
ebrus 0:0a673c671a56 2104
ebrus 0:0a673c671a56 2105 In the Interrupt Mode it is advised to use the following functions:
ebrus 0:0a673c671a56 2106 - ADC_ITConfig() : to enable or disable the interrupt source.
ebrus 0:0a673c671a56 2107 - ADC_GetITStatus() : to check if Interrupt occurs.
ebrus 0:0a673c671a56 2108 - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
ebrus 0:0a673c671a56 2109 (corresponding Flag).
ebrus 0:0a673c671a56 2110 @endverbatim
ebrus 0:0a673c671a56 2111 * @{
ebrus 0:0a673c671a56 2112 */
ebrus 0:0a673c671a56 2113
ebrus 0:0a673c671a56 2114 /**
ebrus 0:0a673c671a56 2115 * @brief Enables or disables the specified ADC interrupts.
ebrus 0:0a673c671a56 2116 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
ebrus 0:0a673c671a56 2117 * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
ebrus 0:0a673c671a56 2118 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 2119 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
ebrus 0:0a673c671a56 2120 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
ebrus 0:0a673c671a56 2121 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
ebrus 0:0a673c671a56 2122 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2123 * @arg ADC_IT_OVR: ADC overrun interrupt source
ebrus 0:0a673c671a56 2124 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
ebrus 0:0a673c671a56 2125 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2126 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
ebrus 0:0a673c671a56 2127 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
ebrus 0:0a673c671a56 2128 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
ebrus 0:0a673c671a56 2129 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
ebrus 0:0a673c671a56 2130 * @param NewState: new state of the specified ADC interrupts.
ebrus 0:0a673c671a56 2131 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 2132 * @retval None
ebrus 0:0a673c671a56 2133 */
ebrus 0:0a673c671a56 2134 void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
ebrus 0:0a673c671a56 2135 {
ebrus 0:0a673c671a56 2136 /* Check the parameters */
ebrus 0:0a673c671a56 2137 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2138 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 2139 assert_param(IS_ADC_IT(ADC_IT));
ebrus 0:0a673c671a56 2140
ebrus 0:0a673c671a56 2141 if (NewState != DISABLE)
ebrus 0:0a673c671a56 2142 {
ebrus 0:0a673c671a56 2143 /* Enable the selected ADC interrupts */
ebrus 0:0a673c671a56 2144 ADCx->IER |= ADC_IT;
ebrus 0:0a673c671a56 2145 }
ebrus 0:0a673c671a56 2146 else
ebrus 0:0a673c671a56 2147 {
ebrus 0:0a673c671a56 2148 /* Disable the selected ADC interrupts */
ebrus 0:0a673c671a56 2149 ADCx->IER &= (~(uint32_t)ADC_IT);
ebrus 0:0a673c671a56 2150 }
ebrus 0:0a673c671a56 2151 }
ebrus 0:0a673c671a56 2152
ebrus 0:0a673c671a56 2153 /**
ebrus 0:0a673c671a56 2154 * @brief Checks whether the specified ADC flag is set or not.
ebrus 0:0a673c671a56 2155 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 2156 * @param ADC_FLAG: specifies the flag to check.
ebrus 0:0a673c671a56 2157 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 2158 * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
ebrus 0:0a673c671a56 2159 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
ebrus 0:0a673c671a56 2160 * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
ebrus 0:0a673c671a56 2161 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2162 * @arg ADC_FLAG_OVR: ADC overrun flag
ebrus 0:0a673c671a56 2163 * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
ebrus 0:0a673c671a56 2164 * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2165 * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
ebrus 0:0a673c671a56 2166 * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
ebrus 0:0a673c671a56 2167 * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
ebrus 0:0a673c671a56 2168 * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2169 * @retval The new state of ADC_FLAG (SET or RESET).
ebrus 0:0a673c671a56 2170 */
ebrus 0:0a673c671a56 2171 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
ebrus 0:0a673c671a56 2172 {
ebrus 0:0a673c671a56 2173 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 2174 /* Check the parameters */
ebrus 0:0a673c671a56 2175 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2176 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
ebrus 0:0a673c671a56 2177
ebrus 0:0a673c671a56 2178 /* Check the status of the specified ADC flag */
ebrus 0:0a673c671a56 2179 if ((ADCx->ISR & ADC_FLAG) != (uint32_t)RESET)
ebrus 0:0a673c671a56 2180 {
ebrus 0:0a673c671a56 2181 /* ADC_FLAG is set */
ebrus 0:0a673c671a56 2182 bitstatus = SET;
ebrus 0:0a673c671a56 2183 }
ebrus 0:0a673c671a56 2184 else
ebrus 0:0a673c671a56 2185 {
ebrus 0:0a673c671a56 2186 /* ADC_FLAG is reset */
ebrus 0:0a673c671a56 2187 bitstatus = RESET;
ebrus 0:0a673c671a56 2188 }
ebrus 0:0a673c671a56 2189 /* Return the ADC_FLAG status */
ebrus 0:0a673c671a56 2190 return bitstatus;
ebrus 0:0a673c671a56 2191 }
ebrus 0:0a673c671a56 2192
ebrus 0:0a673c671a56 2193 /**
ebrus 0:0a673c671a56 2194 * @brief Clears the ADCx's pending flags.
ebrus 0:0a673c671a56 2195 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 2196 * @param ADC_FLAG: specifies the flag to clear.
ebrus 0:0a673c671a56 2197 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 2198 * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
ebrus 0:0a673c671a56 2199 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
ebrus 0:0a673c671a56 2200 * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
ebrus 0:0a673c671a56 2201 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2202 * @arg ADC_FLAG_OVR: ADC overrun flag
ebrus 0:0a673c671a56 2203 * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
ebrus 0:0a673c671a56 2204 * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2205 * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
ebrus 0:0a673c671a56 2206 * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
ebrus 0:0a673c671a56 2207 * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
ebrus 0:0a673c671a56 2208 * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2209 * @retval None
ebrus 0:0a673c671a56 2210 */
ebrus 0:0a673c671a56 2211 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
ebrus 0:0a673c671a56 2212 {
ebrus 0:0a673c671a56 2213 /* Check the parameters */
ebrus 0:0a673c671a56 2214 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2215 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
ebrus 0:0a673c671a56 2216 /* Clear the selected ADC flags */
ebrus 0:0a673c671a56 2217 ADCx->ISR = (uint32_t)ADC_FLAG;
ebrus 0:0a673c671a56 2218 }
ebrus 0:0a673c671a56 2219
ebrus 0:0a673c671a56 2220 /**
ebrus 0:0a673c671a56 2221 * @brief Checks whether the specified ADC flag is set or not.
ebrus 0:0a673c671a56 2222 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 2223 * @param ADC_FLAG: specifies the master or slave flag to check.
ebrus 0:0a673c671a56 2224 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 2225 * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
ebrus 0:0a673c671a56 2226 * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
ebrus 0:0a673c671a56 2227 * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
ebrus 0:0a673c671a56 2228 * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2229 * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
ebrus 0:0a673c671a56 2230 * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
ebrus 0:0a673c671a56 2231 * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2232 * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
ebrus 0:0a673c671a56 2233 * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
ebrus 0:0a673c671a56 2234 * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
ebrus 0:0a673c671a56 2235 * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2236 * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
ebrus 0:0a673c671a56 2237 * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
ebrus 0:0a673c671a56 2238 * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
ebrus 0:0a673c671a56 2239 * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2240 * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
ebrus 0:0a673c671a56 2241 * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
ebrus 0:0a673c671a56 2242 * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2243 * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
ebrus 0:0a673c671a56 2244 * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
ebrus 0:0a673c671a56 2245 * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
ebrus 0:0a673c671a56 2246 * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2247 * @retval The new state of ADC_FLAG (SET or RESET).
ebrus 0:0a673c671a56 2248 */
ebrus 0:0a673c671a56 2249 FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
ebrus 0:0a673c671a56 2250 {
ebrus 0:0a673c671a56 2251 uint32_t tmpreg1 = 0;
ebrus 0:0a673c671a56 2252 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 2253
ebrus 0:0a673c671a56 2254 /* Check the parameters */
ebrus 0:0a673c671a56 2255 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2256 assert_param(IS_ADC_GET_COMMONFLAG(ADC_FLAG));
ebrus 0:0a673c671a56 2257
ebrus 0:0a673c671a56 2258 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 2259 {
ebrus 0:0a673c671a56 2260 tmpreg1 = ADC1_2->CSR;
ebrus 0:0a673c671a56 2261 }
ebrus 0:0a673c671a56 2262 else
ebrus 0:0a673c671a56 2263 {
ebrus 0:0a673c671a56 2264 tmpreg1 = ADC3_4->CSR;
ebrus 0:0a673c671a56 2265 }
ebrus 0:0a673c671a56 2266 /* Check the status of the specified ADC flag */
ebrus 0:0a673c671a56 2267 if ((tmpreg1 & ADC_FLAG) != (uint32_t)RESET)
ebrus 0:0a673c671a56 2268 {
ebrus 0:0a673c671a56 2269 /* ADC_FLAG is set */
ebrus 0:0a673c671a56 2270 bitstatus = SET;
ebrus 0:0a673c671a56 2271 }
ebrus 0:0a673c671a56 2272 else
ebrus 0:0a673c671a56 2273 {
ebrus 0:0a673c671a56 2274 /* ADC_FLAG is reset */
ebrus 0:0a673c671a56 2275 bitstatus = RESET;
ebrus 0:0a673c671a56 2276 }
ebrus 0:0a673c671a56 2277 /* Return the ADC_FLAG status */
ebrus 0:0a673c671a56 2278 return bitstatus;
ebrus 0:0a673c671a56 2279 }
ebrus 0:0a673c671a56 2280
ebrus 0:0a673c671a56 2281 /**
ebrus 0:0a673c671a56 2282 * @brief Clears the ADCx's pending flags.
ebrus 0:0a673c671a56 2283 * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
ebrus 0:0a673c671a56 2284 * @param ADC_FLAG: specifies the master or slave flag to clear.
ebrus 0:0a673c671a56 2285 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 2286 * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
ebrus 0:0a673c671a56 2287 * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
ebrus 0:0a673c671a56 2288 * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
ebrus 0:0a673c671a56 2289 * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2290 * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
ebrus 0:0a673c671a56 2291 * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
ebrus 0:0a673c671a56 2292 * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2293 * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
ebrus 0:0a673c671a56 2294 * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
ebrus 0:0a673c671a56 2295 * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
ebrus 0:0a673c671a56 2296 * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2297 * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
ebrus 0:0a673c671a56 2298 * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
ebrus 0:0a673c671a56 2299 * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
ebrus 0:0a673c671a56 2300 * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
ebrus 0:0a673c671a56 2301 * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
ebrus 0:0a673c671a56 2302 * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
ebrus 0:0a673c671a56 2303 * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
ebrus 0:0a673c671a56 2304 * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
ebrus 0:0a673c671a56 2305 * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
ebrus 0:0a673c671a56 2306 * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
ebrus 0:0a673c671a56 2307 * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
ebrus 0:0a673c671a56 2308 * @retval None
ebrus 0:0a673c671a56 2309 */
ebrus 0:0a673c671a56 2310 void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
ebrus 0:0a673c671a56 2311 {
ebrus 0:0a673c671a56 2312 /* Check the parameters */
ebrus 0:0a673c671a56 2313 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2314 assert_param(IS_ADC_CLEAR_COMMONFLAG(ADC_FLAG));
ebrus 0:0a673c671a56 2315
ebrus 0:0a673c671a56 2316 if((ADCx == ADC1) || (ADCx == ADC2))
ebrus 0:0a673c671a56 2317 {
ebrus 0:0a673c671a56 2318 /* Clear the selected ADC flags */
ebrus 0:0a673c671a56 2319 ADC1_2->CSR |= (uint32_t)ADC_FLAG;
ebrus 0:0a673c671a56 2320 }
ebrus 0:0a673c671a56 2321 else
ebrus 0:0a673c671a56 2322 {
ebrus 0:0a673c671a56 2323 /* Clear the selected ADC flags */
ebrus 0:0a673c671a56 2324 ADC3_4->CSR |= (uint32_t)ADC_FLAG;
ebrus 0:0a673c671a56 2325 }
ebrus 0:0a673c671a56 2326 }
ebrus 0:0a673c671a56 2327
ebrus 0:0a673c671a56 2328 /**
ebrus 0:0a673c671a56 2329 * @brief Checks whether the specified ADC interrupt has occurred or not.
ebrus 0:0a673c671a56 2330 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
ebrus 0:0a673c671a56 2331 * @param ADC_IT: specifies the ADC interrupt source to check.
ebrus 0:0a673c671a56 2332 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 2333 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
ebrus 0:0a673c671a56 2334 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
ebrus 0:0a673c671a56 2335 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
ebrus 0:0a673c671a56 2336 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2337 * @arg ADC_IT_OVR: ADC overrun interrupt source
ebrus 0:0a673c671a56 2338 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
ebrus 0:0a673c671a56 2339 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2340 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
ebrus 0:0a673c671a56 2341 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
ebrus 0:0a673c671a56 2342 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
ebrus 0:0a673c671a56 2343 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
ebrus 0:0a673c671a56 2344 * @retval The new state of ADC_IT (SET or RESET).
ebrus 0:0a673c671a56 2345 */
ebrus 0:0a673c671a56 2346 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
ebrus 0:0a673c671a56 2347 {
ebrus 0:0a673c671a56 2348 ITStatus bitstatus = RESET;
ebrus 0:0a673c671a56 2349 uint16_t itstatus = 0x0, itenable = 0x0;
ebrus 0:0a673c671a56 2350 /* Check the parameters */
ebrus 0:0a673c671a56 2351 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2352 assert_param(IS_ADC_GET_IT(ADC_IT));
ebrus 0:0a673c671a56 2353
ebrus 0:0a673c671a56 2354 itstatus = ADCx->ISR & ADC_IT;
ebrus 0:0a673c671a56 2355
ebrus 0:0a673c671a56 2356 itenable = ADCx->IER & ADC_IT;
ebrus 0:0a673c671a56 2357 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
ebrus 0:0a673c671a56 2358 {
ebrus 0:0a673c671a56 2359 bitstatus = SET;
ebrus 0:0a673c671a56 2360 }
ebrus 0:0a673c671a56 2361 else
ebrus 0:0a673c671a56 2362 {
ebrus 0:0a673c671a56 2363 bitstatus = RESET;
ebrus 0:0a673c671a56 2364 }
ebrus 0:0a673c671a56 2365 return bitstatus;
ebrus 0:0a673c671a56 2366 }
ebrus 0:0a673c671a56 2367
ebrus 0:0a673c671a56 2368 /**
ebrus 0:0a673c671a56 2369 * @brief Clears the ADCx's interrupt pending bits.
ebrus 0:0a673c671a56 2370 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
ebrus 0:0a673c671a56 2371 * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
ebrus 0:0a673c671a56 2372 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 2373 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
ebrus 0:0a673c671a56 2374 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
ebrus 0:0a673c671a56 2375 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
ebrus 0:0a673c671a56 2376 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2377 * @arg ADC_IT_OVR: ADC overrun interrupt source
ebrus 0:0a673c671a56 2378 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
ebrus 0:0a673c671a56 2379 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
ebrus 0:0a673c671a56 2380 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
ebrus 0:0a673c671a56 2381 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
ebrus 0:0a673c671a56 2382 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
ebrus 0:0a673c671a56 2383 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
ebrus 0:0a673c671a56 2384 * @retval None
ebrus 0:0a673c671a56 2385 */
ebrus 0:0a673c671a56 2386 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
ebrus 0:0a673c671a56 2387 {
ebrus 0:0a673c671a56 2388 /* Check the parameters */
ebrus 0:0a673c671a56 2389 assert_param(IS_ADC_ALL_PERIPH(ADCx));
ebrus 0:0a673c671a56 2390 assert_param(IS_ADC_IT(ADC_IT));
ebrus 0:0a673c671a56 2391 /* Clear the selected ADC interrupt pending bit */
ebrus 0:0a673c671a56 2392 ADCx->ISR = (uint32_t)ADC_IT;
ebrus 0:0a673c671a56 2393 }
ebrus 0:0a673c671a56 2394
ebrus 0:0a673c671a56 2395 /**
ebrus 0:0a673c671a56 2396 * @}
ebrus 0:0a673c671a56 2397 */
ebrus 0:0a673c671a56 2398
ebrus 0:0a673c671a56 2399 /**
ebrus 0:0a673c671a56 2400 * @}
ebrus 0:0a673c671a56 2401 */
ebrus 0:0a673c671a56 2402
ebrus 0:0a673c671a56 2403 /**
ebrus 0:0a673c671a56 2404 * @}
ebrus 0:0a673c671a56 2405 */
ebrus 0:0a673c671a56 2406
ebrus 0:0a673c671a56 2407 /**
ebrus 0:0a673c671a56 2408 * @}
ebrus 0:0a673c671a56 2409 */
ebrus 0:0a673c671a56 2410
ebrus 0:0a673c671a56 2411 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/