Duncan McIntyre / UniGraphic

My controller identifies as an ILI9328, but only works if initialised as an ILI9325. This fork includes a fix to force 9325 initialization when a 9328 is detected.

Dependents:   TouchScreenCalibrate TouchScreenGUIDemo

Fork of UniGraphic by GraphicsDisplay

Protocols/MINISTM32.h@34:091b954c3205, 2020-06-21 (annotated)

Committer:
Duncan McIntyre
Date:
Sun Jun 21 15:23:02 2020 +0100
Revision:
34:091b954c3205
Updated to include latest changes from upstream

Added a class to provide an interface for my MINI-STM32-V3.0 board.

This class uses direct GPIO access to achieve decent update speeds.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Duncan McIntyre 34:091b954c3205 1 #ifndef MINISTM32_H
Duncan McIntyre 34:091b954c3205 2 #define MINISTM32_H
Duncan McIntyre 34:091b954c3205 3
Duncan McIntyre 34:091b954c3205 4 #include "mbed.h"
Duncan McIntyre 34:091b954c3205 5 #include "Protocols.h"
Duncan McIntyre 34:091b954c3205 6 //#include "GraphicsDisplay.h"
Duncan McIntyre 34:091b954c3205 7 #if DEVICE_PORTINOUT
Duncan McIntyre 34:091b954c3205 8 /**
Duncan McIntyre 34:091b954c3205 9 * My MINI-STM32-V3.0 board is wired up to the display in a bizarre way
Duncan McIntyre 34:091b954c3205 10 * Data lines are PC0-7 and PB8-15
Duncan McIntyre 34:091b954c3205 11 * Using them with BUS16 is very slow, so this wrapper does more direct port access
Duncan McIntyre 34:091b954c3205 12 */
Duncan McIntyre 34:091b954c3205 13 class MINISTM32 : public Protocols
Duncan McIntyre 34:091b954c3205 14 {
Duncan McIntyre 34:091b954c3205 15 public:
Duncan McIntyre 34:091b954c3205 16
Duncan McIntyre 34:091b954c3205 17 /**
Duncan McIntyre 34:091b954c3205 18 * Create a MINISTM32 display interface
Duncan McIntyre 34:091b954c3205 19 * Pins are hard-wired
Duncan McIntyre 34:091b954c3205 20 * DB0 - PC0
Duncan McIntyre 34:091b954c3205 21 * DB1 - PC1
Duncan McIntyre 34:091b954c3205 22 * DB2 - PC2
Duncan McIntyre 34:091b954c3205 23 * DB3 - PC3
Duncan McIntyre 34:091b954c3205 24 * DB4 - PC4
Duncan McIntyre 34:091b954c3205 25 * DB5 - PC5
Duncan McIntyre 34:091b954c3205 26 * DB6 - PC6
Duncan McIntyre 34:091b954c3205 27 * DB7 - PC7
Duncan McIntyre 34:091b954c3205 28 * DB8 - N/C
Duncan McIntyre 34:091b954c3205 29 * DB9 - N/C
Duncan McIntyre 34:091b954c3205 30 * DB10 - PB8
Duncan McIntyre 34:091b954c3205 31 * DB11 - PB9
Duncan McIntyre 34:091b954c3205 32 * DB12 - PB10
Duncan McIntyre 34:091b954c3205 33 * DB13 - PB11
Duncan McIntyre 34:091b954c3205 34 * DB14 - PB12
Duncan McIntyre 34:091b954c3205 35 * DB15 - PB13
Duncan McIntyre 34:091b954c3205 36 * DB16 - PB14
Duncan McIntyre 34:091b954c3205 37 * DB17 - PB15
Duncan McIntyre 34:091b954c3205 38 * CS - PC8
Duncan McIntyre 34:091b954c3205 39 * RS - PC9
Duncan McIntyre 34:091b954c3205 40 * WR - PC10
Duncan McIntyre 34:091b954c3205 41 * RD - PC11
Duncan McIntyre 34:091b954c3205 42 * RESET - Connected to the board global reset line
Duncan McIntyre 34:091b954c3205 43 * EN - PC12
Duncan McIntyre 34:091b954c3205 44 */
Duncan McIntyre 34:091b954c3205 45 MINISTM32();
Duncan McIntyre 34:091b954c3205 46
Duncan McIntyre 34:091b954c3205 47 protected:
Duncan McIntyre 34:091b954c3205 48
Duncan McIntyre 34:091b954c3205 49 /** Send 8bit command to display controller
Duncan McIntyre 34:091b954c3205 50 *
Duncan McIntyre 34:091b954c3205 51 * @param cmd: byte to send
Duncan McIntyre 34:091b954c3205 52 *
Duncan McIntyre 34:091b954c3205 53 */
Duncan McIntyre 34:091b954c3205 54 virtual void wr_cmd8(unsigned char cmd);
Duncan McIntyre 34:091b954c3205 55
Duncan McIntyre 34:091b954c3205 56 /** Send 8bit data to display controller
Duncan McIntyre 34:091b954c3205 57 *
Duncan McIntyre 34:091b954c3205 58 * @param data: byte to send
Duncan McIntyre 34:091b954c3205 59 *
Duncan McIntyre 34:091b954c3205 60 */
Duncan McIntyre 34:091b954c3205 61 virtual void wr_data8(unsigned char data);
Duncan McIntyre 34:091b954c3205 62
Duncan McIntyre 34:091b954c3205 63 /** Send 2x8bit command to display controller
Duncan McIntyre 34:091b954c3205 64 *
Duncan McIntyre 34:091b954c3205 65 * @param cmd: halfword to send
Duncan McIntyre 34:091b954c3205 66 * @note 2cycles using pins[7:0]
Duncan McIntyre 34:091b954c3205 67 */
Duncan McIntyre 34:091b954c3205 68 virtual void wr_cmd16(unsigned short cmd);
Duncan McIntyre 34:091b954c3205 69
Duncan McIntyre 34:091b954c3205 70 /** Send 2x8bit data to display controller
Duncan McIntyre 34:091b954c3205 71 *
Duncan McIntyre 34:091b954c3205 72 * @param data: halfword to send
Duncan McIntyre 34:091b954c3205 73 * @note 2cycles using pins[7:0], only gram write cmd uses pins[15:8]
Duncan McIntyre 34:091b954c3205 74 */
Duncan McIntyre 34:091b954c3205 75 virtual void wr_data16(unsigned short data);
Duncan McIntyre 34:091b954c3205 76
Duncan McIntyre 34:091b954c3205 77 /** Send 16bit pixeldata to display controller
Duncan McIntyre 34:091b954c3205 78 *
Duncan McIntyre 34:091b954c3205 79 * @param data: halfword to send
Duncan McIntyre 34:091b954c3205 80 * @note here using all pins[15:0]
Duncan McIntyre 34:091b954c3205 81 */
Duncan McIntyre 34:091b954c3205 82 virtual void wr_gram(unsigned short data);
Duncan McIntyre 34:091b954c3205 83
Duncan McIntyre 34:091b954c3205 84 /** Send same 16bit pixeldata to display controller multiple times
Duncan McIntyre 34:091b954c3205 85 *
Duncan McIntyre 34:091b954c3205 86 * @param data: halfword to send
Duncan McIntyre 34:091b954c3205 87 * @param count: how many
Duncan McIntyre 34:091b954c3205 88 * @note here using all pins[15:0]
Duncan McIntyre 34:091b954c3205 89 */
Duncan McIntyre 34:091b954c3205 90 virtual void wr_gram(unsigned short data, unsigned int count);
Duncan McIntyre 34:091b954c3205 91
Duncan McIntyre 34:091b954c3205 92 /** Send array of pixeldata shorts to display controller
Duncan McIntyre 34:091b954c3205 93 *
Duncan McIntyre 34:091b954c3205 94 * @param data: unsigned short pixeldata array
Duncan McIntyre 34:091b954c3205 95 * @param lenght: lenght (in shorts)
Duncan McIntyre 34:091b954c3205 96 * @note here using all pins[15:0]
Duncan McIntyre 34:091b954c3205 97 */
Duncan McIntyre 34:091b954c3205 98 virtual void wr_grambuf(unsigned short* data, unsigned int lenght);
Duncan McIntyre 34:091b954c3205 99
Duncan McIntyre 34:091b954c3205 100 /** Read 16bit pixeldata from display controller (with dummy cycle)
Duncan McIntyre 34:091b954c3205 101 *
Duncan McIntyre 34:091b954c3205 102 * @param convert true/false. Convert 18bit to 16bit, some controllers returns 18bit
Duncan McIntyre 34:091b954c3205 103 * @returns 16bit color
Duncan McIntyre 34:091b954c3205 104 */
Duncan McIntyre 34:091b954c3205 105 virtual unsigned short rd_gram(bool convert);
Duncan McIntyre 34:091b954c3205 106
Duncan McIntyre 34:091b954c3205 107 /** Read 4x8bit register data (with dummy cycle)
Duncan McIntyre 34:091b954c3205 108 * @param reg the register to read
Duncan McIntyre 34:091b954c3205 109 * @returns data as uint
Duncan McIntyre 34:091b954c3205 110 *
Duncan McIntyre 34:091b954c3205 111 */
Duncan McIntyre 34:091b954c3205 112 virtual unsigned int rd_reg_data32(unsigned char reg);
Duncan McIntyre 34:091b954c3205 113
Duncan McIntyre 34:091b954c3205 114 /** Read 3x8bit ExtendedCommands register data
Duncan McIntyre 34:091b954c3205 115 * @param reg the register to read
Duncan McIntyre 34:091b954c3205 116 * @returns data as uint
Duncan McIntyre 34:091b954c3205 117 * @note EXTC regs (0xB0 to 0xFF) are read/write registers, for Parallel mode directly accessible in both directions
Duncan McIntyre 34:091b954c3205 118 */
Duncan McIntyre 34:091b954c3205 119 virtual unsigned int rd_extcreg_data32(unsigned char reg, unsigned char SPIreadenablecmd);
Duncan McIntyre 34:091b954c3205 120
Duncan McIntyre 34:091b954c3205 121 /** ILI932x specific, does a dummy read cycle, number of bits is protocol dependent
Duncan McIntyre 34:091b954c3205 122 * for PAR protocols: a signle RD bit toggle
Duncan McIntyre 34:091b954c3205 123 * for SPI8: 8clocks
Duncan McIntyre 34:091b954c3205 124 * for SPI16: 16 clocks
Duncan McIntyre 34:091b954c3205 125 */
Duncan McIntyre 34:091b954c3205 126 virtual void dummyread ();
Duncan McIntyre 34:091b954c3205 127
Duncan McIntyre 34:091b954c3205 128 /** ILI932x specific, select register for a successive write or read
Duncan McIntyre 34:091b954c3205 129 *
Duncan McIntyre 34:091b954c3205 130 * @param reg register to be selected
Duncan McIntyre 34:091b954c3205 131 * @param forread false = a write next (default), true = a read next
Duncan McIntyre 34:091b954c3205 132 * @note forread only used by SPI protocols
Duncan McIntyre 34:091b954c3205 133 */
Duncan McIntyre 34:091b954c3205 134 virtual void reg_select(unsigned char reg, bool forread =false);
Duncan McIntyre 34:091b954c3205 135
Duncan McIntyre 34:091b954c3205 136 /** ILI932x specific, write register with data
Duncan McIntyre 34:091b954c3205 137 *
Duncan McIntyre 34:091b954c3205 138 * @param reg register to write
Duncan McIntyre 34:091b954c3205 139 * @param data 16bit data
Duncan McIntyre 34:091b954c3205 140 */
Duncan McIntyre 34:091b954c3205 141 virtual void reg_write(unsigned char reg, unsigned short data);
Duncan McIntyre 34:091b954c3205 142
Duncan McIntyre 34:091b954c3205 143 /** ILI932x specific, read register
Duncan McIntyre 34:091b954c3205 144 *
Duncan McIntyre 34:091b954c3205 145 * @param reg register to be read
Duncan McIntyre 34:091b954c3205 146 * @returns 16bit register value
Duncan McIntyre 34:091b954c3205 147 */
Duncan McIntyre 34:091b954c3205 148 virtual unsigned short reg_read(unsigned char reg);
Duncan McIntyre 34:091b954c3205 149
Duncan McIntyre 34:091b954c3205 150 /** HW reset sequence (without display init commands)
Duncan McIntyre 34:091b954c3205 151 */
Duncan McIntyre 34:091b954c3205 152 virtual void hw_reset();
Duncan McIntyre 34:091b954c3205 153
Duncan McIntyre 34:091b954c3205 154 /** Set ChipSelect high or low
Duncan McIntyre 34:091b954c3205 155 * @param enable 0/1
Duncan McIntyre 34:091b954c3205 156 */
Duncan McIntyre 34:091b954c3205 157 virtual void BusEnable(bool enable);
Duncan McIntyre 34:091b954c3205 158
Duncan McIntyre 34:091b954c3205 159
Duncan McIntyre 34:091b954c3205 160
Duncan McIntyre 34:091b954c3205 161 private:
Duncan McIntyre 34:091b954c3205 162
Duncan McIntyre 34:091b954c3205 163 PortInOut _HI;
Duncan McIntyre 34:091b954c3205 164 PortInOut _LO;
Duncan McIntyre 34:091b954c3205 165 DigitalOut _CS;
Duncan McIntyre 34:091b954c3205 166 DigitalOut _DC;
Duncan McIntyre 34:091b954c3205 167 DigitalOut _WR;
Duncan McIntyre 34:091b954c3205 168 DigitalOut _RD;
Duncan McIntyre 34:091b954c3205 169
Duncan McIntyre 34:091b954c3205 170 };
Duncan McIntyre 34:091b954c3205 171 #endif
Duncan McIntyre 34:091b954c3205 172 #endif