driver for sx1280
Dependents: alarm_slave_extended_SX1280 alarm_master_extended_Vance_SX1280
Diff: sx12xx.h
- Revision:
- 5:aba2d8b29702
- Parent:
- 2:8a442c3511ae
- Child:
- 6:a12ec083ce61
diff -r ac55132283cb -r aba2d8b29702 sx12xx.h --- a/sx12xx.h Wed Jul 18 18:07:29 2018 -0700 +++ b/sx12xx.h Tue Aug 21 17:16:12 2018 -0700 @@ -44,6 +44,7 @@ #define REG_ADDR_LORA_PKTPAR1 0x903 // 8bit #define REG_ADDR_LORA_LRCTL 0x904 // 8bit #define REG_ADDR_LORA_IRQMASK 0x90f // 24bit +#define REG_ADDR_LORA_FE_GAIN 0x929 // 8bit #define REG_ADDR_LORA_PREAMBLE 0x93f // 8bit #define REG_ADDR_LORA_SYNC 0x944 // LrCfg7, LrCfg8 post-preamble gap (AKA lora sync) #define REG_ADDR_LORA_MODEMSTAT 0x95c // 8bit @@ -61,7 +62,7 @@ #define REG_ADDR_FLORA_PREAMBLE_HI 0x9ca // 8bit contains data rate #define REG_ADDR_PKT_SYNC_ADRS_CTRL 0x9cd // 8bit #define REG_ADDR_PKT_SYNC_ADRS_1 0x9ce // 40bit / 5bytes -#define REG_ADDR_PKT_SYNC_ADRS_2 0x9d2 // 40bit / 5bytes +#define REG_ADDR_PKT_SYNC_ADRS_2 0x9d3 // 40bit / 5bytes #define REG_ADDR_PKT_SYNC_ADRS_3 0x9d8 // 40bit / 5bytes #define REG_ADDR_FLRC_SYNCWORDCTRL 0x98b // 5bit @@ -148,6 +149,8 @@ #define LORA_BW_800 0x18 // 812.5KHz #define LORA_BW_400 0x26 // 406.25KHz #define LORA_BW_200 0x34 // 203.125KHz +#define LORA_BW_100 0x42 // +#define LORA_BW_50 0x51 // // LoRa modParam3 #define LORA_CR_4_5 0x01 // 4/5 @@ -358,7 +361,7 @@ status_t status; uint8_t rssiSync; uint8_t snr; - uint8_t reserved[4]; + uint8_t reserved[3]; } lora; uint8_t buf[6]; } pktStatus_t; @@ -607,6 +610,7 @@ void (*rxDone)(uint8_t size, const pktStatus_t*); // user context Callback<void()> chipModeChange; // read chipMode_e chipMode void (*timeout)(bool tx); // user context + void (*cadDone)(bool); //! RF transmit packet buffer uint8_t tx_buf[256]; // lora fifo size @@ -625,6 +629,7 @@ void setStandby(stby_t); void setSleep(bool warm); void setFS(void); + void setCAD(void); void writeReg(uint16_t addr, uint32_t data, uint8_t len); uint32_t readReg(uint16_t addr, uint8_t len); void setPacketType(uint8_t);