Diff: sx12xx.h

Revision:

6:a12ec083ce61

Parent:

5:aba2d8b29702

Child:

7:aa7047cdf47b

--- a/sx12xx.h	Tue Aug 21 17:16:12 2018 -0700
+++ b/sx12xx.h	Sun Nov 25 15:31:18 2018 -0800
@@ -29,6 +29,7 @@
 #define OPCODE_SET_PA_CONFIG            0x95
 #define OPCODE_SET_REGULATOR_MODE       0x96
 #define OPCODE_CLEAR_IRQ_STATUS         0x97
+#define OPCODE_SET_RANGING_ROLE         0xa3
 #define OPCODE_GET_STATUS               0xc0
 #define OPCODE_SET_FS                   0xc1
 #define OPCODE_SET_CAD                  0xc5
@@ -44,10 +45,21 @@
 #define REG_ADDR_LORA_PKTPAR1             0x903 // 8bit
 #define REG_ADDR_LORA_LRCTL               0x904 // 8bit
 #define REG_ADDR_LORA_IRQMASK             0x90f // 24bit
+#define REG_ADDR_LORA_MASTER_REQ_ID       0x912 // 32bit
+#define REG_ADDR_LORA_SLAVE_ID            0x916 // 32bit
+#define REG_ADDR_RNGFLTWNDSIZE            0x91e // 32bit
+#define REG_ADDR_RNGCFG0                  0x923 // 8bit
+#define REG_ADDR_RNGCFG1                  0x924 // 7bit
 #define REG_ADDR_LORA_FE_GAIN             0x929 // 8bit
+#define REG_ADDR_LORA_DELAY_CAL           0x92b // 24bit
+#define REG_ADDR_LORA_RNGDEBTH2           0x931 // 8bit
+#define REG_ADDR_RNGDEBTH4H               0x935 // 8bit
+
 #define REG_ADDR_LORA_PREAMBLE            0x93f // 8bit
 #define REG_ADDR_LORA_SYNC                0x944 // LrCfg7, LrCfg8  post-preamble gap (AKA lora sync)
 #define REG_ADDR_LORA_MODEMSTAT           0x95c // 8bit
+#define REG_ADDR_RNGRESULT                0x961 // 24bit
+#define REG_ADDR_RNGRSSI                  0x964 // 8bit
 
 #define REG_ADDR_FSK_CFG                  0x9a0 // 8bit
 #define REG_ADDR_FSK_MODDFH               0x9a1 // 8bit
@@ -65,9 +77,10 @@
 #define REG_ADDR_PKT_SYNC_ADRS_2          0x9d3 // 40bit / 5bytes
 #define REG_ADDR_PKT_SYNC_ADRS_3          0x9d8 // 40bit / 5bytes
 
-#define REG_ADDR_FLRC_SYNCWORDCTRL       0x98b // 5bit
-#define REG_ADDR_FLRC_IRQSTATUS          0x990 // 3bit
-
+#define REG_ADDR_FLRC_SYNCWORDCTRL        0x98b // 5bit
+#define REG_ADDR_FLRC_IRQSTATUS           0x990 // 3bit
+#define REG_ADDR_XTA_TRIM                 0xa0e // crystal trim
+#define REG_ADDR_XTB_TRIM                 0xa0f // crystal trim
 #define REG_ADDR_PA_PWR_CTRL              0xa53 // 8bit
 /***************************************************************/
 #define PLL_STEP_HZ        198.364257812       // 52MHz / 2^18
@@ -455,6 +468,46 @@
     uint8_t octet;
 } LoRaLrCtl_t; // 0x904
 
+
+typedef union {
+    struct {
+        uint8_t ranging_res_bits         : 2; // 0,1
+        uint8_t ranging_resp_en          : 1; // 2      slave enable
+        uint8_t timing_synch_en          : 1; // 3
+        uint8_t ranging_synched_start_en : 1; // 4
+        uint8_t ranging_result_clear_reg : 1; // 5
+        uint8_t rx_fifo_addr_clear       : 1; // 6
+        uint8_t counters_clear_reg       : 1; // 7
+    } bits;
+    uint8_t octet;
+} RngCfg0_t; // 0x923
+
+typedef union {
+    struct {
+        uint8_t muxed_counter_select       : 4; // 0,1,2,3
+        uint8_t ranging_result_mux_sel     : 2; // 4,5
+        uint8_t ranging_result_trigger_sel : 1; // 6
+        uint8_t res                        : 1; // 7
+    } bits;
+    uint8_t octet;
+} RngCfg1_t; // 0x924
+
+typedef union {
+    struct {
+        uint8_t ranging_filter_debias_th2 : 6; // 0,1,2,3,4,5
+        uint8_t ranging_id_check_length   : 2; // 6,7
+    } bits;
+    uint8_t octet;
+} RngDebTh2_t; // 0x931
+
+typedef union {
+    struct {
+        uint8_t debias_th4         : 2; // 0,1
+        uint8_t rng_rssi_threshold : 6; // 2...7
+    } bits;
+    uint8_t octet;
+} RngDebTh4H_t; // 0x935
+
 typedef union {
     struct {
         uint8_t preamble_symb1_nb : 4; // 0,1,2,3