wayne roberts / sx128x

driver for sx1280

Dependents:   alarm_slave_extended_SX1280 alarm_master_extended_Vance_SX1280

sx12xx.h@5:aba2d8b29702, 2018-08-21 (annotated)

Committer:
Wayne Roberts
Date:
Tue Aug 21 17:16:12 2018 -0700
Revision:
5:aba2d8b29702
Parent:
2:8a442c3511ae
Child:
6:a12ec083ce61
add CAD support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Wayne Roberts 0:abb827c65ff5 1 #include "mbed.h"
Wayne Roberts 0:abb827c65ff5 2 #ifndef SX128x_H
Wayne Roberts 0:abb827c65ff5 3 #define SX128x_H
Wayne Roberts 0:abb827c65ff5 4
Wayne Roberts 0:abb827c65ff5 5 /***************************************************************/
Wayne Roberts 0:abb827c65ff5 6 #define OPCODE_GET_PACKET_TYPE 0x03
Wayne Roberts 0:abb827c65ff5 7 #define OPCODE_CLEAR_DEVICE_ERRORS 0x07
Wayne Roberts 0:abb827c65ff5 8 #define OPCODE_GET_IRQ_STATUS 0x15
Wayne Roberts 0:abb827c65ff5 9 #define OPCODE_GET_RX_BUFFER_STATUS 0x17
Wayne Roberts 0:abb827c65ff5 10 #define OPCODE_WRITE_REGISTER 0x18
Wayne Roberts 0:abb827c65ff5 11 #define OPCODE_READ_REGISTER 0x19
Wayne Roberts 0:abb827c65ff5 12 #define OPCODE_WRITE_BUFFER 0x1a
Wayne Roberts 0:abb827c65ff5 13 #define OPCODE_READ_BUFFER 0x1b
Wayne Roberts 0:abb827c65ff5 14 #define OPCODE_GET_PACKET_STATUS 0x1d
Wayne Roberts 0:abb827c65ff5 15 #define OPCODE_GET_RSSIINST 0x1f
Wayne Roberts 0:abb827c65ff5 16 #define OPCODE_SET_STANDBY 0x80
Wayne Roberts 0:abb827c65ff5 17 #define OPCODE_SET_RX 0x82
Wayne Roberts 0:abb827c65ff5 18 #define OPCODE_SET_TX 0x83
Wayne Roberts 0:abb827c65ff5 19 #define OPCODE_SET_SLEEP 0x84
Wayne Roberts 0:abb827c65ff5 20 #define OPCODE_SET_RF_FREQUENCY 0x86
Wayne Roberts 0:abb827c65ff5 21 #define OPCODE_SET_CAD_PARAM 0x88
Wayne Roberts 0:abb827c65ff5 22 #define OPCODE_CALIBRATE 0x89
Wayne Roberts 0:abb827c65ff5 23 #define OPCODE_SET_PACKET_TYPE 0x8a
Wayne Roberts 0:abb827c65ff5 24 #define OPCODE_SET_MODULATION_PARAMS 0x8b
Wayne Roberts 0:abb827c65ff5 25 #define OPCODE_SET_PACKET_PARAMS 0x8c
Wayne Roberts 0:abb827c65ff5 26 #define OPCODE_SET_DIO_IRQ_PARAMS 0x8d
Wayne Roberts 0:abb827c65ff5 27 #define OPCODE_SET_TX_PARAMS 0x8e
Wayne Roberts 0:abb827c65ff5 28 #define OPCODE_SET_BUFFER_BASE_ADDR 0x8f
Wayne Roberts 0:abb827c65ff5 29 #define OPCODE_SET_PA_CONFIG 0x95
Wayne Roberts 0:abb827c65ff5 30 #define OPCODE_SET_REGULATOR_MODE 0x96
Wayne Roberts 0:abb827c65ff5 31 #define OPCODE_CLEAR_IRQ_STATUS 0x97
Wayne Roberts 0:abb827c65ff5 32 #define OPCODE_GET_STATUS 0xc0
Wayne Roberts 0:abb827c65ff5 33 #define OPCODE_SET_FS 0xc1
Wayne Roberts 0:abb827c65ff5 34 #define OPCODE_SET_CAD 0xc5
Wayne Roberts 0:abb827c65ff5 35 #define OPCODE_SET_TX_CARRIER 0xd1
Wayne Roberts 0:abb827c65ff5 36 #define OPCODE_SET_TX_PREAMBLE 0xd2
Wayne Roberts 2:8a442c3511ae 37 #define OPCODE_SAVE_CONTEXT 0xd5
Wayne Roberts 0:abb827c65ff5 38 /***************************************************************/
Wayne Roberts 0:abb827c65ff5 39 #define REG_ADDR_AFIRQ 0x053 // 7bit
Wayne Roberts 0:abb827c65ff5 40 #define REG_ADDR_RXBW 0x881 // 7bit
Wayne Roberts 0:abb827c65ff5 41 #define REG_ADDR_GFSK_DEMODSTATUS 0x8cb // 5bit
Wayne Roberts 0:abb827c65ff5 42 #define REG_ADDR_LORA_TX_PAYLOAD_LENGTH 0x901 // 8bit
Wayne Roberts 0:abb827c65ff5 43 #define REG_ADDR_LORA_PKTPAR0 0x902 // 8bit
Wayne Roberts 2:8a442c3511ae 44 #define REG_ADDR_LORA_PKTPAR1 0x903 // 8bit
Wayne Roberts 0:abb827c65ff5 45 #define REG_ADDR_LORA_LRCTL 0x904 // 8bit
Wayne Roberts 0:abb827c65ff5 46 #define REG_ADDR_LORA_IRQMASK 0x90f // 24bit
Wayne Roberts 5:aba2d8b29702 47 #define REG_ADDR_LORA_FE_GAIN 0x929 // 8bit
Wayne Roberts 0:abb827c65ff5 48 #define REG_ADDR_LORA_PREAMBLE 0x93f // 8bit
Wayne Roberts 1:70ef46fa6fc6 49 #define REG_ADDR_LORA_SYNC 0x944 // LrCfg7, LrCfg8 post-preamble gap (AKA lora sync)
Wayne Roberts 0:abb827c65ff5 50 #define REG_ADDR_LORA_MODEMSTAT 0x95c // 8bit
Wayne Roberts 0:abb827c65ff5 51
Wayne Roberts 0:abb827c65ff5 52 #define REG_ADDR_FSK_CFG 0x9a0 // 8bit
Wayne Roberts 0:abb827c65ff5 53 #define REG_ADDR_FSK_MODDFH 0x9a1 // 8bit
Wayne Roberts 0:abb827c65ff5 54 #define REG_ADDR_FSK_MODDFL 0x9a2 // 8bit
Wayne Roberts 0:abb827c65ff5 55 #define REG_ADDR_RFFREQ 0x9a3 // 24bit
Wayne Roberts 0:abb827c65ff5 56
Wayne Roberts 0:abb827c65ff5 57 #define REG_ADDR_PKTCTRL0 0x9c0 // 8bit
Wayne Roberts 0:abb827c65ff5 58 #define REG_ADDR_PKTCTRL1 0x9c1 // 8bit
Wayne Roberts 0:abb827c65ff5 59 #define REG_ADDR_PKT_TX_HEADER 0x9c2 // 8bit
Wayne Roberts 0:abb827c65ff5 60 #define REG_ADDR_PAYLOAD_LEN 0x9c3 // 8bit
Wayne Roberts 0:abb827c65ff5 61 #define REG_ADDR_PKT_BITSTREAM_CTRL 0x9c4 // 8bit
Wayne Roberts 0:abb827c65ff5 62 #define REG_ADDR_FLORA_PREAMBLE_HI 0x9ca // 8bit contains data rate
Wayne Roberts 0:abb827c65ff5 63 #define REG_ADDR_PKT_SYNC_ADRS_CTRL 0x9cd // 8bit
Wayne Roberts 0:abb827c65ff5 64 #define REG_ADDR_PKT_SYNC_ADRS_1 0x9ce // 40bit / 5bytes
Wayne Roberts 5:aba2d8b29702 65 #define REG_ADDR_PKT_SYNC_ADRS_2 0x9d3 // 40bit / 5bytes
Wayne Roberts 0:abb827c65ff5 66 #define REG_ADDR_PKT_SYNC_ADRS_3 0x9d8 // 40bit / 5bytes
Wayne Roberts 0:abb827c65ff5 67
Wayne Roberts 0:abb827c65ff5 68 #define REG_ADDR_FLRC_SYNCWORDCTRL 0x98b // 5bit
Wayne Roberts 0:abb827c65ff5 69 #define REG_ADDR_FLRC_IRQSTATUS 0x990 // 3bit
Wayne Roberts 0:abb827c65ff5 70
Wayne Roberts 0:abb827c65ff5 71 #define REG_ADDR_PA_PWR_CTRL 0xa53 // 8bit
Wayne Roberts 0:abb827c65ff5 72 /***************************************************************/
Wayne Roberts 0:abb827c65ff5 73 #define PLL_STEP_HZ 198.364257812 // 52MHz / 2^18
Wayne Roberts 0:abb827c65ff5 74 #define PLL_STEP_MHZ 0.000198364257812 // 52 / 2^18
Wayne Roberts 0:abb827c65ff5 75
Wayne Roberts 0:abb827c65ff5 76 #define RX_CONTINUOUS_TIMEOUT 0xffff // receive forever
Wayne Roberts 0:abb827c65ff5 77 #define RX_SINGLE_TIMEOUT 0x0000 // receive until packet received
Wayne Roberts 0:abb827c65ff5 78
Wayne Roberts 0:abb827c65ff5 79 #define PACKET_TYPE_GFSK 0
Wayne Roberts 0:abb827c65ff5 80 #define PACKET_TYPE_LORA 1
Wayne Roberts 0:abb827c65ff5 81 #define PACKET_TYPE_RANGING 2
Wayne Roberts 0:abb827c65ff5 82 #define PACKET_TYPE_FLRC 3
Wayne Roberts 0:abb827c65ff5 83 #define PACKET_TYPE_BLE 4
Wayne Roberts 0:abb827c65ff5 84
Wayne Roberts 0:abb827c65ff5 85
Wayne Roberts 0:abb827c65ff5 86 #define RADIO_PACKET_FIXED_LENGTH 0x00
Wayne Roberts 0:abb827c65ff5 87 #define RADIO_PACKET_VARIABLE_LENGTH 0x20
Wayne Roberts 0:abb827c65ff5 88
Wayne Roberts 0:abb827c65ff5 89 // birate & bandwidth modParam1:
Wayne Roberts 0:abb827c65ff5 90 #define GFSK_BLE_BR_2_000_BW_2_4 0x04 // Mbps:2 bw:2.4MHz 0000 0100
Wayne Roberts 0:abb827c65ff5 91 #define GFSK_BLE_BR_1_600_BW_2_4 0x28 // Mbps:1.6 bw:2.4MHz 0010 1000
Wayne Roberts 0:abb827c65ff5 92 #define GFSK_BLE_BR_1_000_BW_2_4 0x4C // Mbps:1 bw:2.4MHz 0100 1100
Wayne Roberts 0:abb827c65ff5 93 #define GFSK_BLE_BR_1_000_BW_1_2 0x45 // Mbps:1 bw:1.2MHz 0100 0101
Wayne Roberts 0:abb827c65ff5 94 #define GFSK_BLE_BR_0_800_BW_2_4 0x70 // Mbps:0.8 bw:2.4MHz 0111 0000
Wayne Roberts 0:abb827c65ff5 95 #define GFSK_BLE_BR_0_800_BW_1_2 0x69 // Mbps:0.8 bw:1.2MHz 0110 1001
Wayne Roberts 0:abb827c65ff5 96 #define GFSK_BLE_BR_0_500_BW_1_2 0x8D // Mbps:0.5 bw:1.2MHz 1000 1101
Wayne Roberts 0:abb827c65ff5 97 #define GFSK_BLE_BR_0_500_BW_0_6 0x86 // Mbps:0.5 bw:0.6MHz 1000 0110
Wayne Roberts 0:abb827c65ff5 98 #define GFSK_BLE_BR_0_400_BW_1_2 0xB1 // Mbps:0.4 bw:1.2MHz 1011 0001
Wayne Roberts 0:abb827c65ff5 99 #define GFSK_BLE_BR_0_400_BW_0_6 0xAA // Mbps:0.4 bw:0.6MHz 1010 1010
Wayne Roberts 0:abb827c65ff5 100 #define GFSK_BLE_BR_0_250_BW_0_6 0xCE // Mbps:0.25 bw:0.6MHz 1100 1110
Wayne Roberts 0:abb827c65ff5 101 #define GFSK_BLE_BR_0_250_BW_0_3 0xC7 // Mbps:0.25 bw:0.3MHz 1100 0111
Wayne Roberts 0:abb827c65ff5 102 #define GFSK_BLE_BR_0_125_BW_0_3 0xEF // Mbps:0.125 bw:0.3MHz 1110 1111
Wayne Roberts 0:abb827c65ff5 103
Wayne Roberts 0:abb827c65ff5 104 // modulationIndex modParam2
Wayne Roberts 0:abb827c65ff5 105 #define MOD_IND_0_35 0x00 // 0.35
Wayne Roberts 0:abb827c65ff5 106 #define MOD_IND_0_5 0x01 // 0.5
Wayne Roberts 0:abb827c65ff5 107 #define MOD_IND_0_75 0x02 // 0.75
Wayne Roberts 0:abb827c65ff5 108 #define MOD_IND_1_00 0x03 // 1
Wayne Roberts 0:abb827c65ff5 109 #define MOD_IND_1_25 0x04 // 1.25
Wayne Roberts 0:abb827c65ff5 110 #define MOD_IND_1_50 0x05 // 1.5
Wayne Roberts 0:abb827c65ff5 111 #define MOD_IND_1_75 0x06 // 1.75
Wayne Roberts 0:abb827c65ff5 112 #define MOD_IND_2_00 0x07 // 2
Wayne Roberts 0:abb827c65ff5 113 #define MOD_IND_2_25 0x08 // 2.25
Wayne Roberts 0:abb827c65ff5 114 #define MOD_IND_2_50 0x09 // 2.5
Wayne Roberts 0:abb827c65ff5 115 #define MOD_IND_2_75 0x0A // 2.75
Wayne Roberts 0:abb827c65ff5 116 #define MOD_IND_3_00 0x0B // 3
Wayne Roberts 0:abb827c65ff5 117 #define MOD_IND_3_25 0x0C // 3.25
Wayne Roberts 0:abb827c65ff5 118 #define MOD_IND_3_50 0x0D // 3.5
Wayne Roberts 0:abb827c65ff5 119 #define MOD_IND_3_75 0x0E // 3.75
Wayne Roberts 0:abb827c65ff5 120 #define MOD_IND_4_00 0x0F // 4
Wayne Roberts 0:abb827c65ff5 121
Wayne Roberts 0:abb827c65ff5 122 // modulationShaping modParam3:
Wayne Roberts 0:abb827c65ff5 123 #define BT_OFF 0x00 // No filtering
Wayne Roberts 0:abb827c65ff5 124 #define BT_1_0 0x10 // BT1
Wayne Roberts 0:abb827c65ff5 125 #define BT_0_5 0x20 // BT0.5
Wayne Roberts 0:abb827c65ff5 126
Wayne Roberts 0:abb827c65ff5 127 // packetParam6:
Wayne Roberts 0:abb827c65ff5 128 #define RADIO_CRC_OFF 0x00 // CRC off
Wayne Roberts 0:abb827c65ff5 129 #define RADIO_CRC_1_BYTES 0x10 // CRC field used 1 byte
Wayne Roberts 0:abb827c65ff5 130 #define RADIO_CRC_2_BYTES 0x20 // CRC field uses 2 bytes
Wayne Roberts 0:abb827c65ff5 131 #define RADIO_CRC_3_BYTES 0x30 // ??? CRC field uses 3 bytes FLRC ????
Wayne Roberts 0:abb827c65ff5 132
Wayne Roberts 0:abb827c65ff5 133 // GFSK packetParam7:
Wayne Roberts 0:abb827c65ff5 134 #define WHITENING_ENABLE 0x00
Wayne Roberts 0:abb827c65ff5 135 #define WHITENING_DISABLE 0x08
Wayne Roberts 0:abb827c65ff5 136
Wayne Roberts 0:abb827c65ff5 137 // LoRa spreadingFactor modParam1:
Wayne Roberts 0:abb827c65ff5 138 #define LORA_SF_5 0x50
Wayne Roberts 0:abb827c65ff5 139 #define LORA_SF_6 0x60
Wayne Roberts 0:abb827c65ff5 140 #define LORA_SF_7 0x70
Wayne Roberts 0:abb827c65ff5 141 #define LORA_SF_8 0x80
Wayne Roberts 0:abb827c65ff5 142 #define LORA_SF_9 0x90
Wayne Roberts 0:abb827c65ff5 143 #define LORA_SF_10 0xA0
Wayne Roberts 0:abb827c65ff5 144 #define LORA_SF_11 0xB0
Wayne Roberts 0:abb827c65ff5 145 #define LORA_SF_12 0xC0
Wayne Roberts 0:abb827c65ff5 146
Wayne Roberts 0:abb827c65ff5 147 // LoRa modParam2
Wayne Roberts 0:abb827c65ff5 148 #define LORA_BW_1600 0x0A // 1625.0KHz
Wayne Roberts 0:abb827c65ff5 149 #define LORA_BW_800 0x18 // 812.5KHz
Wayne Roberts 0:abb827c65ff5 150 #define LORA_BW_400 0x26 // 406.25KHz
Wayne Roberts 0:abb827c65ff5 151 #define LORA_BW_200 0x34 // 203.125KHz
Wayne Roberts 5:aba2d8b29702 152 #define LORA_BW_100 0x42 //
Wayne Roberts 5:aba2d8b29702 153 #define LORA_BW_50 0x51 //
Wayne Roberts 0:abb827c65ff5 154
Wayne Roberts 0:abb827c65ff5 155 // LoRa modParam3
Wayne Roberts 0:abb827c65ff5 156 #define LORA_CR_4_5 0x01 // 4/5
Wayne Roberts 0:abb827c65ff5 157 #define LORA_CR_4_6 0x02 // 4/6
Wayne Roberts 0:abb827c65ff5 158 #define LORA_CR_4_7 0x03 // 4/7
Wayne Roberts 0:abb827c65ff5 159 #define LORA_CR_4_8 0x04 // 4/8
Wayne Roberts 0:abb827c65ff5 160 #define LORA_CR_LI_4_5 0x05 // 4/5*
Wayne Roberts 0:abb827c65ff5 161 #define LORA_CR_LI_4_6 0x06 // 4/6*
Wayne Roberts 0:abb827c65ff5 162 #define LORA_CR_LI_4_7 0x07 // 4/8*
Wayne Roberts 0:abb827c65ff5 163
Wayne Roberts 0:abb827c65ff5 164 // LoRa packetParam2:
Wayne Roberts 0:abb827c65ff5 165 #define EXPLICIT_HEADER 0x00 // var length
Wayne Roberts 0:abb827c65ff5 166 #define IMPLICIT_HEADER 0x80 // fixed Length
Wayne Roberts 0:abb827c65ff5 167
Wayne Roberts 0:abb827c65ff5 168 // LoRa packetParam4:
Wayne Roberts 0:abb827c65ff5 169 #define LORA_CRC_ENABLE 0x20
Wayne Roberts 0:abb827c65ff5 170 #define LORA_CRC_DISABLE 0x00
Wayne Roberts 0:abb827c65ff5 171
Wayne Roberts 0:abb827c65ff5 172 // LoRa packetParam5
Wayne Roberts 0:abb827c65ff5 173 #define LORA_IQ_STD 0x40 // IQ as defined
Wayne Roberts 0:abb827c65ff5 174 #define LORA_IQ_INVERTED 0x00 // IQ swapped
Wayne Roberts 0:abb827c65ff5 175
Wayne Roberts 0:abb827c65ff5 176 // transmitter power ramping
Wayne Roberts 0:abb827c65ff5 177 #define RADIO_RAMP_02_US 0x00 // 2 microseconds
Wayne Roberts 0:abb827c65ff5 178 #define RADIO_RAMP_04_US 0x20 // 4 microseconds
Wayne Roberts 0:abb827c65ff5 179 #define RADIO_RAMP_06_US 0x40 // 6 microseconds
Wayne Roberts 0:abb827c65ff5 180 #define RADIO_RAMP_08_US 0x60 // 8 microseconds
Wayne Roberts 0:abb827c65ff5 181 #define RADIO_RAMP_10_US 0x80 // 10 microseconds
Wayne Roberts 0:abb827c65ff5 182 #define RADIO_RAMP_12_US 0xA0 // 12 microseconds
Wayne Roberts 0:abb827c65ff5 183 #define RADIO_RAMP_16_US 0xC0 // 16 microseconds
Wayne Roberts 0:abb827c65ff5 184 #define RADIO_RAMP_20_US 0xE0 // 20 microseconds
Wayne Roberts 0:abb827c65ff5 185
Wayne Roberts 0:abb827c65ff5 186 // BLE packetParam1
Wayne Roberts 0:abb827c65ff5 187 #define BLE_PAYLOAD_LENGTH_MAX_31_BYTES 0x00 // maxlen:31 Bluetooth® 4.1 and above
Wayne Roberts 0:abb827c65ff5 188 #define BLE_PAYLOAD_LENGTH_MAX_37_BYTES 0x20 // maxlen:37 Bluetooth® 4.1 and above
Wayne Roberts 0:abb827c65ff5 189 #define BLE_TX_TEST_MODE 0x40 // maxlen:63 Bluetooth® 4.1 and above
Wayne Roberts 0:abb827c65ff5 190 #define BLE_PAYLOAD_LENGTH_MAX_255_BYTES 0x80 // maxlen:255 Bluetooth® 4.2 and above
Wayne Roberts 0:abb827c65ff5 191
Wayne Roberts 0:abb827c65ff5 192 // BLE packetParam2
Wayne Roberts 0:abb827c65ff5 193 #define BLE_CRC_OFF 0x00 // No CRC No
Wayne Roberts 0:abb827c65ff5 194 #define BLE_CRC_3B 0x10 // CRC field used 3bytes Yes
Wayne Roberts 0:abb827c65ff5 195
Wayne Roberts 0:abb827c65ff5 196 // BLE packetParam3 ignored in BLE_TX_TEST_MODE
Wayne Roberts 0:abb827c65ff5 197 #define BLE_PRBS_9 0x00// P7(x) = x9+ x5+ 1 PRBS9 sequence ‘1111111110000011110 1....’ (in transmission order)
Wayne Roberts 0:abb827c65ff5 198 #define BLE_EYELONG_1_0 0x04 // Repeated ‘11110000’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 199 #define BLE_EYESHORT_1_0 0x08 // Repeated ‘10101010’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 200 #define BLE_PRBS_15 0x0C // Pseudo Random Binary Sequence based on 15th degree polynomial P15(x) = x15+ x14+ x13 + x12+ x2+ x + 1
Wayne Roberts 0:abb827c65ff5 201 #define BLE_ALL_1 0x10 // Repeated ‘11111111’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 202 #define BLE_ALL_0 0x14 // Repeated ‘11111111’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 203 #define BLE_EYELONG_0_1 0x18 // Repeated ‘00001111’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 204 #define BLE_EYESHORT_0_1 0x1C // Repeated ‘01010101’ (in transmission order) sequence
Wayne Roberts 0:abb827c65ff5 205
Wayne Roberts 0:abb827c65ff5 206 // packetParam1
Wayne Roberts 0:abb827c65ff5 207 #define PREAMBLE_LENGTH_4_BITS 0x00 // 4bits
Wayne Roberts 0:abb827c65ff5 208 #define PREAMBLE_LENGTH_8_BITS 0x10 // 8bits
Wayne Roberts 0:abb827c65ff5 209 #define PREAMBLE_LENGTH_12_BITS 0x20 // 12bits
Wayne Roberts 0:abb827c65ff5 210 #define PREAMBLE_LENGTH_16_BITS 0x30 // 16bits
Wayne Roberts 0:abb827c65ff5 211 #define PREAMBLE_LENGTH_20_BITS 0x40 // 20bits
Wayne Roberts 0:abb827c65ff5 212 #define PREAMBLE_LENGTH_24_BITS 0x50 // 24bits
Wayne Roberts 0:abb827c65ff5 213 #define PREAMBLE_LENGTH_28_BITS 0x60 // 28bits
Wayne Roberts 0:abb827c65ff5 214 #define PREAMBLE_LENGTH_32_BITS 0x70 // 32bits
Wayne Roberts 0:abb827c65ff5 215
Wayne Roberts 0:abb827c65ff5 216 // FLRC pktParam2
Wayne Roberts 0:abb827c65ff5 217 #define FLRC_SYNC_NOSYNC 0x00 // 21 bits preamble
Wayne Roberts 0:abb827c65ff5 218 #define FLRC_SYNC_WORD_LEN_P32S 0x04 // 21 bits preamble + 32bit syncword
Wayne Roberts 0:abb827c65ff5 219
Wayne Roberts 0:abb827c65ff5 220 // FLRC modParam1
Wayne Roberts 0:abb827c65ff5 221 #define FLRC_BR_1_300_BW_1_2 0x45 // 1.3Mb/s 1.2MHz
Wayne Roberts 0:abb827c65ff5 222 #define FLRC_BR_1_000_BW_1_2 0x69 // 1.04Mb/s 1.2MHz
Wayne Roberts 0:abb827c65ff5 223 #define FLRC_BR_0_650_BW_0_6 0x86 // 0.65Mb/s 0.6MHz
Wayne Roberts 0:abb827c65ff5 224 #define FLRC_BR_0_520_BW_0_6 0xAA // 0.52Mb/s 0.6MHz
Wayne Roberts 0:abb827c65ff5 225 #define FLRC_BR_0_325_BW_0_3 0xC7 // 0.325Mb/s 0.3MHz
Wayne Roberts 0:abb827c65ff5 226 #define FLRC_BR_0_260_BW_0_3 0xEB // 0.26Mb/s 0.3MHz
Wayne Roberts 0:abb827c65ff5 227
Wayne Roberts 0:abb827c65ff5 228 // FLRC modParam2
Wayne Roberts 0:abb827c65ff5 229 #define FLRC_CR_1_2 0x00
Wayne Roberts 0:abb827c65ff5 230 #define FLRC_CR_3_4 0x02
Wayne Roberts 0:abb827c65ff5 231 #define FLRC_CR_1_0 0x04
Wayne Roberts 0:abb827c65ff5 232
Wayne Roberts 0:abb827c65ff5 233 typedef enum {
Wayne Roberts 0:abb827c65ff5 234 STDBY_RC = 0, // Device running on RC 13MHz, set STDBY_RC mode
Wayne Roberts 0:abb827c65ff5 235 STDBY_XOSC // Device running on XTAL 52MHz, set STDBY_XOSC mode
Wayne Roberts 0:abb827c65ff5 236 } stby_t;
Wayne Roberts 0:abb827c65ff5 237
Wayne Roberts 0:abb827c65ff5 238 typedef union {
Wayne Roberts 0:abb827c65ff5 239 struct {
Wayne Roberts 0:abb827c65ff5 240 uint8_t PreambleLength; // param1
Wayne Roberts 0:abb827c65ff5 241 uint8_t HeaderType; // param2
Wayne Roberts 0:abb827c65ff5 242 uint8_t PayloadLength; // param3
Wayne Roberts 0:abb827c65ff5 243 uint8_t crc; // param4
Wayne Roberts 0:abb827c65ff5 244 uint8_t InvertIQ; // param5
Wayne Roberts 0:abb827c65ff5 245 uint8_t unused[2];
Wayne Roberts 0:abb827c65ff5 246 } lora;
Wayne Roberts 0:abb827c65ff5 247 struct {
Wayne Roberts 0:abb827c65ff5 248 uint8_t PreambleLength; // param1
Wayne Roberts 0:abb827c65ff5 249 uint8_t SyncWordLength; // param2 bytes
Wayne Roberts 0:abb827c65ff5 250 uint8_t SyncWordMatch; // param3
Wayne Roberts 0:abb827c65ff5 251 uint8_t HeaderType; // param4
Wayne Roberts 0:abb827c65ff5 252 uint8_t PayloadLength; // param5
Wayne Roberts 0:abb827c65ff5 253 uint8_t CRCLength; // param6
Wayne Roberts 0:abb827c65ff5 254 uint8_t Whitening; // param7
Wayne Roberts 0:abb827c65ff5 255 } gfskFLRC;
Wayne Roberts 0:abb827c65ff5 256 struct {
Wayne Roberts 0:abb827c65ff5 257 uint8_t ConnectionState; // param1
Wayne Roberts 0:abb827c65ff5 258 uint8_t CrcLength; // param2
Wayne Roberts 0:abb827c65ff5 259 uint8_t BleTestPayload; // param3
Wayne Roberts 0:abb827c65ff5 260 uint8_t Whitening; // param4
Wayne Roberts 0:abb827c65ff5 261 uint8_t unused[3];
Wayne Roberts 0:abb827c65ff5 262 } ble;
Wayne Roberts 0:abb827c65ff5 263 uint8_t buf[7];
Wayne Roberts 0:abb827c65ff5 264 } PacketParams_t;
Wayne Roberts 0:abb827c65ff5 265
Wayne Roberts 0:abb827c65ff5 266 //TODO -- uint8_t LowDatarateOptimize; // param4
Wayne Roberts 0:abb827c65ff5 267 typedef union {
Wayne Roberts 0:abb827c65ff5 268 struct {
Wayne Roberts 0:abb827c65ff5 269 uint8_t spreadingFactor; // param1
Wayne Roberts 0:abb827c65ff5 270 uint8_t bandwidth; // param2
Wayne Roberts 0:abb827c65ff5 271 uint8_t codingRate; // param3
Wayne Roberts 0:abb827c65ff5 272 } lora;
Wayne Roberts 0:abb827c65ff5 273 struct {
Wayne Roberts 0:abb827c65ff5 274 uint8_t bitrateBandwidth; // param1
Wayne Roberts 0:abb827c65ff5 275 uint8_t ModulationIndex; // param1
Wayne Roberts 0:abb827c65ff5 276 uint8_t ModulationShaping; // param3
Wayne Roberts 0:abb827c65ff5 277 } gfskBle;
Wayne Roberts 0:abb827c65ff5 278 struct {
Wayne Roberts 0:abb827c65ff5 279 uint8_t bitrateBandwidth; // param1
Wayne Roberts 0:abb827c65ff5 280 uint8_t CodingRate; // param1
Wayne Roberts 0:abb827c65ff5 281 uint8_t ModulationShaping; // param3
Wayne Roberts 0:abb827c65ff5 282 } flrc;
Wayne Roberts 0:abb827c65ff5 283 uint8_t buf[3];
Wayne Roberts 0:abb827c65ff5 284 } ModulationParams_t;
Wayne Roberts 0:abb827c65ff5 285
Wayne Roberts 0:abb827c65ff5 286 typedef union {
Wayne Roberts 0:abb827c65ff5 287 struct { //
Wayne Roberts 0:abb827c65ff5 288 uint16_t TxDone : 1; // 0
Wayne Roberts 0:abb827c65ff5 289 uint16_t RxDone : 1; // 1
Wayne Roberts 0:abb827c65ff5 290 uint16_t SyncWordValid: 1; // 2
Wayne Roberts 0:abb827c65ff5 291 uint16_t SyncWordError: 1; // 3
Wayne Roberts 0:abb827c65ff5 292 uint16_t HeaderValid: 1; // 4
Wayne Roberts 0:abb827c65ff5 293 uint16_t HeaderError: 1; // 5
Wayne Roberts 0:abb827c65ff5 294 uint16_t CrcError: 1; // 6
Wayne Roberts 0:abb827c65ff5 295 uint16_t RangingSlaveResponseDone: 1; // 7
Wayne Roberts 0:abb827c65ff5 296 uint16_t RangingSlaveRequestDiscard: 1; // 8
Wayne Roberts 0:abb827c65ff5 297 uint16_t RangingMasterResultValid: 1; // 9
Wayne Roberts 0:abb827c65ff5 298 uint16_t RangingMasterTimeout: 1; // 10
Wayne Roberts 0:abb827c65ff5 299 uint16_t RangingMasterRequestValid: 1; // 11
Wayne Roberts 0:abb827c65ff5 300 uint16_t CadDone: 1; // 12
Wayne Roberts 0:abb827c65ff5 301 uint16_t CadDetected: 1; // 13
Wayne Roberts 0:abb827c65ff5 302 uint16_t RxTxTimeout: 1; // 14
Wayne Roberts 0:abb827c65ff5 303 uint16_t PreambleDetected: 1; // 15
Wayne Roberts 0:abb827c65ff5 304 } bits;
Wayne Roberts 0:abb827c65ff5 305 uint16_t word;
Wayne Roberts 0:abb827c65ff5 306 } IrqFlags_t;
Wayne Roberts 0:abb827c65ff5 307
Wayne Roberts 0:abb827c65ff5 308 typedef union {
Wayne Roberts 0:abb827c65ff5 309 struct { //
Wayne Roberts 0:abb827c65ff5 310 uint8_t busy : 1; // 0
Wayne Roberts 0:abb827c65ff5 311 uint8_t reserved : 1; // 1
Wayne Roberts 0:abb827c65ff5 312 uint8_t cmdStatus : 3; // 2,3,4
Wayne Roberts 0:abb827c65ff5 313 uint8_t chipMode : 3; // 5,6,7
Wayne Roberts 0:abb827c65ff5 314 } bits;
Wayne Roberts 0:abb827c65ff5 315 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 316 } status_t;
Wayne Roberts 0:abb827c65ff5 317
Wayne Roberts 0:abb827c65ff5 318 typedef enum {
Wayne Roberts 0:abb827c65ff5 319 CHIPMODE_NONE = 0,
Wayne Roberts 0:abb827c65ff5 320 CHIPMODE_RX,
Wayne Roberts 0:abb827c65ff5 321 CHIPMODE_TX
Wayne Roberts 0:abb827c65ff5 322 } chipMode_e;
Wayne Roberts 0:abb827c65ff5 323
Wayne Roberts 0:abb827c65ff5 324 typedef union {
Wayne Roberts 0:abb827c65ff5 325 struct {
Wayne Roberts 0:abb827c65ff5 326 uint8_t dataRAM : 1; // 0
Wayne Roberts 0:abb827c65ff5 327 uint8_t dataBuffer : 1; // 1
Wayne Roberts 0:abb827c65ff5 328 uint8_t instructionRAM : 1; // 2
Wayne Roberts 0:abb827c65ff5 329 } retentionBits;
Wayne Roberts 0:abb827c65ff5 330 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 331 } sleepConfig_t;
Wayne Roberts 0:abb827c65ff5 332
Wayne Roberts 0:abb827c65ff5 333
Wayne Roberts 0:abb827c65ff5 334 typedef union {
Wayne Roberts 0:abb827c65ff5 335 struct {
Wayne Roberts 0:abb827c65ff5 336 status_t status;
Wayne Roberts 0:abb827c65ff5 337 uint8_t rfu;
Wayne Roberts 0:abb827c65ff5 338 uint8_t rssiSync;
Wayne Roberts 0:abb827c65ff5 339 struct {
Wayne Roberts 0:abb827c65ff5 340 uint8_t pktCtrlBusy : 1; // 0
Wayne Roberts 0:abb827c65ff5 341 uint8_t packetReceived : 1; // 1
Wayne Roberts 0:abb827c65ff5 342 uint8_t headerReceived : 1; // 2
Wayne Roberts 0:abb827c65ff5 343 uint8_t AbortErr : 1; // 3
Wayne Roberts 0:abb827c65ff5 344 uint8_t CrcError : 1; // 4
Wayne Roberts 0:abb827c65ff5 345 uint8_t LengthError : 1; // 5
Wayne Roberts 0:abb827c65ff5 346 uint8_t SyncError : 1; // 6
Wayne Roberts 0:abb827c65ff5 347 uint8_t reserved : 1; // 7
Wayne Roberts 0:abb827c65ff5 348 } errors;
Wayne Roberts 0:abb827c65ff5 349 struct {
Wayne Roberts 0:abb827c65ff5 350 uint8_t pktSent : 1; // 0
Wayne Roberts 0:abb827c65ff5 351 uint8_t res41 : 4; // 1,2,3,4
Wayne Roberts 0:abb827c65ff5 352 uint8_t rxNoAck : 1; // 5
Wayne Roberts 0:abb827c65ff5 353 uint8_t res67 : 1; // 6,7
Wayne Roberts 0:abb827c65ff5 354 } pkt_status;
Wayne Roberts 0:abb827c65ff5 355 struct {
Wayne Roberts 0:abb827c65ff5 356 uint8_t syncAddrsCode : 3; // 0,1,2
Wayne Roberts 0:abb827c65ff5 357 uint8_t reserved : 5; // 3,4,5,6,7
Wayne Roberts 0:abb827c65ff5 358 } sync;
Wayne Roberts 0:abb827c65ff5 359 } ble_gfsk_flrc;
Wayne Roberts 0:abb827c65ff5 360 struct {
Wayne Roberts 0:abb827c65ff5 361 status_t status;
Wayne Roberts 0:abb827c65ff5 362 uint8_t rssiSync;
Wayne Roberts 0:abb827c65ff5 363 uint8_t snr;
Wayne Roberts 5:aba2d8b29702 364 uint8_t reserved[3];
Wayne Roberts 0:abb827c65ff5 365 } lora;
Wayne Roberts 0:abb827c65ff5 366 uint8_t buf[6];
Wayne Roberts 0:abb827c65ff5 367 } pktStatus_t;
Wayne Roberts 0:abb827c65ff5 368
Wayne Roberts 0:abb827c65ff5 369 /**********************************************************/
Wayne Roberts 0:abb827c65ff5 370
Wayne Roberts 0:abb827c65ff5 371 typedef union {
Wayne Roberts 0:abb827c65ff5 372 struct {
Wayne Roberts 0:abb827c65ff5 373 uint8_t irq0 : 2; // 0,1
Wayne Roberts 0:abb827c65ff5 374 uint8_t irq1 : 2; // 2,3
Wayne Roberts 0:abb827c65ff5 375 uint8_t alt_func : 4; // 4,5,6,7
Wayne Roberts 0:abb827c65ff5 376 } bits;
Wayne Roberts 0:abb827c65ff5 377 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 378 } RegAfIrq_t; // 0x053
Wayne Roberts 0:abb827c65ff5 379
Wayne Roberts 0:abb827c65ff5 380 typedef union {
Wayne Roberts 0:abb827c65ff5 381 struct {
Wayne Roberts 0:abb827c65ff5 382 uint8_t dig_fe_en : 1; // 0
Wayne Roberts 0:abb827c65ff5 383 uint8_t zero_if : 1; // 1
Wayne Roberts 0:abb827c65ff5 384 uint8_t if_sel : 1; // 2
Wayne Roberts 0:abb827c65ff5 385 uint8_t lora_mode : 1; // 3
Wayne Roberts 0:abb827c65ff5 386 uint8_t res : 4; // 4,5,6,7
Wayne Roberts 0:abb827c65ff5 387 } bits;
Wayne Roberts 0:abb827c65ff5 388 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 389 } RegCfg_t; // 0x880
Wayne Roberts 0:abb827c65ff5 390
Wayne Roberts 0:abb827c65ff5 391 typedef union {
Wayne Roberts 0:abb827c65ff5 392 struct {
Wayne Roberts 0:abb827c65ff5 393 uint8_t bw : 3; // 0,1,2
Wayne Roberts 0:abb827c65ff5 394 uint8_t res3 : 1; // 3
Wayne Roberts 0:abb827c65ff5 395 uint8_t interp_factor : 1; // 4,5,6
Wayne Roberts 0:abb827c65ff5 396 uint8_t res7 : 1; // 7
Wayne Roberts 0:abb827c65ff5 397 } bits;
Wayne Roberts 0:abb827c65ff5 398 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 399 } RegRxBw_t; // 0x881
Wayne Roberts 0:abb827c65ff5 400
Wayne Roberts 0:abb827c65ff5 401 typedef union {
Wayne Roberts 0:abb827c65ff5 402 struct {
Wayne Roberts 0:abb827c65ff5 403 uint8_t DccBw : 2; // 0,1
Wayne Roberts 0:abb827c65ff5 404 uint8_t DccInit : 1; // 2
Wayne Roberts 0:abb827c65ff5 405 uint8_t IgnoreAutoDccRestart : 1; // 3
Wayne Roberts 0:abb827c65ff5 406 uint8_t DccForce : 1; // 4
Wayne Roberts 0:abb827c65ff5 407 uint8_t DccBypass : 1; // 5
Wayne Roberts 0:abb827c65ff5 408 uint8_t DccFreeze : 1; // 6
Wayne Roberts 0:abb827c65ff5 409 uint8_t res7 : 1; // 7
Wayne Roberts 0:abb827c65ff5 410 } bits;
Wayne Roberts 0:abb827c65ff5 411 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 412 } RegDcc_t; // 0x882
Wayne Roberts 0:abb827c65ff5 413
Wayne Roberts 0:abb827c65ff5 414 typedef union {
Wayne Roberts 0:abb827c65ff5 415 struct {
Wayne Roberts 0:abb827c65ff5 416 uint8_t SyncAdrsIrqStatus : 1; // 0
Wayne Roberts 0:abb827c65ff5 417 uint8_t PreambleIrqStatus : 1; // 1
Wayne Roberts 0:abb827c65ff5 418 uint8_t dtb_pa2sel_sel : 2; // 2,3
Wayne Roberts 0:abb827c65ff5 419 uint8_t db_out_sel : 1; // 4
Wayne Roberts 0:abb827c65ff5 420 uint8_t reserved : 3; // 5,6,7
Wayne Roberts 0:abb827c65ff5 421 } bits;
Wayne Roberts 0:abb827c65ff5 422 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 423 } GfskDemodStatus_t; // 0x8cb
Wayne Roberts 0:abb827c65ff5 424
Wayne Roberts 0:abb827c65ff5 425 typedef union {
Wayne Roberts 0:abb827c65ff5 426 struct {
Wayne Roberts 0:abb827c65ff5 427 uint8_t cont_rx : 1; // 0
Wayne Roberts 0:abb827c65ff5 428 uint8_t modem_bw : 3; // 1,2,3
Wayne Roberts 0:abb827c65ff5 429 uint8_t modem_sf : 4; // 4,5,6,7
Wayne Roberts 0:abb827c65ff5 430 } bits;
Wayne Roberts 0:abb827c65ff5 431 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 432 } LoRaPktPar0_t; // 0x902
Wayne Roberts 0:abb827c65ff5 433
Wayne Roberts 0:abb827c65ff5 434 typedef union {
Wayne Roberts 0:abb827c65ff5 435 struct {
Wayne Roberts 0:abb827c65ff5 436 uint8_t coding_rate : 3; // 0,1,2
Wayne Roberts 0:abb827c65ff5 437 uint8_t ppm_offset : 2; // 3,4
Wayne Roberts 0:abb827c65ff5 438 uint8_t tx_mode : 1; // 5
Wayne Roberts 0:abb827c65ff5 439 uint8_t rxinvert_iq : 1; // 6
Wayne Roberts 0:abb827c65ff5 440 uint8_t implicit_header : 1; // 7
Wayne Roberts 0:abb827c65ff5 441 } bits;
Wayne Roberts 0:abb827c65ff5 442 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 443 } LoRaPktPar1_t; // 0x903
Wayne Roberts 0:abb827c65ff5 444
Wayne Roberts 0:abb827c65ff5 445 typedef union {
Wayne Roberts 0:abb827c65ff5 446 struct {
Wayne Roberts 0:abb827c65ff5 447 uint8_t cadrxtx : 2; // 0,1
Wayne Roberts 0:abb827c65ff5 448 uint8_t sd_en : 1; // 2
Wayne Roberts 0:abb827c65ff5 449 uint8_t modem_en : 1; // 3
Wayne Roberts 0:abb827c65ff5 450 uint8_t lora_register_clear : 1; // 4
Wayne Roberts 0:abb827c65ff5 451 uint8_t crc_en : 1; // 5
Wayne Roberts 0:abb827c65ff5 452 uint8_t fine_sync_en : 1; // 6
Wayne Roberts 0:abb827c65ff5 453 uint8_t sd_force_tx_mode : 1; // 7
Wayne Roberts 0:abb827c65ff5 454 } bits;
Wayne Roberts 0:abb827c65ff5 455 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 456 } LoRaLrCtl_t; // 0x904
Wayne Roberts 0:abb827c65ff5 457
Wayne Roberts 0:abb827c65ff5 458 typedef union {
Wayne Roberts 0:abb827c65ff5 459 struct {
Wayne Roberts 0:abb827c65ff5 460 uint8_t preamble_symb1_nb : 4; // 0,1,2,3
Wayne Roberts 0:abb827c65ff5 461 uint8_t preamble_symb_nb_exp : 4; // 4,5,6,7
Wayne Roberts 0:abb827c65ff5 462 } bits;
Wayne Roberts 0:abb827c65ff5 463 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 464 } LoRaPreambleReg_t; // 0x93f
Wayne Roberts 0:abb827c65ff5 465
Wayne Roberts 0:abb827c65ff5 466 typedef union {
Wayne Roberts 0:abb827c65ff5 467 struct {
Wayne Roberts 0:abb827c65ff5 468 uint8_t rx_state : 4; // 0,1,2,3
Wayne Roberts 0:abb827c65ff5 469 uint8_t tx_state : 3; // 4,5,6
Wayne Roberts 0:abb827c65ff5 470 uint8_t tx_ranging_on : 1; // 7
Wayne Roberts 0:abb827c65ff5 471 } bits;
Wayne Roberts 0:abb827c65ff5 472 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 473 } LoRaModemStat_t; // 0x95c
Wayne Roberts 0:abb827c65ff5 474
Wayne Roberts 0:abb827c65ff5 475 typedef union {
Wayne Roberts 0:abb827c65ff5 476 struct {
Wayne Roberts 0:abb827c65ff5 477 uint8_t mod_on : 1; // 0
Wayne Roberts 0:abb827c65ff5 478 uint8_t sd_on : 1; // 1
Wayne Roberts 0:abb827c65ff5 479 uint8_t mod_mode : 1; // 2 0=gfsk 1=flora
Wayne Roberts 0:abb827c65ff5 480 uint8_t tx_mode : 1; // 3
Wayne Roberts 0:abb827c65ff5 481 uint8_t gf_bt : 2; // 4,5 0=noFilter 1=BT1.0 2=BT0.5 3=BT0.3
Wayne Roberts 0:abb827c65ff5 482 uint8_t rxtxn : 1; // 6 0=tx 1=rx
Wayne Roberts 0:abb827c65ff5 483 uint8_t cal_en : 1; // 7
Wayne Roberts 0:abb827c65ff5 484 } bits;
Wayne Roberts 0:abb827c65ff5 485 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 486 } FskCfg_t; // 0x9a0
Wayne Roberts 0:abb827c65ff5 487
Wayne Roberts 0:abb827c65ff5 488 typedef union {
Wayne Roberts 0:abb827c65ff5 489 struct {
Wayne Roberts 0:abb827c65ff5 490 uint8_t freqDev : 5; // 0,1,2,3,4
Wayne Roberts 0:abb827c65ff5 491 uint8_t sd_in_lsb : 1; // 5
Wayne Roberts 0:abb827c65ff5 492 uint8_t disable_dclk : 1; // 7
Wayne Roberts 0:abb827c65ff5 493 } bits;
Wayne Roberts 0:abb827c65ff5 494 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 495 } FskModDfH_t; // 0x9a1
Wayne Roberts 0:abb827c65ff5 496
Wayne Roberts 0:abb827c65ff5 497 typedef union {
Wayne Roberts 0:abb827c65ff5 498 struct {
Wayne Roberts 0:abb827c65ff5 499 uint8_t pkt_ctrl_on : 1; // 0
Wayne Roberts 0:abb827c65ff5 500 uint8_t pkt_start_p : 1; // 1 0=idle 1=busy
Wayne Roberts 0:abb827c65ff5 501 uint8_t pkt_abort_p : 1; // 2
Wayne Roberts 0:abb827c65ff5 502 uint8_t pkt_software_clear_p : 1; // 3 software reset pulse
Wayne Roberts 0:abb827c65ff5 503 uint8_t pkt_rx_ntx : 1; // 4 0=tx 1=rx
Wayne Roberts 0:abb827c65ff5 504 uint8_t pkt_len_format : 1; // 5 0=fixed 1=dynamic
Wayne Roberts 0:abb827c65ff5 505 uint8_t pkt_protocol : 2; // 6,7 1=flora 2=ble 3=generic
Wayne Roberts 0:abb827c65ff5 506 } bits;
Wayne Roberts 0:abb827c65ff5 507 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 508 } PktCtrl0_t; // 0x9c0
Wayne Roberts 0:abb827c65ff5 509
Wayne Roberts 0:abb827c65ff5 510 typedef union {
Wayne Roberts 0:abb827c65ff5 511 struct {
Wayne Roberts 0:abb827c65ff5 512 uint8_t infinite_preamble : 1; // 0
Wayne Roberts 0:abb827c65ff5 513 uint8_t sync_adrs_len : 3; // 1,2,3 bytes = sync_adrs_len + 1
Wayne Roberts 0:abb827c65ff5 514 uint8_t preamble_len : 3; // 4,5,6 bits = (preamble_len*4) + 4
Wayne Roberts 0:abb827c65ff5 515 uint8_t preamble_det_on : 1; // 7
Wayne Roberts 0:abb827c65ff5 516 } gfsk;
Wayne Roberts 0:abb827c65ff5 517 struct {
Wayne Roberts 0:abb827c65ff5 518 uint8_t reserved : 1; // 0
Wayne Roberts 0:abb827c65ff5 519 uint8_t sync_adrs_len : 2; // 1,2 0=preamble only 1=preamble+16bitSync 2=preamble+32bitSync
Wayne Roberts 0:abb827c65ff5 520 uint8_t reserved3 : 1; // 3
Wayne Roberts 0:abb827c65ff5 521 uint8_t agc_preamble_len : 3; // 4,5,6
Wayne Roberts 0:abb827c65ff5 522 uint8_t reserved7 : 1; // 7
Wayne Roberts 0:abb827c65ff5 523 } flrc;
Wayne Roberts 0:abb827c65ff5 524 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 525 } PktCtrl1_t; // 0x9c1
Wayne Roberts 0:abb827c65ff5 526
Wayne Roberts 0:abb827c65ff5 527 typedef union {
Wayne Roberts 0:abb827c65ff5 528 struct {
Wayne Roberts 0:abb827c65ff5 529 uint8_t payload_len_N : 1; // 0
Wayne Roberts 0:abb827c65ff5 530 uint8_t tx_reserved : 4; // 1,2,3,4
Wayne Roberts 0:abb827c65ff5 531 uint8_t tx_no_ack : 1; // 5
Wayne Roberts 0:abb827c65ff5 532 uint8_t tx_pkt_type : 2; // 6,7 defines packet type field in header
Wayne Roberts 0:abb827c65ff5 533 } bits;
Wayne Roberts 0:abb827c65ff5 534 struct {
Wayne Roberts 0:abb827c65ff5 535 uint8_t infinite_rxtx : 1; // 0
Wayne Roberts 0:abb827c65ff5 536 uint8_t tx_payload_src : 1; // 1 0=fifo 1=prbs
Wayne Roberts 0:abb827c65ff5 537 uint8_t tx_type : 3; // 2,3,4 payload for BLE tx test
Wayne Roberts 0:abb827c65ff5 538 uint8_t cs_type : 3; // 5,6,7 connection state
Wayne Roberts 0:abb827c65ff5 539 } ble;
Wayne Roberts 0:abb827c65ff5 540 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 541 } PktTxHeader_t; // 0x9c2
Wayne Roberts 0:abb827c65ff5 542
Wayne Roberts 0:abb827c65ff5 543 typedef union {
Wayne Roberts 0:abb827c65ff5 544 struct {
Wayne Roberts 0:abb827c65ff5 545 uint8_t crc_in_fifo : 1; // 0 1=received CRC written to FIFO at end
Wayne Roberts 0:abb827c65ff5 546 uint8_t flora_coding_rate : 2; // 1,2
Wayne Roberts 0:abb827c65ff5 547 uint8_t whit_disable : 1; // 3
Wayne Roberts 0:abb827c65ff5 548 uint8_t crc_mode : 2; // 4,5 0=nocrc 1=1byteCRC 2=2byteCRC 3=reserved
Wayne Roberts 0:abb827c65ff5 549 uint8_t rssi_mode : 2; // 6,7 enables rssi read mode of received packets 0=none 1=syncReg 2=avgReg 3=bothRegs
Wayne Roberts 0:abb827c65ff5 550 } bits;
Wayne Roberts 0:abb827c65ff5 551 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 552 } PktBitStreamCtrl_t; // 0x9c4
Wayne Roberts 0:abb827c65ff5 553
Wayne Roberts 0:abb827c65ff5 554 typedef union {
Wayne Roberts 0:abb827c65ff5 555 struct {
Wayne Roberts 0:abb827c65ff5 556 uint8_t flora_preamble_20_16 : 5; // 0,1,2,3,4
Wayne Roberts 0:abb827c65ff5 557 uint8_t data_rate : 3; // 5,6,7
Wayne Roberts 0:abb827c65ff5 558 } bits;
Wayne Roberts 0:abb827c65ff5 559 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 560 } FloraPreambleHi_t; // 0x9ca
Wayne Roberts 0:abb827c65ff5 561
Wayne Roberts 0:abb827c65ff5 562 typedef union {
Wayne Roberts 0:abb827c65ff5 563 struct {
Wayne Roberts 0:abb827c65ff5 564 uint8_t sync_adrs_bit_detections : 2; // 0,1 last bits matching 0=none 1=2bits 2=4bits 3=8bits
Wayne Roberts 0:abb827c65ff5 565 uint8_t reserved : 2; // 2,3
Wayne Roberts 0:abb827c65ff5 566 uint8_t sync_addr_mask : 3; // 4,5,6
Wayne Roberts 0:abb827c65ff5 567 uint8_t cont_rx : 1; // 7
Wayne Roberts 0:abb827c65ff5 568 } ble;
Wayne Roberts 0:abb827c65ff5 569 struct {
Wayne Roberts 0:abb827c65ff5 570 uint8_t sync_adrs_errors : 4; // 0,12,3 how many bit errors are tolerated in sync word
Wayne Roberts 0:abb827c65ff5 571 uint8_t sync_addr_mask : 3; // 4,5,6
Wayne Roberts 0:abb827c65ff5 572 uint8_t cont_rx : 1; // 7
Wayne Roberts 0:abb827c65ff5 573 } gfskflrc;
Wayne Roberts 0:abb827c65ff5 574 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 575 } PktSyncAdrs_t; // 0x9cd
Wayne Roberts 0:abb827c65ff5 576
Wayne Roberts 0:abb827c65ff5 577 typedef union {
Wayne Roberts 0:abb827c65ff5 578 struct {
Wayne Roberts 0:abb827c65ff5 579 uint8_t tolerated_errors : 4; // 0,1,2,3 for sync word
Wayne Roberts 0:abb827c65ff5 580 uint8_t valid_status : 1; // 4 0x98c-98f is valid
Wayne Roberts 0:abb827c65ff5 581 uint8_t reserved : 3; // 5,6,7
Wayne Roberts 0:abb827c65ff5 582 } bits;
Wayne Roberts 0:abb827c65ff5 583 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 584 } FlrcSyncWordCtrl_t; // 0x98b
Wayne Roberts 0:abb827c65ff5 585
Wayne Roberts 0:abb827c65ff5 586 typedef union {
Wayne Roberts 0:abb827c65ff5 587 struct {
Wayne Roberts 0:abb827c65ff5 588 uint8_t sync_word_irq : 1; // 0
Wayne Roberts 0:abb827c65ff5 589 uint8_t preamble_irq : 1; // 1
Wayne Roberts 0:abb827c65ff5 590 uint8_t stop_radio : 1; // 3
Wayne Roberts 0:abb827c65ff5 591 uint8_t reserved : 1; // 4,5,6,7
Wayne Roberts 0:abb827c65ff5 592 } bits;
Wayne Roberts 0:abb827c65ff5 593 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 594 } FlrcIrqStatus_t; // 0x990
Wayne Roberts 0:abb827c65ff5 595
Wayne Roberts 0:abb827c65ff5 596 typedef union {
Wayne Roberts 0:abb827c65ff5 597 struct {
Wayne Roberts 0:abb827c65ff5 598 uint8_t tx_pwr : 5; // 0,1,2,3,4
Wayne Roberts 0:abb827c65ff5 599 uint8_t ramp_time : 3; // 5,6,7
Wayne Roberts 0:abb827c65ff5 600 } bits;
Wayne Roberts 0:abb827c65ff5 601 uint8_t octet;
Wayne Roberts 0:abb827c65ff5 602 } PaPwrCtrl_t; // 0xa53
Wayne Roberts 0:abb827c65ff5 603
Wayne Roberts 0:abb827c65ff5 604 class SX128x {
Wayne Roberts 0:abb827c65ff5 605 public:
Wayne Roberts 2:8a442c3511ae 606 SX128x(SPI&, PinName nss, PinName busy, PinName diox, PinName nrst);
Wayne Roberts 0:abb827c65ff5 607
Wayne Roberts 0:abb827c65ff5 608 static Callback<void()> diox_topHalf; // low latency ISR context
Wayne Roberts 0:abb827c65ff5 609 Callback<void()> txDone; // user context
Wayne Roberts 0:abb827c65ff5 610 void (*rxDone)(uint8_t size, const pktStatus_t*); // user context
Wayne Roberts 0:abb827c65ff5 611 Callback<void()> chipModeChange; // read chipMode_e chipMode
Wayne Roberts 0:abb827c65ff5 612 void (*timeout)(bool tx); // user context
Wayne Roberts 5:aba2d8b29702 613 void (*cadDone)(bool);
Wayne Roberts 0:abb827c65ff5 614
Wayne Roberts 0:abb827c65ff5 615 //! RF transmit packet buffer
Wayne Roberts 0:abb827c65ff5 616 uint8_t tx_buf[256]; // lora fifo size
Wayne Roberts 0:abb827c65ff5 617
Wayne Roberts 0:abb827c65ff5 618 //! RF receive packet buffer
Wayne Roberts 0:abb827c65ff5 619 uint8_t rx_buf[256]; // lora fifo size
Wayne Roberts 0:abb827c65ff5 620
Wayne Roberts 0:abb827c65ff5 621 void service(void);
Wayne Roberts 0:abb827c65ff5 622 uint8_t xfer(uint8_t opcode, uint8_t writeLen, uint8_t readLen, uint8_t* buf);
Wayne Roberts 0:abb827c65ff5 623 void start_tx(uint8_t pktLen, float timeout_ms); // tx_buf must be filled prior to calling
Wayne Roberts 0:abb827c65ff5 624 void start_rx(float timeout_ms); // timeout given in milliseconds, -1 = forever
Wayne Roberts 2:8a442c3511ae 625 void hw_reset(void);
Wayne Roberts 0:abb827c65ff5 626 void set_tx_dbm(int8_t dbm);
Wayne Roberts 0:abb827c65ff5 627 void setMHz(float);
Wayne Roberts 0:abb827c65ff5 628 float getMHz(void);
Wayne Roberts 0:abb827c65ff5 629 void setStandby(stby_t);
Wayne Roberts 2:8a442c3511ae 630 void setSleep(bool warm);
Wayne Roberts 0:abb827c65ff5 631 void setFS(void);
Wayne Roberts 5:aba2d8b29702 632 void setCAD(void);
Wayne Roberts 0:abb827c65ff5 633 void writeReg(uint16_t addr, uint32_t data, uint8_t len);
Wayne Roberts 0:abb827c65ff5 634 uint32_t readReg(uint16_t addr, uint8_t len);
Wayne Roberts 0:abb827c65ff5 635 void setPacketType(uint8_t);
Wayne Roberts 0:abb827c65ff5 636 uint8_t getPacketType(void);
Wayne Roberts 0:abb827c65ff5 637 void ReadBuffer(uint8_t size, uint8_t offset);
Wayne Roberts 0:abb827c65ff5 638 uint64_t getSyncAddr(uint8_t num);
Wayne Roberts 0:abb827c65ff5 639 void setSyncAddr(uint8_t num, uint64_t sa);
Wayne Roberts 0:abb827c65ff5 640 void setRegulator(uint8_t);
Wayne Roberts 0:abb827c65ff5 641 void setBufferBase(uint8_t txAddr, uint8_t rxAddr);
Wayne Roberts 0:abb827c65ff5 642
Wayne Roberts 0:abb827c65ff5 643 chipMode_e chipMode;
Wayne Roberts 0:abb827c65ff5 644 uint8_t periodBase;
Wayne Roberts 0:abb827c65ff5 645 static const float timeOutStep[4];
Wayne Roberts 2:8a442c3511ae 646 uint8_t pktType;
Wayne Roberts 0:abb827c65ff5 647
Wayne Roberts 0:abb827c65ff5 648 private:
Wayne Roberts 0:abb827c65ff5 649 SPI& spi;
Wayne Roberts 0:abb827c65ff5 650 DigitalOut nss;
Wayne Roberts 0:abb827c65ff5 651 DigitalIn busy;
Wayne Roberts 0:abb827c65ff5 652 InterruptIn diox;
Wayne Roberts 2:8a442c3511ae 653 DigitalInOut nrst;
Wayne Roberts 0:abb827c65ff5 654 static void dioxisr(void);
Wayne Roberts 0:abb827c65ff5 655 bool sleeping;
Wayne Roberts 0:abb827c65ff5 656 };
Wayne Roberts 0:abb827c65ff5 657
Wayne Roberts 0:abb827c65ff5 658 #endif /* SX126x_H */
Wayne Roberts 0:abb827c65ff5 659