sx12xx.h

00001 #include "mbed.h"
00002 #ifndef SX126x_H
00003 #define SX126x_H
00004 
00005 #define RC_TICKS_PER_MS         0.015625    /* 64KHz */
00006 #define RC_TICKS_PER_US         15.625    /* 64KHz */
00007 
00008 #define XTAL_FREQ_HZ            32000000
00009 #define FREQ_DIV                33554432
00010 #define FREQ_STEP               0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) )
00011 #define MHZ_TO_FRF              1048576 // = (1<<25) / Fxtal_MHz
00012 #define KHZ_TO_FRF              1048.576
00013 #define HZ_TO_FRF               1.048576 // = (1<<25) / Fxtal_Hz
00014 
00015 /***************************************************************/
00016 #define OPCODE_RESET_STATS              0x00
00017 #define OPCODE_CLEAR_IRQ_STATUS         0x02
00018 #define OPCODE_CLEAR_DEVICE_ERRORS      0x07
00019 #define OPCODE_SET_DIO_IRQ_PARAMS       0x08
00020 #define OPCODE_WRITE_REGISTER           0x0d
00021 #define OPCODE_WRITE_BUFFER             0x0e
00022 #define OPCODE_GET_STATS                0x10
00023 #define OPCODE_GET_PACKET_TYPE          0x11
00024 #define OPCODE_GET_IRQ_STATUS           0x12
00025 #define OPCODE_GET_RX_BUFFER_STATUS     0x13
00026 #define OPCODE_GET_PACKET_STATUS        0x14
00027 #define OPCODE_GET_RSSIINST             0x15
00028 #define OPCODE_GET_DEVICE_ERRORS        0x17
00029 #define OPCODE_READ_REGISTER            0x1d
00030 #define OPCODE_READ_BUFFER              0x1e
00031 #define OPCODE_SET_STANDBY              0x80
00032 #define OPCODE_SET_RX                   0x82
00033 #define OPCODE_SET_TX                   0x83
00034 #define OPCODE_SET_SLEEP                0x84
00035 #define OPCODE_SET_RF_FREQUENCY         0x86
00036 #define OPCODE_SET_CAD_PARAM            0x88
00037 #define OPCODE_CALIBRATE                0x89
00038 #define OPCODE_SET_PACKET_TYPE          0x8a
00039 #define OPCODE_SET_MODULATION_PARAMS    0x8b
00040 #define OPCODE_SET_PACKET_PARAMS        0x8c
00041 #define OPCODE_SET_TX_PARAMS            0x8e
00042 #define OPCODE_SET_BUFFER_BASE_ADDR     0x8f
00043 #define OPCODE_SET_FALLBACK_MODE        0x93
00044 #define OPCODE_SET_RX_DUTY_CYCLE        0x94
00045 #define OPCODE_SET_PA_CONFIG            0x95
00046 #define OPCODE_SET_REGULATOR_MODE       0x96
00047 #define OPCODE_SET_DIO3_AS_TCXO_CTRL    0x97
00048 #define OPCODE_CALIBRATE_IMAGE          0x98
00049 #define OPCODE_SET_DIO2_AS_RFSWITCH     0x9d
00050 #define OPCODE_STOP_TIMER_ON_PREAMBLE   0x9f
00051 #define OPCODE_SET_LORA_SYMBOL_TIMEOUT  0xa0
00052 #define OPCODE_GET_STATUS               0xc0
00053 #define OPCODE_SET_FS                   0xc1
00054 #define OPCODE_SET_CAD                  0xc5
00055 #define OPCODE_SET_TX_CARRIER           0xd1
00056 #define OPCODE_SET_TX_PREAMBLE          0xd2
00057 /***************************************************************/
00058 #define PACKET_TYPE_GFSK    0
00059 #define PACKET_TYPE_LORA    1
00060 
00061 #define HEADER_TYPE_VARIABLE_LENGTH     0
00062 #define HEADER_TYPE_FIXED_LENGTH        1
00063 
00064 #define LROA_CRC_OFF                    0
00065 #define LORA_CRC_ON                     1
00066 
00067 #define STANDARD_IQ                     0
00068 #define INVERTED_IQ                     1
00069 
00070 /* direct register access */
00071 #define REG_ADDR_IRQ_STATUS            0x58a // 16bit
00072 #define REG_ADDR_IRQ_MASK              0x58c // 16bit
00073 #define REG_ADDR_MODCFG                0x680 // 8bit
00074 #define REG_ADDR_BITRATE               0x6a1 // 24bit fsk
00075 #define REG_ADDR_FREQDEV               0x6a4 // 18bit fsk
00076 #define REG_ADDR_SHAPECFG              0x6a7 // 5bit
00077 #define REG_ADDR_FSK_DEMOD_CFO         0x6b0 // 12bit  center frequency offset
00078 #define REG_ADDR_FSK_PKTCTRL0          0x6b3 // 8bit
00079 #define REG_ADDR_FSK_PKTCTRL1          0x6b4 // 3bit
00080 #define REG_ADDR_FSK_PREAMBLE_TXLEN    0x6b5 // 16bit
00081 #define REG_ADDR_FSK_SYNC_LEN          0x6b7 // 7bit
00082 #define REG_ADDR_FSK_PKTCTRL1A         0x6b8 // 14bit   5bits+9bits
00083 #define REG_ADDR_FSK_PKTCTRL2          0x6ba // 8bit
00084 #define REG_ADDR_FSK_PAYLOAD_LEN       0x6bb // 8bit
00085 #define REG_ADDR_FSK_CRCINIT           0x6bc // 16bit
00086 #define REG_ADDR_FSK_CRCPOLY           0x6be // 16bit
00087 #define REG_ADDR_SYNCADDR              0x6c0 // 64bit fsk
00088 #define REG_ADDR_NODEADDR              0x6cd // 8bit fsk
00089 #define REG_ADDR_BROADCAST             0x6ce // 8bit fsk
00090 #define REG_ADDR_NODEADDRCOMP          0x6cf // 2bit fsk
00091 
00092 #define REG_ADDR_LORA_TXPKTLEN         0x702 // 8bit
00093 #define REG_ADDR_LORA_CONFIG0          0x703 // 8bit  bw/sf
00094 #define REG_ADDR_LORA_CONFIG1          0x704 // 8bit  ppm_offset, fixlen, invertiq, cr
00095 #define REG_ADDR_LORA_CONFIG2          0x705 // 8bit  crcType
00096 #define REG_ADDR_LORA_IRQ_MASK         0x70a // 24bit
00097 #define REG_ADDR_LORA_CONFIG9          0x724 // 8bit
00098 #define REG_ADDR_LORA_PREAMBLE_SYMBNB  0x73a // 16bit
00099 #define REG_ADDR_LORA_CAD_PN_RATIO     0x73e // 8bit
00100 #define REG_ADDR_LORA_CAD_MINPEAK      0x73f // 8bit
00101 #define REG_ADDR_LORA_SYNC             0x740 // config22, config23: frame sync peak position
00102 #define REG_ADDR_LORA_STATUS           0x76b //
00103 
00104 #define REG_ADDR_DIGFECTL              0x804 // 6bits
00105 #define REG_ADDR_BWSEL                 0x807 // 5bits
00106 #define REG_ADDR_RANDOM                0x819 //        ro
00107 #define REG_ADDR_PA_CTRL0              0x880 // 8bits
00108 #define REG_ADDR_PA_CTRL1              0x881 // 8bits
00109 #define REG_ADDR_DIG_CTRL              0x882 // 8bits
00110 #define REG_ADDR_PWR_CTRL              0x883 // 8bits
00111 #define REG_ADDR_I_GAIN                0x884 // 8bits  integral gain in pi filter
00112 #define REG_ADDR_P_GAIN                0x885 // 8bits  proportional gain in pi filter
00113 #define REG_ADDR_SDCFG0                0x889 // 
00114 #define REG_ADDR_RFFREQ                0x88b // 31bits
00115 #define REG_ADDR_FREQ_OFFSET           0x88f // 19bits
00116 #define REG_ADDR_AGC_SENSI_ADJ         0x8ac // 8bits
00117 #define REG_ADDR_ANACTRL6              0x8d7 // 6bits
00118 #define REG_ADDR_ANACTRL7              0x8d8 // 6bits
00119 #define REG_ADDR_ANACTRL15             0x8e1 // 7bits
00120 #define REG_ADDR_ANACTRL16             0x8e2
00121 #define REG_ADDR_PA_CTRL1B             0x8e6
00122 #define REG_ADDR_OCP                   0x8e7 // 6bits   Imax        2.5mA steps
00123 #define REG_ADDR_IMAX_OFFSET           0x8e8 // 5bits  OCP offset
00124 #define REG_ADDR_XTA_TRIM              0x911 // crystal trim only in xosc
00125 #define REG_ADDR_XTB_TRIM              0x912 // crystal trim only in xosc
00126 #define REG_ADDR_                      0x
00127 
00128 /**********************************************/
00129 
00130 #define SET_RAMP_10U        0x00
00131 #define SET_RAMP_20U        0x01
00132 #define SET_RAMP_40U        0x02
00133 #define SET_RAMP_80U        0x03
00134 #define SET_RAMP_200U       0x04
00135 #define SET_RAMP_800U       0x05
00136 #define SET_RAMP_1700U      0x06
00137 #define SET_RAMP_3400U      0x07
00138 
00139 
00140 
00141 typedef union {
00142     struct {
00143         uint8_t rtcWakeup    : 1;    // 0
00144         uint8_t rfu          : 1;    // 1
00145         uint8_t warmStart    : 1;    // 2
00146     } bits;
00147     uint8_t octet;
00148 } sleepConfig_t;
00149 
00150 typedef union {
00151     struct {
00152         uint8_t PreambleLengthHi;   // param1
00153         uint8_t PreambleLengthLo;   // param2
00154         uint8_t HeaderType;         // param3
00155         uint8_t PayloadLength;      // param4
00156         uint8_t CRCType;            // param5
00157         uint8_t InvertIQ;           // param6
00158         uint8_t unused[2];
00159     } lora;
00160     struct {
00161         uint8_t PreambleLengthHi;       // param1
00162         uint8_t PreambleLengthLo;       // param2
00163         uint8_t PreambleDetectorLength; // param3
00164         uint8_t SyncWordLength;         // param4
00165         uint8_t AddrComp;               // param5
00166         uint8_t PacketType;             // param6
00167         uint8_t PayloadLength;          // param7
00168         uint8_t CRCType;                // param8
00169         uint8_t Whitening;              // param9
00170     } gfsk;
00171     uint8_t buf[9];
00172 } PacketParams_t;
00173 
00174 typedef union {
00175     struct {
00176         uint8_t phase_step:     2; // 0,1
00177         uint8_t sd_mode:        1; // 2
00178         uint8_t sd_en:          1; // 3
00179         uint8_t div_ratio_edge: 1; // 4
00180         uint8_t reserved:       3; // 5,6,7
00181     } bits;
00182     uint8_t octet;
00183 } sdCfg0_t;  // at 0x889
00184 
00185 typedef union {
00186     struct {
00187         uint8_t power_mode:     2; // 0,1
00188         uint8_t sensi_adjust:   6; // 2,3,4,5,6,7
00189     } bits;
00190     uint8_t octet;
00191 } AgcSensiAdj_t;  // at 0x8ac
00192 
00193 #define LORA_BW_7           0x00 // 7.81 kHz real
00194 #define LORA_BW_10          0x08 // 10.42 kHz real
00195 #define LORA_BW_15          0x01 // 15.63 kHz real
00196 #define LORA_BW_20          0x09 // 20.83 kHz real
00197 #define LORA_BW_31          0x02 // 31.25 kHz real
00198 #define LORA_BW_41          0x0A // 41.67 kHz real
00199 #define LORA_BW_62          0x03 // 62.50 kHz real
00200 #define LORA_BW_125         0x04 // 125 kHz real
00201 #define LORA_BW_250         0x05 // 250 kHz real
00202 #define LORA_BW_500         0x06 // 500 kHz real
00203 
00204 #define LORA_CR_4_5         1
00205 #define LORA_CR_4_6         2
00206 #define LORA_CR_4_7         3
00207 #define LORA_CR_4_8         4
00208 
00209 #define GFSK_PREAMBLE_DETECTOR_OFF                  0x00
00210 #define GFSK_PREAMBLE_DETECTOR_LENGTH_8BITS         0x04
00211 #define GFSK_PREAMBLE_DETECTOR_LENGTH_16BITS        0x05
00212 #define GFSK_PREAMBLE_DETECTOR_LENGTH_24BITS        0x06
00213 #define GFSK_PREAMBLE_DETECTOR_LENGTH_32BITS        0x07
00214 
00215 #define GFSK_WHITENING_OFF      0
00216 #define GFSK_WHITENING_ON       1
00217 
00218 #define GFSK_CRC_OFF            0x01
00219 #define GFSK_CRC_1_BYTE         0x00
00220 #define GFSK_CRC_2_BYTE         0x02
00221 #define GFSK_CRC_1_BYTE_INV     0x04
00222 #define GFSK_CRC_2_BYTE_INV     0x06
00223 
00224 #define GFSK_RX_BW_4800             0x1F 
00225 #define GFSK_RX_BW_5800             0x17 
00226 #define GFSK_RX_BW_7300             0x0F 
00227 #define GFSK_RX_BW_9700             0x1E 
00228 #define GFSK_RX_BW_11700            0x16 
00229 #define GFSK_RX_BW_14600            0x0E 
00230 #define GFSK_RX_BW_19500            0x1D 
00231 #define GFSK_RX_BW_23400            0x15 
00232 #define GFSK_RX_BW_29300            0x0D 
00233 #define GFSK_RX_BW_39000            0x1C 
00234 #define GFSK_RX_BW_46900            0x14 
00235 #define GFSK_RX_BW_58600            0x0C 
00236 #define GFSK_RX_BW_78200            0x1B 
00237 #define GFSK_RX_BW_93800            0x13 
00238 #define GFSK_RX_BW_117300           0x0B 
00239 #define GFSK_RX_BW_156200           0x1A 
00240 #define GFSK_RX_BW_187200           0x12 
00241 #define GFSK_RX_BW_234300           0x0A 
00242 #define GFSK_RX_BW_312000           0x19 
00243 #define GFSK_RX_BW_373600           0x11 
00244 #define GFSK_RX_BW_467000           0x09 
00245 
00246 #define GFSK_SHAPE_NONE             0x00
00247 #define GFSK_SHAPE_BT0_3            0x08
00248 #define GFSK_SHAPE_BT0_5            0x09
00249 #define GFSK_SHAPE_BT0_7            0x0a
00250 #define GFSK_SHAPE_BT1_0            0x0b
00251 
00252 typedef enum {
00253     STBY_RC = 0,
00254     STBY_XOSC
00255 } stby_t;
00256 
00257 #define MOD_TYPE_IQ      0
00258 #define MOD_TYPE_FSK     1
00259 #define MOD_TYPE_MSK     2
00260 #define MOD_TYPE_LORA    3
00261 typedef union {
00262     struct {
00263         uint8_t mod_order :  2; // 0,1   modulation size      2points to 16points
00264         uint8_t mod_type  :  2; // 2,3   IQ, FSK, MSK, LoRa
00265         uint8_t data_src  :  1; // 4     
00266         uint8_t clk_src   :  2; // 5,6
00267         uint8_t mod_en    :  1; // 7
00268     } bits;
00269     uint8_t octet;
00270 } modCfg_t;  // at 0x680  fsk
00271 
00272 typedef union {
00273     struct {
00274         uint8_t bt           :  2; // 0,1    0=BT0.3   1=BT0.5   2=BT0.7  3=BT1.0
00275         uint8_t double_rate  :  1; // 2      double oversampling rate
00276         uint8_t pulse_shape  :  2; // 3,4    0=noFilter  1=gaussian   2=RRC
00277         uint8_t res          :  3; // 5,6,7
00278     } bits;
00279     uint8_t octet;
00280 } shapeCfg_t;  // at 0x6a7 fsk
00281 
00282 typedef union {
00283     struct {
00284         uint8_t pkt_start_p    :  1; // 0   ros1
00285         uint8_t pkt_abort_p    :  1; // 1   ros1
00286         uint8_t pkt_sw_clr_p   :  1; // 2   ros1
00287         uint8_t crl_status_p   :  1; // 3   ros1
00288         uint8_t clk_en         :  1; // 4   ro
00289         uint8_t pkt_rx_ntx     :  1; // 5
00290         uint8_t pkt_len_format :  1; // 6
00291         uint8_t cont_rx        :  1; // 7
00292     } bits;
00293     uint8_t octet;
00294 } pktCtrl0_t;  // at 0x6b3 fsk
00295 
00296 typedef union {
00297     struct {
00298         uint8_t preamble_len_rx :  2; // 0,1   number of preamble bits detected
00299         uint8_t preamble_det_on :  1; // 2   enable rx-sde preamble detector
00300         uint8_t res             :  5; // 7
00301     } bits;
00302     uint8_t octet;
00303 } pktCtrl1_t;  // at 0x6b4 fsk
00304 
00305 typedef union {
00306     struct {
00307         uint16_t whit_init_val       : 9; // 0...8     at 0x6b9
00308         uint16_t infinite_seq_en     : 1; // 9
00309         uint16_t infinite_seq_select : 2; // 10,11
00310         uint16_t cont_tx             : 1; // 12
00311         uint16_t sync_det_on         : 1; // 13
00312         uint16_t res                 : 2; // 14,15
00313     } bits;
00314     uint16_t word;
00315 } PktCtrl1a_t;  // at 0x6b8
00316 
00317 typedef union {
00318     struct {
00319         uint8_t crc_disable    :  1; // 0
00320         uint8_t crc_len        :  1; // 1     0=1byte  1=2byte
00321         uint8_t crc_inv        :  1; // 2
00322         uint8_t crc_in_fifo    :  1; // 3
00323         uint8_t whit_enable    :  1; // 4
00324         uint8_t manchester_en  :  1; // 5
00325         uint8_t rssi_mode      :  2; // 6,7
00326     } bits;
00327     uint8_t octet;
00328 } pktCtrl2_t;  // at 0x6ba fsk
00329 
00330 
00331 typedef union {
00332     struct {
00333         uint8_t modem_sf:  4; // 0,1,2,3
00334         uint8_t modem_bw:  4; // 4,5,6,7
00335     } bits;
00336     uint8_t octet;
00337 } loraConfig0_t;  // at 0x703
00338 
00339 typedef union {
00340     struct {
00341         uint8_t tx_coding_rate :  3; // 0,1,2
00342         uint8_t ppm_offset      : 2; // 3,4     aka long range mode
00343         uint8_t tx_mode         : 1; // 5
00344         uint8_t rx_invert_iq    : 1; // 6
00345         uint8_t implicit_header : 1; // 7     0=variable length packet
00346     } bits;
00347     uint8_t octet;
00348 } loraConfig1_t;  // at 0x704
00349 
00350 typedef union {
00351     struct {
00352         uint8_t cad_rxtx               :  2; // 0,1
00353         uint8_t tx_payload_crc16_en    :  1; // 2
00354         uint8_t cont_rx                :  1; // 3
00355         uint8_t freeze_dagc_upon_synch :  2; // 4,5
00356         uint8_t fine_sync_en           :  1; // 6
00357         uint8_t res                    :  1; // 7
00358     } bits;
00359     uint8_t octet;
00360 } loraConfig2_t;  // at 0x705
00361 
00362 typedef union {
00363     struct {
00364         uint32_t est_freq_error               :20; // 0..19
00365         uint32_t header_crc16_en              : 1; // 20
00366         uint32_t rf_en_request                : 2; // 21,22
00367         uint32_t raw_ranging_result_available : 1; // 23
00368         uint32_t unused                       : 8; // 24..31
00369     } bits;
00370     uint32_t dword;
00371 } loraStatus1_t;  // at 0x76b
00372 
00373 typedef union {
00374     struct {
00375         uint8_t inv_edge        : 1; // 0
00376         uint8_t swap_iq         : 1; // 1
00377         uint8_t dig_fe_clear    : 1; // 2
00378         uint8_t lora_ngfsk      : 1; // 3   data buffer selection lora/gfsk
00379         uint8_t adc_from_dio    : 1; // 4
00380         uint8_t lora_pre_cf_en  : 1; // 5
00381         uint8_t res             : 2; // 6,7
00382     } bits;
00383     uint8_t octet;
00384 } digFeCtrl_t;  // at 0x804
00385 
00386 typedef union {
00387     struct {
00388         uint8_t exp  : 3; // 0,1,2
00389         uint8_t mant : 2; // 3,4
00390         uint8_t res  : 3; // 5,6,7
00391     } bits;
00392     uint8_t octet;
00393 } bwSel_t;  // at 0x807   rx_bw
00394 
00395 typedef union {
00396     struct {
00397         uint8_t reg_pa_discharge_en : 1; // 0
00398         uint8_t reg_pa_boost_en     : 1; // 1
00399         uint8_t dac_pol             : 2; // 2,3
00400     } bits;
00401     uint8_t octet;
00402 } paCtrl0_t;  // at 0x880
00403 
00404 typedef union {
00405     struct {
00406         uint8_t boost_delay : 6; // 0,1,2,3,4,5
00407         uint8_t boost_width : 2; // 6,7
00408     } bits;
00409     uint8_t octet;
00410 } paCtrl1_t;  // at 0x881
00411 
00412 typedef union {
00413     struct {
00414         uint8_t ramp_on           : 1; // 0
00415         uint8_t ramp_down         : 1; // 1
00416         uint8_t ramp_up           : 1; // 2
00417         uint8_t ramp_status       : 1; // 3
00418         uint8_t force_dac_code_en : 1; // 4
00419         uint8_t pa_mod_en         : 1; // 5
00420     } bits;
00421     uint8_t octet;
00422 } DigCtrl_t;  // at 0x882
00423 
00424 typedef union {
00425     struct {
00426         uint8_t tx_pwr    : 5; // 0,1,2,3,4
00427         uint8_t ramp_time : 3; // 5,6,7
00428     } bits;
00429     uint8_t octet;
00430 } PwrCtrl_t;  // at 0x883
00431 
00432 
00433 
00434 
00435 typedef union {
00436     struct {
00437         uint8_t pa_hp_ena_ana        : 1; // 0
00438         uint8_t tx_ena_bat           : 1; // 1
00439         uint8_t pa_dctrim_select_ana : 4; // 2,3,4,5        paDutyCycle
00440         uint8_t res                  : 2; // 6,7
00441     } bits;
00442     uint8_t octet;
00443 } AnaCtrl6_t;  // at 0x8d7
00444 
00445 typedef union {
00446     struct {
00447         uint8_t pa_lp_ena_ana         : 1; // 0
00448         uint8_t pa_clamp_code_bat     : 3; // 1,2,3
00449         uint8_t pa_clamp_override_bat : 1; // 4
00450         uint8_t pa_hp_sel_ana         : 3; // 5,6,7     hpMax
00451     } bits;
00452     uint8_t octet;
00453 } AnaCtrl7_t;  // at 0x8d8
00454 
00455 typedef union {
00456     struct {
00457         uint8_t reg_pa_comp_poarity_ana  : 1; // 0
00458         uint8_t reg_pa_comp_en_ana       : 1; // 1
00459         uint8_t fir_dac_sign_ana         : 2; // 2,3
00460         uint8_t fir_dac_pole_ana         : 3; // 4,5,6
00461         uint8_t res                      : 1; // 7
00462     } bits;
00463     uint8_t octet;
00464 } AnaCtrl15_t;  // at 0x8e1
00465 
00466 typedef union {
00467     struct {
00468         uint8_t force_ref         : 1; // 0
00469         uint8_t pa_voltage_lim_en : 1; // 1
00470         uint8_t pa_current_lim_en : 1; // 2
00471         uint8_t tx_mode_bat       : 1; // 3  deviceSel  0=hipower   1=lopower  take precedence over hpp_mode
00472         uint8_t hp_mode           : 1; // 4 hi-power submode  0=14dBm LUT,   1=20dBm LUT
00473     } bits;
00474     uint8_t octet;
00475 } PaCtrl1b_t;  // at 0x8e6
00476 
00477 typedef union {
00478     struct {
00479         uint8_t spreadingFactor; // param1
00480         uint8_t bandwidth; // param2
00481         uint8_t codingRate; // param3
00482         uint8_t LowDatarateOptimize; // param4
00483     } lora;
00484     struct {
00485         uint8_t bitrateHi;  // param1
00486         uint8_t bitrateMid; // param2
00487         uint8_t bitrateLo;  // param3
00488         uint8_t PulseShape; // param4
00489         uint8_t bandwidth;  // param5
00490         uint8_t fdevHi;     // param6
00491         uint8_t fdevMid;    // param7
00492         uint8_t fdevLo;     // param8
00493     } gfsk;
00494     uint8_t buf[8];
00495 } ModulationParams_t;
00496 
00497 typedef union {
00498     struct {    // 
00499         uint16_t TxDone           : 1;    // 0
00500         uint16_t RxDone           : 1;    // 1
00501         uint16_t PreambleDetected : 1;    // 2
00502         uint16_t SyncWordValid    : 1;    // 3
00503         uint16_t HeaderValid      : 1;    // 4
00504         uint16_t HeaderErr        : 1;    // 5
00505         uint16_t CrCerr           : 1;    // 6
00506         uint16_t CadDone          : 1;    // 7
00507         uint16_t CadDetected      : 1;    // 8
00508         uint16_t Timeout          : 1;    // 9
00509         uint16_t res              : 6;    // 10,11,12,13,14,15
00510     } bits;
00511     uint16_t word;
00512 } IrqFlags_t;
00513 
00514 typedef union {
00515     struct {    // 
00516         uint8_t _reserved    : 1;    // 0
00517         uint8_t cmdStatus    : 3;    // 1,2,3
00518         uint8_t chipMode     : 3;    // 4,5,6
00519         uint8_t reserved_    : 1;    // 7
00520     } bits;
00521     uint8_t octet;
00522 } status_t;
00523 
00524 typedef enum {
00525     CHIPMODE_NONE = 0,
00526     CHIPMODE_RX,
00527     CHIPMODE_TX
00528 } chipMote_e;
00529 
00530 class SX126x {
00531     public:
00532         SX126x(SPI&, PinName nss, PinName busy, PinName dio1);
00533 
00534 
00535         void hw_reset(PinName nrst);
00536         void xfer(uint8_t opcode, uint8_t writeLen, uint8_t readLen, uint8_t* buf);
00537         void setPacketType(uint8_t);
00538         uint8_t getPacketType(void);
00539         uint8_t setMHz(float);
00540         float getMHz(void);
00541 
00542         /* start_tx and start_rx assumes DIO1 is connected, and only pin used to generate radio interrupt */
00543         void start_tx(uint8_t pktLen);  // tx_buf must be filled prior to calling
00544 
00545 #define RX_TIMEOUT_SINGLE         0x000000  /* stop RX after first packet */
00546 #define RX_TIMEOUT_CONTINUOUS     0xffffff  /* keep RXing */
00547         void start_rx(unsigned);
00548 
00549         void ReadBuffer(uint8_t size, uint8_t offset);
00550         void SetDIO2AsRfSwitchCtrl(uint8_t);
00551         void set_tx_dbm(bool is1262, int8_t dbm);
00552         uint32_t readReg(uint16_t addr, uint8_t len);
00553         void writeReg(uint16_t addr, uint32_t data, uint8_t len);
00554         void setStandby(stby_t);
00555         void setSleep(bool warmStart, bool rtcWakeup);
00556         void setFS(void);
00557         void setCAD(void);
00558         void setBufferBase(uint8_t txAddr, uint8_t rxAddr);
00559 
00560         static Callback<void()> dio1_topHalf;    // low latency ISR context
00561         void service(void);
00562         Callback<void()> txDone; // user context
00563         Callback<void()> chipModeChange; // read chipMode_e chipMode
00564         void (*rxDone)(uint8_t size, float rssi, float snr); // user context
00565         void (*timeout)(bool tx); // user context
00566         void (*cadDone)(bool detected); // user context
00567         void (*preambleDetected)(void); // user context
00568 
00569         //! RF transmit packet buffer
00570         uint8_t tx_buf[256];    // lora fifo size
00571         
00572         //! RF receive packet buffer
00573         uint8_t rx_buf[256];    // lora fifo size
00574 
00575         /** Test if dio1 pin is asserted 
00576          */
00577         inline bool getDIO1(void) { return dio1.read(); }
00578         void PrintChipStatus(status_t);
00579         chipMote_e chipMode;
00580 
00581     private:
00582         SPI& spi;
00583         DigitalOut nss;
00584         DigitalIn busy;
00585         InterruptIn dio1;
00586         static void dio1isr(void);
00587         bool sleeping;
00588 };
00589 
00590 #endif /* SX126x_H */
00591