wayne roberts / lib_sx9500

sx9500 driver

Dependents:   Senet NAMote scpi_sx127x NAMote72_Utility scpi_sx127x_firstTest

sx9500.h@1:aa30dc96dc77, 2015-05-08 (annotated)

Committer:
dudmuck
Date:
Fri May 08 01:32:54 2015 +0000
Revision:
1:aa30dc96dc77
Parent:
0:d46a1b9267a3 
added interrupt handling

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 0:d46a1b9267a3 1 #include "mbed.h"
dudmuck 0:d46a1b9267a3 2
dudmuck 0:d46a1b9267a3 3
dudmuck 0:d46a1b9267a3 4 #define SX9500_REG_IRQSRC 0x00
dudmuck 0:d46a1b9267a3 5 #define SX9500_REG_STAT 0x01
dudmuck 0:d46a1b9267a3 6 #define SX9500_REG_IRQMSK 0x03
dudmuck 0:d46a1b9267a3 7 #define SX9500_REG_PROXCTRL0 0x06
dudmuck 0:d46a1b9267a3 8 #define SX9500_REG_PROXCTRL1 0x07
dudmuck 0:d46a1b9267a3 9 #define SX9500_REG_PROXCTRL2 0x08
dudmuck 0:d46a1b9267a3 10 #define SX9500_REG_PROXCTRL3 0x09
dudmuck 0:d46a1b9267a3 11 #define SX9500_REG_PROXCTRL4 0x0A
dudmuck 0:d46a1b9267a3 12 #define SX9500_REG_PROXCTRL5 0x0B
dudmuck 0:d46a1b9267a3 13 #define SX9500_REG_PROXCTRL6 0x0C
dudmuck 0:d46a1b9267a3 14 #define SX9500_REG_PROXCTRL7 0x0D
dudmuck 0:d46a1b9267a3 15 #define SX9500_REG_PROXCTRL8 0x0E
dudmuck 0:d46a1b9267a3 16 #define SX9500_REG_SENSORSEL 0x20
dudmuck 0:d46a1b9267a3 17 #define SX9500_REG_USEMSB 0x21
dudmuck 0:d46a1b9267a3 18 #define SX9500_REG_USELSB 0x22
dudmuck 0:d46a1b9267a3 19 #define SX9500_REG_AVGMSB 0x23
dudmuck 0:d46a1b9267a3 20 #define SX9500_REG_AVGLSB 0x24
dudmuck 0:d46a1b9267a3 21 #define SX9500_REG_DIFFMSB 0x25
dudmuck 0:d46a1b9267a3 22 #define SX9500_REG_DIFFLSB 0x26
dudmuck 0:d46a1b9267a3 23 #define SX9500_REG_OFFSETMSB 0x27
dudmuck 0:d46a1b9267a3 24 #define SX9500_REG_OFFSETLSB 0x28
dudmuck 0:d46a1b9267a3 25 #define SX9500_REG_RESET 0x7F
dudmuck 0:d46a1b9267a3 26
dudmuck 0:d46a1b9267a3 27 #define SX9500_RESET_CMD 0xDE
dudmuck 0:d46a1b9267a3 28
dudmuck 1:aa30dc96dc77 29 typedef union {
dudmuck 1:aa30dc96dc77 30 struct { // sx9500 register 0x09
dudmuck 1:aa30dc96dc77 31 uint8_t txen_stat : 1; // 0
dudmuck 1:aa30dc96dc77 32 uint8_t reserved : 2; // 1,2
dudmuck 1:aa30dc96dc77 33 uint8_t conv_done : 1; // 3
dudmuck 1:aa30dc96dc77 34 uint8_t comp_done : 1; // 4
dudmuck 1:aa30dc96dc77 35 uint8_t far : 1; // 5
dudmuck 1:aa30dc96dc77 36 uint8_t close : 1; // 6
dudmuck 1:aa30dc96dc77 37 uint8_t reset : 1; // 7
dudmuck 1:aa30dc96dc77 38 } bits;
dudmuck 1:aa30dc96dc77 39 uint8_t octet;
dudmuck 1:aa30dc96dc77 40 } RegIrqSrc_t;
dudmuck 1:aa30dc96dc77 41
dudmuck 1:aa30dc96dc77 42 typedef union {
dudmuck 1:aa30dc96dc77 43 struct { // sx9500 register 0x09
dudmuck 1:aa30dc96dc77 44 uint8_t compstat : 4; // 0,1,2,3
dudmuck 1:aa30dc96dc77 45 uint8_t proxstat0 : 1; // 4
dudmuck 1:aa30dc96dc77 46 uint8_t proxstat1 : 1; // 5
dudmuck 1:aa30dc96dc77 47 uint8_t proxstat2 : 1; // 6
dudmuck 1:aa30dc96dc77 48 uint8_t proxstat3 : 1; // 7
dudmuck 1:aa30dc96dc77 49 } bits;
dudmuck 1:aa30dc96dc77 50 uint8_t octet;
dudmuck 1:aa30dc96dc77 51 } RegStat_t;
dudmuck 1:aa30dc96dc77 52
dudmuck 1:aa30dc96dc77 53 typedef union {
dudmuck 1:aa30dc96dc77 54 struct { // sx9500 register 0x06
dudmuck 1:aa30dc96dc77 55 uint8_t sensor_en : 4; // 0,1,2,3
dudmuck 1:aa30dc96dc77 56 uint8_t scan_period : 3; // 4,5,6
dudmuck 1:aa30dc96dc77 57 uint8_t reserved : 1; // 7
dudmuck 1:aa30dc96dc77 58 } bits;
dudmuck 1:aa30dc96dc77 59 uint8_t octet;
dudmuck 1:aa30dc96dc77 60 } RegProxCtrl0_t;
dudmuck 1:aa30dc96dc77 61
dudmuck 1:aa30dc96dc77 62 typedef union {
dudmuck 1:aa30dc96dc77 63 struct { // sx9500 register 0x09
dudmuck 1:aa30dc96dc77 64 uint8_t raw_filt : 2; // 0,1
dudmuck 1:aa30dc96dc77 65 uint8_t reserved : 2; // 2,3
dudmuck 1:aa30dc96dc77 66 uint8_t doze_period : 2; // 4,5
dudmuck 1:aa30dc96dc77 67 uint8_t doze_en : 1; // 6
dudmuck 1:aa30dc96dc77 68 uint8_t res7 : 1; // 7
dudmuck 1:aa30dc96dc77 69 } bits;
dudmuck 1:aa30dc96dc77 70 uint8_t octet;
dudmuck 1:aa30dc96dc77 71 } RegProxCtrl3_t;
dudmuck 1:aa30dc96dc77 72
dudmuck 0:d46a1b9267a3 73 class SX9500 {
dudmuck 0:d46a1b9267a3 74 public:
dudmuck 1:aa30dc96dc77 75 SX9500(I2C& r, PinName en_pin, PinName nirq_pin);
dudmuck 0:d46a1b9267a3 76 ~SX9500();
dudmuck 0:d46a1b9267a3 77 //void try_read(void);
dudmuck 0:d46a1b9267a3 78 uint8_t read_single(uint8_t addr);
dudmuck 0:d46a1b9267a3 79 void read(uint8_t addr, uint8_t *dst_buf, int length);
dudmuck 0:d46a1b9267a3 80 void write(uint8_t addr, uint8_t data);
dudmuck 0:d46a1b9267a3 81 void reset(void);
dudmuck 1:aa30dc96dc77 82 //uint16_t get_sensor(char CSn);
dudmuck 1:aa30dc96dc77 83 void print_sensor(char CSn);
dudmuck 1:aa30dc96dc77 84 void set_active(bool);
dudmuck 1:aa30dc96dc77 85 bool get_active(void);
dudmuck 1:aa30dc96dc77 86 void service(void);
dudmuck 1:aa30dc96dc77 87
dudmuck 1:aa30dc96dc77 88 RegIrqSrc_t RegIrqSrc;
dudmuck 1:aa30dc96dc77 89 RegProxCtrl0_t RegProxCtrl0;
dudmuck 0:d46a1b9267a3 90
dudmuck 0:d46a1b9267a3 91 private:
dudmuck 0:d46a1b9267a3 92 I2C& m_i2c;
dudmuck 0:d46a1b9267a3 93 DigitalOut m_txen;
dudmuck 1:aa30dc96dc77 94 DigitalIn m_nirq; // polled irq pin, because i2c is shared
dudmuck 0:d46a1b9267a3 95 };
dudmuck 0:d46a1b9267a3 96