mma8451q driver

Dependents:   nRF51822_DataLogger_PowerImpulseCounter scpi_sx127x NAMote72_Utility

Committer:
dudmuck
Date:
Wed Mar 18 00:58:44 2015 +0000
Revision:
0:cb0046a629c1
Child:
1:778b685c3ad0
mma8451q driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 0:cb0046a629c1 1 #include "mma8451q.h"
dudmuck 0:cb0046a629c1 2 /* turn on: CTRL_REG1 active_bit = 1
dudmuck 0:cb0046a629c1 3 * back to standby: CTRL_REG1 active_bit = 0
dudmuck 0:cb0046a629c1 4 */
dudmuck 0:cb0046a629c1 5
dudmuck 0:cb0046a629c1 6 /* STANDBY: SYSMOD = 00 */
dudmuck 0:cb0046a629c1 7
dudmuck 0:cb0046a629c1 8 /*
dudmuck 0:cb0046a629c1 9 * MMA8451 I2C address
dudmuck 0:cb0046a629c1 10 */
dudmuck 0:cb0046a629c1 11 #define MMA8451_I2C_ADDRESS 0x38 //0x1C
dudmuck 0:cb0046a629c1 12
dudmuck 0:cb0046a629c1 13
dudmuck 0:cb0046a629c1 14 MMA8451Q::MMA8451Q(I2C& r) : m_i2c(r)
dudmuck 0:cb0046a629c1 15 {
dudmuck 0:cb0046a629c1 16 /* char cmd[2];
dudmuck 0:cb0046a629c1 17
dudmuck 0:cb0046a629c1 18 cmd[0] = MMA8451_ID;
dudmuck 0:cb0046a629c1 19 m_i2c.read(MMA8451_I2C_ADDRESS, cmd, 1);*/
dudmuck 0:cb0046a629c1 20
dudmuck 0:cb0046a629c1 21 }
dudmuck 0:cb0046a629c1 22
dudmuck 0:cb0046a629c1 23 MMA8451Q::~MMA8451Q()
dudmuck 0:cb0046a629c1 24 {
dudmuck 0:cb0046a629c1 25 }
dudmuck 0:cb0046a629c1 26
dudmuck 0:cb0046a629c1 27 void MMA8451Q::read(uint8_t addr, uint8_t *dst_buf, int length)
dudmuck 0:cb0046a629c1 28 {
dudmuck 0:cb0046a629c1 29 char cmd[2];
dudmuck 0:cb0046a629c1 30
dudmuck 0:cb0046a629c1 31 cmd[0] = addr;
dudmuck 0:cb0046a629c1 32 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 1, true))
dudmuck 0:cb0046a629c1 33 printf("MMA8451Q write-fail\n");
dudmuck 0:cb0046a629c1 34 if (m_i2c.read(MMA8451_I2C_ADDRESS, (char *)dst_buf, length))
dudmuck 0:cb0046a629c1 35 printf("MMA8451Q read-fail\n");
dudmuck 0:cb0046a629c1 36 }
dudmuck 0:cb0046a629c1 37
dudmuck 0:cb0046a629c1 38 uint8_t MMA8451Q::read_single(uint8_t addr)
dudmuck 0:cb0046a629c1 39 {
dudmuck 0:cb0046a629c1 40 char cmd[2];
dudmuck 0:cb0046a629c1 41
dudmuck 0:cb0046a629c1 42 cmd[0] = addr;
dudmuck 0:cb0046a629c1 43 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 1, true))
dudmuck 0:cb0046a629c1 44 printf("MMA8451Q write-fail\n");
dudmuck 0:cb0046a629c1 45 if (m_i2c.read(MMA8451_I2C_ADDRESS, cmd, 1))
dudmuck 0:cb0046a629c1 46 printf("MMA8451Q read-fail\n");
dudmuck 0:cb0046a629c1 47
dudmuck 0:cb0046a629c1 48 return cmd[0];
dudmuck 0:cb0046a629c1 49 }
dudmuck 0:cb0046a629c1 50
dudmuck 0:cb0046a629c1 51 void MMA8451Q::print_regs()
dudmuck 0:cb0046a629c1 52 {
dudmuck 0:cb0046a629c1 53 printf("ID: %x\n", read_single(MMA8451_ID));
dudmuck 0:cb0046a629c1 54 printf("sysmod:%x\n", read_single(MMA8451_SYSMOD));
dudmuck 0:cb0046a629c1 55 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 56 printf("ctrl_reg1:%x\n", ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 57 printf("ctrl_reg2:%x\n", read_single(MMA8451_CTRL_REG2));
dudmuck 0:cb0046a629c1 58 printf("status: %x\n", read_single(MMA8451_STATUS));
dudmuck 0:cb0046a629c1 59 }
dudmuck 0:cb0046a629c1 60
dudmuck 0:cb0046a629c1 61 void MMA8451Q::write(uint8_t addr, uint8_t data)
dudmuck 0:cb0046a629c1 62 {
dudmuck 0:cb0046a629c1 63 uint8_t cmd[2];
dudmuck 0:cb0046a629c1 64
dudmuck 0:cb0046a629c1 65 cmd[0] = addr;
dudmuck 0:cb0046a629c1 66 cmd[1] = data;
dudmuck 0:cb0046a629c1 67
dudmuck 0:cb0046a629c1 68 if (m_i2c.write(MMA8451_I2C_ADDRESS, (char *)cmd, 2))
dudmuck 0:cb0046a629c1 69 printf("MMA8451Q write-fail\n");
dudmuck 0:cb0046a629c1 70 }
dudmuck 0:cb0046a629c1 71
dudmuck 0:cb0046a629c1 72 void MMA8451Q::set_active(char arg)
dudmuck 0:cb0046a629c1 73 {
dudmuck 0:cb0046a629c1 74 char cmd[2];
dudmuck 0:cb0046a629c1 75
dudmuck 0:cb0046a629c1 76 cmd[0] = MMA8451_CTRL_REG1;
dudmuck 0:cb0046a629c1 77 cmd[1] = arg;
dudmuck 0:cb0046a629c1 78
dudmuck 0:cb0046a629c1 79 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 2))
dudmuck 0:cb0046a629c1 80 printf("write-fail\n");
dudmuck 0:cb0046a629c1 81 }
dudmuck 0:cb0046a629c1 82
dudmuck 0:cb0046a629c1 83 uint8_t MMA8451Q::get_active(void)
dudmuck 0:cb0046a629c1 84 {
dudmuck 0:cb0046a629c1 85 uint8_t ret = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 86 printf("CTRL_REG1: %x\n", ret);
dudmuck 0:cb0046a629c1 87 return ret;
dudmuck 0:cb0046a629c1 88 }
dudmuck 0:cb0046a629c1 89
dudmuck 0:cb0046a629c1 90
dudmuck 0:cb0046a629c1 91 void MMA8451Q::transient_detect()
dudmuck 0:cb0046a629c1 92 {
dudmuck 0:cb0046a629c1 93 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 94 /* AN4071 Sensors Freescale Semiconductor, Inc.
dudmuck 0:cb0046a629c1 95 * 7.1 Example Steps for Configuring Transient Detection
dudmuck 0:cb0046a629c1 96 * Change in X or Y > 0.5g for 50 ms at 100 Hz ODR, Normal mode */
dudmuck 0:cb0046a629c1 97
dudmuck 0:cb0046a629c1 98 /* Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1 */
dudmuck 0:cb0046a629c1 99 ctrl_reg1.bits.ACTIVE = 0;
dudmuck 0:cb0046a629c1 100 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 101 ctrl_reg1.bits.DR = 3; //Set device in 100 Hz ODR, Standby
dudmuck 0:cb0046a629c1 102 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 103
dudmuck 0:cb0046a629c1 104 /* Step 2: Enable X and Y Axes and enable the latch: Register 0x1D Configuration Register */
dudmuck 0:cb0046a629c1 105 transient_cfg.octet = 0;
dudmuck 0:cb0046a629c1 106 transient_cfg.bits.ELE = 1; // enable latch
dudmuck 0:cb0046a629c1 107 transient_cfg.bits.YTEFE = 1; // enable Y
dudmuck 0:cb0046a629c1 108 transient_cfg.bits.XTEFE = 1; // enable X
dudmuck 0:cb0046a629c1 109 transient_cfg.bits.ZTEFE = 1; // enable Z
dudmuck 0:cb0046a629c1 110 write(MMA8451_TRANSIENT_CFG, transient_cfg.octet);
dudmuck 0:cb0046a629c1 111
dudmuck 0:cb0046a629c1 112 /* Step 3: Set the Threshold: Register 0x1F
dudmuck 0:cb0046a629c1 113 * Note: Step count is 0.063g per count, 0.5g / 0.063g = 7.93.
dudmuck 0:cb0046a629c1 114 * Therefore set the threshold to 8 counts */
dudmuck 0:cb0046a629c1 115 write(MMA8451_TRANSIENT_THS, 8);
dudmuck 0:cb0046a629c1 116
dudmuck 0:cb0046a629c1 117 /* Step 4: Set the Debounce Counter for 50 ms: Register 0x20
dudmuck 0:cb0046a629c1 118 * Note: 100 Hz ODR, therefore 10 ms step sizes */
dudmuck 0:cb0046a629c1 119 write(MMA8451_TRANSIENT_COUNT, 5);
dudmuck 0:cb0046a629c1 120
dudmuck 0:cb0046a629c1 121 /* Step 5: Enable Transient Detection Interrupt in the System (CTRL_REG4) */
dudmuck 0:cb0046a629c1 122 ctrl_reg4.octet = 0;
dudmuck 0:cb0046a629c1 123 ctrl_reg4.bits.INT_EN_TRANS = 1;
dudmuck 0:cb0046a629c1 124 write(MMA8451_CTRL_REG4, ctrl_reg4.octet);
dudmuck 0:cb0046a629c1 125
dudmuck 0:cb0046a629c1 126 /* Step 6: Route the Transient Interrupt to INT 1 hardware pin (CTRL_REG5) */
dudmuck 0:cb0046a629c1 127 ctrl_reg5.octet = 0;
dudmuck 0:cb0046a629c1 128 ctrl_reg5.bits.INT_CFG_TRANS = 1;
dudmuck 0:cb0046a629c1 129 write(MMA8451_CTRL_REG5, ctrl_reg5.octet);
dudmuck 0:cb0046a629c1 130
dudmuck 0:cb0046a629c1 131 /* Step 7: Put the device in Active Mode: Register 0x2A CTRL_REG1 */
dudmuck 0:cb0046a629c1 132 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 133 ctrl_reg1.bits.ACTIVE = 1;
dudmuck 0:cb0046a629c1 134 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 135
dudmuck 0:cb0046a629c1 136 /* Step 8: Write Interrupt Service Routine Reading the
dudmuck 0:cb0046a629c1 137 * System Interrupt Status and the Transient Status */
dudmuck 0:cb0046a629c1 138 }
dudmuck 0:cb0046a629c1 139