mma8451q driver

Dependents:   nRF51822_DataLogger_PowerImpulseCounter scpi_sx127x NAMote72_Utility

Committer:
dudmuck
Date:
Tue Sep 01 00:27:13 2015 +0000
Revision:
2:4bc96749141e
Parent:
1:778b685c3ad0
added orientation detection mode

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 0:cb0046a629c1 1 #include "mbed.h"
dudmuck 0:cb0046a629c1 2
dudmuck 0:cb0046a629c1 3 /* Xtrinsic accelerometer */
dudmuck 0:cb0046a629c1 4
dudmuck 0:cb0046a629c1 5 /*
dudmuck 0:cb0046a629c1 6 * MMA8451 Registers
dudmuck 0:cb0046a629c1 7 */
dudmuck 0:cb0046a629c1 8 #define MMA8451_STATUS 0x00
dudmuck 0:cb0046a629c1 9 #define MMA8451_OUT_X_MSB 0x01
dudmuck 0:cb0046a629c1 10 #define MMA8451_SYSMOD 0x0b //
dudmuck 0:cb0046a629c1 11 #define MMA8451_INT_SOURCE 0x0c //
dudmuck 0:cb0046a629c1 12 #define MMA8451_ID 0x0d
dudmuck 1:778b685c3ad0 13 #define MMA8451_PL_STATUS 0x10
dudmuck 2:4bc96749141e 14 #define MMA8451_PL_CFG 0x11
dudmuck 2:4bc96749141e 15 #define MMA8451_PL_COUNT 0x12 // orientation debounce
dudmuck 2:4bc96749141e 16 #define MMA8451_PL_BF_ZCOMP 0x13
dudmuck 2:4bc96749141e 17 #define MMA8451_PL_THS_REG 0x14
dudmuck 1:778b685c3ad0 18 #define MMA8451_FF_MT_SRC 0x16
dudmuck 0:cb0046a629c1 19 #define MMA8451_TRANSIENT_CFG 0x1d // transient enable
dudmuck 0:cb0046a629c1 20 #define MMA8451_TRANSIENT_SRC 0x1e // transient read/clear interrupt
dudmuck 0:cb0046a629c1 21 #define MMA8451_TRANSIENT_THS 0x1f // transient threshold
dudmuck 0:cb0046a629c1 22 #define MMA8451_TRANSIENT_COUNT 0x20 // transient debounce
dudmuck 1:778b685c3ad0 23 #define MMA8451_PULSE_SRC 0x22
dudmuck 0:cb0046a629c1 24 #define MMA8451_CTRL_REG1 0x2a
dudmuck 0:cb0046a629c1 25 #define MMA8451_CTRL_REG2 0x2b
dudmuck 1:778b685c3ad0 26 #define MMA8451_CTRL_REG3 0x2c // interrupt control
dudmuck 0:cb0046a629c1 27 #define MMA8451_CTRL_REG4 0x2d // interrupt enable
dudmuck 0:cb0046a629c1 28 #define MMA8451_CTRL_REG5 0x2e // interrupt pin selection
dudmuck 0:cb0046a629c1 29
dudmuck 0:cb0046a629c1 30 typedef union {
dudmuck 0:cb0046a629c1 31 struct {
dudmuck 0:cb0046a629c1 32 int16_t x;
dudmuck 0:cb0046a629c1 33 int16_t y;
dudmuck 0:cb0046a629c1 34 int16_t z;
dudmuck 0:cb0046a629c1 35 } v;
dudmuck 0:cb0046a629c1 36 uint8_t octets[6];
dudmuck 0:cb0046a629c1 37 } mma_out_t;
dudmuck 0:cb0046a629c1 38
dudmuck 0:cb0046a629c1 39 typedef union {
dudmuck 0:cb0046a629c1 40 struct { // at 0x0c
dudmuck 0:cb0046a629c1 41 uint8_t SRC_DRDY : 1; // 0
dudmuck 0:cb0046a629c1 42 uint8_t reserved1 : 1; // 1
dudmuck 0:cb0046a629c1 43 uint8_t SRC_FF_MT : 1; // 2
dudmuck 0:cb0046a629c1 44 uint8_t SRC_PULSE : 1; // 3
dudmuck 0:cb0046a629c1 45 uint8_t SRC_LNDPRT : 1; // 4
dudmuck 0:cb0046a629c1 46 uint8_t SRC_TRANS : 1; // 5
dudmuck 0:cb0046a629c1 47 uint8_t reserved6 : 1; // 6
dudmuck 0:cb0046a629c1 48 uint8_t SRC_ASLP : 1; // 7
dudmuck 0:cb0046a629c1 49 } bits;
dudmuck 0:cb0046a629c1 50 uint8_t octet;
dudmuck 1:778b685c3ad0 51 } mma_int_source_t;
dudmuck 0:cb0046a629c1 52
dudmuck 2:4bc96749141e 53 typedef union {
dudmuck 2:4bc96749141e 54 struct { // at 0x10
dudmuck 2:4bc96749141e 55 uint8_t BAFRO : 1; // 0 0=front, 1=back
dudmuck 2:4bc96749141e 56 uint8_t LAPO : 2; // 1,2 up, down, right, left
dudmuck 2:4bc96749141e 57 uint8_t res : 3; // 3,4,5
dudmuck 2:4bc96749141e 58 uint8_t LO : 1; // 6 Z-tilt lockout
dudmuck 2:4bc96749141e 59 uint8_t NEWLP : 1; // 7 1 = BAFRO or LO has changed
dudmuck 2:4bc96749141e 60 } bits;
dudmuck 2:4bc96749141e 61 uint8_t octet;
dudmuck 2:4bc96749141e 62 } mma_pl_status_t;
dudmuck 2:4bc96749141e 63
dudmuck 0:cb0046a629c1 64 typedef union {
dudmuck 0:cb0046a629c1 65 struct { // at 0x1d
dudmuck 0:cb0046a629c1 66 uint8_t HPF_BYP : 1; // 0
dudmuck 0:cb0046a629c1 67 uint8_t XTEFE : 1; // 1
dudmuck 0:cb0046a629c1 68 uint8_t YTEFE : 1; // 2
dudmuck 0:cb0046a629c1 69 uint8_t ZTEFE : 1; // 3
dudmuck 0:cb0046a629c1 70 uint8_t ELE : 1; // 4
dudmuck 0:cb0046a629c1 71 uint8_t pad : 3; // 5,6,7
dudmuck 0:cb0046a629c1 72 } bits;
dudmuck 0:cb0046a629c1 73 uint8_t octet;
dudmuck 0:cb0046a629c1 74 } transient_cfg_t;
dudmuck 0:cb0046a629c1 75
dudmuck 0:cb0046a629c1 76 typedef union {
dudmuck 0:cb0046a629c1 77 struct { // at 0x1e
dudmuck 0:cb0046a629c1 78 uint8_t X_Trans_Pol : 1; // 0
dudmuck 0:cb0046a629c1 79 uint8_t XTRANSE : 1; // 1
dudmuck 0:cb0046a629c1 80 uint8_t Y_Trans_Pol : 1; // 2
dudmuck 0:cb0046a629c1 81 uint8_t YTRANSE : 1; // 3
dudmuck 0:cb0046a629c1 82 uint8_t Z_Trans_Pol : 1; // 4
dudmuck 0:cb0046a629c1 83 uint8_t ZTRANSE : 1; // 5
dudmuck 0:cb0046a629c1 84 uint8_t EA : 1; // 6
dudmuck 0:cb0046a629c1 85 uint8_t pad : 1; // 7
dudmuck 0:cb0046a629c1 86 } bits;
dudmuck 0:cb0046a629c1 87 uint8_t octet;
dudmuck 0:cb0046a629c1 88 } transient_src_t;
dudmuck 0:cb0046a629c1 89
dudmuck 0:cb0046a629c1 90 typedef union {
dudmuck 0:cb0046a629c1 91 struct { // at 0x2a
dudmuck 0:cb0046a629c1 92 uint8_t ACTIVE : 1; // 0
dudmuck 0:cb0046a629c1 93 uint8_t F_READ : 1; // 1
dudmuck 0:cb0046a629c1 94 uint8_t LNOISE : 1; // 2
dudmuck 0:cb0046a629c1 95 uint8_t DR : 3; // 3,4,5
dudmuck 0:cb0046a629c1 96 uint8_t ASLP_RATE : 2; // 6,7
dudmuck 0:cb0046a629c1 97 } bits;
dudmuck 0:cb0046a629c1 98 uint8_t octet;
dudmuck 0:cb0046a629c1 99 } ctrl_reg1_t;
dudmuck 0:cb0046a629c1 100
dudmuck 0:cb0046a629c1 101 typedef union {
dudmuck 0:cb0046a629c1 102 struct { // at 0x2d
dudmuck 0:cb0046a629c1 103 uint8_t INT_EN_DRDY : 1; // 0
dudmuck 0:cb0046a629c1 104 uint8_t reserved1 : 1; // 1
dudmuck 0:cb0046a629c1 105 uint8_t INT_EN_FF_MT : 1; // 2
dudmuck 0:cb0046a629c1 106 uint8_t INT_EN_PULSE : 1; // 3
dudmuck 0:cb0046a629c1 107 uint8_t INT_EN_LNDPRT : 1; // 4
dudmuck 0:cb0046a629c1 108 uint8_t INT_EN_TRANS : 1; // 5
dudmuck 0:cb0046a629c1 109 uint8_t reserved6 : 1; // 6
dudmuck 0:cb0046a629c1 110 uint8_t INT_EN_ASLP : 1; // 7
dudmuck 0:cb0046a629c1 111 } bits;
dudmuck 0:cb0046a629c1 112 uint8_t octet;
dudmuck 0:cb0046a629c1 113 } ctrl_reg4_t;
dudmuck 0:cb0046a629c1 114
dudmuck 0:cb0046a629c1 115 typedef union {
dudmuck 0:cb0046a629c1 116 struct { // at 0x2e
dudmuck 0:cb0046a629c1 117 uint8_t INT_CFG_DRDY : 1; // 0
dudmuck 0:cb0046a629c1 118 uint8_t reserved1 : 1; // 1
dudmuck 0:cb0046a629c1 119 uint8_t INT_CFG_FF_MT : 1; // 2
dudmuck 0:cb0046a629c1 120 uint8_t INT_CFG_PULSE : 1; // 3
dudmuck 0:cb0046a629c1 121 uint8_t INT_CFG_LNDPRT : 1; // 4
dudmuck 0:cb0046a629c1 122 uint8_t INT_CFG_TRANS : 1; // 5
dudmuck 0:cb0046a629c1 123 uint8_t reserved6 : 1; // 6
dudmuck 0:cb0046a629c1 124 uint8_t INT_CFG_ASLP : 1; // 7
dudmuck 0:cb0046a629c1 125 } bits;
dudmuck 0:cb0046a629c1 126 uint8_t octet;
dudmuck 0:cb0046a629c1 127 } ctrl_reg5_t;
dudmuck 0:cb0046a629c1 128
dudmuck 0:cb0046a629c1 129 class MMA8451Q {
dudmuck 0:cb0046a629c1 130 public:
dudmuck 1:778b685c3ad0 131 MMA8451Q(I2C& r, DigitalIn& int_pin);
dudmuck 0:cb0046a629c1 132 ~MMA8451Q();
dudmuck 0:cb0046a629c1 133 void print_regs(void);
dudmuck 0:cb0046a629c1 134 void set_active(char);
dudmuck 1:778b685c3ad0 135 bool get_active(void);
dudmuck 0:cb0046a629c1 136
dudmuck 0:cb0046a629c1 137 uint8_t read_single(uint8_t addr);
dudmuck 0:cb0046a629c1 138 void read(uint8_t addr, uint8_t *dst_buf, int length);
dudmuck 0:cb0046a629c1 139 void write(uint8_t addr, uint8_t data);
dudmuck 0:cb0046a629c1 140 void transient_detect(void);
dudmuck 2:4bc96749141e 141 void orient_detect(void);
dudmuck 2:4bc96749141e 142 uint8_t service(void); // returns 0 if no interrupt occurred
dudmuck 0:cb0046a629c1 143
dudmuck 2:4bc96749141e 144 bool verbose; // print interrupt event
dudmuck 0:cb0046a629c1 145 mma_out_t out;
dudmuck 0:cb0046a629c1 146 transient_cfg_t transient_cfg;
dudmuck 0:cb0046a629c1 147 ctrl_reg1_t ctrl_reg1;
dudmuck 0:cb0046a629c1 148 ctrl_reg4_t ctrl_reg4;
dudmuck 0:cb0046a629c1 149 ctrl_reg5_t ctrl_reg5;
dudmuck 0:cb0046a629c1 150
dudmuck 0:cb0046a629c1 151 private:
dudmuck 0:cb0046a629c1 152 I2C& m_i2c;
dudmuck 1:778b685c3ad0 153 DigitalIn& m_int_pin;
dudmuck 0:cb0046a629c1 154 };
dudmuck 0:cb0046a629c1 155