
UART console application for testing SX1272/SX1276
This is a UART console test application for using SX127x library driver for SX1272/SX1276 radio transceivers. Serial console is provided at 57600bps. Refer to Serial Communication with a PC for information about using the serial port with your PC.
Using this command interface, you can exercise the functionality of radio chip without needing specialized software application for your PC.
Commands which can be used include ?
to list available commands, or .
to query status from radio chip, for example.
The serial console allows you to configure the radio chip, such as setting spreading factor, bandwidth, operating frequency, etc.
A simple chat application is provided to try communications between two boards. The SX127x library object is instantiated with pin assignments generic arduino headers, but can be easily reassigned for any mbed board.
The same driver library can operate for both SX1272 and SX1276. Upon starting, the driver auto-detects whether SX1272 or SX1276 transceiver chip is connected by attempting to change the LowFrequencyModeOn
bit in RegOpMode
register. If this bit can be changed, then the radio device is SX1276. This bit is not implemented in SX1272. A few of the radio driver functions select behavior based on this detection. The differences between these two devices is small, from a software perspective.
Using with SX1276MB1xAS Shield
This component plugs into any board with arduino uno headers.
There are two different version of this shield. European version (MAS), and North American (LAS). The LAS shield uses PA_BOOST transmit pin to permit +20dBm power. The MAS version uses RFO transmit pin in Europe. This software reads RF switch pin (A4 pin) pulling resistor to determine which type of shield is installed.
Using with your own production board
This software is useful for validating RF performance your own LoRa board design, because only two external pins needs to be provided to PC (UART TX/RX). You can select an mbed platform which matches the CPU on your own board. If the memory size doesnt match exactly, you can export the program to an offline toolchain and edit the target type or linker file there.
Transmitter Test Guidelines
FSK mode is used for transmitter testing, because an unmodulated carrier can be sent, permitting easy measurement of TX power and frequency error.
commands used for transmitter testing:
frf915.0
change to your desired RF center frequency (in this case 915MHz)L
to toggle the radio chip into FSK mode.fdev0
to configure TX frequency deviation to zero, to put the transmitted carrier on the center frequency.pas
to select which TX pin is connected to antenna matching (RFO vs PA_BOOST).op<dBm>
to configure TX power.- If you desire to test higher power PA_BOOST, use
ocp<mA>
w 01 03
put radio chip into transmit mode (skips writing to FIFO). This will cause radio to transmit preamble, because the FIFO is empty in TX mode. Since Fdev is zero, an unmodulated carrier is sent.- Spectrum analyzer can now be used to to observe TX power, harmonics, power consumption, or frequency error.
stby
to end transmission, or useh
to reset radio chip to default condition.- Use period
.
command at any time to review current radio configuration.
LoRa transmitter testing
- use
L
command to toggle radio into LoRa, if necessary. - Normally the
tx
command is used to manually send single packets. txc
will toggleTxContinuousMode
in LoRa modem to send continuous modulated transmission.- Useful for checking adjacent channel power.
- enter
txc
again to end transmission.
Receiver Test Guidelines
FSK mode is used for receiver sensitivity testing, allowing the use of a BERT signal generator (such as R/S SMIQ03B). Using this method provides real-time indication of receiver sensitivity, useful for tuning and impedance matching. The radio chip outputs DCLK and DATA digital signals which are connected back to BERT signal generator.
commands used for receiver testing:
L
to toggle the radio chip into FSK mode.datam
to toggle FSK modem into continuous mode. This disables packet engine and gives direct access to demodulator.- configure DIO1 pin to DCLK function, and DIO2 pin to DATA function:
dio
command to list current DIO pin asignmentsd1
to cycle DIO1 function untilDclk
is selectedd2
for DIO2, onlyData
function is available in FSK continuous mode
frf915.0
change to your desired RF center frequency (in this case 915MHz)rx
to start receiverstby
to disable receiver
Full command list
Arguments shown in square brackets []
indicate required. <>
are optional, where leaving off the argument usually causes a read of the item, and providing the value causes a write operation. You should always have the radio chip datasheet on-hand when using these commands.
Hitting <enter> key by itself will repeat last command.
<Ctrl-C> will cancel an operation in progress.
command list: common commands (both LoRa and FSK)
command | description |
---|---|
. (period) | print current radio status |
? | list available commands |
L | toggle active radio modem (LoRa vs FSK) |
h | hardware reset, put radio into default power-on condition |
frf<MHz> | get/set RF operating frequency |
rx | start radio receiver (any received packets are printed onto your serial terminal) |
rssi | read instantaneous RSSI (level read at the time command is issued) |
tx<%d> | transmit test packet. Packet length value can be provided as argument, or uses last value if not provided |
payl<%d> | get/set payload length |
bw<KHz> | get/set bandwidth. In LoRa mode, both receive and transmit bandwidth are changed. For FSK, only receive bandwidth is affected. bwa accesses AFC bandwidth in FSK |
pas | toggle RFO / PA_BOOST transmit pin output selection |
op<dBm> | get/set TX output power. Value is provided in dBm. Special case is value of 20dBm (on PA_BOOST), which causes increase in TX DAC voltage |
ocp<mA> | get/set TX current limit, in milliamps. Necessary adjustment when +20dBm is used |
dio | show DIO pin assignments |
d<0-5> | change DIO pin assignment, the pin number is given as arguement. Each pin has up to 4 possible functions |
pres<%d> | set preamble length. LoRa: number of symbols. FSK: number of bytes |
crcon | toggle crcOn |
lnab | cycle LNA-boost setting (receiver performance adjustment) |
R | read all radio registers (use only while reading chip datasheet) |
r[%x] | read single radio register (use only while reading chip datasheet) |
w[%x %x] | write single radio register (use only while reading chip datasheet) |
pllbw | change PLL bandwidth |
stby | set chip mode to standby |
sleep | set chip mode to sleep |
fstx | set chip mode to fstx |
fsrx | set chip mode to fsrx |
Eiger range test commands | description |
pid<%d> | get set ID number in range test payload |
pertx<%d> | start Eiger PER transmit. The count of packets to send is provided as arguement |
perrx | start Eiger PER receive |
txpd<%d> | get/set tx delay between PER packets transmitted |
command list: LoRa modem commands
LoRa command | LoRa description |
---|---|
iqinv | toggle RX IQ invert |
cin | toggle TX IQ invert |
lhp<%d> | (RX) get/set hop period |
sync<%x> | get/set sync (post-preamble gap, single byte) |
cr<1-4> | get/set codingRate |
lhm | toggle explicit/implicit (explicit mode sends payload length with each packet) |
sf<%d> | get/set spreadingFactor (SF7 to SF12) |
ldr | toggle LowDataRateOptimize (changes payload encoding, for long packets) |
txc | toggle TxContinuousMode |
rxt<%d> | get/set SymbTimeout |
rxs | start RX_SINGLE (receives only for SymbTimeout symbols) |
cad<%d num tries> | run channel activity detection |
command list: FSK modem commands
FSK command | FSK description |
---|---|
c<%d> | get/set test cases. Several FSK bitrates/bandwidths pre-configured to give optimal performance. |
fdev<kHz> | (TX) get/set frequency deviation |
mods | (TX) increment modulation shaping |
par | (TX) increment paRamp |
datam | toggle DataMode (packet/continuous) |
fifot | toggle TxStartCondition (FifoThreshold level vs FifoNotEmpty) |
br<%f kbps> | get/set bitrate |
dcf | increment DcFree (manchester / whitening) |
pktf | toggle PacketFormat fixed/variable length |
syncon | toggle SyncOn (frame sync, SFD enable) |
bitsync | toggle BitSyncOn (continuous mode only) |
syncw<hex bytes> | get/set syncword. Sync bytes are provided by hex octects separated by spaces. |
fei | (RX) read FEI |
rxt | (RX) increment RxTrigger (RX start on rssi vs. preamble detect) |
rssit<-dBm> | (RX) get/set rssi threshold (trigger level for RSSI interrupt) |
rssis<%d> | (RX) get/set rssi smoothing |
rssio<%d> | (RX) get/set rssi offset |
agcauto | (RX) toggle AgcAutoOn (true = LNA gain set automatically) |
afcauto | (RX) toggle AfcAutoOn |
ac | (RX) AfcClear |
ar | (RX) increment AutoRestartRxMode |
alc | (RX) toggle AfcAutoClearOn (only if AfcAutoOn is set) |
prep | (RX) toggle PreamblePolarity (0xAA vs 0x55) |
pde | (RX) toggle PreambleDetectorOn |
pds<%d> | (RX) get/set PreambleDetectorSize |
pdt<%d> | (RX) get/set PreambleDetectorTol |
mp | (RX) toggle MapPreambleDetect (DIO function RSSI vs PreambleDetect) |
thr<%d> | get/set FifoThreshold (triggers FifoLevel interrupt) |
poll | toggle poll_irq_en. Radio events read from DIO pins vs polling of IrqFlags register |
E | empty out FIFO |
clkout | increment ClkOut divider |
ook | enter OOK mode |
ookt | increment OokThreshType |
ooks | increment OokPeakTheshStep |
sqlch<%d> | get/set OokFixedThresh |
main.cpp@25:0479cbc2967b, 2020-04-06 (annotated)
- Committer:
- dudmuck
- Date:
- Mon Apr 06 17:25:46 2020 +0000
- Revision:
- 25:0479cbc2967b
- Parent:
- 24:9ba45aa15b53
update mbed-os to latest
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dudmuck | 1:1cd0afbed23c | 1 | #include "sx127x_lora.h" |
dudmuck | 1:1cd0afbed23c | 2 | #include "sx127x_fsk.h" |
dudmuck | 19:be8a8b0e7320 | 3 | #define __STDC_FORMAT_MACROS |
dudmuck | 19:be8a8b0e7320 | 4 | #include <inttypes.h> |
dudmuck | 22:2005df80c8a8 | 5 | |
dudmuck | 18:9530d682fd9a | 6 | //#include "kermit.h" |
dudmuck | 0:be215de91a68 | 7 | |
dudmuck | 13:c73caaee93a5 | 8 | //#define FSK_PER |
dudmuck | 10:d9bb2ce57f05 | 9 | //#define START_EIGER_RX |
dudmuck | 10:d9bb2ce57f05 | 10 | //#define START_EIGER_TX |
dudmuck | 21:b84a77dfb43c | 11 | //#define START_OOK_TX_TEST |
dudmuck | 10:d9bb2ce57f05 | 12 | |
dudmuck | 10:d9bb2ce57f05 | 13 | DigitalOut led1(LED1); |
dudmuck | 0:be215de91a68 | 14 | Serial pc(USBTX, USBRX); |
dudmuck | 0:be215de91a68 | 15 | |
dudmuck | 0:be215de91a68 | 16 | uint8_t tx_cnt; |
dudmuck | 0:be215de91a68 | 17 | char pcbuf[64]; |
dudmuck | 5:360069ec9953 | 18 | int pcbuf_len; |
dudmuck | 0:be215de91a68 | 19 | |
dudmuck | 0:be215de91a68 | 20 | typedef enum { |
dudmuck | 0:be215de91a68 | 21 | APP_NONE = 0, |
dudmuck | 0:be215de91a68 | 22 | APP_CHAT |
dudmuck | 0:be215de91a68 | 23 | } app_e; |
dudmuck | 0:be215de91a68 | 24 | |
dudmuck | 0:be215de91a68 | 25 | app_e app = APP_NONE; |
dudmuck | 0:be215de91a68 | 26 | |
dudmuck | 18:9530d682fd9a | 27 | #define FSK_LARGE_PKT_THRESHOLD 0x3f |
dudmuck | 7:c3c54f222ced | 28 | |
dudmuck | 21:b84a77dfb43c | 29 | bool crc32_en; // ethcrc |
dudmuck | 21:b84a77dfb43c | 30 | |
dudmuck | 21:b84a77dfb43c | 31 | /*********** cmd_ulrx()... ************/ |
dudmuck | 21:b84a77dfb43c | 32 | typedef enum { |
dudmuck | 21:b84a77dfb43c | 33 | ULRX_STATE_OFF = 0, |
dudmuck | 21:b84a77dfb43c | 34 | ULRX_STATE_NEED_LENGTH, |
dudmuck | 21:b84a77dfb43c | 35 | ULRX_STATE_PAYLOAD, |
dudmuck | 21:b84a77dfb43c | 36 | ULRX_STATE_SYNC1 |
dudmuck | 21:b84a77dfb43c | 37 | } ulrx_state_e; |
dudmuck | 21:b84a77dfb43c | 38 | ulrx_state_e ulrx_state = ULRX_STATE_OFF; |
dudmuck | 21:b84a77dfb43c | 39 | bool ulrx_enable; |
dudmuck | 21:b84a77dfb43c | 40 | /*********** ...cmd_ulrx() ************/ |
dudmuck | 21:b84a77dfb43c | 41 | |
dudmuck | 21:b84a77dfb43c | 42 | uint8_t rx_payload_idx; |
dudmuck | 21:b84a77dfb43c | 43 | |
dudmuck | 21:b84a77dfb43c | 44 | /************** fsk modeReady isr... **********/ |
dudmuck | 21:b84a77dfb43c | 45 | bool rx_payloadReady_int_en; // cmd_prrx() |
dudmuck | 21:b84a77dfb43c | 46 | #define N_RX_PKTS 32 |
dudmuck | 21:b84a77dfb43c | 47 | #define RX_PKT_SIZE_LIMIT 32 |
dudmuck | 21:b84a77dfb43c | 48 | uint8_t rx_pkts[N_RX_PKTS][RX_PKT_SIZE_LIMIT]; |
dudmuck | 21:b84a77dfb43c | 49 | uint8_t n_rx_pkts; |
dudmuck | 21:b84a77dfb43c | 50 | /************** ...fsk modeReady isr **********/ |
dudmuck | 21:b84a77dfb43c | 51 | |
dudmuck | 21:b84a77dfb43c | 52 | #ifdef TARGET_STM |
dudmuck | 21:b84a77dfb43c | 53 | CRC_HandleTypeDef CrcHandle; |
dudmuck | 21:b84a77dfb43c | 54 | #endif /* TARGET_STM */ |
dudmuck | 21:b84a77dfb43c | 55 | |
dudmuck | 21:b84a77dfb43c | 56 | int rssi_polling_thresh; // 0 = polling off |
dudmuck | 18:9530d682fd9a | 57 | bool ook_test_en; |
dudmuck | 18:9530d682fd9a | 58 | bool poll_irq_en; |
dudmuck | 20:b11592c9ba5f | 59 | volatile RegIrqFlags2_t fsk_RegIrqFlags2_prev; |
dudmuck | 20:b11592c9ba5f | 60 | volatile RegIrqFlags1_t fsk_RegIrqFlags1_prev; |
dudmuck | 20:b11592c9ba5f | 61 | Timer rx_start_timer; |
dudmuck | 20:b11592c9ba5f | 62 | uint32_t secs_rx_start; |
dudmuck | 1:1cd0afbed23c | 63 | |
dudmuck | 8:227605e4a760 | 64 | /***************************** eiger per: *************************************************/ |
dudmuck | 8:227605e4a760 | 65 | |
dudmuck | 18:9530d682fd9a | 66 | uint32_t num_cads; |
dudmuck | 18:9530d682fd9a | 67 | bool cadper_enable; |
dudmuck | 8:227605e4a760 | 68 | bool per_en; |
dudmuck | 8:227605e4a760 | 69 | float per_tx_delay = 0.1; |
dudmuck | 8:227605e4a760 | 70 | int per_id; |
dudmuck | 18:9530d682fd9a | 71 | uint32_t PacketTxCnt, PacketTxCntEnd; |
dudmuck | 8:227605e4a760 | 72 | uint32_t PacketPerOkCnt; |
dudmuck | 8:227605e4a760 | 73 | int PacketRxSequencePrev; |
dudmuck | 8:227605e4a760 | 74 | uint32_t PacketPerKoCnt; |
dudmuck | 8:227605e4a760 | 75 | uint32_t PacketNormalCnt; |
dudmuck | 8:227605e4a760 | 76 | Timeout per_timeout; |
dudmuck | 8:227605e4a760 | 77 | |
dudmuck | 18:9530d682fd9a | 78 | |
dudmuck | 18:9530d682fd9a | 79 | |
dudmuck | 0:be215de91a68 | 80 | /******************************************************************************/ |
dudmuck | 9:2f13a9ef27b4 | 81 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 9:2f13a9ef27b4 | 82 | // mosi, miso, sclk, cs, rst, dio0, dio1 |
dudmuck | 23:821b4f426ee6 | 83 | //SX127x radio(LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1); |
dudmuck | 23:821b4f426ee6 | 84 | SPI spi(LORA_MOSI, LORA_MISO, LORA_SCK); // mosi, miso, sclk |
dudmuck | 23:821b4f426ee6 | 85 | // dio0, dio1, nss, spi, rst |
dudmuck | 23:821b4f426ee6 | 86 | SX127x radio(LORA_DIO0, LORA_DIO1, LORA_NSS, spi, LORA_RESET); // multitech mdot |
dudmuck | 23:821b4f426ee6 | 87 | |
dudmuck | 23:821b4f426ee6 | 88 | DigitalIn dio3(LORA_DIO3); |
dudmuck | 9:2f13a9ef27b4 | 89 | DigitalOut txctl(LORA_TXCTL); |
dudmuck | 9:2f13a9ef27b4 | 90 | DigitalOut rxctl(LORA_RXCTL); |
dudmuck | 9:2f13a9ef27b4 | 91 | |
dudmuck | 9:2f13a9ef27b4 | 92 | void rfsw_callback() |
dudmuck | 9:2f13a9ef27b4 | 93 | { |
dudmuck | 9:2f13a9ef27b4 | 94 | /* SKY13350 */ |
dudmuck | 9:2f13a9ef27b4 | 95 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { // start of transmission |
dudmuck | 9:2f13a9ef27b4 | 96 | txctl = 1; |
dudmuck | 9:2f13a9ef27b4 | 97 | rxctl = 0; |
dudmuck | 9:2f13a9ef27b4 | 98 | } else { // reception: |
dudmuck | 9:2f13a9ef27b4 | 99 | txctl = 0; |
dudmuck | 9:2f13a9ef27b4 | 100 | rxctl = 1; |
dudmuck | 9:2f13a9ef27b4 | 101 | } |
dudmuck | 9:2f13a9ef27b4 | 102 | } |
dudmuck | 9:2f13a9ef27b4 | 103 | |
dudmuck | 15:c69b942685ea | 104 | #define FSK_RSSI_OFFSET 0 |
dudmuck | 15:c69b942685ea | 105 | #define FSK_RSSI_SMOOTHING 2 |
dudmuck | 20:b11592c9ba5f | 106 | DigitalIn dio2(LORA_DIO2); |
dudmuck | 20:b11592c9ba5f | 107 | DigitalIn dio4(LORA_DIO4); |
dudmuck | 15:c69b942685ea | 108 | |
Wayne Roberts |
24:9ba45aa15b53 | 109 | #elif defined(TARGET_DISCO_L072CZ_LRWAN1) /********************* ...mDot **********************/ |
dudmuck | 23:821b4f426ee6 | 110 | /* Murata TypeABZ discovery board B-L072Z-LRWAN1 */ |
dudmuck | 22:2005df80c8a8 | 111 | // mosi, miso, sclk, cs, rst, dio0, dio1 |
dudmuck | 23:821b4f426ee6 | 112 | //SX127x radio(PA_7, PA_6, PB_3, PA_15, PC_0, PB_4, PB_1); |
dudmuck | 23:821b4f426ee6 | 113 | |
dudmuck | 23:821b4f426ee6 | 114 | SPI spi(PA_7, PA_6, PB_3); // mosi, miso, sclk |
dudmuck | 23:821b4f426ee6 | 115 | // dio0, dio1, nss, spi, rst |
dudmuck | 23:821b4f426ee6 | 116 | SX127x radio(PB_4, PB_1, PA_15, spi, PC_0); // sx1276 arduino shield |
dudmuck | 23:821b4f426ee6 | 117 | |
dudmuck | 22:2005df80c8a8 | 118 | DigitalIn dio2(PB_0); |
dudmuck | 22:2005df80c8a8 | 119 | DigitalIn dio3(PC_13); |
dudmuck | 22:2005df80c8a8 | 120 | #define FSK_RSSI_OFFSET 0 |
dudmuck | 22:2005df80c8a8 | 121 | #define FSK_RSSI_SMOOTHING 2 |
dudmuck | 22:2005df80c8a8 | 122 | #define CRF1 PA_1 |
dudmuck | 22:2005df80c8a8 | 123 | #define CRF2 PC_2 |
dudmuck | 22:2005df80c8a8 | 124 | #define CRF3 PC_1 |
dudmuck | 22:2005df80c8a8 | 125 | DigitalOut Vctl1(CRF1); |
dudmuck | 22:2005df80c8a8 | 126 | DigitalOut Vctl2(CRF2); |
dudmuck | 22:2005df80c8a8 | 127 | DigitalOut Vctl3(CRF3); |
dudmuck | 22:2005df80c8a8 | 128 | |
dudmuck | 22:2005df80c8a8 | 129 | void rfsw_callback() |
dudmuck | 22:2005df80c8a8 | 130 | { |
dudmuck | 22:2005df80c8a8 | 131 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { |
dudmuck | 22:2005df80c8a8 | 132 | Vctl1 = 0; |
dudmuck | 22:2005df80c8a8 | 133 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 22:2005df80c8a8 | 134 | Vctl2 = 0; |
dudmuck | 22:2005df80c8a8 | 135 | Vctl3 = 1; |
dudmuck | 22:2005df80c8a8 | 136 | } else { |
dudmuck | 22:2005df80c8a8 | 137 | Vctl2 = 1; |
dudmuck | 22:2005df80c8a8 | 138 | Vctl3 = 0; |
dudmuck | 22:2005df80c8a8 | 139 | } |
dudmuck | 22:2005df80c8a8 | 140 | } else { |
dudmuck | 22:2005df80c8a8 | 141 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER_SINGLE) |
dudmuck | 22:2005df80c8a8 | 142 | Vctl1 = 1; |
dudmuck | 22:2005df80c8a8 | 143 | else |
dudmuck | 22:2005df80c8a8 | 144 | Vctl1 = 0; |
dudmuck | 22:2005df80c8a8 | 145 | |
dudmuck | 22:2005df80c8a8 | 146 | Vctl2 = 0; |
dudmuck | 22:2005df80c8a8 | 147 | Vctl3 = 0; |
dudmuck | 22:2005df80c8a8 | 148 | } |
dudmuck | 22:2005df80c8a8 | 149 | } |
dudmuck | 22:2005df80c8a8 | 150 | #else /***************** ..Type-ABZ and L073RZ *************/ |
dudmuck | 23:821b4f426ee6 | 151 | SPI spi(D11, D12, D13); // mosi, miso, sclk |
dudmuck | 23:821b4f426ee6 | 152 | // dio0, dio1, nss, spi, rst |
dudmuck | 23:821b4f426ee6 | 153 | SX127x radio( D2, D3, D10, spi, A0); // sx1276 arduino shield |
dudmuck | 0:be215de91a68 | 154 | |
dudmuck | 15:c69b942685ea | 155 | // for SX1276 arduino shield: |
dudmuck | 7:c3c54f222ced | 156 | #ifdef TARGET_LPC11U6X |
dudmuck | 15:c69b942685ea | 157 | DigitalInOut rfsw(P0_23); |
dudmuck | 7:c3c54f222ced | 158 | #else |
dudmuck | 15:c69b942685ea | 159 | DigitalInOut rfsw(A4); |
dudmuck | 7:c3c54f222ced | 160 | #endif |
dudmuck | 6:fe16f96ee335 | 161 | |
dudmuck | 21:b84a77dfb43c | 162 | InterruptIn dio0int(D2); |
dudmuck | 21:b84a77dfb43c | 163 | InterruptIn dio1int(D3); |
dudmuck | 21:b84a77dfb43c | 164 | InterruptIn dio2int(D4); |
dudmuck | 21:b84a77dfb43c | 165 | InterruptIn dio4int(D8); |
dudmuck | 14:c57ea544dc18 | 166 | DigitalIn dio2(D4); |
dudmuck | 21:b84a77dfb43c | 167 | DigitalIn dio3(D5); |
dudmuck | 20:b11592c9ba5f | 168 | DigitalIn dio4(D8); |
dudmuck | 22:2005df80c8a8 | 169 | DigitalIn dio5(D9); |
dudmuck | 22:2005df80c8a8 | 170 | |
dudmuck | 22:2005df80c8a8 | 171 | #if defined(TARGET_STM) |
dudmuck | 21:b84a77dfb43c | 172 | DigitalOut pc3(PC_3); // nucleo corner pin for misc indication |
dudmuck | 21:b84a77dfb43c | 173 | #endif |
dudmuck | 21:b84a77dfb43c | 174 | |
dudmuck | 6:fe16f96ee335 | 175 | void rfsw_callback() |
dudmuck | 6:fe16f96ee335 | 176 | { |
dudmuck | 6:fe16f96ee335 | 177 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) |
dudmuck | 6:fe16f96ee335 | 178 | rfsw = 1; |
dudmuck | 6:fe16f96ee335 | 179 | else |
dudmuck | 6:fe16f96ee335 | 180 | rfsw = 0; |
dudmuck | 6:fe16f96ee335 | 181 | } |
dudmuck | 6:fe16f96ee335 | 182 | |
dudmuck | 15:c69b942685ea | 183 | #define FSK_RSSI_OFFSET 5 |
dudmuck | 15:c69b942685ea | 184 | #define FSK_RSSI_SMOOTHING 2 |
dudmuck | 15:c69b942685ea | 185 | |
dudmuck | 15:c69b942685ea | 186 | typedef enum { |
dudmuck | 15:c69b942685ea | 187 | SHIELD_TYPE_NONE = 0, |
dudmuck | 15:c69b942685ea | 188 | SHIELD_TYPE_LAS, |
dudmuck | 15:c69b942685ea | 189 | SHIELD_TYPE_MAS, |
dudmuck | 15:c69b942685ea | 190 | } shield_type_e; |
dudmuck | 15:c69b942685ea | 191 | shield_type_e shield_type; |
dudmuck | 15:c69b942685ea | 192 | |
dudmuck | 9:2f13a9ef27b4 | 193 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 9:2f13a9ef27b4 | 194 | |
dudmuck | 9:2f13a9ef27b4 | 195 | SX127x_fsk fsk(radio); |
dudmuck | 9:2f13a9ef27b4 | 196 | SX127x_lora lora(radio); |
dudmuck | 18:9530d682fd9a | 197 | //Kermit kermit(lora); |
dudmuck | 9:2f13a9ef27b4 | 198 | |
Wayne Roberts |
24:9ba45aa15b53 | 199 | #ifndef TARGET_DISCO_L072CZ_LRWAN1 |
dudmuck | 20:b11592c9ba5f | 200 | volatile bool saved_dio4; |
dudmuck | 22:2005df80c8a8 | 201 | #endif |
dudmuck | 20:b11592c9ba5f | 202 | |
dudmuck | 21:b84a77dfb43c | 203 | uint32_t crcTable[256]; |
dudmuck | 21:b84a77dfb43c | 204 | void make_crc_table() |
dudmuck | 21:b84a77dfb43c | 205 | { |
dudmuck | 21:b84a77dfb43c | 206 | const uint32_t POLYNOMIAL = 0xEDB88320; |
dudmuck | 21:b84a77dfb43c | 207 | uint32_t remainder; |
dudmuck | 21:b84a77dfb43c | 208 | uint8_t b = 0; |
dudmuck | 21:b84a77dfb43c | 209 | do{ |
dudmuck | 21:b84a77dfb43c | 210 | // Start with the data byte |
dudmuck | 21:b84a77dfb43c | 211 | remainder = b; |
dudmuck | 21:b84a77dfb43c | 212 | for (unsigned long bit = 8; bit > 0; --bit) |
dudmuck | 21:b84a77dfb43c | 213 | { |
dudmuck | 21:b84a77dfb43c | 214 | if (remainder & 1) |
dudmuck | 21:b84a77dfb43c | 215 | remainder = (remainder >> 1) ^ POLYNOMIAL; |
dudmuck | 21:b84a77dfb43c | 216 | else |
dudmuck | 21:b84a77dfb43c | 217 | remainder = (remainder >> 1); |
dudmuck | 21:b84a77dfb43c | 218 | } |
dudmuck | 21:b84a77dfb43c | 219 | crcTable[(size_t)b] = remainder; |
dudmuck | 21:b84a77dfb43c | 220 | } while(0 != ++b); |
dudmuck | 21:b84a77dfb43c | 221 | } |
dudmuck | 21:b84a77dfb43c | 222 | |
dudmuck | 21:b84a77dfb43c | 223 | uint32_t gen_crc(const uint8_t *p, size_t n) |
dudmuck | 21:b84a77dfb43c | 224 | { |
dudmuck | 21:b84a77dfb43c | 225 | uint32_t crc = 0xffffffff; |
dudmuck | 21:b84a77dfb43c | 226 | size_t i; |
dudmuck | 21:b84a77dfb43c | 227 | for(i = 0; i < n; i++) { |
dudmuck | 21:b84a77dfb43c | 228 | crc = crcTable[*p++ ^ (crc&0xff)] ^ (crc>>8); |
dudmuck | 21:b84a77dfb43c | 229 | } |
dudmuck | 21:b84a77dfb43c | 230 | |
dudmuck | 21:b84a77dfb43c | 231 | return(~crc); |
dudmuck | 21:b84a77dfb43c | 232 | } |
dudmuck | 21:b84a77dfb43c | 233 | |
dudmuck | 21:b84a77dfb43c | 234 | |
dudmuck | 0:be215de91a68 | 235 | void printLoraIrqs_(bool clear) |
dudmuck | 0:be215de91a68 | 236 | { |
dudmuck | 0:be215de91a68 | 237 | //in radio class -- RegIrqFlags_t RegIrqFlags; |
dudmuck | 0:be215de91a68 | 238 | |
dudmuck | 0:be215de91a68 | 239 | //already read RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 0:be215de91a68 | 240 | printf("\r\nIrqFlags:"); |
dudmuck | 1:1cd0afbed23c | 241 | if (lora.RegIrqFlags.bits.CadDetected) |
dudmuck | 0:be215de91a68 | 242 | printf("CadDetected "); |
dudmuck | 1:1cd0afbed23c | 243 | if (lora.RegIrqFlags.bits.FhssChangeChannel) { |
dudmuck | 0:be215de91a68 | 244 | //radio.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); |
dudmuck | 1:1cd0afbed23c | 245 | printf("FhssChangeChannel:%d ", lora.RegHopChannel.bits.FhssPresentChannel); |
dudmuck | 0:be215de91a68 | 246 | } |
dudmuck | 1:1cd0afbed23c | 247 | if (lora.RegIrqFlags.bits.CadDone) |
dudmuck | 0:be215de91a68 | 248 | printf("CadDone "); |
dudmuck | 1:1cd0afbed23c | 249 | if (lora.RegIrqFlags.bits.TxDone) |
dudmuck | 0:be215de91a68 | 250 | printf("TxDone "); |
dudmuck | 1:1cd0afbed23c | 251 | if (lora.RegIrqFlags.bits.ValidHeader) |
dudmuck | 0:be215de91a68 | 252 | printf("[42mValidHeader[0m "); |
dudmuck | 1:1cd0afbed23c | 253 | if (lora.RegIrqFlags.bits.PayloadCrcError) |
dudmuck | 0:be215de91a68 | 254 | printf("[41mPayloadCrcError[0m "); |
dudmuck | 1:1cd0afbed23c | 255 | if (lora.RegIrqFlags.bits.RxDone) |
dudmuck | 0:be215de91a68 | 256 | printf("[42mRxDone[0m "); |
dudmuck | 1:1cd0afbed23c | 257 | if (lora.RegIrqFlags.bits.RxTimeout) |
dudmuck | 0:be215de91a68 | 258 | printf("RxTimeout "); |
dudmuck | 0:be215de91a68 | 259 | |
dudmuck | 0:be215de91a68 | 260 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 261 | |
dudmuck | 0:be215de91a68 | 262 | if (clear) |
dudmuck | 1:1cd0afbed23c | 263 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 0:be215de91a68 | 264 | |
dudmuck | 0:be215de91a68 | 265 | } |
dudmuck | 0:be215de91a68 | 266 | |
dudmuck | 1:1cd0afbed23c | 267 | void lora_printCodingRate(bool from_rx) |
dudmuck | 0:be215de91a68 | 268 | { |
dudmuck | 1:1cd0afbed23c | 269 | uint8_t d = lora.getCodingRate(from_rx); |
dudmuck | 0:be215de91a68 | 270 | printf("CodingRate:"); |
dudmuck | 0:be215de91a68 | 271 | switch (d) { |
dudmuck | 0:be215de91a68 | 272 | case 1: printf("4/5 "); break; |
dudmuck | 0:be215de91a68 | 273 | case 2: printf("4/6 "); break; |
dudmuck | 0:be215de91a68 | 274 | case 3: printf("4/7 "); break; |
dudmuck | 0:be215de91a68 | 275 | case 4: printf("4/8 "); break; |
dudmuck | 0:be215de91a68 | 276 | default: |
dudmuck | 0:be215de91a68 | 277 | printf("%d ", d); |
dudmuck | 0:be215de91a68 | 278 | break; |
dudmuck | 0:be215de91a68 | 279 | } |
dudmuck | 0:be215de91a68 | 280 | } |
dudmuck | 0:be215de91a68 | 281 | |
dudmuck | 1:1cd0afbed23c | 282 | void lora_printHeaderMode() |
dudmuck | 0:be215de91a68 | 283 | { |
dudmuck | 1:1cd0afbed23c | 284 | if (lora.getHeaderMode()) |
dudmuck | 0:be215de91a68 | 285 | printf("implicit "); |
dudmuck | 0:be215de91a68 | 286 | else |
dudmuck | 0:be215de91a68 | 287 | printf("explicit "); |
dudmuck | 0:be215de91a68 | 288 | } |
dudmuck | 0:be215de91a68 | 289 | |
dudmuck | 1:1cd0afbed23c | 290 | void lora_printBw() |
dudmuck | 0:be215de91a68 | 291 | { |
dudmuck | 19:be8a8b0e7320 | 292 | (void)lora.getBw(); |
dudmuck | 0:be215de91a68 | 293 | |
dudmuck | 0:be215de91a68 | 294 | printf("Bw:"); |
dudmuck | 0:be215de91a68 | 295 | if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 296 | switch (lora.RegModemConfig.sx1276bits.Bw) { |
dudmuck | 0:be215de91a68 | 297 | case 0: printf("7.8KHz "); break; |
dudmuck | 0:be215de91a68 | 298 | case 1: printf("10.4KHz "); break; |
dudmuck | 0:be215de91a68 | 299 | case 2: printf("15.6KHz "); break; |
dudmuck | 0:be215de91a68 | 300 | case 3: printf("20.8KHz "); break; |
dudmuck | 0:be215de91a68 | 301 | case 4: printf("31.25KHz "); break; |
dudmuck | 0:be215de91a68 | 302 | case 5: printf("41.7KHz "); break; |
dudmuck | 0:be215de91a68 | 303 | case 6: printf("62.5KHz "); break; |
dudmuck | 0:be215de91a68 | 304 | case 7: printf("125KHz "); break; |
dudmuck | 0:be215de91a68 | 305 | case 8: printf("250KHz "); break; |
dudmuck | 0:be215de91a68 | 306 | case 9: printf("500KHz "); break; |
dudmuck | 1:1cd0afbed23c | 307 | default: printf("%x ", lora.RegModemConfig.sx1276bits.Bw); break; |
dudmuck | 0:be215de91a68 | 308 | } |
dudmuck | 0:be215de91a68 | 309 | } else if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 310 | switch (lora.RegModemConfig.sx1272bits.Bw) { |
dudmuck | 0:be215de91a68 | 311 | case 0: printf("125KHz "); break; |
dudmuck | 0:be215de91a68 | 312 | case 1: printf("250KHz "); break; |
dudmuck | 0:be215de91a68 | 313 | case 2: printf("500KHz "); break; |
dudmuck | 0:be215de91a68 | 314 | case 3: printf("11b "); break; |
dudmuck | 0:be215de91a68 | 315 | } |
dudmuck | 0:be215de91a68 | 316 | } |
dudmuck | 0:be215de91a68 | 317 | } |
dudmuck | 0:be215de91a68 | 318 | |
dudmuck | 1:1cd0afbed23c | 319 | void lora_printAllBw() |
dudmuck | 0:be215de91a68 | 320 | { |
dudmuck | 0:be215de91a68 | 321 | int i, s; |
dudmuck | 0:be215de91a68 | 322 | |
dudmuck | 0:be215de91a68 | 323 | if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 324 | s = lora.RegModemConfig.sx1276bits.Bw; |
dudmuck | 0:be215de91a68 | 325 | for (i = 0; i < 10; i++ ) { |
dudmuck | 1:1cd0afbed23c | 326 | lora.RegModemConfig.sx1276bits.Bw = i; |
dudmuck | 0:be215de91a68 | 327 | printf("%d ", i); |
dudmuck | 1:1cd0afbed23c | 328 | lora_printBw(); |
dudmuck | 0:be215de91a68 | 329 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 330 | } |
dudmuck | 1:1cd0afbed23c | 331 | lora.RegModemConfig.sx1276bits.Bw = s; |
dudmuck | 0:be215de91a68 | 332 | } else if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 333 | s = lora.RegModemConfig.sx1272bits.Bw; |
dudmuck | 0:be215de91a68 | 334 | for (i = 0; i < 3; i++ ) { |
dudmuck | 1:1cd0afbed23c | 335 | lora.RegModemConfig.sx1272bits.Bw = i; |
dudmuck | 0:be215de91a68 | 336 | printf("%d ", i); |
dudmuck | 1:1cd0afbed23c | 337 | lora_printBw(); |
dudmuck | 0:be215de91a68 | 338 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 339 | } |
dudmuck | 1:1cd0afbed23c | 340 | lora.RegModemConfig.sx1272bits.Bw = s; |
dudmuck | 0:be215de91a68 | 341 | } |
dudmuck | 0:be215de91a68 | 342 | } |
dudmuck | 0:be215de91a68 | 343 | |
dudmuck | 1:1cd0afbed23c | 344 | void lora_printSf() |
dudmuck | 0:be215de91a68 | 345 | { |
dudmuck | 0:be215de91a68 | 346 | // spreading factor same between sx127[26] |
dudmuck | 1:1cd0afbed23c | 347 | printf("sf:%d ", lora.getSf()); |
dudmuck | 0:be215de91a68 | 348 | } |
dudmuck | 0:be215de91a68 | 349 | |
dudmuck | 1:1cd0afbed23c | 350 | void lora_printRxPayloadCrcOn() |
dudmuck | 0:be215de91a68 | 351 | { |
dudmuck | 1:1cd0afbed23c | 352 | bool on = lora.getRxPayloadCrcOn(); |
dudmuck | 18:9530d682fd9a | 353 | printf("RxPayloadCrcOn:%d = ", on); |
dudmuck | 18:9530d682fd9a | 354 | if (lora.getHeaderMode()) |
dudmuck | 18:9530d682fd9a | 355 | printf("Rx/"); // implicit mode |
dudmuck | 18:9530d682fd9a | 356 | |
dudmuck | 0:be215de91a68 | 357 | if (on) |
dudmuck | 18:9530d682fd9a | 358 | printf("Tx CRC Enabled\r\n"); |
dudmuck | 0:be215de91a68 | 359 | else |
dudmuck | 18:9530d682fd9a | 360 | printf("Tx CRC disabled\r\n"); |
dudmuck | 0:be215de91a68 | 361 | } |
dudmuck | 0:be215de91a68 | 362 | |
dudmuck | 1:1cd0afbed23c | 363 | void lora_printTxContinuousMode() |
dudmuck | 0:be215de91a68 | 364 | { |
dudmuck | 1:1cd0afbed23c | 365 | printf("TxContinuousMode:%d ", lora.RegModemConfig2.sx1276bits.TxContinuousMode); // same for sx1272 and sx1276 |
dudmuck | 0:be215de91a68 | 366 | } |
dudmuck | 0:be215de91a68 | 367 | |
dudmuck | 1:1cd0afbed23c | 368 | void lora_printAgcAutoOn() |
dudmuck | 0:be215de91a68 | 369 | { |
dudmuck | 1:1cd0afbed23c | 370 | printf("AgcAutoOn:%d", lora.getAgcAutoOn()); |
dudmuck | 0:be215de91a68 | 371 | } |
dudmuck | 0:be215de91a68 | 372 | |
dudmuck | 1:1cd0afbed23c | 373 | void lora_print_dio() |
dudmuck | 0:be215de91a68 | 374 | { |
dudmuck | 1:1cd0afbed23c | 375 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 0:be215de91a68 | 376 | printf("DIO5:"); |
dudmuck | 0:be215de91a68 | 377 | switch (radio.RegDioMapping2.bits.Dio5Mapping) { |
dudmuck | 0:be215de91a68 | 378 | case 0: printf("ModeReady"); break; |
dudmuck | 0:be215de91a68 | 379 | case 1: printf("ClkOut"); break; |
dudmuck | 0:be215de91a68 | 380 | case 2: printf("ClkOut"); break; |
dudmuck | 0:be215de91a68 | 381 | } |
dudmuck | 0:be215de91a68 | 382 | printf(" DIO4:"); |
dudmuck | 0:be215de91a68 | 383 | switch (radio.RegDioMapping2.bits.Dio4Mapping) { |
dudmuck | 0:be215de91a68 | 384 | case 0: printf("CadDetected"); break; |
dudmuck | 0:be215de91a68 | 385 | case 1: printf("PllLock"); break; |
dudmuck | 0:be215de91a68 | 386 | case 2: printf("PllLock"); break; |
dudmuck | 0:be215de91a68 | 387 | } |
dudmuck | 0:be215de91a68 | 388 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 0:be215de91a68 | 389 | printf(" DIO3:"); |
dudmuck | 0:be215de91a68 | 390 | switch (radio.RegDioMapping1.bits.Dio3Mapping) { |
dudmuck | 0:be215de91a68 | 391 | case 0: printf("CadDone"); break; |
dudmuck | 0:be215de91a68 | 392 | case 1: printf("ValidHeader"); break; |
dudmuck | 0:be215de91a68 | 393 | case 2: printf("PayloadCrcError"); break; |
dudmuck | 0:be215de91a68 | 394 | } |
dudmuck | 0:be215de91a68 | 395 | printf(" DIO2:"); |
dudmuck | 0:be215de91a68 | 396 | switch (radio.RegDioMapping1.bits.Dio2Mapping) { |
dudmuck | 0:be215de91a68 | 397 | case 0: |
dudmuck | 0:be215de91a68 | 398 | case 1: |
dudmuck | 0:be215de91a68 | 399 | case 2: |
dudmuck | 0:be215de91a68 | 400 | printf("FhssChangeChannel"); |
dudmuck | 0:be215de91a68 | 401 | break; |
dudmuck | 0:be215de91a68 | 402 | } |
dudmuck | 0:be215de91a68 | 403 | printf(" DIO1:"); |
dudmuck | 0:be215de91a68 | 404 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 0:be215de91a68 | 405 | case 0: printf("RxTimeout"); break; |
dudmuck | 0:be215de91a68 | 406 | case 1: printf("FhssChangeChannel"); break; |
dudmuck | 0:be215de91a68 | 407 | case 2: printf("CadDetected"); break; |
dudmuck | 0:be215de91a68 | 408 | } |
dudmuck | 0:be215de91a68 | 409 | printf(" DIO0:"); |
dudmuck | 0:be215de91a68 | 410 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 0:be215de91a68 | 411 | case 0: printf("RxDone"); break; |
dudmuck | 0:be215de91a68 | 412 | case 1: printf("TxDone"); break; |
dudmuck | 0:be215de91a68 | 413 | case 2: printf("CadDone"); break; |
dudmuck | 0:be215de91a68 | 414 | } |
dudmuck | 0:be215de91a68 | 415 | |
dudmuck | 0:be215de91a68 | 416 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 417 | } |
dudmuck | 0:be215de91a68 | 418 | |
dudmuck | 1:1cd0afbed23c | 419 | void fsk_print_dio() |
dudmuck | 1:1cd0afbed23c | 420 | { |
dudmuck | 1:1cd0afbed23c | 421 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 1:1cd0afbed23c | 422 | |
dudmuck | 2:c6b23a43a9d9 | 423 | printf("DIO5:"); |
dudmuck | 1:1cd0afbed23c | 424 | switch (radio.RegDioMapping2.bits.Dio5Mapping) { |
dudmuck | 1:1cd0afbed23c | 425 | case 0: printf("ClkOut"); break; |
dudmuck | 1:1cd0afbed23c | 426 | case 1: printf("PllLock"); break; |
dudmuck | 1:1cd0afbed23c | 427 | case 2: |
dudmuck | 1:1cd0afbed23c | 428 | if (fsk.RegPktConfig2.bits.DataModePacket) |
dudmuck | 1:1cd0afbed23c | 429 | printf("data"); |
dudmuck | 1:1cd0afbed23c | 430 | else { |
dudmuck | 1:1cd0afbed23c | 431 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 432 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 433 | else |
dudmuck | 1:1cd0afbed23c | 434 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 435 | } |
dudmuck | 1:1cd0afbed23c | 436 | break; |
dudmuck | 1:1cd0afbed23c | 437 | case 3: printf("ModeReady"); break; |
dudmuck | 1:1cd0afbed23c | 438 | } |
dudmuck | 1:1cd0afbed23c | 439 | |
dudmuck | 2:c6b23a43a9d9 | 440 | printf(" DIO4:"); |
dudmuck | 1:1cd0afbed23c | 441 | switch (radio.RegDioMapping2.bits.Dio4Mapping) { |
dudmuck | 1:1cd0afbed23c | 442 | case 0: printf("temp/eol"); break; |
dudmuck | 1:1cd0afbed23c | 443 | case 1: printf("PllLock"); break; |
dudmuck | 1:1cd0afbed23c | 444 | case 2: printf("TimeOut"); break; |
dudmuck | 1:1cd0afbed23c | 445 | case 3: |
dudmuck | 1:1cd0afbed23c | 446 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 447 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 448 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 449 | else |
dudmuck | 1:1cd0afbed23c | 450 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 451 | } else |
dudmuck | 1:1cd0afbed23c | 452 | printf("ModeReady"); |
dudmuck | 1:1cd0afbed23c | 453 | break; |
dudmuck | 1:1cd0afbed23c | 454 | } |
dudmuck | 1:1cd0afbed23c | 455 | |
dudmuck | 1:1cd0afbed23c | 456 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 1:1cd0afbed23c | 457 | |
dudmuck | 2:c6b23a43a9d9 | 458 | printf(" DIO3:"); |
dudmuck | 21:b84a77dfb43c | 459 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 21:b84a77dfb43c | 460 | if (radio.RegDioMapping1.bits.Dio3Mapping == 1) |
dudmuck | 21:b84a77dfb43c | 461 | printf("TxReady"); |
dudmuck | 21:b84a77dfb43c | 462 | else |
dudmuck | 21:b84a77dfb43c | 463 | printf("FifoEmpty"); |
dudmuck | 21:b84a77dfb43c | 464 | } else { |
dudmuck | 21:b84a77dfb43c | 465 | switch (radio.RegDioMapping1.bits.Dio3Mapping) { |
dudmuck | 21:b84a77dfb43c | 466 | case 0: printf("Timeout"); break; |
dudmuck | 21:b84a77dfb43c | 467 | case 1: |
dudmuck | 21:b84a77dfb43c | 468 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 21:b84a77dfb43c | 469 | printf("preamble"); |
dudmuck | 21:b84a77dfb43c | 470 | else |
dudmuck | 21:b84a77dfb43c | 471 | printf("rssi"); |
dudmuck | 21:b84a77dfb43c | 472 | break; |
dudmuck | 21:b84a77dfb43c | 473 | case 2: printf("?automode_status?"); break; |
dudmuck | 21:b84a77dfb43c | 474 | case 3: printf("TempChange/LowBat"); break; |
dudmuck | 21:b84a77dfb43c | 475 | } |
dudmuck | 1:1cd0afbed23c | 476 | } |
dudmuck | 1:1cd0afbed23c | 477 | |
dudmuck | 2:c6b23a43a9d9 | 478 | printf(" DIO2:"); |
dudmuck | 1:1cd0afbed23c | 479 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 480 | switch (radio.RegDioMapping1.bits.Dio2Mapping) { |
dudmuck | 1:1cd0afbed23c | 481 | case 0: printf("FifoFull"); break; |
dudmuck | 1:1cd0afbed23c | 482 | case 1: printf("RxReady"); break; |
dudmuck | 1:1cd0afbed23c | 483 | case 2: printf("FifoFull/rx-timeout"); break; |
dudmuck | 1:1cd0afbed23c | 484 | case 3: printf("FifoFull/rx-syncadrs"); break; |
dudmuck | 1:1cd0afbed23c | 485 | } |
dudmuck | 1:1cd0afbed23c | 486 | } else { |
dudmuck | 1:1cd0afbed23c | 487 | printf("Data"); |
dudmuck | 1:1cd0afbed23c | 488 | } |
dudmuck | 1:1cd0afbed23c | 489 | |
dudmuck | 2:c6b23a43a9d9 | 490 | printf(" DIO1:"); |
dudmuck | 1:1cd0afbed23c | 491 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 492 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 1:1cd0afbed23c | 493 | case 0: printf("FifoThresh"); break; |
dudmuck | 1:1cd0afbed23c | 494 | case 1: printf("FifoEmpty"); break; |
dudmuck | 1:1cd0afbed23c | 495 | case 2: printf("FifoFull"); break; |
dudmuck | 1:1cd0afbed23c | 496 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 497 | } |
dudmuck | 1:1cd0afbed23c | 498 | } else { |
dudmuck | 1:1cd0afbed23c | 499 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 1:1cd0afbed23c | 500 | case 0: printf("Dclk"); break; |
dudmuck | 1:1cd0afbed23c | 501 | case 1: |
dudmuck | 1:1cd0afbed23c | 502 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 503 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 504 | else |
dudmuck | 1:1cd0afbed23c | 505 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 506 | break; |
dudmuck | 1:1cd0afbed23c | 507 | case 2: printf("[41m-2-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 508 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 509 | } |
dudmuck | 1:1cd0afbed23c | 510 | } |
dudmuck | 1:1cd0afbed23c | 511 | |
dudmuck | 2:c6b23a43a9d9 | 512 | printf(" DIO0:"); |
dudmuck | 1:1cd0afbed23c | 513 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 514 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 1:1cd0afbed23c | 515 | case 0: printf("PayloadReady/PacketSent"); break; |
dudmuck | 1:1cd0afbed23c | 516 | case 1: printf("CrcOk"); break; |
dudmuck | 1:1cd0afbed23c | 517 | case 2: printf("[41m-2-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 518 | case 3: printf("TempChange/LowBat"); break; |
dudmuck | 1:1cd0afbed23c | 519 | } |
dudmuck | 1:1cd0afbed23c | 520 | } else { |
dudmuck | 1:1cd0afbed23c | 521 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 1:1cd0afbed23c | 522 | case 0: printf("SyncAdrs/TxReady"); break; |
dudmuck | 1:1cd0afbed23c | 523 | case 1: |
dudmuck | 1:1cd0afbed23c | 524 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 525 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 526 | else |
dudmuck | 1:1cd0afbed23c | 527 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 528 | break; |
dudmuck | 1:1cd0afbed23c | 529 | case 2: printf("RxReady"); break; |
dudmuck | 1:1cd0afbed23c | 530 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 531 | } |
dudmuck | 1:1cd0afbed23c | 532 | } |
dudmuck | 1:1cd0afbed23c | 533 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 534 | } |
dudmuck | 1:1cd0afbed23c | 535 | |
dudmuck | 0:be215de91a68 | 536 | void lora_print_status() |
dudmuck | 15:c69b942685ea | 537 | { |
dudmuck | 0:be215de91a68 | 538 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 0:be215de91a68 | 539 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 0:be215de91a68 | 540 | printf("FSK\r\n"); |
dudmuck | 0:be215de91a68 | 541 | return; |
dudmuck | 0:be215de91a68 | 542 | } |
dudmuck | 0:be215de91a68 | 543 | |
dudmuck | 1:1cd0afbed23c | 544 | lora_print_dio(); |
dudmuck | 0:be215de91a68 | 545 | printf("LoRa "); |
dudmuck | 0:be215de91a68 | 546 | |
dudmuck | 0:be215de91a68 | 547 | // printing LoRa registers at 0x0d -> 0x3f |
dudmuck | 0:be215de91a68 | 548 | |
dudmuck | 1:1cd0afbed23c | 549 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 1:1cd0afbed23c | 550 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 0:be215de91a68 | 551 | |
dudmuck | 1:1cd0afbed23c | 552 | lora_printCodingRate(false); // false: transmitted coding rate |
dudmuck | 1:1cd0afbed23c | 553 | lora_printHeaderMode(); |
dudmuck | 1:1cd0afbed23c | 554 | lora_printBw(); |
dudmuck | 1:1cd0afbed23c | 555 | lora_printSf(); |
dudmuck | 1:1cd0afbed23c | 556 | lora_printRxPayloadCrcOn(); |
dudmuck | 0:be215de91a68 | 557 | // RegModemStat |
dudmuck | 0:be215de91a68 | 558 | printf("ModemStat:0x%02x\r\n", radio.read_reg(REG_LR_MODEMSTAT)); |
dudmuck | 0:be215de91a68 | 559 | |
dudmuck | 0:be215de91a68 | 560 | // fifo ptrs: |
dudmuck | 1:1cd0afbed23c | 561 | lora.RegPayloadLength = radio.read_reg(REG_LR_PAYLOADLENGTH); |
dudmuck | 1:1cd0afbed23c | 562 | lora.RegRxMaxPayloadLength = radio.read_reg(REG_LR_RX_MAX_PAYLOADLENGTH); |
dudmuck | 0:be215de91a68 | 563 | printf("fifoptr=0x%02x txbase=0x%02x rxbase=0x%02x payloadLength=0x%02x maxlen=0x%02x", |
dudmuck | 0:be215de91a68 | 564 | radio.read_reg(REG_LR_FIFOADDRPTR), |
dudmuck | 0:be215de91a68 | 565 | radio.read_reg(REG_LR_FIFOTXBASEADDR), |
dudmuck | 0:be215de91a68 | 566 | radio.read_reg(REG_LR_FIFORXBASEADDR), |
dudmuck | 1:1cd0afbed23c | 567 | lora.RegPayloadLength, |
dudmuck | 1:1cd0afbed23c | 568 | lora.RegRxMaxPayloadLength |
dudmuck | 0:be215de91a68 | 569 | ); |
dudmuck | 0:be215de91a68 | 570 | |
dudmuck | 1:1cd0afbed23c | 571 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 0:be215de91a68 | 572 | printLoraIrqs_(false); |
dudmuck | 0:be215de91a68 | 573 | |
dudmuck | 1:1cd0afbed23c | 574 | lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); |
dudmuck | 1:1cd0afbed23c | 575 | if (lora.RegHopPeriod != 0) { |
dudmuck | 1:1cd0afbed23c | 576 | printf("\r\nHopPeriod:0x%02x\r\n", lora.RegHopPeriod); |
dudmuck | 0:be215de91a68 | 577 | } |
dudmuck | 0:be215de91a68 | 578 | |
dudmuck | 18:9530d682fd9a | 579 | printf("SymbTimeout:%d ", radio.read_u16(REG_LR_MODEMCONFIG2) & 0x3ff); |
dudmuck | 0:be215de91a68 | 580 | |
dudmuck | 1:1cd0afbed23c | 581 | lora.RegPreamble = radio.read_u16(REG_LR_PREAMBLEMSB); |
dudmuck | 4:7a9007dfc0e5 | 582 | printf("PreambleLength:%d ", lora.RegPreamble); |
dudmuck | 0:be215de91a68 | 583 | |
dudmuck | 0:be215de91a68 | 584 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER_SINGLE) { |
dudmuck | 15:c69b942685ea | 585 | printf("rssi:%ddBm ", lora.get_current_rssi()); |
dudmuck | 0:be215de91a68 | 586 | } |
dudmuck | 0:be215de91a68 | 587 | |
dudmuck | 1:1cd0afbed23c | 588 | lora_printTxContinuousMode(); |
dudmuck | 0:be215de91a68 | 589 | |
dudmuck | 0:be215de91a68 | 590 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 591 | lora_printAgcAutoOn(); |
dudmuck | 0:be215de91a68 | 592 | if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 593 | printf(" LowDataRateOptimize:%d\r\n", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 594 | } |
dudmuck | 0:be215de91a68 | 595 | |
dudmuck | 0:be215de91a68 | 596 | printf("\r\nHeaderCount:%d PacketCount:%d, ", |
dudmuck | 0:be215de91a68 | 597 | radio.read_u16(REG_LR_RXHEADERCNTVALUE_MSB), radio.read_u16(REG_LR_RXPACKETCNTVALUE_MSB)); |
dudmuck | 0:be215de91a68 | 598 | |
dudmuck | 0:be215de91a68 | 599 | printf("Lora detection threshold:%02x\r\n", radio.read_reg(REG_LR_DETECTION_THRESHOLD)); |
dudmuck | 1:1cd0afbed23c | 600 | lora.RegTest31.octet = radio.read_reg(REG_LR_TEST31); |
dudmuck | 1:1cd0afbed23c | 601 | printf("detect_trig_same_peaks_nb:%d\r\n", lora.RegTest31.bits.detect_trig_same_peaks_nb); |
dudmuck | 0:be215de91a68 | 602 | |
dudmuck | 0:be215de91a68 | 603 | if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 604 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 6:fe16f96ee335 | 605 | printf("LowDataRateOptimize:%d ", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 606 | } else if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 607 | lora.RegModemConfig3.octet = radio.read_reg(REG_LR_MODEMCONFIG3); |
dudmuck | 6:fe16f96ee335 | 608 | printf("LowDataRateOptimize:%d ", lora.RegModemConfig3.sx1276bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 609 | } |
dudmuck | 0:be215de91a68 | 610 | |
dudmuck | 6:fe16f96ee335 | 611 | printf(" invert: rx=%d tx=%d\r\n", lora.RegTest33.bits.invert_i_q, !lora.RegTest33.bits.chirp_invert_tx); |
dudmuck | 6:fe16f96ee335 | 612 | |
dudmuck | 0:be215de91a68 | 613 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 614 | //printf("A %02x\r\n", radio.RegModemConfig2.octet); |
dudmuck | 0:be215de91a68 | 615 | } |
dudmuck | 0:be215de91a68 | 616 | |
dudmuck | 1:1cd0afbed23c | 617 | uint16_t |
dudmuck | 1:1cd0afbed23c | 618 | fsk_get_PayloadLength(void) |
dudmuck | 1:1cd0afbed23c | 619 | { |
dudmuck | 1:1cd0afbed23c | 620 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 1:1cd0afbed23c | 621 | |
dudmuck | 1:1cd0afbed23c | 622 | return fsk.RegPktConfig2.bits.PayloadLength; |
dudmuck | 1:1cd0afbed23c | 623 | } |
dudmuck | 1:1cd0afbed23c | 624 | |
dudmuck | 1:1cd0afbed23c | 625 | void fsk_printAddressFiltering() |
dudmuck | 1:1cd0afbed23c | 626 | { |
dudmuck | 1:1cd0afbed23c | 627 | uint8_t FSKRegNodeAdrs, FSKRegBroadcastAdrs; |
dudmuck | 1:1cd0afbed23c | 628 | |
dudmuck | 1:1cd0afbed23c | 629 | printf(" AddressFiltering:"); |
dudmuck | 1:1cd0afbed23c | 630 | switch (fsk.RegPktConfig1.bits.AddressFiltering) { |
dudmuck | 1:1cd0afbed23c | 631 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 632 | case 1: // NodeAddress |
dudmuck | 1:1cd0afbed23c | 633 | FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); |
dudmuck | 6:fe16f96ee335 | 634 | printf("NodeAdrs:%02x\r\n", FSKRegNodeAdrs); |
dudmuck | 1:1cd0afbed23c | 635 | break; |
dudmuck | 1:1cd0afbed23c | 636 | case 2: // NodeAddress & BroadcastAddress |
dudmuck | 1:1cd0afbed23c | 637 | FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); |
dudmuck | 1:1cd0afbed23c | 638 | printf("NodeAdrs:%02x ", FSKRegNodeAdrs); |
dudmuck | 1:1cd0afbed23c | 639 | FSKRegBroadcastAdrs = radio.read_reg(REG_FSK_BROADCASTADRS); |
dudmuck | 6:fe16f96ee335 | 640 | printf("BroadcastAdrs:%02x\r\n", FSKRegBroadcastAdrs ); |
dudmuck | 1:1cd0afbed23c | 641 | break; |
dudmuck | 1:1cd0afbed23c | 642 | default: |
dudmuck | 1:1cd0afbed23c | 643 | printf("%d", fsk.RegPktConfig1.bits.AddressFiltering); |
dudmuck | 1:1cd0afbed23c | 644 | break; |
dudmuck | 1:1cd0afbed23c | 645 | } |
dudmuck | 1:1cd0afbed23c | 646 | } |
dudmuck | 1:1cd0afbed23c | 647 | |
dudmuck | 1:1cd0afbed23c | 648 | void fsk_print_IrqFlags2() |
dudmuck | 1:1cd0afbed23c | 649 | { |
dudmuck | 2:c6b23a43a9d9 | 650 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 1:1cd0afbed23c | 651 | |
dudmuck | 1:1cd0afbed23c | 652 | printf("IrqFlags2: "); |
dudmuck | 2:c6b23a43a9d9 | 653 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 2:c6b23a43a9d9 | 654 | if (RegIrqFlags2.bits.FifoFull) |
dudmuck | 1:1cd0afbed23c | 655 | printf("FifoFull "); |
dudmuck | 2:c6b23a43a9d9 | 656 | if (RegIrqFlags2.bits.FifoEmpty) |
dudmuck | 1:1cd0afbed23c | 657 | printf("FifoEmpty "); |
dudmuck | 2:c6b23a43a9d9 | 658 | if (RegIrqFlags2.bits.FifoLevel) |
dudmuck | 1:1cd0afbed23c | 659 | printf("FifoLevel "); |
dudmuck | 2:c6b23a43a9d9 | 660 | if (RegIrqFlags2.bits.FifoOverrun) |
dudmuck | 1:1cd0afbed23c | 661 | printf("FifoOverrun "); |
dudmuck | 2:c6b23a43a9d9 | 662 | if (RegIrqFlags2.bits.PacketSent) |
dudmuck | 1:1cd0afbed23c | 663 | printf("PacketSent "); |
dudmuck | 2:c6b23a43a9d9 | 664 | if (RegIrqFlags2.bits.PayloadReady) |
dudmuck | 1:1cd0afbed23c | 665 | printf("PayloadReady "); |
dudmuck | 2:c6b23a43a9d9 | 666 | if (RegIrqFlags2.bits.CrcOk) |
dudmuck | 1:1cd0afbed23c | 667 | printf("CrcOk "); |
dudmuck | 2:c6b23a43a9d9 | 668 | if (RegIrqFlags2.bits.LowBat) |
dudmuck | 1:1cd0afbed23c | 669 | printf("LowBat "); |
dudmuck | 2:c6b23a43a9d9 | 670 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 671 | } |
dudmuck | 1:1cd0afbed23c | 672 | |
dudmuck | 1:1cd0afbed23c | 673 | void |
dudmuck | 1:1cd0afbed23c | 674 | fsk_print_status() |
dudmuck | 1:1cd0afbed23c | 675 | { |
dudmuck | 1:1cd0afbed23c | 676 | //uint16_t s; |
dudmuck | 2:c6b23a43a9d9 | 677 | RegIrqFlags1_t RegIrqFlags1; |
dudmuck | 1:1cd0afbed23c | 678 | |
dudmuck | 1:1cd0afbed23c | 679 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 1:1cd0afbed23c | 680 | printf("LoRa\r\n"); |
dudmuck | 1:1cd0afbed23c | 681 | return; |
dudmuck | 1:1cd0afbed23c | 682 | } |
dudmuck | 1:1cd0afbed23c | 683 | |
dudmuck | 1:1cd0afbed23c | 684 | if (radio.RegOpMode.bits.ModulationType == 0) { |
dudmuck | 1:1cd0afbed23c | 685 | printf("FSK "); |
dudmuck | 1:1cd0afbed23c | 686 | switch (radio.RegOpMode.bits.ModulationShaping) { |
dudmuck | 1:1cd0afbed23c | 687 | case 1: printf("BT1.0 "); break; |
dudmuck | 1:1cd0afbed23c | 688 | case 2: printf("BT0.5 "); break; |
dudmuck | 1:1cd0afbed23c | 689 | case 3: printf("BT0.3 "); break; |
dudmuck | 1:1cd0afbed23c | 690 | } |
dudmuck | 1:1cd0afbed23c | 691 | } else if (radio.RegOpMode.bits.ModulationType == 1) { |
dudmuck | 1:1cd0afbed23c | 692 | printf("OOK "); |
dudmuck | 18:9530d682fd9a | 693 | switch (radio.RegOpMode.bits.ModulationShaping) { |
dudmuck | 18:9530d682fd9a | 694 | case 1: printf("Fcutoff=bitrate"); break; |
dudmuck | 18:9530d682fd9a | 695 | case 2: printf("Fcutoff=2*bitrate"); break; |
dudmuck | 18:9530d682fd9a | 696 | case 3: printf("?"); break; |
dudmuck | 18:9530d682fd9a | 697 | } |
dudmuck | 1:1cd0afbed23c | 698 | } |
dudmuck | 1:1cd0afbed23c | 699 | |
dudmuck | 19:be8a8b0e7320 | 700 | printf("%" PRIu32 "bps fdev:%" PRIu32 "Hz\r\n", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 1:1cd0afbed23c | 701 | |
dudmuck | 1:1cd0afbed23c | 702 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 1:1cd0afbed23c | 703 | |
dudmuck | 1:1cd0afbed23c | 704 | fsk_print_dio(); |
dudmuck | 1:1cd0afbed23c | 705 | |
dudmuck | 19:be8a8b0e7320 | 706 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 19:be8a8b0e7320 | 707 | printf("afcbw:%" PRIu32 "Hz\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW)); |
dudmuck | 1:1cd0afbed23c | 708 | |
dudmuck | 1:1cd0afbed23c | 709 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 1:1cd0afbed23c | 710 | printf("RssiOffset:%ddB smoothing:%dsamples\r\n", fsk.RegRssiConfig.bits.RssiOffset, 1 << (fsk.RegRssiConfig.bits.RssiSmoothing+1)); |
dudmuck | 1:1cd0afbed23c | 711 | |
dudmuck | 1:1cd0afbed23c | 712 | |
dudmuck | 1:1cd0afbed23c | 713 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 1:1cd0afbed23c | 714 | |
dudmuck | 1:1cd0afbed23c | 715 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 716 | uint16_t len; |
dudmuck | 1:1cd0afbed23c | 717 | /* packet mode */ |
dudmuck | 1:1cd0afbed23c | 718 | len = fsk_get_PayloadLength(); |
dudmuck | 1:1cd0afbed23c | 719 | printf("packet RegPayloadLength:0x%03x ", len); |
dudmuck | 1:1cd0afbed23c | 720 | |
dudmuck | 1:1cd0afbed23c | 721 | if (fsk.RegPktConfig2.bits.BeaconOn) |
dudmuck | 1:1cd0afbed23c | 722 | printf("BeaconOn "); |
dudmuck | 1:1cd0afbed23c | 723 | |
dudmuck | 1:1cd0afbed23c | 724 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 1:1cd0afbed23c | 725 | printf("FifoThreshold:%d TxStartCondition:", fsk.RegFifoThreshold.bits.FifoThreshold); |
dudmuck | 1:1cd0afbed23c | 726 | if (fsk.RegFifoThreshold.bits.TxStartCondition) |
dudmuck | 1:1cd0afbed23c | 727 | printf("!FifoEmpty"); |
dudmuck | 1:1cd0afbed23c | 728 | else |
dudmuck | 1:1cd0afbed23c | 729 | printf("FifoLevel"); |
dudmuck | 1:1cd0afbed23c | 730 | |
dudmuck | 1:1cd0afbed23c | 731 | printf("\r\nAutoRestartRxMode:"); |
dudmuck | 1:1cd0afbed23c | 732 | switch (fsk.RegSyncConfig.bits.AutoRestartRxMode) { |
dudmuck | 1:1cd0afbed23c | 733 | case 0: printf("off "); break; |
dudmuck | 1:1cd0afbed23c | 734 | case 1: printf("no-pll-wait "); break; |
dudmuck | 1:1cd0afbed23c | 735 | case 2: printf("pll-wait "); break; |
dudmuck | 1:1cd0afbed23c | 736 | case 3: printf("3 "); break; |
dudmuck | 1:1cd0afbed23c | 737 | } |
dudmuck | 1:1cd0afbed23c | 738 | //...todo |
dudmuck | 1:1cd0afbed23c | 739 | |
dudmuck | 1:1cd0afbed23c | 740 | printf("PreambleSize:%d ", radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 1:1cd0afbed23c | 741 | |
dudmuck | 1:1cd0afbed23c | 742 | fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); |
dudmuck | 1:1cd0afbed23c | 743 | if (fsk.RegOokPeak.bits.barker_en) |
dudmuck | 1:1cd0afbed23c | 744 | printf("barker "); |
dudmuck | 1:1cd0afbed23c | 745 | if (!fsk.RegOokPeak.bits.BitSyncOn) |
dudmuck | 1:1cd0afbed23c | 746 | printf("BitSyncOff "); |
dudmuck | 1:1cd0afbed23c | 747 | //...todo |
dudmuck | 1:1cd0afbed23c | 748 | |
dudmuck | 1:1cd0afbed23c | 749 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 1:1cd0afbed23c | 750 | if (fsk.RegPktConfig1.bits.PacketFormatVariable) |
dudmuck | 1:1cd0afbed23c | 751 | printf("variable"); |
dudmuck | 1:1cd0afbed23c | 752 | else |
dudmuck | 1:1cd0afbed23c | 753 | printf("fixed"); |
dudmuck | 1:1cd0afbed23c | 754 | printf("-length\r\ncrc"); |
dudmuck | 1:1cd0afbed23c | 755 | if (fsk.RegPktConfig1.bits.CrcOn) { |
dudmuck | 1:1cd0afbed23c | 756 | printf("On"); |
dudmuck | 1:1cd0afbed23c | 757 | } else |
dudmuck | 1:1cd0afbed23c | 758 | printf("Off"); |
dudmuck | 1:1cd0afbed23c | 759 | printf(" crctype:"); |
dudmuck | 1:1cd0afbed23c | 760 | if (fsk.RegPktConfig1.bits.CrCWhiteningType) |
dudmuck | 1:1cd0afbed23c | 761 | printf("IBM"); |
dudmuck | 1:1cd0afbed23c | 762 | else |
dudmuck | 1:1cd0afbed23c | 763 | printf("CCITT"); |
dudmuck | 1:1cd0afbed23c | 764 | printf(" dcFree:"); |
dudmuck | 1:1cd0afbed23c | 765 | switch (fsk.RegPktConfig1.bits.DcFree) { |
dudmuck | 1:1cd0afbed23c | 766 | case 0: printf("none "); break; |
dudmuck | 1:1cd0afbed23c | 767 | case 1: printf("Manchester "); break; |
dudmuck | 1:1cd0afbed23c | 768 | case 2: printf("Whitening "); break; |
dudmuck | 1:1cd0afbed23c | 769 | case 3: printf("[41mreserved[0m "); break; |
dudmuck | 1:1cd0afbed23c | 770 | } |
dudmuck | 1:1cd0afbed23c | 771 | fsk_printAddressFiltering(); |
dudmuck | 1:1cd0afbed23c | 772 | |
dudmuck | 1:1cd0afbed23c | 773 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 774 | fsk_print_IrqFlags2(); |
dudmuck | 1:1cd0afbed23c | 775 | } else { |
dudmuck | 1:1cd0afbed23c | 776 | /* continuous mode */ |
dudmuck | 1:1cd0afbed23c | 777 | printf("[7mcontinuous[27m "); |
dudmuck | 1:1cd0afbed23c | 778 | } |
dudmuck | 1:1cd0afbed23c | 779 | |
dudmuck | 1:1cd0afbed23c | 780 | fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); |
dudmuck | 1:1cd0afbed23c | 781 | printf("PreambleDetect:"); |
dudmuck | 1:1cd0afbed23c | 782 | if (fsk.RegPreambleDetect.bits.PreambleDetectorOn) { |
dudmuck | 1:1cd0afbed23c | 783 | printf("size=%d,tol=%d ", |
dudmuck | 1:1cd0afbed23c | 784 | fsk.RegPreambleDetect.bits.PreambleDetectorSize, |
dudmuck | 1:1cd0afbed23c | 785 | fsk.RegPreambleDetect.bits.PreambleDetectorTol); |
dudmuck | 1:1cd0afbed23c | 786 | } else |
dudmuck | 1:1cd0afbed23c | 787 | printf("Off "); |
dudmuck | 1:1cd0afbed23c | 788 | |
dudmuck | 18:9530d682fd9a | 789 | if (fsk.RegSyncConfig.bits.SyncOn) { |
dudmuck | 18:9530d682fd9a | 790 | printf(" syncsize:%d ", fsk.RegSyncConfig.bits.SyncSize); |
dudmuck | 18:9530d682fd9a | 791 | printf(" : %02x ", radio.read_reg(REG_FSK_SYNCVALUE1)); |
dudmuck | 18:9530d682fd9a | 792 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE2)); |
dudmuck | 18:9530d682fd9a | 793 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE3)); |
dudmuck | 18:9530d682fd9a | 794 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE4)); |
dudmuck | 18:9530d682fd9a | 795 | } else |
dudmuck | 18:9530d682fd9a | 796 | printf("Sync Off"); |
dudmuck | 1:1cd0afbed23c | 797 | printf("\r\n"); // end sync config |
dudmuck | 1:1cd0afbed23c | 798 | |
dudmuck | 1:1cd0afbed23c | 799 | fsk.RegAfcFei.octet = radio.read_reg(REG_FSK_AFCFEI); |
dudmuck | 1:1cd0afbed23c | 800 | printf("afcAutoClear:"); |
dudmuck | 1:1cd0afbed23c | 801 | if (fsk.RegAfcFei.bits.AfcAutoClearOn) |
dudmuck | 1:1cd0afbed23c | 802 | printf("On"); |
dudmuck | 1:1cd0afbed23c | 803 | else |
dudmuck | 1:1cd0afbed23c | 804 | printf("OFF"); |
dudmuck | 1:1cd0afbed23c | 805 | printf(" afc:%dHz ", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); |
dudmuck | 1:1cd0afbed23c | 806 | |
dudmuck | 1:1cd0afbed23c | 807 | printf("fei:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_FEIMSB))); |
dudmuck | 1:1cd0afbed23c | 808 | |
dudmuck | 1:1cd0afbed23c | 809 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 1:1cd0afbed23c | 810 | printf("RxTrigger:"); |
dudmuck | 1:1cd0afbed23c | 811 | switch (fsk.RegRxConfig.bits.RxTrigger) { |
dudmuck | 1:1cd0afbed23c | 812 | case 0: printf("none "); break; |
dudmuck | 1:1cd0afbed23c | 813 | case 1: printf("rssi "); break; |
dudmuck | 1:1cd0afbed23c | 814 | case 6: printf("preamble "); break; |
dudmuck | 1:1cd0afbed23c | 815 | case 7: printf("both "); break; |
dudmuck | 1:1cd0afbed23c | 816 | default: printf("-%d- ", fsk.RegRxConfig.bits.RxTrigger); break; |
dudmuck | 1:1cd0afbed23c | 817 | } |
dudmuck | 1:1cd0afbed23c | 818 | printf("AfcAuto:"); |
dudmuck | 1:1cd0afbed23c | 819 | if (fsk.RegRxConfig.bits.AfcAutoOn) |
dudmuck | 1:1cd0afbed23c | 820 | printf("On "); |
dudmuck | 1:1cd0afbed23c | 821 | else |
dudmuck | 1:1cd0afbed23c | 822 | printf("OFF "); |
dudmuck | 15:c69b942685ea | 823 | |
dudmuck | 15:c69b942685ea | 824 | radio.RegLna.octet = radio.read_reg(REG_LNA); |
dudmuck | 1:1cd0afbed23c | 825 | if (!fsk.RegRxConfig.bits.AgcAutoOn) { |
dudmuck | 1:1cd0afbed23c | 826 | printf("AgcAutoOff:G%d ", radio.RegLna.bits.LnaGain); |
dudmuck | 1:1cd0afbed23c | 827 | } |
dudmuck | 15:c69b942685ea | 828 | printf("LnaBoostHF:%d ", radio.RegLna.bits.LnaBoostHF); |
dudmuck | 1:1cd0afbed23c | 829 | |
dudmuck | 1:1cd0afbed23c | 830 | fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); |
dudmuck | 1:1cd0afbed23c | 831 | if (fsk.RegTimerResol.bits.hlm_started) |
dudmuck | 1:1cd0afbed23c | 832 | printf("[35mhlm_started[0m "); |
dudmuck | 1:1cd0afbed23c | 833 | else |
dudmuck | 1:1cd0afbed23c | 834 | printf("hlm_stopped "); |
dudmuck | 1:1cd0afbed23c | 835 | |
dudmuck | 1:1cd0afbed23c | 836 | fsk.RegRssiThresh = radio.read_reg(REG_FSK_RSSITHRESH); |
dudmuck | 1:1cd0afbed23c | 837 | printf("rssiThreshold:-%.1f@%02x ", fsk.RegRssiThresh / 2.0, REG_FSK_RSSITHRESH); |
dudmuck | 1:1cd0afbed23c | 838 | |
dudmuck | 1:1cd0afbed23c | 839 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 1:1cd0afbed23c | 840 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || |
dudmuck | 1:1cd0afbed23c | 841 | radio.RegOpMode.bits.Mode == RF_OPMODE_SYNTHESIZER_RX) |
dudmuck | 1:1cd0afbed23c | 842 | { |
dudmuck | 1:1cd0afbed23c | 843 | printf("rssi:-%.1f ", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 1:1cd0afbed23c | 844 | } |
dudmuck | 1:1cd0afbed23c | 845 | |
dudmuck | 1:1cd0afbed23c | 846 | fsk.RegSeqConfig1.octet = radio.read_reg(REG_FSK_SEQCONFIG1); |
dudmuck | 1:1cd0afbed23c | 847 | printf("\r\nsequencer: "); |
dudmuck | 1:1cd0afbed23c | 848 | printf("FromStart:"); |
dudmuck | 1:1cd0afbed23c | 849 | switch (fsk.RegSeqConfig1.bits.FromStart) { |
dudmuck | 1:1cd0afbed23c | 850 | case 0: |
dudmuck | 1:1cd0afbed23c | 851 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 852 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 853 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 854 | else |
dudmuck | 1:1cd0afbed23c | 855 | printf("sequencerOff"); |
dudmuck | 1:1cd0afbed23c | 856 | break; |
dudmuck | 1:1cd0afbed23c | 857 | case 1: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 858 | case 2: printf("tx"); break; |
dudmuck | 1:1cd0afbed23c | 859 | case 3: printf("tx on fifolevel"); break; |
dudmuck | 1:1cd0afbed23c | 860 | } |
dudmuck | 1:1cd0afbed23c | 861 | printf(" lowPowerSelection:"); |
dudmuck | 1:1cd0afbed23c | 862 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 863 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 864 | else |
dudmuck | 1:1cd0afbed23c | 865 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 866 | if (fsk.RegSeqConfig1.bits.FromStart != 0 && |
dudmuck | 1:1cd0afbed23c | 867 | fsk.RegSeqConfig1.bits.LowPowerSelection != 0) |
dudmuck | 1:1cd0afbed23c | 868 | { // if sequencer enabled: |
dudmuck | 1:1cd0afbed23c | 869 | printf("\r\nsequencer: IdleMode:"); |
dudmuck | 1:1cd0afbed23c | 870 | if (fsk.RegSeqConfig1.bits.IdleMode) |
dudmuck | 1:1cd0afbed23c | 871 | printf("Sleep"); |
dudmuck | 1:1cd0afbed23c | 872 | else |
dudmuck | 1:1cd0afbed23c | 873 | printf("standby"); |
dudmuck | 1:1cd0afbed23c | 874 | printf("\r\nsequencer: FromIdle to:"); |
dudmuck | 1:1cd0afbed23c | 875 | if (fsk.RegSeqConfig1.bits.FromIdle) |
dudmuck | 1:1cd0afbed23c | 876 | printf("rx"); |
dudmuck | 1:1cd0afbed23c | 877 | else |
dudmuck | 1:1cd0afbed23c | 878 | printf("tx"); |
dudmuck | 1:1cd0afbed23c | 879 | printf("\r\nsequencer: FromTransmit to:"); |
dudmuck | 1:1cd0afbed23c | 880 | if (fsk.RegSeqConfig1.bits.FromTransmit) |
dudmuck | 1:1cd0afbed23c | 881 | printf("rx-on-PacketSent"); |
dudmuck | 1:1cd0afbed23c | 882 | else { |
dudmuck | 1:1cd0afbed23c | 883 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 884 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 885 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 886 | else |
dudmuck | 1:1cd0afbed23c | 887 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 888 | printf("-on-PacketSent"); |
dudmuck | 1:1cd0afbed23c | 889 | } |
dudmuck | 1:1cd0afbed23c | 890 | fsk.RegSeqConfig2.octet = radio.read_reg(REG_FSK_SEQCONFIG2); |
dudmuck | 1:1cd0afbed23c | 891 | printf("\r\nsequencer: FromReceive:"); |
dudmuck | 1:1cd0afbed23c | 892 | switch (fsk.RegSeqConfig2.bits.FromReceive) { |
dudmuck | 1:1cd0afbed23c | 893 | case 1: printf("PacketRecevied on PayloadReady"); break; |
dudmuck | 1:1cd0afbed23c | 894 | case 2: |
dudmuck | 1:1cd0afbed23c | 895 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 896 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 897 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 898 | else |
dudmuck | 1:1cd0afbed23c | 899 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 900 | printf("-on-payloadReady"); |
dudmuck | 1:1cd0afbed23c | 901 | break; |
dudmuck | 1:1cd0afbed23c | 902 | case 3: printf("PacketRecevied-on-CrcOk"); break; |
dudmuck | 1:1cd0afbed23c | 903 | case 4: printf("SequencerOff-on-Rssi"); break; |
dudmuck | 1:1cd0afbed23c | 904 | case 5: printf("SequencerOff-on-SyncAddress"); break; |
dudmuck | 1:1cd0afbed23c | 905 | case 6: printf("SequencerOff-PreambleDetect"); break; |
dudmuck | 1:1cd0afbed23c | 906 | default: printf("-%d-", fsk.RegSeqConfig2.bits.FromReceive); break; |
dudmuck | 1:1cd0afbed23c | 907 | } |
dudmuck | 1:1cd0afbed23c | 908 | printf("\r\nsequencer: FromRxTimeout:"); |
dudmuck | 1:1cd0afbed23c | 909 | switch (fsk.RegSeqConfig2.bits.FromRxTimeout) { |
dudmuck | 1:1cd0afbed23c | 910 | case 0: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 911 | case 1: printf("tx"); break; |
dudmuck | 1:1cd0afbed23c | 912 | case 2: |
dudmuck | 1:1cd0afbed23c | 913 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 914 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 915 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 916 | else |
dudmuck | 1:1cd0afbed23c | 917 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 918 | break; |
dudmuck | 1:1cd0afbed23c | 919 | case 3: printf("SequencerOff"); break; |
dudmuck | 1:1cd0afbed23c | 920 | } |
dudmuck | 1:1cd0afbed23c | 921 | printf("\r\nsequencer: FromPacketReceived to:"); |
dudmuck | 1:1cd0afbed23c | 922 | switch (fsk.RegSeqConfig2.bits.FromPacketReceived) { |
dudmuck | 1:1cd0afbed23c | 923 | case 0: printf("SequencerOff"); break; |
dudmuck | 1:1cd0afbed23c | 924 | case 1: printf("tx on FifoEmpty"); break; |
dudmuck | 1:1cd0afbed23c | 925 | case 2: |
dudmuck | 1:1cd0afbed23c | 926 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 927 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 928 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 929 | else |
dudmuck | 1:1cd0afbed23c | 930 | printf("sequencerOff"); |
dudmuck | 1:1cd0afbed23c | 931 | break; |
dudmuck | 1:1cd0afbed23c | 932 | case 3: printf("rx via fs"); break; |
dudmuck | 1:1cd0afbed23c | 933 | case 4: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 934 | } |
dudmuck | 1:1cd0afbed23c | 935 | |
dudmuck | 1:1cd0afbed23c | 936 | fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); |
dudmuck | 1:1cd0afbed23c | 937 | printf("\r\nsequencer: timer1:"); |
dudmuck | 1:1cd0afbed23c | 938 | switch (fsk.RegTimerResol.bits.timer1_resol) { |
dudmuck | 1:1cd0afbed23c | 939 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 940 | case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER1COEF) * 64); break; |
dudmuck | 1:1cd0afbed23c | 941 | case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER1COEF) * 4.1); break; |
dudmuck | 1:1cd0afbed23c | 942 | case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER1COEF) * 0.262); break; |
dudmuck | 1:1cd0afbed23c | 943 | } |
dudmuck | 1:1cd0afbed23c | 944 | |
dudmuck | 1:1cd0afbed23c | 945 | printf(" timer2:"); |
dudmuck | 1:1cd0afbed23c | 946 | switch (fsk.RegTimerResol.bits.timer2_resol) { |
dudmuck | 1:1cd0afbed23c | 947 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 948 | case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER2COEF) * 64); break; |
dudmuck | 1:1cd0afbed23c | 949 | case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER2COEF) * 4.1); break; |
dudmuck | 1:1cd0afbed23c | 950 | case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER2COEF) * 0.262); break; |
dudmuck | 1:1cd0afbed23c | 951 | } |
dudmuck | 1:1cd0afbed23c | 952 | } // ..if sequencer enabled |
dudmuck | 1:1cd0afbed23c | 953 | |
dudmuck | 1:1cd0afbed23c | 954 | printf("\r\nIrqFlags1:"); |
dudmuck | 2:c6b23a43a9d9 | 955 | RegIrqFlags1.octet = radio.read_reg(REG_FSK_IRQFLAGS1); |
dudmuck | 2:c6b23a43a9d9 | 956 | if (RegIrqFlags1.bits.ModeReady) |
dudmuck | 1:1cd0afbed23c | 957 | printf("ModeReady "); |
dudmuck | 2:c6b23a43a9d9 | 958 | if (RegIrqFlags1.bits.RxReady) |
dudmuck | 1:1cd0afbed23c | 959 | printf("RxReady "); |
dudmuck | 2:c6b23a43a9d9 | 960 | if (RegIrqFlags1.bits.TxReady) |
dudmuck | 1:1cd0afbed23c | 961 | printf("TxReady "); |
dudmuck | 2:c6b23a43a9d9 | 962 | if (RegIrqFlags1.bits.PllLock) |
dudmuck | 1:1cd0afbed23c | 963 | printf("PllLock "); |
dudmuck | 2:c6b23a43a9d9 | 964 | if (RegIrqFlags1.bits.Rssi) |
dudmuck | 1:1cd0afbed23c | 965 | printf("Rssi "); |
dudmuck | 2:c6b23a43a9d9 | 966 | if (RegIrqFlags1.bits.Timeout) |
dudmuck | 1:1cd0afbed23c | 967 | printf("Timeout "); |
dudmuck | 2:c6b23a43a9d9 | 968 | if (RegIrqFlags1.bits.PreambleDetect) |
dudmuck | 1:1cd0afbed23c | 969 | printf("PreambleDetect "); |
dudmuck | 2:c6b23a43a9d9 | 970 | if (RegIrqFlags1.bits.SyncAddressMatch) |
dudmuck | 1:1cd0afbed23c | 971 | printf("SyncAddressMatch "); |
dudmuck | 1:1cd0afbed23c | 972 | |
dudmuck | 1:1cd0afbed23c | 973 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 974 | |
dudmuck | 1:1cd0afbed23c | 975 | /* TODO if (!SX1272FSK->RegPktConfig1.bits.PacketFormatVariable) { // if fixed-length packet format: |
dudmuck | 1:1cd0afbed23c | 976 | s = fsk_get_PayloadLength(); |
dudmuck | 1:1cd0afbed23c | 977 | if (s > FSK_LARGE_PKT_THRESHOLD) |
dudmuck | 1:1cd0afbed23c | 978 | flags.fifo_flow_ctl = 1; |
dudmuck | 1:1cd0afbed23c | 979 | else |
dudmuck | 1:1cd0afbed23c | 980 | flags.fifo_flow_ctl = 0; |
dudmuck | 1:1cd0afbed23c | 981 | }*/ |
dudmuck | 1:1cd0afbed23c | 982 | |
dudmuck | 1:1cd0afbed23c | 983 | fsk.RegImageCal.octet = radio.read_reg(REG_FSK_IMAGECAL); |
dudmuck | 1:1cd0afbed23c | 984 | if (fsk.RegImageCal.bits.TempMonitorOff) { |
dudmuck | 1:1cd0afbed23c | 985 | printf("[42mTempMonitorOff[\r0m\n"); |
dudmuck | 1:1cd0afbed23c | 986 | } else { |
dudmuck | 1:1cd0afbed23c | 987 | printf("TempThreshold:"); |
dudmuck | 1:1cd0afbed23c | 988 | switch (fsk.RegImageCal.bits.TempThreshold) { |
dudmuck | 1:1cd0afbed23c | 989 | case 0: printf("5C"); break; |
dudmuck | 1:1cd0afbed23c | 990 | case 1: printf("10C"); break; |
dudmuck | 1:1cd0afbed23c | 991 | case 2: printf("15C"); break; |
dudmuck | 1:1cd0afbed23c | 992 | case 3: printf("20C"); break; |
dudmuck | 1:1cd0afbed23c | 993 | } |
dudmuck | 1:1cd0afbed23c | 994 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 995 | } |
dudmuck | 1:1cd0afbed23c | 996 | if (fsk.RegImageCal.bits.ImageCalRunning) |
dudmuck | 1:1cd0afbed23c | 997 | printf("[33mImageCalRunning[\r0m\n"); |
dudmuck | 21:b84a77dfb43c | 998 | |
dudmuck | 21:b84a77dfb43c | 999 | if (rx_payloadReady_int_en) { |
Wayne Roberts |
24:9ba45aa15b53 | 1000 | #ifdef TARGET_DISCO_L072CZ_LRWAN1 |
dudmuck | 22:2005df80c8a8 | 1001 | printf("n_rx_pkts:%u, dio:%u,%u,%u,%u\r\n", n_rx_pkts, dio3.read(), dio2.read(), radio.dio1.read(), radio.dio0.read()); |
dudmuck | 22:2005df80c8a8 | 1002 | #else |
dudmuck | 21:b84a77dfb43c | 1003 | printf("n_rx_pkts:%u, dio:%u,%u,%u,%u,%u\r\n", n_rx_pkts, dio4.read(), dio3.read(), dio2.read(), radio.dio1.read(), radio.dio0.read()); |
dudmuck | 22:2005df80c8a8 | 1004 | #endif |
dudmuck | 21:b84a77dfb43c | 1005 | } |
dudmuck | 1:1cd0afbed23c | 1006 | } |
dudmuck | 1:1cd0afbed23c | 1007 | |
dudmuck | 0:be215de91a68 | 1008 | void printOpMode() |
dudmuck | 0:be215de91a68 | 1009 | { |
dudmuck | 0:be215de91a68 | 1010 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 0:be215de91a68 | 1011 | switch (radio.RegOpMode.bits.Mode) { |
dudmuck | 0:be215de91a68 | 1012 | case RF_OPMODE_SLEEP: printf("[7msleep[0m"); break; |
dudmuck | 0:be215de91a68 | 1013 | case RF_OPMODE_STANDBY: printf("[7mstby[0m"); break; |
dudmuck | 0:be215de91a68 | 1014 | case RF_OPMODE_SYNTHESIZER_TX: printf("[33mfstx[0m"); break; |
dudmuck | 0:be215de91a68 | 1015 | case RF_OPMODE_TRANSMITTER: printf("[31mtx[0m"); break; |
dudmuck | 0:be215de91a68 | 1016 | case RF_OPMODE_SYNTHESIZER_RX: printf("[33mfsrx[0m"); break; |
dudmuck | 0:be215de91a68 | 1017 | case RF_OPMODE_RECEIVER: printf("[32mrx[0m"); break; |
dudmuck | 0:be215de91a68 | 1018 | case 6: |
dudmuck | 0:be215de91a68 | 1019 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 0:be215de91a68 | 1020 | printf("[42mrxs[0m"); |
dudmuck | 0:be215de91a68 | 1021 | else |
dudmuck | 0:be215de91a68 | 1022 | printf("-6-"); |
dudmuck | 0:be215de91a68 | 1023 | break; // todo: different lora/fsk |
dudmuck | 0:be215de91a68 | 1024 | case 7: |
dudmuck | 0:be215de91a68 | 1025 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 0:be215de91a68 | 1026 | printf("[45mcad[0m"); |
dudmuck | 0:be215de91a68 | 1027 | else |
dudmuck | 0:be215de91a68 | 1028 | printf("-7-"); |
dudmuck | 0:be215de91a68 | 1029 | break; // todo: different lora/fsk |
dudmuck | 0:be215de91a68 | 1030 | } |
dudmuck | 0:be215de91a68 | 1031 | } |
dudmuck | 0:be215de91a68 | 1032 | |
dudmuck | 0:be215de91a68 | 1033 | void |
dudmuck | 0:be215de91a68 | 1034 | printPa() |
dudmuck | 0:be215de91a68 | 1035 | { |
dudmuck | 0:be215de91a68 | 1036 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 0:be215de91a68 | 1037 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 0:be215de91a68 | 1038 | float output_dBm = 17 - (15-radio.RegPaConfig.bits.OutputPower); |
dudmuck | 0:be215de91a68 | 1039 | printf(" PABOOST OutputPower=%.1fdBm", output_dBm); |
dudmuck | 0:be215de91a68 | 1040 | } else { |
dudmuck | 0:be215de91a68 | 1041 | float pmax = (0.6*radio.RegPaConfig.bits.MaxPower) + 10.8; |
dudmuck | 0:be215de91a68 | 1042 | float output_dBm = pmax - (15-radio.RegPaConfig.bits.OutputPower); |
dudmuck | 20:b11592c9ba5f | 1043 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 20:b11592c9ba5f | 1044 | printf(" \x1b[31mRFO pmax=%.1fdBm OutputPower=%.1fdBm\x1b[0m", pmax, output_dBm); // not connected |
dudmuck | 20:b11592c9ba5f | 1045 | #else |
dudmuck | 0:be215de91a68 | 1046 | printf(" RFO pmax=%.1fdBm OutputPower=%.1fdBm", pmax, output_dBm); |
dudmuck | 20:b11592c9ba5f | 1047 | #endif |
dudmuck | 0:be215de91a68 | 1048 | } |
dudmuck | 0:be215de91a68 | 1049 | } |
dudmuck | 0:be215de91a68 | 1050 | |
dudmuck | 0:be215de91a68 | 1051 | void /* things always present, whether lora or fsk */ |
dudmuck | 0:be215de91a68 | 1052 | common_print_status() |
dudmuck | 0:be215de91a68 | 1053 | { |
dudmuck | 0:be215de91a68 | 1054 | printf("version:0x%02x %.3fMHz ", radio.read_reg(REG_VERSION), radio.get_frf_MHz()); |
dudmuck | 0:be215de91a68 | 1055 | printOpMode(); |
dudmuck | 0:be215de91a68 | 1056 | |
dudmuck | 0:be215de91a68 | 1057 | printPa(); |
dudmuck | 0:be215de91a68 | 1058 | |
dudmuck | 0:be215de91a68 | 1059 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 0:be215de91a68 | 1060 | if (radio.RegOcp.bits.OcpOn) { |
dudmuck | 0:be215de91a68 | 1061 | int imax = 0; |
dudmuck | 0:be215de91a68 | 1062 | if (radio.RegOcp.bits.OcpTrim < 16) |
dudmuck | 0:be215de91a68 | 1063 | imax = 45 + (5 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 0:be215de91a68 | 1064 | else if (radio.RegOcp.bits.OcpTrim < 28) |
dudmuck | 0:be215de91a68 | 1065 | imax = -30 + (10 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 0:be215de91a68 | 1066 | else |
dudmuck | 0:be215de91a68 | 1067 | imax = 240; |
dudmuck | 0:be215de91a68 | 1068 | printf(" OcpOn %dmA ", imax); |
dudmuck | 0:be215de91a68 | 1069 | } else |
dudmuck | 0:be215de91a68 | 1070 | printf(" OcpOFF "); |
dudmuck | 0:be215de91a68 | 1071 | |
dudmuck | 0:be215de91a68 | 1072 | printf("\r\n"); |
dudmuck | 8:227605e4a760 | 1073 | |
dudmuck | 8:227605e4a760 | 1074 | if (per_en) { |
dudmuck | 18:9530d682fd9a | 1075 | if (cadper_enable) { |
dudmuck | 19:be8a8b0e7320 | 1076 | printf("cadper %" PRIu32 ", ", num_cads); |
dudmuck | 18:9530d682fd9a | 1077 | } |
dudmuck | 8:227605e4a760 | 1078 | printf("per_tx_delay:%f\r\n", per_tx_delay); |
dudmuck | 8:227605e4a760 | 1079 | printf("PER device ID:%d\r\n", per_id); |
dudmuck | 8:227605e4a760 | 1080 | } |
dudmuck | 18:9530d682fd9a | 1081 | |
dudmuck | 20:b11592c9ba5f | 1082 | if (poll_irq_en) { |
dudmuck | 18:9530d682fd9a | 1083 | printf("poll_irq_en\r\n"); |
dudmuck | 20:b11592c9ba5f | 1084 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 20:b11592c9ba5f | 1085 | printf("saved irqs: %02x %02x\r\n", fsk_RegIrqFlags1_prev.octet, fsk_RegIrqFlags2_prev.octet); |
dudmuck | 20:b11592c9ba5f | 1086 | } |
dudmuck | 20:b11592c9ba5f | 1087 | } |
dudmuck | 0:be215de91a68 | 1088 | |
dudmuck | 0:be215de91a68 | 1089 | } |
dudmuck | 0:be215de91a68 | 1090 | |
dudmuck | 0:be215de91a68 | 1091 | void print_rx_buf(int len) |
dudmuck | 0:be215de91a68 | 1092 | { |
dudmuck | 0:be215de91a68 | 1093 | int i; |
dudmuck | 0:be215de91a68 | 1094 | |
dudmuck | 0:be215de91a68 | 1095 | printf("000:"); |
dudmuck | 0:be215de91a68 | 1096 | for (i = 0; i < len; i++) { |
dudmuck | 0:be215de91a68 | 1097 | //printf("(%d)%02x ", i % 16, rx_buf[i]); |
dudmuck | 0:be215de91a68 | 1098 | printf("%02x ", radio.rx_buf[i]); |
dudmuck | 0:be215de91a68 | 1099 | if (i % 16 == 15 && i != len-1) |
dudmuck | 0:be215de91a68 | 1100 | printf("\r\n%03d:", i+1); |
dudmuck | 0:be215de91a68 | 1101 | |
dudmuck | 0:be215de91a68 | 1102 | } |
dudmuck | 0:be215de91a68 | 1103 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 1104 | } |
dudmuck | 0:be215de91a68 | 1105 | |
dudmuck | 21:b84a77dfb43c | 1106 | void lora_print_rx_verbose(uint8_t dlen) |
dudmuck | 7:c3c54f222ced | 1107 | { |
dudmuck | 7:c3c54f222ced | 1108 | float dbm; |
dudmuck | 7:c3c54f222ced | 1109 | printLoraIrqs_(false); |
dudmuck | 7:c3c54f222ced | 1110 | if (lora.RegHopPeriod > 0) { |
dudmuck | 7:c3c54f222ced | 1111 | lora.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); |
dudmuck | 7:c3c54f222ced | 1112 | printf("HopCH:%d ", lora.RegHopChannel.bits.FhssPresentChannel); |
dudmuck | 7:c3c54f222ced | 1113 | } |
dudmuck | 7:c3c54f222ced | 1114 | printf("%dHz ", lora.get_freq_error_Hz()); |
dudmuck | 7:c3c54f222ced | 1115 | lora_printCodingRate(true); // true: of received packet |
dudmuck | 7:c3c54f222ced | 1116 | dbm = lora.get_pkt_rssi(); |
dudmuck | 7:c3c54f222ced | 1117 | printf(" crc%s %.1fdB %.1fdBm\r\n", |
dudmuck | 7:c3c54f222ced | 1118 | lora.RegHopChannel.bits.RxPayloadCrcOn ? "On" : "OFF", |
dudmuck | 7:c3c54f222ced | 1119 | lora.RegPktSnrValue / 4.0, |
dudmuck | 7:c3c54f222ced | 1120 | dbm |
dudmuck | 7:c3c54f222ced | 1121 | ); |
dudmuck | 7:c3c54f222ced | 1122 | print_rx_buf(dlen); |
dudmuck | 18:9530d682fd9a | 1123 | } |
dudmuck | 7:c3c54f222ced | 1124 | |
dudmuck | 18:9530d682fd9a | 1125 | void set_per_en(bool en) |
dudmuck | 18:9530d682fd9a | 1126 | { |
dudmuck | 18:9530d682fd9a | 1127 | if (en) { |
dudmuck | 18:9530d682fd9a | 1128 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 1129 | if (radio.type == SX1272) { |
dudmuck | 18:9530d682fd9a | 1130 | lora.RegModemConfig.sx1272bits.LowDataRateOptimize = 1; |
dudmuck | 18:9530d682fd9a | 1131 | radio.write_reg(REG_LR_MODEMCONFIG, lora.RegModemConfig.octet); |
dudmuck | 18:9530d682fd9a | 1132 | } else if (radio.type == SX1276) { |
dudmuck | 18:9530d682fd9a | 1133 | lora.RegModemConfig3.sx1276bits.LowDataRateOptimize = 1; |
dudmuck | 18:9530d682fd9a | 1134 | radio.write_reg(REG_LR_MODEMCONFIG3, lora.RegModemConfig3.octet); |
dudmuck | 18:9530d682fd9a | 1135 | } |
dudmuck | 18:9530d682fd9a | 1136 | lora.RegPayloadLength = 9; |
dudmuck | 18:9530d682fd9a | 1137 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1138 | radio.RegDioMapping1.bits.Dio3Mapping = 1; // to ValidHeader |
dudmuck | 18:9530d682fd9a | 1139 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 1140 | } else { // fsk.. |
dudmuck | 18:9530d682fd9a | 1141 | //fsk_tx_length = 9; |
dudmuck | 7:c3c54f222ced | 1142 | } |
dudmuck | 20:b11592c9ba5f | 1143 | PacketRxSequencePrev = 0; // transmitter side PacketTxCnt is 1 at first TX |
dudmuck | 18:9530d682fd9a | 1144 | //PacketRxSequence = 0; |
dudmuck | 18:9530d682fd9a | 1145 | PacketPerKoCnt = 0; |
dudmuck | 18:9530d682fd9a | 1146 | PacketPerOkCnt = 0; |
dudmuck | 18:9530d682fd9a | 1147 | PacketNormalCnt = 0; |
dudmuck | 18:9530d682fd9a | 1148 | } // ..if (per_en) |
dudmuck | 18:9530d682fd9a | 1149 | else { |
dudmuck | 18:9530d682fd9a | 1150 | per_timeout.detach(); |
dudmuck | 18:9530d682fd9a | 1151 | } |
dudmuck | 18:9530d682fd9a | 1152 | |
dudmuck | 18:9530d682fd9a | 1153 | per_en = en; |
dudmuck | 18:9530d682fd9a | 1154 | } |
dudmuck | 7:c3c54f222ced | 1155 | |
dudmuck | 8:227605e4a760 | 1156 | void per_cb() |
dudmuck | 8:227605e4a760 | 1157 | { |
dudmuck | 8:227605e4a760 | 1158 | int i; |
dudmuck | 8:227605e4a760 | 1159 | |
dudmuck | 8:227605e4a760 | 1160 | PacketTxCnt++; |
dudmuck | 8:227605e4a760 | 1161 | |
dudmuck | 8:227605e4a760 | 1162 | radio.tx_buf[0] = per_id; |
dudmuck | 8:227605e4a760 | 1163 | radio.tx_buf[1] = PacketTxCnt >> 24; |
dudmuck | 8:227605e4a760 | 1164 | radio.tx_buf[2] = PacketTxCnt >> 16; |
dudmuck | 8:227605e4a760 | 1165 | radio.tx_buf[3] = PacketTxCnt >> 8; |
dudmuck | 8:227605e4a760 | 1166 | radio.tx_buf[4] = PacketTxCnt; |
dudmuck | 8:227605e4a760 | 1167 | radio.tx_buf[5] = 'P'; |
dudmuck | 8:227605e4a760 | 1168 | radio.tx_buf[6] = 'E'; |
dudmuck | 8:227605e4a760 | 1169 | radio.tx_buf[7] = 'R'; |
dudmuck | 8:227605e4a760 | 1170 | radio.tx_buf[8] = 0; |
dudmuck | 8:227605e4a760 | 1171 | for (i = 0; i < 8; i++) |
dudmuck | 8:227605e4a760 | 1172 | radio.tx_buf[8] += radio.tx_buf[i]; |
dudmuck | 8:227605e4a760 | 1173 | |
dudmuck | 13:c73caaee93a5 | 1174 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 13:c73caaee93a5 | 1175 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 13:c73caaee93a5 | 1176 | } else { |
dudmuck | 13:c73caaee93a5 | 1177 | fsk.start_tx(9); |
dudmuck | 13:c73caaee93a5 | 1178 | } |
dudmuck | 10:d9bb2ce57f05 | 1179 | |
dudmuck | 10:d9bb2ce57f05 | 1180 | led1 = !led1.read(); |
dudmuck | 18:9530d682fd9a | 1181 | |
dudmuck | 18:9530d682fd9a | 1182 | if (PacketTxCnt == PacketTxCntEnd) { |
dudmuck | 18:9530d682fd9a | 1183 | set_per_en(false); |
dudmuck | 18:9530d682fd9a | 1184 | return; |
dudmuck | 18:9530d682fd9a | 1185 | } |
dudmuck | 8:227605e4a760 | 1186 | } |
dudmuck | 8:227605e4a760 | 1187 | |
dudmuck | 13:c73caaee93a5 | 1188 | int per_parse_rx(uint8_t len) |
dudmuck | 13:c73caaee93a5 | 1189 | { |
dudmuck | 13:c73caaee93a5 | 1190 | if (len > 8 && radio.rx_buf[5] == 'P' && radio.rx_buf[6] == 'E' && radio.rx_buf[7] == 'R') { |
dudmuck | 13:c73caaee93a5 | 1191 | int i; |
dudmuck | 13:c73caaee93a5 | 1192 | float per; |
dudmuck | 13:c73caaee93a5 | 1193 | |
dudmuck | 13:c73caaee93a5 | 1194 | /* this is PER packet */ |
dudmuck | 19:be8a8b0e7320 | 1195 | int PacketRxSequence = (radio.rx_buf[1] << 24) | (radio.rx_buf[2] << 16) | (radio.rx_buf[3] << 8) | radio.rx_buf[4]; |
dudmuck | 13:c73caaee93a5 | 1196 | PacketPerOkCnt++; |
dudmuck | 13:c73caaee93a5 | 1197 | |
dudmuck | 13:c73caaee93a5 | 1198 | if( PacketRxSequence <= PacketRxSequencePrev ) |
dudmuck | 13:c73caaee93a5 | 1199 | { // Sequence went back => resynchronization |
dudmuck | 13:c73caaee93a5 | 1200 | // dont count missed packets this time |
dudmuck | 13:c73caaee93a5 | 1201 | i = 0; |
dudmuck | 13:c73caaee93a5 | 1202 | } |
dudmuck | 13:c73caaee93a5 | 1203 | else |
dudmuck | 13:c73caaee93a5 | 1204 | { |
dudmuck | 13:c73caaee93a5 | 1205 | // determine number of missed packets |
dudmuck | 13:c73caaee93a5 | 1206 | i = PacketRxSequence - PacketRxSequencePrev - 1; |
dudmuck | 13:c73caaee93a5 | 1207 | } |
dudmuck | 13:c73caaee93a5 | 1208 | |
dudmuck | 13:c73caaee93a5 | 1209 | led1 = !led1.read(); |
dudmuck | 13:c73caaee93a5 | 1210 | // be ready for the next |
dudmuck | 13:c73caaee93a5 | 1211 | PacketRxSequencePrev = PacketRxSequence; |
dudmuck | 13:c73caaee93a5 | 1212 | // increment 'missed' counter for the RX session |
dudmuck | 13:c73caaee93a5 | 1213 | PacketPerKoCnt += i; |
dudmuck | 18:9530d682fd9a | 1214 | per = ( (float)1.0 - ( float )PacketPerOkCnt / ( float )( PacketPerOkCnt + PacketPerKoCnt ) ) * (float)100.0; |
dudmuck | 19:be8a8b0e7320 | 1215 | printf("%d, ok=%" PRIu32 " missed=%" PRIu32 " normal=%" PRIu32 " per:%.3f ", PacketRxSequence, PacketPerOkCnt, PacketPerKoCnt, PacketNormalCnt, per); |
dudmuck | 15:c69b942685ea | 1216 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 15:c69b942685ea | 1217 | printf("pkt:%ddBm, snr:%.1fdB, %ddBm\r\n", lora.get_pkt_rssi(), lora.RegPktSnrValue / 4.0, lora.get_current_rssi()); |
dudmuck | 15:c69b942685ea | 1218 | else { |
dudmuck | 16:b9d36c60f2d3 | 1219 | wait_us(10000); |
dudmuck | 15:c69b942685ea | 1220 | printf(" -%.1fdBm\r\n", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 15:c69b942685ea | 1221 | } |
dudmuck | 15:c69b942685ea | 1222 | |
dudmuck | 13:c73caaee93a5 | 1223 | return 1; |
dudmuck | 13:c73caaee93a5 | 1224 | } else { |
dudmuck | 13:c73caaee93a5 | 1225 | return 0; |
dudmuck | 13:c73caaee93a5 | 1226 | } |
dudmuck | 13:c73caaee93a5 | 1227 | } |
dudmuck | 13:c73caaee93a5 | 1228 | |
dudmuck | 18:9530d682fd9a | 1229 | typedef enum { |
dudmuck | 18:9530d682fd9a | 1230 | ON_TXDONE_STATE_NONE = 0, |
dudmuck | 18:9530d682fd9a | 1231 | ON_TXDONE_STATE_SYNC_HI_NIBBLE, |
dudmuck | 18:9530d682fd9a | 1232 | ON_TXDONE_STATE_SYNC_LO_NIBBLE, |
dudmuck | 18:9530d682fd9a | 1233 | ON_TXDONE_STATE_PAYLOAD_LENGTH, |
dudmuck | 18:9530d682fd9a | 1234 | } on_txdone_state_e; |
dudmuck | 18:9530d682fd9a | 1235 | |
dudmuck | 18:9530d682fd9a | 1236 | on_txdone_state_e on_txdone_state; |
dudmuck | 18:9530d682fd9a | 1237 | |
dudmuck | 18:9530d682fd9a | 1238 | uint8_t lora_sync_byte; |
dudmuck | 18:9530d682fd9a | 1239 | float on_txdone_delay; |
dudmuck | 18:9530d682fd9a | 1240 | Timeout on_txdone_timeout; |
dudmuck | 18:9530d682fd9a | 1241 | uint8_t on_txdone_repeat_cnt; |
dudmuck | 18:9530d682fd9a | 1242 | |
dudmuck | 18:9530d682fd9a | 1243 | void txdone_timeout_cb() |
dudmuck | 18:9530d682fd9a | 1244 | { |
dudmuck | 18:9530d682fd9a | 1245 | uint8_t nib; |
dudmuck | 18:9530d682fd9a | 1246 | |
dudmuck | 18:9530d682fd9a | 1247 | switch (on_txdone_state) { |
dudmuck | 18:9530d682fd9a | 1248 | case ON_TXDONE_STATE_SYNC_HI_NIBBLE: |
dudmuck | 18:9530d682fd9a | 1249 | nib = lora_sync_byte >> 4; |
dudmuck | 18:9530d682fd9a | 1250 | if (nib >= 15) { |
dudmuck | 18:9530d682fd9a | 1251 | on_txdone_state = ON_TXDONE_STATE_SYNC_LO_NIBBLE; |
dudmuck | 18:9530d682fd9a | 1252 | lora_sync_byte = 0x00; |
dudmuck | 18:9530d682fd9a | 1253 | } else |
dudmuck | 18:9530d682fd9a | 1254 | nib++; |
dudmuck | 18:9530d682fd9a | 1255 | |
dudmuck | 18:9530d682fd9a | 1256 | lora_sync_byte = nib << 4; |
dudmuck | 18:9530d682fd9a | 1257 | |
dudmuck | 18:9530d682fd9a | 1258 | radio.write_reg(REG_LR_SYNC_BYTE, lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1259 | printf("upper %02x\r\n", lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1260 | break; |
dudmuck | 18:9530d682fd9a | 1261 | case ON_TXDONE_STATE_SYNC_LO_NIBBLE: |
dudmuck | 18:9530d682fd9a | 1262 | nib = lora_sync_byte & 0x0f; |
dudmuck | 18:9530d682fd9a | 1263 | if (nib >= 15) { |
dudmuck | 18:9530d682fd9a | 1264 | on_txdone_state = ON_TXDONE_STATE_SYNC_LO_NIBBLE; |
dudmuck | 18:9530d682fd9a | 1265 | lora_sync_byte = 0x00; |
dudmuck | 18:9530d682fd9a | 1266 | } else |
dudmuck | 18:9530d682fd9a | 1267 | nib++; |
dudmuck | 18:9530d682fd9a | 1268 | |
dudmuck | 18:9530d682fd9a | 1269 | lora_sync_byte = nib & 0x0f; |
dudmuck | 18:9530d682fd9a | 1270 | |
dudmuck | 18:9530d682fd9a | 1271 | radio.write_reg(REG_LR_SYNC_BYTE, lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1272 | printf("lower %02x\r\n", lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1273 | break; |
dudmuck | 18:9530d682fd9a | 1274 | case ON_TXDONE_STATE_PAYLOAD_LENGTH: |
dudmuck | 18:9530d682fd9a | 1275 | if (++on_txdone_repeat_cnt >= 10) { |
dudmuck | 18:9530d682fd9a | 1276 | on_txdone_repeat_cnt = 0; |
dudmuck | 18:9530d682fd9a | 1277 | if (lora.RegPayloadLength == 255) { |
dudmuck | 18:9530d682fd9a | 1278 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 1279 | printf("done\r\n"); |
dudmuck | 18:9530d682fd9a | 1280 | on_txdone_state = ON_TXDONE_STATE_NONE; |
dudmuck | 18:9530d682fd9a | 1281 | return; |
dudmuck | 18:9530d682fd9a | 1282 | } |
dudmuck | 18:9530d682fd9a | 1283 | lora.RegPayloadLength++; |
dudmuck | 18:9530d682fd9a | 1284 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1285 | printf("pl %d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1286 | } |
dudmuck | 18:9530d682fd9a | 1287 | tx_cnt++; |
dudmuck | 18:9530d682fd9a | 1288 | radio.tx_buf[0] = tx_cnt; |
dudmuck | 18:9530d682fd9a | 1289 | radio.tx_buf[1] = ~tx_cnt; |
dudmuck | 18:9530d682fd9a | 1290 | break; |
dudmuck | 18:9530d682fd9a | 1291 | default: |
dudmuck | 18:9530d682fd9a | 1292 | return; |
dudmuck | 18:9530d682fd9a | 1293 | } // ..switch (on_txdone_state) |
dudmuck | 18:9530d682fd9a | 1294 | |
dudmuck | 18:9530d682fd9a | 1295 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1296 | } |
dudmuck | 18:9530d682fd9a | 1297 | |
dudmuck | 20:b11592c9ba5f | 1298 | |
dudmuck | 18:9530d682fd9a | 1299 | void |
dudmuck | 18:9530d682fd9a | 1300 | poll_service_radio() |
dudmuck | 18:9530d682fd9a | 1301 | { |
dudmuck | 18:9530d682fd9a | 1302 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 1303 | } else { // fsk: |
dudmuck | 21:b84a77dfb43c | 1304 | if (rx_payloadReady_int_en) |
dudmuck | 21:b84a77dfb43c | 1305 | return; |
dudmuck | 21:b84a77dfb43c | 1306 | |
dudmuck | 20:b11592c9ba5f | 1307 | /*RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 18:9530d682fd9a | 1308 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { |
dudmuck | 18:9530d682fd9a | 1309 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 1310 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 18:9530d682fd9a | 1311 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 18:9530d682fd9a | 1312 | printf("poll mode fsk tx done\r\n"); |
dudmuck | 18:9530d682fd9a | 1313 | } |
dudmuck | 20:b11592c9ba5f | 1314 | }*/ |
dudmuck | 20:b11592c9ba5f | 1315 | static uint8_t rssi; |
dudmuck | 20:b11592c9ba5f | 1316 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 20:b11592c9ba5f | 1317 | RegIrqFlags1_t RegIrqFlags1; |
dudmuck | 20:b11592c9ba5f | 1318 | RegIrqFlags1.octet = radio.read_reg(REG_FSK_IRQFLAGS1); |
dudmuck | 20:b11592c9ba5f | 1319 | if (RegIrqFlags1.octet != fsk_RegIrqFlags1_prev.octet) { |
dudmuck | 20:b11592c9ba5f | 1320 | printf("iF1:"); |
dudmuck | 20:b11592c9ba5f | 1321 | if (RegIrqFlags1.bits.ModeReady ^ fsk_RegIrqFlags1_prev.bits.ModeReady) { |
dudmuck | 20:b11592c9ba5f | 1322 | printf("ModeReady-"); |
dudmuck | 20:b11592c9ba5f | 1323 | if (RegIrqFlags1.bits.ModeReady) |
dudmuck | 20:b11592c9ba5f | 1324 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1325 | else |
dudmuck | 20:b11592c9ba5f | 1326 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1327 | } |
dudmuck | 20:b11592c9ba5f | 1328 | if (RegIrqFlags1.bits.RxReady ^ fsk_RegIrqFlags1_prev.bits.RxReady) { |
dudmuck | 20:b11592c9ba5f | 1329 | printf("RxReady-"); |
dudmuck | 20:b11592c9ba5f | 1330 | if (RegIrqFlags1.bits.RxReady) |
dudmuck | 20:b11592c9ba5f | 1331 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1332 | else |
dudmuck | 20:b11592c9ba5f | 1333 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1334 | } |
dudmuck | 20:b11592c9ba5f | 1335 | if (RegIrqFlags1.bits.TxReady ^ fsk_RegIrqFlags1_prev.bits.TxReady) { |
dudmuck | 20:b11592c9ba5f | 1336 | printf("TxReady-"); |
dudmuck | 20:b11592c9ba5f | 1337 | if (RegIrqFlags1.bits.TxReady) |
dudmuck | 20:b11592c9ba5f | 1338 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1339 | else |
dudmuck | 20:b11592c9ba5f | 1340 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1341 | } |
dudmuck | 20:b11592c9ba5f | 1342 | if (RegIrqFlags1.bits.PllLock ^ fsk_RegIrqFlags1_prev.bits.PllLock) { |
dudmuck | 20:b11592c9ba5f | 1343 | printf("PllLock-"); |
dudmuck | 20:b11592c9ba5f | 1344 | if (RegIrqFlags1.bits.PllLock) |
dudmuck | 20:b11592c9ba5f | 1345 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1346 | else |
dudmuck | 20:b11592c9ba5f | 1347 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1348 | } |
dudmuck | 20:b11592c9ba5f | 1349 | if (RegIrqFlags1.bits.Rssi ^ fsk_RegIrqFlags1_prev.bits.Rssi) { |
dudmuck | 20:b11592c9ba5f | 1350 | printf("Rssi-"); |
dudmuck | 20:b11592c9ba5f | 1351 | if (RegIrqFlags1.bits.Rssi) |
dudmuck | 20:b11592c9ba5f | 1352 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1353 | else |
dudmuck | 20:b11592c9ba5f | 1354 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1355 | } |
dudmuck | 20:b11592c9ba5f | 1356 | if (RegIrqFlags1.bits.Timeout ^ fsk_RegIrqFlags1_prev.bits.Timeout) { |
dudmuck | 20:b11592c9ba5f | 1357 | printf("Timeout-"); |
dudmuck | 20:b11592c9ba5f | 1358 | if (RegIrqFlags1.bits.Timeout) |
dudmuck | 20:b11592c9ba5f | 1359 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1360 | else |
dudmuck | 20:b11592c9ba5f | 1361 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1362 | } |
dudmuck | 20:b11592c9ba5f | 1363 | if (RegIrqFlags1.bits.PreambleDetect ^ fsk_RegIrqFlags1_prev.bits.PreambleDetect) { |
dudmuck | 20:b11592c9ba5f | 1364 | printf("PreambleDetect-"); |
dudmuck | 20:b11592c9ba5f | 1365 | if (RegIrqFlags1.bits.PreambleDetect) |
dudmuck | 20:b11592c9ba5f | 1366 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1367 | else |
dudmuck | 20:b11592c9ba5f | 1368 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1369 | } |
dudmuck | 20:b11592c9ba5f | 1370 | if (RegIrqFlags1.bits.SyncAddressMatch ^ fsk_RegIrqFlags1_prev.bits.SyncAddressMatch) { |
dudmuck | 20:b11592c9ba5f | 1371 | printf("SyncAddressMatch-"); |
dudmuck | 20:b11592c9ba5f | 1372 | if (RegIrqFlags1.bits.SyncAddressMatch) |
dudmuck | 20:b11592c9ba5f | 1373 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1374 | else |
dudmuck | 20:b11592c9ba5f | 1375 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1376 | } |
dudmuck | 20:b11592c9ba5f | 1377 | fsk_RegIrqFlags1_prev.octet = RegIrqFlags1.octet; |
dudmuck | 20:b11592c9ba5f | 1378 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1379 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1380 | } |
dudmuck | 20:b11592c9ba5f | 1381 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 20:b11592c9ba5f | 1382 | if (RegIrqFlags2.octet != fsk_RegIrqFlags2_prev.octet) { |
dudmuck | 20:b11592c9ba5f | 1383 | printf("iF2:"); |
dudmuck | 20:b11592c9ba5f | 1384 | if (RegIrqFlags2.bits.FifoFull ^ fsk_RegIrqFlags2_prev.bits.FifoFull) { |
dudmuck | 20:b11592c9ba5f | 1385 | printf("FifoFull-"); |
dudmuck | 20:b11592c9ba5f | 1386 | if (RegIrqFlags2.bits.FifoFull) |
dudmuck | 20:b11592c9ba5f | 1387 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1388 | else |
dudmuck | 20:b11592c9ba5f | 1389 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1390 | } |
dudmuck | 20:b11592c9ba5f | 1391 | if (RegIrqFlags2.bits.FifoEmpty ^ fsk_RegIrqFlags2_prev.bits.FifoEmpty) { |
dudmuck | 20:b11592c9ba5f | 1392 | printf("FifoEmpty-"); |
dudmuck | 20:b11592c9ba5f | 1393 | if (RegIrqFlags2.bits.FifoEmpty) |
dudmuck | 20:b11592c9ba5f | 1394 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1395 | else { |
dudmuck | 20:b11592c9ba5f | 1396 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1397 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 20:b11592c9ba5f | 1398 | } |
dudmuck | 20:b11592c9ba5f | 1399 | } |
dudmuck | 20:b11592c9ba5f | 1400 | if (RegIrqFlags2.bits.FifoLevel ^ fsk_RegIrqFlags2_prev.bits.FifoLevel) { |
dudmuck | 20:b11592c9ba5f | 1401 | printf("FifoLevel-"); |
dudmuck | 20:b11592c9ba5f | 1402 | if (RegIrqFlags2.bits.FifoLevel) |
dudmuck | 20:b11592c9ba5f | 1403 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1404 | else |
dudmuck | 20:b11592c9ba5f | 1405 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1406 | } |
dudmuck | 20:b11592c9ba5f | 1407 | if (RegIrqFlags2.bits.FifoOverrun ^ fsk_RegIrqFlags2_prev.bits.FifoOverrun) { |
dudmuck | 20:b11592c9ba5f | 1408 | printf("FifoOverrun-"); |
dudmuck | 20:b11592c9ba5f | 1409 | if (RegIrqFlags2.bits.FifoOverrun) |
dudmuck | 20:b11592c9ba5f | 1410 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1411 | else |
dudmuck | 20:b11592c9ba5f | 1412 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1413 | } |
dudmuck | 20:b11592c9ba5f | 1414 | if (RegIrqFlags2.bits.PacketSent ^ fsk_RegIrqFlags2_prev.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1415 | printf("PacketSent-"); |
dudmuck | 20:b11592c9ba5f | 1416 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1417 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1418 | } else |
dudmuck | 20:b11592c9ba5f | 1419 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1420 | } |
dudmuck | 20:b11592c9ba5f | 1421 | if (RegIrqFlags2.bits.PayloadReady ^ fsk_RegIrqFlags2_prev.bits.PayloadReady) { |
dudmuck | 20:b11592c9ba5f | 1422 | printf("PayloadReady-"); |
dudmuck | 20:b11592c9ba5f | 1423 | if (RegIrqFlags2.bits.PayloadReady) |
dudmuck | 20:b11592c9ba5f | 1424 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1425 | else |
dudmuck | 20:b11592c9ba5f | 1426 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1427 | } |
dudmuck | 20:b11592c9ba5f | 1428 | if (RegIrqFlags2.bits.CrcOk ^ fsk_RegIrqFlags2_prev.bits.CrcOk) { |
dudmuck | 20:b11592c9ba5f | 1429 | printf("CrcOk-"); |
dudmuck | 20:b11592c9ba5f | 1430 | if (RegIrqFlags2.bits.CrcOk) |
dudmuck | 20:b11592c9ba5f | 1431 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1432 | else |
dudmuck | 20:b11592c9ba5f | 1433 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1434 | } |
dudmuck | 20:b11592c9ba5f | 1435 | if (RegIrqFlags2.bits.LowBat ^ fsk_RegIrqFlags2_prev.bits.LowBat) { |
dudmuck | 20:b11592c9ba5f | 1436 | printf("LowBat-"); |
dudmuck | 20:b11592c9ba5f | 1437 | if (RegIrqFlags2.bits.LowBat) |
dudmuck | 20:b11592c9ba5f | 1438 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1439 | else |
dudmuck | 20:b11592c9ba5f | 1440 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1441 | } |
dudmuck | 20:b11592c9ba5f | 1442 | fsk_RegIrqFlags2_prev.octet = RegIrqFlags2.octet; |
dudmuck | 20:b11592c9ba5f | 1443 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1444 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1445 | |
dudmuck | 20:b11592c9ba5f | 1446 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1447 | if (fsk.tx_done_sleep) |
dudmuck | 20:b11592c9ba5f | 1448 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 20:b11592c9ba5f | 1449 | else |
dudmuck | 20:b11592c9ba5f | 1450 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 20:b11592c9ba5f | 1451 | } |
dudmuck | 20:b11592c9ba5f | 1452 | |
dudmuck | 20:b11592c9ba5f | 1453 | if (RegIrqFlags2.bits.CrcOk || RegIrqFlags2.bits.PayloadReady) { |
dudmuck | 20:b11592c9ba5f | 1454 | if (fsk.RegRxConfig.bits.AfcAutoOn) { |
dudmuck | 20:b11592c9ba5f | 1455 | fsk.RegAfcValue = radio.read_s16(REG_FSK_AFCMSB); |
dudmuck | 20:b11592c9ba5f | 1456 | printf("%dHz ", (int)(FREQ_STEP_HZ * fsk.RegAfcValue)); |
dudmuck | 20:b11592c9ba5f | 1457 | if (rssi != 0) { |
dudmuck | 20:b11592c9ba5f | 1458 | printf("pkt:-%.1fdBm ", rssi / 2.0); |
dudmuck | 20:b11592c9ba5f | 1459 | rssi = 0; |
dudmuck | 20:b11592c9ba5f | 1460 | } |
dudmuck | 20:b11592c9ba5f | 1461 | } |
dudmuck | 20:b11592c9ba5f | 1462 | if (fsk.RegPktConfig1.bits.PacketFormatVariable) { |
dudmuck | 20:b11592c9ba5f | 1463 | fsk.rx_buf_length = radio.read_reg(REG_FIFO); |
dudmuck | 20:b11592c9ba5f | 1464 | } else { |
dudmuck | 20:b11592c9ba5f | 1465 | fsk.rx_buf_length = fsk.RegPktConfig2.bits.PayloadLength; |
dudmuck | 20:b11592c9ba5f | 1466 | } |
dudmuck | 20:b11592c9ba5f | 1467 | |
dudmuck | 20:b11592c9ba5f | 1468 | radio.m_cs = 0; |
dudmuck | 20:b11592c9ba5f | 1469 | radio.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 20:b11592c9ba5f | 1470 | for (int i = 0; i < fsk.rx_buf_length; i++) { |
dudmuck | 20:b11592c9ba5f | 1471 | radio.rx_buf[i] = radio.m_spi.write(0); |
dudmuck | 20:b11592c9ba5f | 1472 | } |
dudmuck | 20:b11592c9ba5f | 1473 | radio.m_cs = 1; |
dudmuck | 20:b11592c9ba5f | 1474 | /****/ |
dudmuck | 20:b11592c9ba5f | 1475 | if (per_en) { |
dudmuck | 20:b11592c9ba5f | 1476 | if (!per_parse_rx(fsk.rx_buf_length)) { |
dudmuck | 20:b11592c9ba5f | 1477 | PacketNormalCnt++; |
dudmuck | 20:b11592c9ba5f | 1478 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 20:b11592c9ba5f | 1479 | } |
dudmuck | 20:b11592c9ba5f | 1480 | } else { |
dudmuck | 20:b11592c9ba5f | 1481 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 20:b11592c9ba5f | 1482 | } |
dudmuck | 20:b11592c9ba5f | 1483 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1484 | } // ..if CrcOk or PayloadReady |
dudmuck | 20:b11592c9ba5f | 1485 | } // ..if RegIrqFlags2 changed |
dudmuck | 20:b11592c9ba5f | 1486 | } // ...fsk |
dudmuck | 18:9530d682fd9a | 1487 | } |
dudmuck | 18:9530d682fd9a | 1488 | |
dudmuck | 18:9530d682fd9a | 1489 | void cadper_service() |
dudmuck | 18:9530d682fd9a | 1490 | { |
dudmuck | 18:9530d682fd9a | 1491 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1492 | |
dudmuck | 18:9530d682fd9a | 1493 | |
dudmuck | 18:9530d682fd9a | 1494 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 1495 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 1496 | do { |
dudmuck | 18:9530d682fd9a | 1497 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1498 | if (lora.RegIrqFlags.bits.RxDone) { |
dudmuck | 18:9530d682fd9a | 1499 | service_action_e act = lora.service(); |
dudmuck | 18:9530d682fd9a | 1500 | if (act == SERVICE_READ_FIFO) { |
dudmuck | 18:9530d682fd9a | 1501 | if (!per_parse_rx(lora.RegRxNbBytes)) { |
dudmuck | 18:9530d682fd9a | 1502 | PacketNormalCnt++; |
dudmuck | 21:b84a77dfb43c | 1503 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 18:9530d682fd9a | 1504 | } |
dudmuck | 18:9530d682fd9a | 1505 | } |
dudmuck | 18:9530d682fd9a | 1506 | break; |
dudmuck | 18:9530d682fd9a | 1507 | } |
dudmuck | 18:9530d682fd9a | 1508 | } while (!lora.RegIrqFlags.bits.RxTimeout); |
dudmuck | 18:9530d682fd9a | 1509 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 1510 | } |
dudmuck | 18:9530d682fd9a | 1511 | |
dudmuck | 18:9530d682fd9a | 1512 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 1513 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1514 | num_cads++; |
dudmuck | 18:9530d682fd9a | 1515 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 1516 | } |
dudmuck | 18:9530d682fd9a | 1517 | |
dudmuck | 18:9530d682fd9a | 1518 | } |
dudmuck | 18:9530d682fd9a | 1519 | |
dudmuck | 20:b11592c9ba5f | 1520 | void cmd_restart_rx(uint8_t); |
dudmuck | 22:2005df80c8a8 | 1521 | int preamble_to_sync_us; |
Wayne Roberts |
24:9ba45aa15b53 | 1522 | #ifndef TARGET_DISCO_L072CZ_LRWAN1 |
dudmuck | 20:b11592c9ba5f | 1523 | Timeout timeout_syncAddress; |
dudmuck | 20:b11592c9ba5f | 1524 | bool get_syncAddress; |
dudmuck | 22:2005df80c8a8 | 1525 | #endif |
dudmuck | 20:b11592c9ba5f | 1526 | float preamble_detect_at; |
dudmuck | 20:b11592c9ba5f | 1527 | |
dudmuck | 20:b11592c9ba5f | 1528 | void callback_sa_timeout() |
dudmuck | 20:b11592c9ba5f | 1529 | { |
dudmuck | 20:b11592c9ba5f | 1530 | printf("syncAddress timeout "); |
dudmuck | 20:b11592c9ba5f | 1531 | if (dio2.read() == 0) { |
dudmuck | 20:b11592c9ba5f | 1532 | //cmd_restart_rx(0); |
dudmuck | 20:b11592c9ba5f | 1533 | rx_start_timer.reset(); |
dudmuck | 20:b11592c9ba5f | 1534 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 23:821b4f426ee6 | 1535 | printf("(false preamble detect at %f, secs:%lu)\r\n", preamble_detect_at, time(NULL) - secs_rx_start); |
dudmuck | 20:b11592c9ba5f | 1536 | secs_rx_start = time(NULL); |
dudmuck | 20:b11592c9ba5f | 1537 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 20:b11592c9ba5f | 1538 | } else |
dudmuck | 20:b11592c9ba5f | 1539 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1540 | } |
dudmuck | 20:b11592c9ba5f | 1541 | |
dudmuck | 0:be215de91a68 | 1542 | void |
dudmuck | 0:be215de91a68 | 1543 | service_radio() |
dudmuck | 0:be215de91a68 | 1544 | { |
dudmuck | 1:1cd0afbed23c | 1545 | service_action_e act; |
dudmuck | 14:c57ea544dc18 | 1546 | static uint8_t rssi = 0; |
dudmuck | 1:1cd0afbed23c | 1547 | |
dudmuck | 1:1cd0afbed23c | 1548 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 21:b84a77dfb43c | 1549 | if (rssi_polling_thresh != 0 && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 23:821b4f426ee6 | 1550 | rssi = lora.get_current_rssi(); // dBm returned, negative value |
Wayne Roberts |
24:9ba45aa15b53 | 1551 | #if defined(TARGET_STM) && !defined(TARGET_DISCO_L072CZ_LRWAN1) && !defined(TARGET_MTS_MDOT_F411RE) |
dudmuck | 21:b84a77dfb43c | 1552 | if (rssi < rssi_polling_thresh) |
dudmuck | 21:b84a77dfb43c | 1553 | pc3 = 0; // signal weaker than threshold |
dudmuck | 21:b84a77dfb43c | 1554 | else |
dudmuck | 21:b84a77dfb43c | 1555 | pc3 = 1; // signal stronger than threshold |
dudmuck | 21:b84a77dfb43c | 1556 | #endif |
dudmuck | 21:b84a77dfb43c | 1557 | } |
dudmuck | 21:b84a77dfb43c | 1558 | |
dudmuck | 18:9530d682fd9a | 1559 | if (cadper_enable) { |
dudmuck | 18:9530d682fd9a | 1560 | cadper_service(); |
dudmuck | 18:9530d682fd9a | 1561 | } |
dudmuck | 4:7a9007dfc0e5 | 1562 | |
dudmuck | 1:1cd0afbed23c | 1563 | act = lora.service(); |
dudmuck | 0:be215de91a68 | 1564 | |
dudmuck | 1:1cd0afbed23c | 1565 | switch (act) { |
dudmuck | 1:1cd0afbed23c | 1566 | case SERVICE_READ_FIFO: |
dudmuck | 8:227605e4a760 | 1567 | if (app == APP_NONE) { |
dudmuck | 8:227605e4a760 | 1568 | if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1569 | if (!per_parse_rx(lora.RegRxNbBytes)) { |
dudmuck | 8:227605e4a760 | 1570 | PacketNormalCnt++; |
dudmuck | 21:b84a77dfb43c | 1571 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 8:227605e4a760 | 1572 | } |
dudmuck | 8:227605e4a760 | 1573 | } else |
dudmuck | 21:b84a77dfb43c | 1574 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 15:c69b942685ea | 1575 | fflush(stdout); |
dudmuck | 1:1cd0afbed23c | 1576 | } else if (app == APP_CHAT) { |
dudmuck | 1:1cd0afbed23c | 1577 | if (lora.RegHopChannel.bits.RxPayloadCrcOn) { |
dudmuck | 1:1cd0afbed23c | 1578 | if (lora.RegIrqFlags.bits.PayloadCrcError) |
dudmuck | 1:1cd0afbed23c | 1579 | printf("crcError\r\n"); |
dudmuck | 1:1cd0afbed23c | 1580 | else { |
dudmuck | 1:1cd0afbed23c | 1581 | int n = lora.RegRxNbBytes; |
dudmuck | 1:1cd0afbed23c | 1582 | radio.rx_buf[n++] = '\r'; |
dudmuck | 1:1cd0afbed23c | 1583 | radio.rx_buf[n++] = '\n'; |
dudmuck | 1:1cd0afbed23c | 1584 | radio.rx_buf[n] = 0; // null terminate |
dudmuck | 1:1cd0afbed23c | 1585 | printf((char *)radio.rx_buf); |
dudmuck | 1:1cd0afbed23c | 1586 | } |
dudmuck | 1:1cd0afbed23c | 1587 | } else |
dudmuck | 1:1cd0afbed23c | 1588 | printf("crcOff\r\n"); |
dudmuck | 1:1cd0afbed23c | 1589 | |
dudmuck | 1:1cd0afbed23c | 1590 | // clear Irq flags |
dudmuck | 1:1cd0afbed23c | 1591 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 1:1cd0afbed23c | 1592 | // should still be in receive mode |
dudmuck | 0:be215de91a68 | 1593 | } |
dudmuck | 1:1cd0afbed23c | 1594 | break; |
dudmuck | 1:1cd0afbed23c | 1595 | case SERVICE_TX_DONE: |
dudmuck | 1:1cd0afbed23c | 1596 | if (app == APP_CHAT) { |
dudmuck | 18:9530d682fd9a | 1597 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 8:227605e4a760 | 1598 | } else if (per_en) { |
dudmuck | 18:9530d682fd9a | 1599 | per_timeout.attach(&per_cb, per_tx_delay); // start next TX |
dudmuck | 18:9530d682fd9a | 1600 | } else if (on_txdone_state != ON_TXDONE_STATE_NONE) { |
dudmuck | 18:9530d682fd9a | 1601 | on_txdone_timeout.attach(&txdone_timeout_cb, on_txdone_delay); |
dudmuck | 1:1cd0afbed23c | 1602 | } |
dudmuck | 1:1cd0afbed23c | 1603 | break; |
dudmuck | 1:1cd0afbed23c | 1604 | case SERVICE_ERROR: |
dudmuck | 1:1cd0afbed23c | 1605 | printf("error\r\n"); |
dudmuck | 1:1cd0afbed23c | 1606 | break; |
dudmuck | 19:be8a8b0e7320 | 1607 | case SERVICE_NONE: |
dudmuck | 19:be8a8b0e7320 | 1608 | break; |
dudmuck | 1:1cd0afbed23c | 1609 | } // ...switch (act) |
dudmuck | 1:1cd0afbed23c | 1610 | } else { |
dudmuck | 1:1cd0afbed23c | 1611 | /* FSK: */ |
dudmuck | 21:b84a77dfb43c | 1612 | |
dudmuck | 21:b84a77dfb43c | 1613 | if (rx_payloadReady_int_en) |
dudmuck | 21:b84a77dfb43c | 1614 | return; // radio service by ISR only |
dudmuck | 21:b84a77dfb43c | 1615 | |
dudmuck | 21:b84a77dfb43c | 1616 | if (ulrx_enable) |
dudmuck | 21:b84a77dfb43c | 1617 | return; |
dudmuck | 21:b84a77dfb43c | 1618 | |
dudmuck | 1:1cd0afbed23c | 1619 | act = fsk.service(); |
dudmuck | 1:1cd0afbed23c | 1620 | |
dudmuck | 1:1cd0afbed23c | 1621 | switch (act) { |
dudmuck | 1:1cd0afbed23c | 1622 | case SERVICE_READ_FIFO: |
dudmuck | 2:c6b23a43a9d9 | 1623 | if (app == APP_CHAT) { |
dudmuck | 2:c6b23a43a9d9 | 1624 | int n = fsk.rx_buf_length; |
dudmuck | 2:c6b23a43a9d9 | 1625 | radio.rx_buf[n++] = '\r'; |
dudmuck | 2:c6b23a43a9d9 | 1626 | radio.rx_buf[n++] = '\n'; |
dudmuck | 2:c6b23a43a9d9 | 1627 | radio.rx_buf[n] = 0; // null terminate |
dudmuck | 2:c6b23a43a9d9 | 1628 | printf((char *)radio.rx_buf); |
dudmuck | 2:c6b23a43a9d9 | 1629 | } else { |
dudmuck | 21:b84a77dfb43c | 1630 | if (fsk.RegRxConfig.bits.AfcAutoOn) { |
dudmuck | 14:c57ea544dc18 | 1631 | printf("%dHz ", (int)(FREQ_STEP_HZ * fsk.RegAfcValue)); |
dudmuck | 14:c57ea544dc18 | 1632 | if (rssi != 0) { |
dudmuck | 15:c69b942685ea | 1633 | printf("pkt:-%.1fdBm ", rssi / 2.0); |
dudmuck | 14:c57ea544dc18 | 1634 | rssi = 0; |
dudmuck | 15:c69b942685ea | 1635 | } |
dudmuck | 21:b84a77dfb43c | 1636 | } |
dudmuck | 13:c73caaee93a5 | 1637 | if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1638 | if (!per_parse_rx(fsk.rx_buf_length)) { |
dudmuck | 13:c73caaee93a5 | 1639 | PacketNormalCnt++; |
dudmuck | 13:c73caaee93a5 | 1640 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 13:c73caaee93a5 | 1641 | } |
dudmuck | 13:c73caaee93a5 | 1642 | } else { |
dudmuck | 13:c73caaee93a5 | 1643 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 13:c73caaee93a5 | 1644 | } |
dudmuck | 21:b84a77dfb43c | 1645 | |
dudmuck | 2:c6b23a43a9d9 | 1646 | } |
dudmuck | 21:b84a77dfb43c | 1647 | if (crc32_en) { |
dudmuck | 21:b84a77dfb43c | 1648 | uint32_t c, *u32_ptr = (uint32_t*)&radio.rx_buf[fsk.rx_buf_length-4]; |
dudmuck | 23:821b4f426ee6 | 1649 | printf("rx crc:%08x, ", (unsigned int)(*u32_ptr)); |
dudmuck | 21:b84a77dfb43c | 1650 | c = gen_crc(radio.rx_buf, fsk.rx_buf_length-4); |
dudmuck | 23:821b4f426ee6 | 1651 | printf("calc crc:%08x\r\n", (unsigned int)c); |
dudmuck | 21:b84a77dfb43c | 1652 | } |
dudmuck | 21:b84a77dfb43c | 1653 | fflush(stdout); |
dudmuck | 1:1cd0afbed23c | 1654 | break; |
dudmuck | 2:c6b23a43a9d9 | 1655 | case SERVICE_TX_DONE: |
dudmuck | 18:9530d682fd9a | 1656 | if (ook_test_en) |
dudmuck | 18:9530d682fd9a | 1657 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 2:c6b23a43a9d9 | 1658 | if (app == APP_CHAT) { |
dudmuck | 2:c6b23a43a9d9 | 1659 | fsk.start_rx(); |
dudmuck | 13:c73caaee93a5 | 1660 | } else if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1661 | per_timeout.attach(&per_cb, per_tx_delay); // start next TX |
dudmuck | 13:c73caaee93a5 | 1662 | } |
dudmuck | 2:c6b23a43a9d9 | 1663 | break; |
dudmuck | 19:be8a8b0e7320 | 1664 | case SERVICE_ERROR: |
dudmuck | 19:be8a8b0e7320 | 1665 | case SERVICE_NONE: |
dudmuck | 19:be8a8b0e7320 | 1666 | break; |
dudmuck | 20:b11592c9ba5f | 1667 | } // ...switch (act) |
dudmuck | 22:2005df80c8a8 | 1668 | |
Wayne Roberts |
24:9ba45aa15b53 | 1669 | #ifndef TARGET_DISCO_L072CZ_LRWAN1 |
dudmuck | 20:b11592c9ba5f | 1670 | /* FSK receiver handling of preamble detection */ |
dudmuck | 20:b11592c9ba5f | 1671 | if (radio.RegDioMapping2.bits.MapPreambleDetect && radio.RegDioMapping2.bits.Dio4Mapping == 3) { |
dudmuck | 20:b11592c9ba5f | 1672 | if (saved_dio4 != dio4.read()) { |
dudmuck | 20:b11592c9ba5f | 1673 | //printf("predet-dio4:%d\r\n", dio4.read()); |
dudmuck | 20:b11592c9ba5f | 1674 | /* FSK: preamble detect state change */ |
dudmuck | 20:b11592c9ba5f | 1675 | if (dio4.read()) { |
dudmuck | 20:b11592c9ba5f | 1676 | if (radio.RegDioMapping1.bits.Dio2Mapping == 3) { // if we can see SyncAddress |
dudmuck | 20:b11592c9ba5f | 1677 | get_syncAddress = true; |
dudmuck | 20:b11592c9ba5f | 1678 | timeout_syncAddress.attach_us(callback_sa_timeout, preamble_to_sync_us); |
dudmuck | 20:b11592c9ba5f | 1679 | } |
dudmuck | 20:b11592c9ba5f | 1680 | /* how long after RX start is preamble detection occuring? */ |
dudmuck | 20:b11592c9ba5f | 1681 | //printf("preamble detect at %f\r\n", rx_start_timer.read()); |
dudmuck | 20:b11592c9ba5f | 1682 | preamble_detect_at = rx_start_timer.read(); |
dudmuck | 20:b11592c9ba5f | 1683 | } else { |
dudmuck | 20:b11592c9ba5f | 1684 | get_syncAddress = false; |
dudmuck | 20:b11592c9ba5f | 1685 | //printf("preamble detect clear\r\n"); |
dudmuck | 20:b11592c9ba5f | 1686 | } |
dudmuck | 20:b11592c9ba5f | 1687 | saved_dio4 = dio4.read(); |
dudmuck | 20:b11592c9ba5f | 1688 | } |
dudmuck | 20:b11592c9ba5f | 1689 | } // ..if dio4 is |
dudmuck | 22:2005df80c8a8 | 1690 | |
dudmuck | 20:b11592c9ba5f | 1691 | if (radio.RegDioMapping1.bits.Dio2Mapping == 3) { |
dudmuck | 20:b11592c9ba5f | 1692 | if (dio2.read()) { |
dudmuck | 20:b11592c9ba5f | 1693 | if (get_syncAddress) { |
dudmuck | 20:b11592c9ba5f | 1694 | timeout_syncAddress.detach(); |
dudmuck | 20:b11592c9ba5f | 1695 | get_syncAddress = false; |
dudmuck | 20:b11592c9ba5f | 1696 | } |
dudmuck | 15:c69b942685ea | 1697 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 14:c57ea544dc18 | 1698 | } |
dudmuck | 14:c57ea544dc18 | 1699 | } |
Wayne Roberts |
24:9ba45aa15b53 | 1700 | #endif /* !TARGET_DISCO_L072CZ_LRWAN1 */ |
dudmuck | 22:2005df80c8a8 | 1701 | |
dudmuck | 21:b84a77dfb43c | 1702 | if (rssi_polling_thresh != 0 && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 21:b84a77dfb43c | 1703 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 21:b84a77dfb43c | 1704 | rssi = -rssi; |
Wayne Roberts |
24:9ba45aa15b53 | 1705 | #if defined(TARGET_STM) && !defined(TARGET_DISCO_L072CZ_LRWAN1) && !defined(TARGET_MTS_MDOT_F411RE) |
dudmuck | 21:b84a77dfb43c | 1706 | if (rssi < rssi_polling_thresh) |
dudmuck | 21:b84a77dfb43c | 1707 | pc3 = 0; // signal weaker than threshold |
dudmuck | 21:b84a77dfb43c | 1708 | else |
dudmuck | 21:b84a77dfb43c | 1709 | pc3 = 1; // signal stronger than threshold |
dudmuck | 22:2005df80c8a8 | 1710 | #endif |
dudmuck | 21:b84a77dfb43c | 1711 | } |
dudmuck | 22:2005df80c8a8 | 1712 | |
dudmuck | 14:c57ea544dc18 | 1713 | } // ...!radio.RegOpMode.bits.LongRangeMode |
dudmuck | 0:be215de91a68 | 1714 | } |
dudmuck | 0:be215de91a68 | 1715 | |
dudmuck | 5:360069ec9953 | 1716 | /*int get_kbd_str(char* buf, int size) |
dudmuck | 0:be215de91a68 | 1717 | { |
dudmuck | 0:be215de91a68 | 1718 | char c; |
dudmuck | 0:be215de91a68 | 1719 | int i; |
dudmuck | 0:be215de91a68 | 1720 | static int prev_len; |
dudmuck | 0:be215de91a68 | 1721 | |
dudmuck | 0:be215de91a68 | 1722 | for (i = 0;;) { |
dudmuck | 0:be215de91a68 | 1723 | if (pc.readable()) { |
dudmuck | 0:be215de91a68 | 1724 | c = pc.getc(); |
dudmuck | 0:be215de91a68 | 1725 | if (c == 8 && i > 0) { |
dudmuck | 0:be215de91a68 | 1726 | pc.putc(8); |
dudmuck | 0:be215de91a68 | 1727 | pc.putc(' '); |
dudmuck | 0:be215de91a68 | 1728 | pc.putc(8); |
dudmuck | 0:be215de91a68 | 1729 | i--; |
dudmuck | 0:be215de91a68 | 1730 | } else if (c == '\r') { |
dudmuck | 0:be215de91a68 | 1731 | if (i == 0) { |
dudmuck | 0:be215de91a68 | 1732 | return prev_len; // repeat previous |
dudmuck | 0:be215de91a68 | 1733 | } else { |
dudmuck | 0:be215de91a68 | 1734 | buf[i] = 0; // null terminate |
dudmuck | 0:be215de91a68 | 1735 | prev_len = i; |
dudmuck | 0:be215de91a68 | 1736 | return i; |
dudmuck | 0:be215de91a68 | 1737 | } |
dudmuck | 0:be215de91a68 | 1738 | } else if (c == 3) { |
dudmuck | 0:be215de91a68 | 1739 | // ctrl-C abort |
dudmuck | 0:be215de91a68 | 1740 | return -1; |
dudmuck | 0:be215de91a68 | 1741 | } else if (i < size) { |
dudmuck | 0:be215de91a68 | 1742 | buf[i++] = c; |
dudmuck | 0:be215de91a68 | 1743 | pc.putc(c); |
dudmuck | 0:be215de91a68 | 1744 | } |
dudmuck | 4:7a9007dfc0e5 | 1745 | } else { |
dudmuck | 0:be215de91a68 | 1746 | service_radio(); |
dudmuck | 4:7a9007dfc0e5 | 1747 | } |
dudmuck | 0:be215de91a68 | 1748 | } // ...for() |
dudmuck | 5:360069ec9953 | 1749 | }*/ |
dudmuck | 0:be215de91a68 | 1750 | |
dudmuck | 0:be215de91a68 | 1751 | void |
dudmuck | 0:be215de91a68 | 1752 | console_chat() |
dudmuck | 0:be215de91a68 | 1753 | { |
dudmuck | 5:360069ec9953 | 1754 | //int i, len = get_kbd_str(pcbuf, sizeof(pcbuf)); |
dudmuck | 5:360069ec9953 | 1755 | |
dudmuck | 5:360069ec9953 | 1756 | service_radio(); |
dudmuck | 5:360069ec9953 | 1757 | |
dudmuck | 5:360069ec9953 | 1758 | if (pcbuf_len < 0) { |
dudmuck | 0:be215de91a68 | 1759 | printf("chat abort\r\n"); |
dudmuck | 5:360069ec9953 | 1760 | pcbuf_len = 0; |
dudmuck | 0:be215de91a68 | 1761 | app = APP_NONE; |
dudmuck | 0:be215de91a68 | 1762 | return; |
dudmuck | 5:360069ec9953 | 1763 | } else if (pcbuf_len == 0) { |
dudmuck | 5:360069ec9953 | 1764 | return; |
dudmuck | 0:be215de91a68 | 1765 | } else { |
dudmuck | 5:360069ec9953 | 1766 | int i; |
dudmuck | 5:360069ec9953 | 1767 | for (i = 0; i < pcbuf_len; i++) |
dudmuck | 0:be215de91a68 | 1768 | radio.tx_buf[i] = pcbuf[i]; |
dudmuck | 1:1cd0afbed23c | 1769 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 5:360069ec9953 | 1770 | lora.RegPayloadLength = pcbuf_len; |
dudmuck | 1:1cd0afbed23c | 1771 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 5:360069ec9953 | 1772 | lora.start_tx(pcbuf_len); |
dudmuck | 2:c6b23a43a9d9 | 1773 | } else { |
dudmuck | 5:360069ec9953 | 1774 | fsk.start_tx(pcbuf_len); |
dudmuck | 2:c6b23a43a9d9 | 1775 | } |
dudmuck | 5:360069ec9953 | 1776 | pcbuf_len = 0; |
dudmuck | 0:be215de91a68 | 1777 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 1778 | } |
dudmuck | 0:be215de91a68 | 1779 | } |
dudmuck | 0:be215de91a68 | 1780 | |
dudmuck | 22:2005df80c8a8 | 1781 | const uint8_t ookt_tx_payload[29] = { |
dudmuck | 21:b84a77dfb43c | 1782 | 0x55, 0x55, 0x55, 0x55, 0xA9, 0x66, 0x69, 0x65, |
dudmuck | 21:b84a77dfb43c | 1783 | 0x39, 0x53, 0xAA, 0xC3, 0xA6, 0x95, 0xC6, 0x3C, |
dudmuck | 21:b84a77dfb43c | 1784 | 0x6A, 0x33, 0x33, 0xC6, 0xCA, 0xA6, 0x33, 0x33, |
dudmuck | 21:b84a77dfb43c | 1785 | 0x55, 0x6A, 0xA6, 0xAA, 0x53 |
dudmuck | 21:b84a77dfb43c | 1786 | }; |
dudmuck | 23:821b4f426ee6 | 1787 | volatile unsigned int ook_tx_cnt = 0; |
dudmuck | 21:b84a77dfb43c | 1788 | |
dudmuck | 21:b84a77dfb43c | 1789 | void callback_ook_tx_test() |
dudmuck | 21:b84a77dfb43c | 1790 | { |
dudmuck | 23:821b4f426ee6 | 1791 | unsigned int i; |
dudmuck | 21:b84a77dfb43c | 1792 | |
dudmuck | 21:b84a77dfb43c | 1793 | //radio.write_reg(REG_FSK_SYNCCONFIG, 0); |
dudmuck | 21:b84a77dfb43c | 1794 | |
dudmuck | 21:b84a77dfb43c | 1795 | printf("%u ookTx: ", ook_tx_cnt++); |
dudmuck | 21:b84a77dfb43c | 1796 | for (i = 0; i < sizeof(ookt_tx_payload); i++) { |
dudmuck | 21:b84a77dfb43c | 1797 | radio.tx_buf[i] = ookt_tx_payload[i]; |
dudmuck | 21:b84a77dfb43c | 1798 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 21:b84a77dfb43c | 1799 | } |
dudmuck | 21:b84a77dfb43c | 1800 | printf("\r\n"); |
dudmuck | 21:b84a77dfb43c | 1801 | |
dudmuck | 21:b84a77dfb43c | 1802 | //printf("syncConf:%x\r\n", radio.read_reg(REG_FSK_SYNCCONFIG)); |
dudmuck | 21:b84a77dfb43c | 1803 | fsk.start_tx(sizeof(ookt_tx_payload)); |
dudmuck | 21:b84a77dfb43c | 1804 | } |
dudmuck | 21:b84a77dfb43c | 1805 | |
dudmuck | 18:9530d682fd9a | 1806 | typedef enum { |
dudmuck | 18:9530d682fd9a | 1807 | TXTICKER_STATE_OFF = 0, |
dudmuck | 18:9530d682fd9a | 1808 | TXTICKER_STATE_TOGGLE_PAYLOAD_BIT, |
dudmuck | 18:9530d682fd9a | 1809 | TXTICKER_STATE_CYCLE_PAYLOAD_LENGTH, |
dudmuck | 18:9530d682fd9a | 1810 | TXTICKER_STATE_CYCLE_CODING_RATE, |
dudmuck | 18:9530d682fd9a | 1811 | TXTICKER_STATE_TOG_HEADER_MODE, |
dudmuck | 18:9530d682fd9a | 1812 | TXTICKER_STATE_TOG_CRC_ON, |
dudmuck | 18:9530d682fd9a | 1813 | TXTICKER_STATE_CYCLE_SYNC_1, |
dudmuck | 18:9530d682fd9a | 1814 | TXTICKER_STATE_CYCLE_SYNC_2, |
dudmuck | 18:9530d682fd9a | 1815 | TXTICKER_STATE_RAMP_PAYLOAD_DATA_START, |
dudmuck | 18:9530d682fd9a | 1816 | TXTICKER_STATE_RAMP_PAYLOAD_DATA, |
dudmuck | 18:9530d682fd9a | 1817 | TXTICKER_STATE_SYMBOL_SWEEP, |
dudmuck | 18:9530d682fd9a | 1818 | TXTICKER_STATE_TOGGLE_ALL_BITS_START, |
dudmuck | 18:9530d682fd9a | 1819 | TXTICKER_STATE_TOGGLE_ALL_BITS, |
dudmuck | 18:9530d682fd9a | 1820 | } txticker_state_e; |
dudmuck | 18:9530d682fd9a | 1821 | |
dudmuck | 18:9530d682fd9a | 1822 | txticker_state_e txticker_state; |
dudmuck | 18:9530d682fd9a | 1823 | float tx_ticker_rate = 0.5; |
dudmuck | 18:9530d682fd9a | 1824 | Ticker tx_ticker; |
dudmuck | 18:9530d682fd9a | 1825 | |
dudmuck | 18:9530d682fd9a | 1826 | uint8_t txticker_sync_byte; |
dudmuck | 18:9530d682fd9a | 1827 | uint8_t payload_length_stop; |
dudmuck | 18:9530d682fd9a | 1828 | uint8_t symbol_num; |
dudmuck | 18:9530d682fd9a | 1829 | uint32_t symbol_sweep_bit_counter = 0; |
dudmuck | 18:9530d682fd9a | 1830 | unsigned int symbol_sweep_bit_counter_stop; |
dudmuck | 18:9530d682fd9a | 1831 | uint8_t symbol_sweep_nbits; |
dudmuck | 18:9530d682fd9a | 1832 | uint8_t byte_pad_length; |
dudmuck | 18:9530d682fd9a | 1833 | |
dudmuck | 18:9530d682fd9a | 1834 | uint8_t tab_current_byte_num; |
dudmuck | 18:9530d682fd9a | 1835 | uint8_t tab_current_bit_in_byte; |
dudmuck | 18:9530d682fd9a | 1836 | |
dudmuck | 18:9530d682fd9a | 1837 | void fp_cb() |
dudmuck | 18:9530d682fd9a | 1838 | { |
dudmuck | 18:9530d682fd9a | 1839 | int i; |
dudmuck | 18:9530d682fd9a | 1840 | if (!radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 1841 | return; |
dudmuck | 18:9530d682fd9a | 1842 | |
dudmuck | 18:9530d682fd9a | 1843 | switch (txticker_state) { |
dudmuck | 18:9530d682fd9a | 1844 | case TXTICKER_STATE_TOGGLE_PAYLOAD_BIT: |
dudmuck | 18:9530d682fd9a | 1845 | /* |
dudmuck | 18:9530d682fd9a | 1846 | { |
dudmuck | 18:9530d682fd9a | 1847 | if (fp_tog_bit_ < 32) { |
dudmuck | 18:9530d682fd9a | 1848 | uint32_t bp = 1 << fp_tog_bit_; |
dudmuck | 18:9530d682fd9a | 1849 | fp_data ^= bp; |
dudmuck | 18:9530d682fd9a | 1850 | //printf("bp%02x ", bp); |
dudmuck | 18:9530d682fd9a | 1851 | } |
dudmuck | 18:9530d682fd9a | 1852 | memcpy(radio.tx_buf, &fp_data, fp_data_length); |
dudmuck | 18:9530d682fd9a | 1853 | printf("TX "); |
dudmuck | 18:9530d682fd9a | 1854 | for (i = 0; i < fp_data_length; i++) |
dudmuck | 18:9530d682fd9a | 1855 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1856 | |
dudmuck | 18:9530d682fd9a | 1857 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1858 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1859 | break; |
dudmuck | 18:9530d682fd9a | 1860 | } |
dudmuck | 18:9530d682fd9a | 1861 | */ |
dudmuck | 18:9530d682fd9a | 1862 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1863 | break; |
dudmuck | 18:9530d682fd9a | 1864 | case TXTICKER_STATE_CYCLE_PAYLOAD_LENGTH: |
dudmuck | 18:9530d682fd9a | 1865 | { |
dudmuck | 18:9530d682fd9a | 1866 | if (lora.RegPayloadLength > payload_length_stop) |
dudmuck | 18:9530d682fd9a | 1867 | lora.RegPayloadLength = 0; |
dudmuck | 18:9530d682fd9a | 1868 | else |
dudmuck | 18:9530d682fd9a | 1869 | lora.RegPayloadLength++; |
dudmuck | 18:9530d682fd9a | 1870 | |
dudmuck | 18:9530d682fd9a | 1871 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1872 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1873 | printf("RegPayloadLength:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1874 | break; |
dudmuck | 18:9530d682fd9a | 1875 | } |
dudmuck | 18:9530d682fd9a | 1876 | case TXTICKER_STATE_CYCLE_CODING_RATE: |
dudmuck | 18:9530d682fd9a | 1877 | { |
dudmuck | 18:9530d682fd9a | 1878 | uint8_t cr = lora.getCodingRate(false); // false: TX coding rate |
dudmuck | 18:9530d682fd9a | 1879 | if (cr == 4) |
dudmuck | 18:9530d682fd9a | 1880 | cr = 0; |
dudmuck | 18:9530d682fd9a | 1881 | else |
dudmuck | 18:9530d682fd9a | 1882 | cr++; |
dudmuck | 18:9530d682fd9a | 1883 | |
dudmuck | 18:9530d682fd9a | 1884 | lora.setCodingRate(cr); |
dudmuck | 18:9530d682fd9a | 1885 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1886 | printf("tx cr:%d\r\n", cr); |
dudmuck | 18:9530d682fd9a | 1887 | break; |
dudmuck | 18:9530d682fd9a | 1888 | } |
dudmuck | 18:9530d682fd9a | 1889 | case TXTICKER_STATE_TOG_HEADER_MODE: |
dudmuck | 18:9530d682fd9a | 1890 | { |
dudmuck | 18:9530d682fd9a | 1891 | lora.setHeaderMode(!lora.getHeaderMode()); |
dudmuck | 18:9530d682fd9a | 1892 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1893 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 1894 | lora_printHeaderMode(); |
dudmuck | 18:9530d682fd9a | 1895 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1896 | break; |
dudmuck | 18:9530d682fd9a | 1897 | } |
dudmuck | 18:9530d682fd9a | 1898 | case TXTICKER_STATE_TOG_CRC_ON: |
dudmuck | 18:9530d682fd9a | 1899 | { |
dudmuck | 18:9530d682fd9a | 1900 | lora.setRxPayloadCrcOn(!lora.getRxPayloadCrcOn()); |
dudmuck | 18:9530d682fd9a | 1901 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1902 | printf("crc on:%d\r\n", lora.getRxPayloadCrcOn()); |
dudmuck | 18:9530d682fd9a | 1903 | break; |
dudmuck | 18:9530d682fd9a | 1904 | } |
dudmuck | 18:9530d682fd9a | 1905 | case TXTICKER_STATE_CYCLE_SYNC_1: |
dudmuck | 18:9530d682fd9a | 1906 | { |
dudmuck | 18:9530d682fd9a | 1907 | /* cycle hi nibble of 0x39 register */ |
dudmuck | 18:9530d682fd9a | 1908 | if ((txticker_sync_byte & 0xf0) == 0xf0) |
dudmuck | 18:9530d682fd9a | 1909 | txticker_sync_byte &= 0x0f; |
dudmuck | 18:9530d682fd9a | 1910 | else |
dudmuck | 18:9530d682fd9a | 1911 | txticker_sync_byte += 0x10; |
dudmuck | 18:9530d682fd9a | 1912 | radio.write_reg(REG_LR_SYNC_BYTE, txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1913 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1914 | printf("0x39: %02x\r\n", txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1915 | break; |
dudmuck | 18:9530d682fd9a | 1916 | } |
dudmuck | 18:9530d682fd9a | 1917 | case TXTICKER_STATE_CYCLE_SYNC_2: |
dudmuck | 18:9530d682fd9a | 1918 | { |
dudmuck | 18:9530d682fd9a | 1919 | /* cycle lo nibble of 0x39 register */ |
dudmuck | 18:9530d682fd9a | 1920 | if ((txticker_sync_byte & 0x0f) == 0x0f) |
dudmuck | 18:9530d682fd9a | 1921 | txticker_sync_byte &= 0xf0; |
dudmuck | 18:9530d682fd9a | 1922 | else |
dudmuck | 18:9530d682fd9a | 1923 | txticker_sync_byte += 0x01; |
dudmuck | 18:9530d682fd9a | 1924 | radio.write_reg(REG_LR_SYNC_BYTE, txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1925 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1926 | printf("0x39: %02x\r\n", txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1927 | break; |
dudmuck | 18:9530d682fd9a | 1928 | } |
dudmuck | 18:9530d682fd9a | 1929 | case TXTICKER_STATE_RAMP_PAYLOAD_DATA_START: |
dudmuck | 18:9530d682fd9a | 1930 | txticker_state = TXTICKER_STATE_RAMP_PAYLOAD_DATA; |
dudmuck | 18:9530d682fd9a | 1931 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1932 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1933 | |
dudmuck | 18:9530d682fd9a | 1934 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1935 | printf("payload start, len:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1936 | break; |
dudmuck | 18:9530d682fd9a | 1937 | case TXTICKER_STATE_RAMP_PAYLOAD_DATA: |
dudmuck | 18:9530d682fd9a | 1938 | for (i = lora.RegPayloadLength-1; i >= 0; i--) { |
dudmuck | 18:9530d682fd9a | 1939 | //printf("i:%d ", i); |
dudmuck | 18:9530d682fd9a | 1940 | if (radio.tx_buf[i] == 255) { |
dudmuck | 18:9530d682fd9a | 1941 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1942 | } else { |
dudmuck | 18:9530d682fd9a | 1943 | radio.tx_buf[i]++; |
dudmuck | 18:9530d682fd9a | 1944 | break; |
dudmuck | 18:9530d682fd9a | 1945 | } |
dudmuck | 18:9530d682fd9a | 1946 | } |
dudmuck | 18:9530d682fd9a | 1947 | //printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1948 | printf("send:"); |
dudmuck | 18:9530d682fd9a | 1949 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 1950 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1951 | } |
dudmuck | 18:9530d682fd9a | 1952 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1953 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1954 | if (radio.tx_buf[0] == 255) { |
dudmuck | 18:9530d682fd9a | 1955 | printf("payload ramp done\r\n"); |
dudmuck | 18:9530d682fd9a | 1956 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1957 | } |
dudmuck | 18:9530d682fd9a | 1958 | break; |
dudmuck | 18:9530d682fd9a | 1959 | case TXTICKER_STATE_SYMBOL_SWEEP: // fpsNL command, where N=symbol num, L=nbytes |
dudmuck | 18:9530d682fd9a | 1960 | { |
dudmuck | 18:9530d682fd9a | 1961 | uint32_t mask; |
dudmuck | 18:9530d682fd9a | 1962 | /*for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1963 | radio.tx_buf[i] = 0;*/ |
dudmuck | 18:9530d682fd9a | 1964 | i = byte_pad_length; |
dudmuck | 19:be8a8b0e7320 | 1965 | printf("bit_counter 0x%" PRIx32 " : ", symbol_sweep_bit_counter); |
dudmuck | 18:9530d682fd9a | 1966 | for (int bn = 0; bn < symbol_sweep_nbits; bn += 2) { |
dudmuck | 18:9530d682fd9a | 1967 | /* 2 lsbits going into first byte */ |
dudmuck | 18:9530d682fd9a | 1968 | mask = 1 << bn; |
dudmuck | 18:9530d682fd9a | 1969 | if (symbol_sweep_bit_counter & mask) |
dudmuck | 18:9530d682fd9a | 1970 | radio.tx_buf[i] |= 1 << symbol_num; |
dudmuck | 18:9530d682fd9a | 1971 | else |
dudmuck | 18:9530d682fd9a | 1972 | radio.tx_buf[i] &= ~(1 << symbol_num); |
dudmuck | 18:9530d682fd9a | 1973 | mask = 2 << bn; |
dudmuck | 18:9530d682fd9a | 1974 | if (symbol_sweep_bit_counter & mask) |
dudmuck | 18:9530d682fd9a | 1975 | radio.tx_buf[i] |= 0x10 << symbol_num; |
dudmuck | 18:9530d682fd9a | 1976 | else |
dudmuck | 18:9530d682fd9a | 1977 | radio.tx_buf[i] &= ~(0x10 << symbol_num); |
dudmuck | 18:9530d682fd9a | 1978 | //printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1979 | i++; |
dudmuck | 18:9530d682fd9a | 1980 | } |
dudmuck | 18:9530d682fd9a | 1981 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1982 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1983 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1984 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1985 | if (++symbol_sweep_bit_counter == symbol_sweep_bit_counter_stop) { |
dudmuck | 18:9530d682fd9a | 1986 | printf("stop\r\n"); |
dudmuck | 18:9530d682fd9a | 1987 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1988 | } |
dudmuck | 18:9530d682fd9a | 1989 | } |
dudmuck | 18:9530d682fd9a | 1990 | break; |
dudmuck | 18:9530d682fd9a | 1991 | case TXTICKER_STATE_TOGGLE_ALL_BITS_START: |
dudmuck | 18:9530d682fd9a | 1992 | tab_current_byte_num = byte_pad_length; |
dudmuck | 18:9530d682fd9a | 1993 | tab_current_bit_in_byte = 0; |
dudmuck | 18:9530d682fd9a | 1994 | printf("tx "); |
dudmuck | 18:9530d682fd9a | 1995 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 1996 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1997 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1998 | } |
dudmuck | 18:9530d682fd9a | 1999 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2000 | txticker_state = TXTICKER_STATE_TOGGLE_ALL_BITS; |
dudmuck | 18:9530d682fd9a | 2001 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2002 | break; |
dudmuck | 18:9530d682fd9a | 2003 | case TXTICKER_STATE_TOGGLE_ALL_BITS: |
dudmuck | 18:9530d682fd9a | 2004 | { |
dudmuck | 18:9530d682fd9a | 2005 | uint8_t mask = 1 << tab_current_bit_in_byte; |
dudmuck | 18:9530d682fd9a | 2006 | radio.tx_buf[tab_current_byte_num] = mask; |
dudmuck | 18:9530d682fd9a | 2007 | printf("bit%d in [%d]: tx ", tab_current_bit_in_byte, tab_current_byte_num); |
dudmuck | 18:9530d682fd9a | 2008 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 2009 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 2010 | } |
dudmuck | 18:9530d682fd9a | 2011 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2012 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2013 | if (++tab_current_bit_in_byte == 8) { |
dudmuck | 18:9530d682fd9a | 2014 | radio.tx_buf[tab_current_byte_num] = 0; |
dudmuck | 18:9530d682fd9a | 2015 | tab_current_bit_in_byte = 0; |
dudmuck | 18:9530d682fd9a | 2016 | if (++tab_current_byte_num == lora.RegPayloadLength) { |
dudmuck | 18:9530d682fd9a | 2017 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 2018 | } |
dudmuck | 18:9530d682fd9a | 2019 | } |
dudmuck | 18:9530d682fd9a | 2020 | } |
dudmuck | 18:9530d682fd9a | 2021 | break; |
dudmuck | 18:9530d682fd9a | 2022 | default: |
dudmuck | 18:9530d682fd9a | 2023 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 2024 | break; |
dudmuck | 18:9530d682fd9a | 2025 | } // ...switch (txticker_state) |
dudmuck | 18:9530d682fd9a | 2026 | } |
dudmuck | 18:9530d682fd9a | 2027 | |
dudmuck | 18:9530d682fd9a | 2028 | void ook_test_tx(int len) |
dudmuck | 18:9530d682fd9a | 2029 | { |
dudmuck | 18:9530d682fd9a | 2030 | int i; |
dudmuck | 18:9530d682fd9a | 2031 | /* |
dudmuck | 18:9530d682fd9a | 2032 | fsk.RegPktConfig2.bits.PayloadLength = i; |
dudmuck | 18:9530d682fd9a | 2033 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word);fsk.RegPktConfig2.bits.PayloadLength = i; |
dudmuck | 18:9530d682fd9a | 2034 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 18:9530d682fd9a | 2035 | */ |
dudmuck | 18:9530d682fd9a | 2036 | for (i = 0; i < 4; i++) { |
dudmuck | 18:9530d682fd9a | 2037 | radio.tx_buf[i] = 0xaa; |
dudmuck | 18:9530d682fd9a | 2038 | } |
dudmuck | 18:9530d682fd9a | 2039 | |
dudmuck | 18:9530d682fd9a | 2040 | printf("ooktx:"); |
dudmuck | 18:9530d682fd9a | 2041 | for (i = 0; i < len; i++) { |
dudmuck | 18:9530d682fd9a | 2042 | radio.tx_buf[i+4] = rand() & 0xff; |
dudmuck | 18:9530d682fd9a | 2043 | printf("%02x ", radio.tx_buf[i+4]); |
dudmuck | 18:9530d682fd9a | 2044 | } |
dudmuck | 18:9530d682fd9a | 2045 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2046 | fsk.start_tx(len+4); |
dudmuck | 18:9530d682fd9a | 2047 | |
dudmuck | 18:9530d682fd9a | 2048 | while (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { |
dudmuck | 18:9530d682fd9a | 2049 | if (poll_irq_en) |
dudmuck | 18:9530d682fd9a | 2050 | poll_service_radio(); |
dudmuck | 18:9530d682fd9a | 2051 | else |
dudmuck | 18:9530d682fd9a | 2052 | service_radio(); |
dudmuck | 18:9530d682fd9a | 2053 | } |
dudmuck | 18:9530d682fd9a | 2054 | } |
dudmuck | 18:9530d682fd9a | 2055 | |
dudmuck | 18:9530d682fd9a | 2056 | void cmd_init(uint8_t args_at) |
dudmuck | 10:d9bb2ce57f05 | 2057 | { |
dudmuck | 18:9530d682fd9a | 2058 | printf("init\r\n"); |
dudmuck | 18:9530d682fd9a | 2059 | radio.init(); |
dudmuck | 18:9530d682fd9a | 2060 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 2061 | fsk.init(); // put FSK modem to some functioning default |
dudmuck | 18:9530d682fd9a | 2062 | } else { |
dudmuck | 18:9530d682fd9a | 2063 | // lora configuration is more simple |
dudmuck | 18:9530d682fd9a | 2064 | } |
dudmuck | 18:9530d682fd9a | 2065 | } |
dudmuck | 18:9530d682fd9a | 2066 | |
dudmuck | 18:9530d682fd9a | 2067 | void cmd_per_tx_delay(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2068 | { |
dudmuck | 18:9530d682fd9a | 2069 | int i; |
dudmuck | 18:9530d682fd9a | 2070 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2071 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2072 | per_tx_delay = i / 1000.0; |
dudmuck | 18:9530d682fd9a | 2073 | } |
dudmuck | 18:9530d682fd9a | 2074 | printf("per_tx_delay:%dms\r\n", (int)(per_tx_delay * 1000)); |
dudmuck | 18:9530d682fd9a | 2075 | } |
dudmuck | 18:9530d682fd9a | 2076 | |
dudmuck | 21:b84a77dfb43c | 2077 | const uint8_t test_payload_A[7] = { |
dudmuck | 21:b84a77dfb43c | 2078 | 0x80, 0x02, 0x58, 0xF5, 0xDF, 0xB8, 0x9E |
dudmuck | 21:b84a77dfb43c | 2079 | }; |
dudmuck | 21:b84a77dfb43c | 2080 | |
dudmuck | 21:b84a77dfb43c | 2081 | const uint8_t test_payload_B[] = { |
dudmuck | 21:b84a77dfb43c | 2082 | 0xca, 0xfe, 0xba, 0xbe |
dudmuck | 21:b84a77dfb43c | 2083 | }; |
dudmuck | 21:b84a77dfb43c | 2084 | |
dudmuck | 21:b84a77dfb43c | 2085 | const uint8_t test_payload_C[0x1a] = { |
dudmuck | 21:b84a77dfb43c | 2086 | 0x88, 0x39, 0x1F, 0xC6, 0xD3, 0xEB, 0xA4, 0xAC, |
dudmuck | 21:b84a77dfb43c | 2087 | 0xFB, 0xB9, 0xBA, 0xB9, 0xBE, 0x13, 0x61, 0x4C, |
dudmuck | 21:b84a77dfb43c | 2088 | 0x43, 0x83, 0x00, 0x92, 0x84, 0x00, 0x6F, 0x87, |
dudmuck | 21:b84a77dfb43c | 2089 | 0x7C, 0xB2 |
dudmuck | 21:b84a77dfb43c | 2090 | }; |
dudmuck | 21:b84a77dfb43c | 2091 | |
dudmuck | 18:9530d682fd9a | 2092 | void cmd_tx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2093 | { |
dudmuck | 18:9530d682fd9a | 2094 | int i; |
dudmuck | 18:9530d682fd9a | 2095 | static uint16_t fsk_tx_length; |
dudmuck | 18:9530d682fd9a | 2096 | |
dudmuck | 18:9530d682fd9a | 2097 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 2098 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2099 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2100 | lora.RegPayloadLength = i; |
dudmuck | 18:9530d682fd9a | 2101 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2102 | } |
dudmuck | 18:9530d682fd9a | 2103 | |
dudmuck | 21:b84a77dfb43c | 2104 | if (pcbuf[idx] == 'A') { |
dudmuck | 21:b84a77dfb43c | 2105 | } else if (pcbuf[idx] == 'B') { |
dudmuck | 21:b84a77dfb43c | 2106 | } else if (pcbuf[idx] == 'C') { |
dudmuck | 21:b84a77dfb43c | 2107 | } else { |
dudmuck | 21:b84a77dfb43c | 2108 | tx_cnt++; |
dudmuck | 21:b84a77dfb43c | 2109 | printf("payload:%02x\r\n", tx_cnt); |
dudmuck | 21:b84a77dfb43c | 2110 | |
dudmuck | 21:b84a77dfb43c | 2111 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 21:b84a77dfb43c | 2112 | radio.tx_buf[i] = tx_cnt; |
dudmuck | 21:b84a77dfb43c | 2113 | } |
dudmuck | 21:b84a77dfb43c | 2114 | |
dudmuck | 18:9530d682fd9a | 2115 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2116 | } else { // FSK: |
dudmuck | 21:b84a77dfb43c | 2117 | |
dudmuck | 21:b84a77dfb43c | 2118 | /* always variable-length format */ |
dudmuck | 21:b84a77dfb43c | 2119 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2120 | if (!fsk.RegPktConfig1.bits.PacketFormatVariable) { |
dudmuck | 21:b84a77dfb43c | 2121 | printf("fsk fixed->variable\r\n"); |
dudmuck | 21:b84a77dfb43c | 2122 | fsk.RegPktConfig1.bits.PacketFormatVariable = 1; |
dudmuck | 21:b84a77dfb43c | 2123 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2124 | } |
dudmuck | 21:b84a77dfb43c | 2125 | |
dudmuck | 18:9530d682fd9a | 2126 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2127 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2128 | fsk_tx_length = i; |
dudmuck | 18:9530d682fd9a | 2129 | } |
dudmuck | 18:9530d682fd9a | 2130 | if (ook_test_en) { |
dudmuck | 18:9530d682fd9a | 2131 | ook_test_tx(fsk_tx_length); |
dudmuck | 18:9530d682fd9a | 2132 | } else { |
dudmuck | 18:9530d682fd9a | 2133 | if (radio.RegOpMode.bits.Mode != RF_OPMODE_TRANSMITTER) { // if not already busy transmitting |
dudmuck | 21:b84a77dfb43c | 2134 | if (pcbuf[idx] == 'A') { |
dudmuck | 21:b84a77dfb43c | 2135 | fsk_tx_length = sizeof(test_payload_A); |
dudmuck | 21:b84a77dfb43c | 2136 | memcpy(radio.tx_buf, test_payload_A, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2137 | } else if (pcbuf[idx] == 'B') { |
dudmuck | 21:b84a77dfb43c | 2138 | fsk_tx_length = sizeof(test_payload_B); |
dudmuck | 21:b84a77dfb43c | 2139 | memcpy(radio.tx_buf, test_payload_B, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2140 | } else if (pcbuf[idx] == 'C') { |
dudmuck | 21:b84a77dfb43c | 2141 | fsk_tx_length = sizeof(test_payload_C); |
dudmuck | 21:b84a77dfb43c | 2142 | memcpy(radio.tx_buf, test_payload_C, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2143 | } else { |
dudmuck | 21:b84a77dfb43c | 2144 | tx_cnt++; |
dudmuck | 21:b84a77dfb43c | 2145 | printf("payload:%02x\r\n", tx_cnt); |
dudmuck | 21:b84a77dfb43c | 2146 | for (i = 0; i < fsk_tx_length; i++) { |
dudmuck | 21:b84a77dfb43c | 2147 | radio.tx_buf[i] = tx_cnt; |
dudmuck | 21:b84a77dfb43c | 2148 | } |
dudmuck | 18:9530d682fd9a | 2149 | } |
dudmuck | 21:b84a77dfb43c | 2150 | |
dudmuck | 18:9530d682fd9a | 2151 | fsk.start_tx(fsk_tx_length); |
dudmuck | 18:9530d682fd9a | 2152 | } |
dudmuck | 18:9530d682fd9a | 2153 | } |
dudmuck | 18:9530d682fd9a | 2154 | } // !LoRa |
dudmuck | 18:9530d682fd9a | 2155 | |
dudmuck | 18:9530d682fd9a | 2156 | } |
dudmuck | 18:9530d682fd9a | 2157 | |
dudmuck | 21:b84a77dfb43c | 2158 | volatile uint16_t long_byte_count, long_byte_count_at_full; |
dudmuck | 21:b84a77dfb43c | 2159 | |
dudmuck | 21:b84a77dfb43c | 2160 | const uint8_t test_preamble_sync[] = { |
dudmuck | 21:b84a77dfb43c | 2161 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xcb, 0x82 |
dudmuck | 21:b84a77dfb43c | 2162 | }; |
dudmuck | 21:b84a77dfb43c | 2163 | |
dudmuck | 21:b84a77dfb43c | 2164 | void _ulm_write_fifo(uint8_t len) |
dudmuck | 21:b84a77dfb43c | 2165 | { |
dudmuck | 21:b84a77dfb43c | 2166 | uint8_t i; |
dudmuck | 21:b84a77dfb43c | 2167 | |
dudmuck | 21:b84a77dfb43c | 2168 | //dio2 is FifoFull |
dudmuck | 21:b84a77dfb43c | 2169 | radio.m_cs = 0; |
dudmuck | 21:b84a77dfb43c | 2170 | radio.m_spi.write(REG_FIFO | 0x80); // bit7 is high for writing to radio |
dudmuck | 21:b84a77dfb43c | 2171 | |
dudmuck | 21:b84a77dfb43c | 2172 | for (i = 0; i < len; ) { |
dudmuck | 21:b84a77dfb43c | 2173 | //printf("_%02x\r\n", radio.tx_buf[i]); |
dudmuck | 21:b84a77dfb43c | 2174 | radio.m_spi.write(radio.tx_buf[i++]); |
dudmuck | 21:b84a77dfb43c | 2175 | long_byte_count++; |
dudmuck | 21:b84a77dfb43c | 2176 | if (dio2) { |
dudmuck | 21:b84a77dfb43c | 2177 | long_byte_count_at_full = long_byte_count; |
dudmuck | 21:b84a77dfb43c | 2178 | while (radio.dio1) |
dudmuck | 21:b84a77dfb43c | 2179 | ; |
dudmuck | 21:b84a77dfb43c | 2180 | } |
dudmuck | 21:b84a77dfb43c | 2181 | } |
dudmuck | 21:b84a77dfb43c | 2182 | radio.m_cs = 1; |
dudmuck | 21:b84a77dfb43c | 2183 | } |
dudmuck | 21:b84a77dfb43c | 2184 | |
dudmuck | 21:b84a77dfb43c | 2185 | int write_buf_to_fifo(const uint8_t* send_buf, uint8_t target_length) |
dudmuck | 21:b84a77dfb43c | 2186 | { |
dudmuck | 21:b84a77dfb43c | 2187 | /* block until all is written */ |
dudmuck | 21:b84a77dfb43c | 2188 | uint8_t total_sent = 0; |
dudmuck | 21:b84a77dfb43c | 2189 | |
dudmuck | 21:b84a77dfb43c | 2190 | //printf("wbtf %u\r\n", target_length); |
dudmuck | 21:b84a77dfb43c | 2191 | while (target_length > total_sent) { |
dudmuck | 21:b84a77dfb43c | 2192 | uint8_t this_length = target_length - total_sent; |
dudmuck | 21:b84a77dfb43c | 2193 | memcpy(radio.tx_buf+total_sent, send_buf+total_sent, this_length); |
dudmuck | 21:b84a77dfb43c | 2194 | _ulm_write_fifo(this_length); |
dudmuck | 21:b84a77dfb43c | 2195 | total_sent += this_length; |
dudmuck | 21:b84a77dfb43c | 2196 | } |
dudmuck | 21:b84a77dfb43c | 2197 | return total_sent; |
dudmuck | 21:b84a77dfb43c | 2198 | } |
dudmuck | 21:b84a77dfb43c | 2199 | |
dudmuck | 21:b84a77dfb43c | 2200 | #define TEST_PAYLOAD test_payload_C |
dudmuck | 21:b84a77dfb43c | 2201 | //#define TEST_PAYLOAD test_payload_A |
dudmuck | 21:b84a77dfb43c | 2202 | void cmd_long_tx(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2203 | { |
dudmuck | 21:b84a77dfb43c | 2204 | unsigned int pkt_cnt = 0; |
dudmuck | 21:b84a77dfb43c | 2205 | bool first_pkt; |
dudmuck | 21:b84a77dfb43c | 2206 | /* transmit multipe packets without any time between packets (back to back) */ |
dudmuck | 21:b84a77dfb43c | 2207 | |
dudmuck | 21:b84a77dfb43c | 2208 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 21:b84a77dfb43c | 2209 | sscanf(pcbuf+idx, "%u", &pkt_cnt); |
dudmuck | 21:b84a77dfb43c | 2210 | } |
dudmuck | 21:b84a77dfb43c | 2211 | |
dudmuck | 21:b84a77dfb43c | 2212 | printf("tx %u pkts\r\n", pkt_cnt); |
dudmuck | 21:b84a77dfb43c | 2213 | if (pkt_cnt < 1) |
dudmuck | 21:b84a77dfb43c | 2214 | return; |
dudmuck | 21:b84a77dfb43c | 2215 | |
dudmuck | 21:b84a77dfb43c | 2216 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 21:b84a77dfb43c | 2217 | radio.RegDioMapping2.bits.Dio5Mapping = 2; // data output to observation |
dudmuck | 21:b84a77dfb43c | 2218 | radio.RegDioMapping2.bits.Dio4Mapping = 3; // output preamble detect indication |
dudmuck | 21:b84a77dfb43c | 2219 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; |
dudmuck | 21:b84a77dfb43c | 2220 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 21:b84a77dfb43c | 2221 | |
dudmuck | 21:b84a77dfb43c | 2222 | //unlimited packet length mode |
dudmuck | 21:b84a77dfb43c | 2223 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2224 | fsk.RegPktConfig1.bits.PacketFormatVariable = 0; // fixed length format |
dudmuck | 21:b84a77dfb43c | 2225 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2226 | |
dudmuck | 21:b84a77dfb43c | 2227 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 21:b84a77dfb43c | 2228 | fsk.RegPktConfig2.bits.PayloadLength = 0; |
dudmuck | 21:b84a77dfb43c | 2229 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 21:b84a77dfb43c | 2230 | //DIO3 to FifoEmpty (for end of tx) |
dudmuck | 21:b84a77dfb43c | 2231 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 2232 | radio.RegDioMapping1.bits.Dio3Mapping = 0; // FifoEmpty |
dudmuck | 21:b84a77dfb43c | 2233 | //DIO2 to FifoFull |
dudmuck | 21:b84a77dfb43c | 2234 | radio.RegDioMapping1.bits.Dio2Mapping = 0; // FIfoFull |
dudmuck | 21:b84a77dfb43c | 2235 | //DIO1 to FifoLevel |
dudmuck | 21:b84a77dfb43c | 2236 | radio.RegDioMapping1.bits.Dio1Mapping = 0; // FifoLevel |
dudmuck | 21:b84a77dfb43c | 2237 | radio.RegDioMapping1.bits.Dio0Mapping = 0; // PacketSent |
dudmuck | 21:b84a77dfb43c | 2238 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 21:b84a77dfb43c | 2239 | //FifoThreshold to approx 1/5th full |
dudmuck | 21:b84a77dfb43c | 2240 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 21:b84a77dfb43c | 2241 | fsk.RegFifoThreshold.bits.FifoThreshold = sizeof(TEST_PAYLOAD)-1; // allow single packet |
dudmuck | 21:b84a77dfb43c | 2242 | // tx start condition to FifoLevel |
dudmuck | 21:b84a77dfb43c | 2243 | fsk.RegFifoThreshold.bits.TxStartCondition = 0; // start on FifoLevel |
dudmuck | 21:b84a77dfb43c | 2244 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 21:b84a77dfb43c | 2245 | |
dudmuck | 21:b84a77dfb43c | 2246 | long_byte_count = 0; |
dudmuck | 21:b84a77dfb43c | 2247 | long_byte_count_at_full = 0xffff; |
dudmuck | 21:b84a77dfb43c | 2248 | |
dudmuck | 21:b84a77dfb43c | 2249 | radio.set_opmode(RF_OPMODE_TRANSMITTER); |
dudmuck | 21:b84a77dfb43c | 2250 | first_pkt = true; // preamble+sync sent by packet engine only for first packet |
dudmuck | 21:b84a77dfb43c | 2251 | for (; pkt_cnt > 0; pkt_cnt--) { |
dudmuck | 21:b84a77dfb43c | 2252 | uint8_t len; |
dudmuck | 21:b84a77dfb43c | 2253 | if (first_pkt) |
dudmuck | 21:b84a77dfb43c | 2254 | first_pkt = false; |
dudmuck | 21:b84a77dfb43c | 2255 | else { |
dudmuck | 21:b84a77dfb43c | 2256 | if (dio3) { |
dudmuck | 21:b84a77dfb43c | 2257 | printf("fail-empty\r\n"); |
dudmuck | 21:b84a77dfb43c | 2258 | } |
dudmuck | 21:b84a77dfb43c | 2259 | write_buf_to_fifo(test_preamble_sync, sizeof(test_preamble_sync)); |
dudmuck | 21:b84a77dfb43c | 2260 | } |
dudmuck | 21:b84a77dfb43c | 2261 | |
dudmuck | 21:b84a77dfb43c | 2262 | len = sizeof(TEST_PAYLOAD); //TEST_PAYLOAD doesnt start with length |
dudmuck | 21:b84a77dfb43c | 2263 | write_buf_to_fifo(&len, 1); |
dudmuck | 21:b84a77dfb43c | 2264 | write_buf_to_fifo(TEST_PAYLOAD, sizeof(TEST_PAYLOAD)); |
dudmuck | 21:b84a77dfb43c | 2265 | } // .. |
dudmuck | 21:b84a77dfb43c | 2266 | |
dudmuck | 21:b84a77dfb43c | 2267 | rx_start_timer.reset(); |
dudmuck | 21:b84a77dfb43c | 2268 | rx_start_timer.start(); |
dudmuck | 21:b84a77dfb43c | 2269 | while (!dio3) { |
dudmuck | 21:b84a77dfb43c | 2270 | if (rx_start_timer.read() > 1) { |
dudmuck | 21:b84a77dfb43c | 2271 | printf("fifoEmpty fail\r\n"); |
dudmuck | 21:b84a77dfb43c | 2272 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2273 | return; |
dudmuck | 21:b84a77dfb43c | 2274 | } |
dudmuck | 21:b84a77dfb43c | 2275 | } |
dudmuck | 21:b84a77dfb43c | 2276 | |
dudmuck | 21:b84a77dfb43c | 2277 | rx_start_timer.reset(); |
dudmuck | 21:b84a77dfb43c | 2278 | rx_start_timer.start(); |
dudmuck | 21:b84a77dfb43c | 2279 | while (!radio.dio0) { |
dudmuck | 21:b84a77dfb43c | 2280 | if (rx_start_timer.read() > 3) { |
dudmuck | 21:b84a77dfb43c | 2281 | printf("PacketSent fail\r\n"); |
dudmuck | 21:b84a77dfb43c | 2282 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2283 | return; |
dudmuck | 21:b84a77dfb43c | 2284 | } |
dudmuck | 21:b84a77dfb43c | 2285 | } |
dudmuck | 21:b84a77dfb43c | 2286 | wait_us(100); |
dudmuck | 21:b84a77dfb43c | 2287 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2288 | printf("done ok %u, %u\r\n", long_byte_count, long_byte_count_at_full); |
dudmuck | 21:b84a77dfb43c | 2289 | |
dudmuck | 21:b84a77dfb43c | 2290 | } |
dudmuck | 21:b84a77dfb43c | 2291 | |
dudmuck | 18:9530d682fd9a | 2292 | void cmd_hw_reset(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2293 | { |
dudmuck | 18:9530d682fd9a | 2294 | printf("hw_reset()\r\n"); |
dudmuck | 18:9530d682fd9a | 2295 | radio.hw_reset(); |
dudmuck | 18:9530d682fd9a | 2296 | ook_test_en = false; |
dudmuck | 18:9530d682fd9a | 2297 | poll_irq_en = false; |
dudmuck | 18:9530d682fd9a | 2298 | } |
dudmuck | 18:9530d682fd9a | 2299 | |
dudmuck | 18:9530d682fd9a | 2300 | void cmd_read_all_regs(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2301 | { |
dudmuck | 18:9530d682fd9a | 2302 | uint8_t a, d; |
dudmuck | 18:9530d682fd9a | 2303 | |
dudmuck | 18:9530d682fd9a | 2304 | // read all registers |
dudmuck | 18:9530d682fd9a | 2305 | for (a = 1; a < 0x71; a++) { |
dudmuck | 18:9530d682fd9a | 2306 | d = radio.read_reg(a); |
dudmuck | 18:9530d682fd9a | 2307 | printf("%02x: %02x\r\n", a, d); |
dudmuck | 18:9530d682fd9a | 2308 | } |
dudmuck | 18:9530d682fd9a | 2309 | } |
dudmuck | 18:9530d682fd9a | 2310 | |
dudmuck | 18:9530d682fd9a | 2311 | void cmd_read_current_rssi(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2312 | { |
dudmuck | 18:9530d682fd9a | 2313 | if (radio.RegOpMode.bits.Mode != RF_OPMODE_RECEIVER) { |
dudmuck | 18:9530d682fd9a | 2314 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 18:9530d682fd9a | 2315 | wait_us(10000); |
dudmuck | 18:9530d682fd9a | 2316 | } |
dudmuck | 18:9530d682fd9a | 2317 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2318 | printf("rssi:%ddBm\r\n", lora.get_current_rssi()); |
dudmuck | 18:9530d682fd9a | 2319 | else |
dudmuck | 18:9530d682fd9a | 2320 | printf("rssi:-%.1f\r\n", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 18:9530d682fd9a | 2321 | } |
dudmuck | 18:9530d682fd9a | 2322 | |
dudmuck | 21:b84a77dfb43c | 2323 | void cmd_rssi_polling(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2324 | { |
dudmuck | 21:b84a77dfb43c | 2325 | if ((pcbuf[idx] >= '0' && pcbuf[idx] <= '9') || pcbuf[idx] == '-') { |
dudmuck | 21:b84a77dfb43c | 2326 | sscanf(pcbuf+idx, "%d", &rssi_polling_thresh); |
dudmuck | 21:b84a77dfb43c | 2327 | } |
dudmuck | 21:b84a77dfb43c | 2328 | printf("rssi_polling_thresh:%d\r\n", rssi_polling_thresh); |
dudmuck | 21:b84a77dfb43c | 2329 | } |
dudmuck | 21:b84a77dfb43c | 2330 | |
dudmuck | 18:9530d682fd9a | 2331 | void cmd_lora_continuous_tx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2332 | { |
dudmuck | 18:9530d682fd9a | 2333 | /* TxContinuousMode same for sx1272 and sx1276 */ |
dudmuck | 18:9530d682fd9a | 2334 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2335 | lora.RegModemConfig2.sx1276bits.TxContinuousMode ^= 1; |
dudmuck | 18:9530d682fd9a | 2336 | radio.write_reg(REG_LR_MODEMCONFIG2, lora.RegModemConfig2.octet); |
dudmuck | 18:9530d682fd9a | 2337 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 13:c73caaee93a5 | 2338 | |
dudmuck | 18:9530d682fd9a | 2339 | lora_printTxContinuousMode(); |
dudmuck | 18:9530d682fd9a | 2340 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2341 | } |
dudmuck | 18:9530d682fd9a | 2342 | |
dudmuck | 18:9530d682fd9a | 2343 | void cmd_fsk_test_case(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2344 | { |
dudmuck | 18:9530d682fd9a | 2345 | if (pcbuf[idx] < '0' || pcbuf[idx] > '9') { |
dudmuck | 19:be8a8b0e7320 | 2346 | printf("%" PRIu32 "bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 19:be8a8b0e7320 | 2347 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 19:be8a8b0e7320 | 2348 | printf("afcbw:%" PRIu32 "Hz preambleLen:%" PRIu16 "\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 18:9530d682fd9a | 2349 | } else { |
dudmuck | 18:9530d682fd9a | 2350 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 2351 | per_tx_delay = 0.3; |
dudmuck | 18:9530d682fd9a | 2352 | |
dudmuck | 18:9530d682fd9a | 2353 | if (radio.read_reg(REG_FSK_SYNCVALUE1) == 0x55 && radio.read_reg(REG_FSK_SYNCVALUE2)) { |
dudmuck | 18:9530d682fd9a | 2354 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 18:9530d682fd9a | 2355 | fsk.RegSyncConfig.bits.SyncSize = 2; |
dudmuck | 18:9530d682fd9a | 2356 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 2357 | radio.write_reg(REG_FSK_SYNCVALUE3, 0x90); |
dudmuck | 18:9530d682fd9a | 2358 | radio.write_reg(REG_FSK_SYNCVALUE2, 0x4e); |
dudmuck | 18:9530d682fd9a | 2359 | radio.write_reg(REG_FSK_SYNCVALUE1, 0x63); |
dudmuck | 18:9530d682fd9a | 2360 | } |
dudmuck | 18:9530d682fd9a | 2361 | |
dudmuck | 18:9530d682fd9a | 2362 | fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); |
dudmuck | 18:9530d682fd9a | 2363 | fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 18:9530d682fd9a | 2364 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 2365 | |
dudmuck | 18:9530d682fd9a | 2366 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 18:9530d682fd9a | 2367 | fsk.RegRxConfig.bits.AfcAutoOn = 1; |
dudmuck | 18:9530d682fd9a | 2368 | fsk.RegRxConfig.bits.AgcAutoOn = 1; |
dudmuck | 20:b11592c9ba5f | 2369 | fsk.RegRxConfig.bits.RxTrigger = 7; // both |
dudmuck | 18:9530d682fd9a | 2370 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 2371 | |
dudmuck | 18:9530d682fd9a | 2372 | fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 18:9530d682fd9a | 2373 | fsk.RegPreambleDetect.bits.PreambleDetectorSize = 1; |
dudmuck | 18:9530d682fd9a | 2374 | fsk.RegPreambleDetect.bits.PreambleDetectorTol = 10; |
dudmuck | 18:9530d682fd9a | 2375 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 2376 | |
dudmuck | 18:9530d682fd9a | 2377 | switch (pcbuf[idx]) { |
dudmuck | 18:9530d682fd9a | 2378 | case '0': |
dudmuck | 18:9530d682fd9a | 2379 | fsk.set_bitrate(4800); |
dudmuck | 18:9530d682fd9a | 2380 | fsk.set_tx_fdev_hz(5005); |
dudmuck | 18:9530d682fd9a | 2381 | fsk.set_rx_dcc_bw_hz(10417, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2382 | fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2383 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2384 | break; |
dudmuck | 18:9530d682fd9a | 2385 | case '1': |
dudmuck | 18:9530d682fd9a | 2386 | fsk.set_bitrate(50000); |
dudmuck | 18:9530d682fd9a | 2387 | fsk.set_tx_fdev_hz(25000); |
dudmuck | 18:9530d682fd9a | 2388 | fsk.set_rx_dcc_bw_hz(62500, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2389 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2390 | radio.write_u16(REG_FSK_PREAMBLEMSB, 9); |
dudmuck | 18:9530d682fd9a | 2391 | break; |
dudmuck | 18:9530d682fd9a | 2392 | case '2': |
dudmuck | 18:9530d682fd9a | 2393 | fsk.set_bitrate(38400); |
dudmuck | 18:9530d682fd9a | 2394 | fsk.set_tx_fdev_hz(20020); |
dudmuck | 18:9530d682fd9a | 2395 | fsk.set_rx_dcc_bw_hz(50000, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2396 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2397 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2398 | break; |
dudmuck | 18:9530d682fd9a | 2399 | case '3': |
dudmuck | 18:9530d682fd9a | 2400 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2401 | fsk.set_tx_fdev_hz(20020); |
dudmuck | 18:9530d682fd9a | 2402 | fsk.set_rx_dcc_bw_hz(25000, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2403 | fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2404 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2405 | break; |
dudmuck | 18:9530d682fd9a | 2406 | case '4': |
dudmuck | 18:9530d682fd9a | 2407 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2408 | fsk.set_tx_fdev_hz(4028); |
dudmuck | 18:9530d682fd9a | 2409 | fsk.set_rx_dcc_bw_hz(7813, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2410 | fsk.set_rx_dcc_bw_hz(25000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2411 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2412 | break; |
dudmuck | 18:9530d682fd9a | 2413 | case '5': |
dudmuck | 18:9530d682fd9a | 2414 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2415 | fsk.set_tx_fdev_hz(4028); |
dudmuck | 18:9530d682fd9a | 2416 | fsk.set_rx_dcc_bw_hz(5208, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2417 | fsk.set_rx_dcc_bw_hz(10417, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2418 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 20:b11592c9ba5f | 2419 | break; |
dudmuck | 20:b11592c9ba5f | 2420 | case '6': |
dudmuck | 20:b11592c9ba5f | 2421 | fsk.set_bitrate(65536); |
dudmuck | 20:b11592c9ba5f | 2422 | fsk.set_tx_fdev_hz(16384); |
dudmuck | 20:b11592c9ba5f | 2423 | fsk.set_rx_dcc_bw_hz(62500, 0); // rxbw |
dudmuck | 20:b11592c9ba5f | 2424 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 21:b84a77dfb43c | 2425 | |
dudmuck | 21:b84a77dfb43c | 2426 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2427 | fsk.RegPktConfig1.bits.CrcOn = 0; |
dudmuck | 21:b84a77dfb43c | 2428 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2429 | |
dudmuck | 20:b11592c9ba5f | 2430 | radio.write_u16(REG_FSK_PREAMBLEMSB, 5); |
dudmuck | 20:b11592c9ba5f | 2431 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 20:b11592c9ba5f | 2432 | fsk.RegSyncConfig.bits.SyncSize = 2; |
dudmuck | 21:b84a77dfb43c | 2433 | fsk.RegSyncConfig.bits.SyncOn = 1; |
dudmuck | 20:b11592c9ba5f | 2434 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2435 | radio.write_reg(REG_FSK_SYNCVALUE1, 0x33); |
dudmuck | 20:b11592c9ba5f | 2436 | radio.write_reg(REG_FSK_SYNCVALUE2, 0xcb); |
dudmuck | 21:b84a77dfb43c | 2437 | radio.write_reg(REG_FSK_SYNCVALUE3, 0x82); |
dudmuck | 21:b84a77dfb43c | 2438 | |
dudmuck | 21:b84a77dfb43c | 2439 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 21:b84a77dfb43c | 2440 | radio.RegOpMode.bits.ModulationType = 0; // 0 = FSK |
dudmuck | 21:b84a77dfb43c | 2441 | radio.RegOpMode.bits.ModulationShaping = 2; // 2=BT0.5 |
dudmuck | 21:b84a77dfb43c | 2442 | radio.write_reg(REG_OPMODE, radio.RegOpMode.octet); |
dudmuck | 21:b84a77dfb43c | 2443 | |
dudmuck | 21:b84a77dfb43c | 2444 | fsk.RegAfcFei.octet = radio.read_reg(REG_FSK_AFCFEI); |
dudmuck | 21:b84a77dfb43c | 2445 | fsk.RegAfcFei.bits.AfcAutoClearOn = 0; |
dudmuck | 21:b84a77dfb43c | 2446 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 20:b11592c9ba5f | 2447 | |
dudmuck | 20:b11592c9ba5f | 2448 | fsk.RegRxConfig.bits.RxTrigger = 6; // preamble |
dudmuck | 20:b11592c9ba5f | 2449 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 20:b11592c9ba5f | 2450 | radio.RegDioMapping2.bits.Dio4Mapping = 3; |
dudmuck | 20:b11592c9ba5f | 2451 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; // dio4 to preambleDetect in RX |
dudmuck | 20:b11592c9ba5f | 2452 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 20:b11592c9ba5f | 2453 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to SyncAddress in RX |
dudmuck | 20:b11592c9ba5f | 2454 | radio.RegDioMapping1.bits.Dio1Mapping = 1; // to FifoEmpty |
dudmuck | 20:b11592c9ba5f | 2455 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 20:b11592c9ba5f | 2456 | break; |
dudmuck | 18:9530d682fd9a | 2457 | } // ...switch (pcbuf[idx]) |
dudmuck | 19:be8a8b0e7320 | 2458 | printf("%" PRIu32 "bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 19:be8a8b0e7320 | 2459 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 20:b11592c9ba5f | 2460 | printf("afcbw:%" PRIu32 "Hz preambleLen:%" PRIu16 "\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 20:b11592c9ba5f | 2461 | |
dudmuck | 20:b11592c9ba5f | 2462 | /* time between preamble occurring and syncAddress occuring |
dudmuck | 20:b11592c9ba5f | 2463 | * = bitrate in microseconds * 8 * (preamble bytes + sync bytes) |
dudmuck | 20:b11592c9ba5f | 2464 | */ |
dudmuck | 20:b11592c9ba5f | 2465 | preamble_to_sync_us = (1.0 / fsk.get_bitrate())*1e6 * 8 * (radio.read_u16(REG_FSK_PREAMBLEMSB)+1 + fsk.RegSyncConfig.bits.SyncSize+2); |
dudmuck | 20:b11592c9ba5f | 2466 | //printf("bitrate:%d, %f\r\n", fsk.get_bitrate(), 1.0 / fsk.get_bitrate()*1e6); |
dudmuck | 20:b11592c9ba5f | 2467 | printf("preamble_to_sync_us:%d\r\n", preamble_to_sync_us); |
dudmuck | 18:9530d682fd9a | 2468 | } |
dudmuck | 18:9530d682fd9a | 2469 | } |
dudmuck | 18:9530d682fd9a | 2470 | |
dudmuck | 20:b11592c9ba5f | 2471 | void cmd_restart_rx(uint8_t idx) |
dudmuck | 20:b11592c9ba5f | 2472 | { |
dudmuck | 20:b11592c9ba5f | 2473 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 20:b11592c9ba5f | 2474 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 20:b11592c9ba5f | 2475 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 20:b11592c9ba5f | 2476 | rx_start_timer.reset(); |
dudmuck | 20:b11592c9ba5f | 2477 | secs_rx_start = time(NULL); |
dudmuck | 20:b11592c9ba5f | 2478 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 0; |
dudmuck | 20:b11592c9ba5f | 2479 | printf("RestartRxWithoutPllLock\r\n"); |
dudmuck | 20:b11592c9ba5f | 2480 | } |
dudmuck | 20:b11592c9ba5f | 2481 | |
dudmuck | 18:9530d682fd9a | 2482 | void cmd_toggle_modem(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2483 | { |
dudmuck | 18:9530d682fd9a | 2484 | ook_test_en = false; |
dudmuck | 18:9530d682fd9a | 2485 | poll_irq_en = false; |
dudmuck | 18:9530d682fd9a | 2486 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2487 | fsk.enable(false); |
dudmuck | 18:9530d682fd9a | 2488 | else |
dudmuck | 18:9530d682fd9a | 2489 | lora.enable(); |
dudmuck | 18:9530d682fd9a | 2490 | |
dudmuck | 18:9530d682fd9a | 2491 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 18:9530d682fd9a | 2492 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2493 | printf("LoRa\r\n"); |
dudmuck | 18:9530d682fd9a | 2494 | else |
dudmuck | 18:9530d682fd9a | 2495 | printf("FSK\r\n"); |
dudmuck | 18:9530d682fd9a | 2496 | } |
dudmuck | 18:9530d682fd9a | 2497 | |
dudmuck | 18:9530d682fd9a | 2498 | void cmd_empty_fifo(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2499 | { |
dudmuck | 18:9530d682fd9a | 2500 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 18:9530d682fd9a | 2501 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 2502 | while (!RegIrqFlags2.bits.FifoEmpty) { |
dudmuck | 18:9530d682fd9a | 2503 | if (pc.readable()) |
dudmuck | 18:9530d682fd9a | 2504 | break; |
dudmuck | 18:9530d682fd9a | 2505 | printf("%02x\r\n", radio.read_reg(REG_FIFO)); |
dudmuck | 18:9530d682fd9a | 2506 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 2507 | } |
dudmuck | 18:9530d682fd9a | 2508 | } |
dudmuck | 18:9530d682fd9a | 2509 | |
dudmuck | 18:9530d682fd9a | 2510 | void cmd_print_status(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2511 | { |
dudmuck | 18:9530d682fd9a | 2512 | if (radio.type == SX1276) { |
Wayne Roberts |
24:9ba45aa15b53 | 2513 | #if defined(TARGET_MTS_MDOT_F411RE) |
dudmuck | 18:9530d682fd9a | 2514 | printf("\r\nSX1276 "); |
dudmuck | 18:9530d682fd9a | 2515 | #else |
dudmuck | 18:9530d682fd9a | 2516 | if (shield_type == SHIELD_TYPE_LAS) |
dudmuck | 18:9530d682fd9a | 2517 | printf("\r\nSX1276LAS "); |
dudmuck | 18:9530d682fd9a | 2518 | if (shield_type == SHIELD_TYPE_MAS) |
dudmuck | 18:9530d682fd9a | 2519 | printf("\r\nSX1276MAS "); |
dudmuck | 18:9530d682fd9a | 2520 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 18:9530d682fd9a | 2521 | } else if (radio.type == SX1272) |
dudmuck | 18:9530d682fd9a | 2522 | printf("\r\nSX1272 "); |
dudmuck | 18:9530d682fd9a | 2523 | |
dudmuck | 18:9530d682fd9a | 2524 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 18:9530d682fd9a | 2525 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2526 | lora_print_status(); |
dudmuck | 18:9530d682fd9a | 2527 | else |
dudmuck | 18:9530d682fd9a | 2528 | fsk_print_status(); |
dudmuck | 18:9530d682fd9a | 2529 | common_print_status(); |
dudmuck | 18:9530d682fd9a | 2530 | } |
dudmuck | 18:9530d682fd9a | 2531 | |
dudmuck | 18:9530d682fd9a | 2532 | void cmd_hop_period(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2533 | { |
dudmuck | 18:9530d682fd9a | 2534 | int i; |
dudmuck | 18:9530d682fd9a | 2535 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2536 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2537 | lora.RegHopPeriod = i; |
dudmuck | 18:9530d682fd9a | 2538 | radio.write_reg(REG_LR_HOPPERIOD, lora.RegHopPeriod); |
dudmuck | 18:9530d682fd9a | 2539 | if (radio.RegDioMapping1.bits.Dio1Mapping != 1) { |
dudmuck | 18:9530d682fd9a | 2540 | radio.RegDioMapping1.bits.Dio1Mapping = 1; |
dudmuck | 18:9530d682fd9a | 2541 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 2542 | } |
dudmuck | 18:9530d682fd9a | 2543 | } |
dudmuck | 18:9530d682fd9a | 2544 | lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); |
dudmuck | 18:9530d682fd9a | 2545 | printf("HopPeriod:0x%02x\r\n", lora.RegHopPeriod); |
dudmuck | 18:9530d682fd9a | 2546 | } |
dudmuck | 18:9530d682fd9a | 2547 | |
dudmuck | 18:9530d682fd9a | 2548 | void cmd_lora_ppg(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2549 | { |
dudmuck | 18:9530d682fd9a | 2550 | int i; |
dudmuck | 18:9530d682fd9a | 2551 | if (pcbuf[idx] != 0) { |
dudmuck | 18:9530d682fd9a | 2552 | sscanf(pcbuf+idx, "%x", &i); |
dudmuck | 18:9530d682fd9a | 2553 | radio.write_reg(REG_LR_SYNC_BYTE, i); |
dudmuck | 18:9530d682fd9a | 2554 | } |
dudmuck | 18:9530d682fd9a | 2555 | printf("lora sync:0x%02x\r\n", radio.read_reg(REG_LR_SYNC_BYTE)); |
dudmuck | 18:9530d682fd9a | 2556 | } |
dudmuck | 18:9530d682fd9a | 2557 | |
dudmuck | 18:9530d682fd9a | 2558 | void cmd_rssi_offset(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2559 | { |
dudmuck | 18:9530d682fd9a | 2560 | int i; |
dudmuck | 18:9530d682fd9a | 2561 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2562 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2563 | fsk.RegRssiConfig.bits.RssiOffset = i; |
dudmuck | 18:9530d682fd9a | 2564 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 18:9530d682fd9a | 2565 | } |
dudmuck | 18:9530d682fd9a | 2566 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 2567 | printf("RssiOffset:%d\r\n", fsk.RegRssiConfig.bits.RssiOffset); |
dudmuck | 18:9530d682fd9a | 2568 | } |
dudmuck | 18:9530d682fd9a | 2569 | |
dudmuck | 18:9530d682fd9a | 2570 | void cmd_rssi_smoothing(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2571 | { |
dudmuck | 18:9530d682fd9a | 2572 | int i; |
dudmuck | 18:9530d682fd9a | 2573 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2574 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2575 | fsk.RegRssiConfig.bits.RssiSmoothing = i; |
dudmuck | 18:9530d682fd9a | 2576 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 18:9530d682fd9a | 2577 | } |
dudmuck | 18:9530d682fd9a | 2578 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 2579 | printf("RssiSmoothing:%d\r\n", fsk.RegRssiConfig.bits.RssiSmoothing); |
dudmuck | 18:9530d682fd9a | 2580 | } |
dudmuck | 18:9530d682fd9a | 2581 | |
dudmuck | 18:9530d682fd9a | 2582 | void cmd_rssi_threshold(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2583 | { |
dudmuck | 19:be8a8b0e7320 | 2584 | if ((pcbuf[idx] >= '0' && pcbuf[idx] <= '9') || pcbuf[idx] == '-') { |
dudmuck | 18:9530d682fd9a | 2585 | float dbm; |
dudmuck | 18:9530d682fd9a | 2586 | sscanf(pcbuf+idx, "%f", &dbm); |
dudmuck | 18:9530d682fd9a | 2587 | dbm *= (float)2.0; |
dudmuck | 18:9530d682fd9a | 2588 | fsk.RegRssiThresh = (int)fabs(dbm); |
dudmuck | 18:9530d682fd9a | 2589 | radio.write_reg(REG_FSK_RSSITHRESH, fsk.RegRssiThresh); |
dudmuck | 18:9530d682fd9a | 2590 | } |
dudmuck | 18:9530d682fd9a | 2591 | fsk.RegRssiThresh = radio.read_reg(REG_FSK_RSSITHRESH); |
dudmuck | 18:9530d682fd9a | 2592 | printf("rssiThreshold:-%.1f\r\n", fsk.RegRssiThresh / 2.0); |
dudmuck | 18:9530d682fd9a | 2593 | } |
dudmuck | 18:9530d682fd9a | 2594 | |
dudmuck | 18:9530d682fd9a | 2595 | void cmd_rx_trigger(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2596 | { |
dudmuck | 18:9530d682fd9a | 2597 | printf("RxTrigger:"); |
dudmuck | 18:9530d682fd9a | 2598 | switch (fsk.RegRxConfig.bits.RxTrigger) { |
dudmuck | 18:9530d682fd9a | 2599 | case 0: fsk.RegRxConfig.bits.RxTrigger = 1; |
dudmuck | 18:9530d682fd9a | 2600 | printf("rssi\r\n"); |
dudmuck | 18:9530d682fd9a | 2601 | break; |
dudmuck | 18:9530d682fd9a | 2602 | case 1: fsk.RegRxConfig.bits.RxTrigger = 6; |
dudmuck | 18:9530d682fd9a | 2603 | printf("preamble\r\n"); |
dudmuck | 18:9530d682fd9a | 2604 | break; |
dudmuck | 18:9530d682fd9a | 2605 | case 6: fsk.RegRxConfig.bits.RxTrigger = 7; |
dudmuck | 18:9530d682fd9a | 2606 | printf("both\r\n"); |
dudmuck | 18:9530d682fd9a | 2607 | break; |
dudmuck | 18:9530d682fd9a | 2608 | case 7: fsk.RegRxConfig.bits.RxTrigger = 0; |
dudmuck | 18:9530d682fd9a | 2609 | printf("none\r\n"); |
dudmuck | 18:9530d682fd9a | 2610 | break; |
dudmuck | 18:9530d682fd9a | 2611 | default: fsk.RegRxConfig.bits.RxTrigger = 0; |
dudmuck | 18:9530d682fd9a | 2612 | printf("none\r\n"); |
dudmuck | 18:9530d682fd9a | 2613 | break; |
dudmuck | 18:9530d682fd9a | 2614 | } |
dudmuck | 18:9530d682fd9a | 2615 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 2616 | } |
dudmuck | 18:9530d682fd9a | 2617 | |
dudmuck | 18:9530d682fd9a | 2618 | void cmd_cadper(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2619 | { |
dudmuck | 18:9530d682fd9a | 2620 | set_per_en(true); |
dudmuck | 18:9530d682fd9a | 2621 | |
dudmuck | 18:9530d682fd9a | 2622 | PacketNormalCnt = 0; |
dudmuck | 20:b11592c9ba5f | 2623 | PacketRxSequencePrev = 0; // transmitter side PacketTxCnt is 1 at first TX |
dudmuck | 18:9530d682fd9a | 2624 | PacketPerKoCnt = 0; |
dudmuck | 18:9530d682fd9a | 2625 | PacketPerOkCnt = 0; |
dudmuck | 18:9530d682fd9a | 2626 | |
dudmuck | 18:9530d682fd9a | 2627 | cadper_enable = true; |
dudmuck | 18:9530d682fd9a | 2628 | |
dudmuck | 18:9530d682fd9a | 2629 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2630 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2631 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2632 | |
dudmuck | 18:9530d682fd9a | 2633 | /* start first CAD */ |
dudmuck | 18:9530d682fd9a | 2634 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2635 | num_cads = 0; |
dudmuck | 18:9530d682fd9a | 2636 | } |
dudmuck | 18:9530d682fd9a | 2637 | |
dudmuck | 18:9530d682fd9a | 2638 | #if 0 |
dudmuck | 18:9530d682fd9a | 2639 | void cmd_cadrx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2640 | { |
dudmuck | 18:9530d682fd9a | 2641 | int n_tries = 1; |
dudmuck | 18:9530d682fd9a | 2642 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2643 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2644 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2645 | |
dudmuck | 18:9530d682fd9a | 2646 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2647 | sscanf(pcbuf+idx, "%d", &n_tries); |
dudmuck | 18:9530d682fd9a | 2648 | } |
dudmuck | 18:9530d682fd9a | 2649 | |
dudmuck | 18:9530d682fd9a | 2650 | while (n_tries > 0) { |
dudmuck | 18:9530d682fd9a | 2651 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2652 | |
dudmuck | 18:9530d682fd9a | 2653 | do { |
dudmuck | 18:9530d682fd9a | 2654 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2655 | } while (!lora.RegIrqFlags.bits.CadDetected && !lora.RegIrqFlags.bits.CadDone); |
dudmuck | 18:9530d682fd9a | 2656 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 2657 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 2658 | n_tries = 1; // end |
dudmuck | 18:9530d682fd9a | 2659 | printf("CadDetected "); |
dudmuck | 18:9530d682fd9a | 2660 | } |
dudmuck | 18:9530d682fd9a | 2661 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 2662 | printf("CadDone "); |
dudmuck | 18:9530d682fd9a | 2663 | } |
dudmuck | 18:9530d682fd9a | 2664 | |
dudmuck | 18:9530d682fd9a | 2665 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2666 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2667 | n_tries--; |
dudmuck | 18:9530d682fd9a | 2668 | } |
dudmuck | 18:9530d682fd9a | 2669 | } |
dudmuck | 18:9530d682fd9a | 2670 | #endif /* #if 0 */ |
dudmuck | 18:9530d682fd9a | 2671 | |
dudmuck | 18:9530d682fd9a | 2672 | void cmd_cad(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2673 | { |
dudmuck | 18:9530d682fd9a | 2674 | int n_tries = 1; |
dudmuck | 18:9530d682fd9a | 2675 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2676 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2677 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2678 | |
dudmuck | 18:9530d682fd9a | 2679 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2680 | sscanf(pcbuf+idx, "%d", &n_tries); |
dudmuck | 18:9530d682fd9a | 2681 | } |
dudmuck | 18:9530d682fd9a | 2682 | |
dudmuck | 18:9530d682fd9a | 2683 | while (n_tries > 0) { |
dudmuck | 18:9530d682fd9a | 2684 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2685 | |
dudmuck | 18:9530d682fd9a | 2686 | do { |
dudmuck | 18:9530d682fd9a | 2687 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2688 | } while (!lora.RegIrqFlags.bits.CadDetected && !lora.RegIrqFlags.bits.CadDone); |
dudmuck | 18:9530d682fd9a | 2689 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 2690 | n_tries = 1; // end |
dudmuck | 18:9530d682fd9a | 2691 | printf("CadDetected "); |
dudmuck | 18:9530d682fd9a | 2692 | } |
dudmuck | 18:9530d682fd9a | 2693 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 2694 | if (n_tries == 1) // print on last try |
dudmuck | 18:9530d682fd9a | 2695 | printf("CadDone "); |
dudmuck | 18:9530d682fd9a | 2696 | } |
dudmuck | 18:9530d682fd9a | 2697 | |
dudmuck | 18:9530d682fd9a | 2698 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2699 | n_tries--; |
dudmuck | 18:9530d682fd9a | 2700 | } |
dudmuck | 18:9530d682fd9a | 2701 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2702 | } |
dudmuck | 18:9530d682fd9a | 2703 | |
dudmuck | 18:9530d682fd9a | 2704 | void cmd_rx_timeout(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2705 | { |
dudmuck | 18:9530d682fd9a | 2706 | int symb_timeout; |
dudmuck | 18:9530d682fd9a | 2707 | uint16_t reg_u16 = radio.read_u16(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2708 | |
dudmuck | 18:9530d682fd9a | 2709 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2710 | sscanf(pcbuf+idx, "%d", &symb_timeout); |
dudmuck | 18:9530d682fd9a | 2711 | reg_u16 &= 0xfc00; |
dudmuck | 18:9530d682fd9a | 2712 | reg_u16 |= symb_timeout; |
dudmuck | 22:2005df80c8a8 | 2713 | radio.write_u16(REG_LR_MODEMCONFIG2, reg_u16); |
dudmuck | 18:9530d682fd9a | 2714 | } |
dudmuck | 18:9530d682fd9a | 2715 | reg_u16 = radio.read_u16(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2716 | printf("SymbTimeout:%d\r\n", reg_u16 & 0x3ff); |
dudmuck | 18:9530d682fd9a | 2717 | } |
dudmuck | 18:9530d682fd9a | 2718 | |
dudmuck | 18:9530d682fd9a | 2719 | void cmd_rx_single(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2720 | { |
dudmuck | 18:9530d682fd9a | 2721 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 2722 | } |
dudmuck | 18:9530d682fd9a | 2723 | |
dudmuck | 21:b84a77dfb43c | 2724 | void preamble_without_sync() |
dudmuck | 21:b84a77dfb43c | 2725 | { |
dudmuck | 21:b84a77dfb43c | 2726 | printf("preamble_without_sync Afc:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); |
dudmuck | 21:b84a77dfb43c | 2727 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 21:b84a77dfb43c | 2728 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2729 | } |
dudmuck | 21:b84a77dfb43c | 2730 | |
dudmuck | 21:b84a77dfb43c | 2731 | Timeout pd_timeout; |
dudmuck | 21:b84a77dfb43c | 2732 | Timeout sync_timeout; |
dudmuck | 21:b84a77dfb43c | 2733 | void preamble_detect_isr() |
dudmuck | 21:b84a77dfb43c | 2734 | { |
dudmuck | 21:b84a77dfb43c | 2735 | // only used between frames, on background noise |
dudmuck | 21:b84a77dfb43c | 2736 | pd_timeout.attach_us(&preamble_without_sync, 1500); // 122us per byte |
dudmuck | 21:b84a77dfb43c | 2737 | } |
dudmuck | 21:b84a77dfb43c | 2738 | |
dudmuck | 18:9530d682fd9a | 2739 | void cmd_rx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2740 | { |
dudmuck | 18:9530d682fd9a | 2741 | set_per_en(false); |
dudmuck | 18:9530d682fd9a | 2742 | |
dudmuck | 18:9530d682fd9a | 2743 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2744 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 18:9530d682fd9a | 2745 | else { |
dudmuck | 20:b11592c9ba5f | 2746 | if (poll_irq_en) { |
dudmuck | 20:b11592c9ba5f | 2747 | fsk_RegIrqFlags2_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 2748 | fsk_RegIrqFlags1_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 2749 | } |
dudmuck | 20:b11592c9ba5f | 2750 | |
dudmuck | 20:b11592c9ba5f | 2751 | rx_start_timer.start(); |
dudmuck | 20:b11592c9ba5f | 2752 | secs_rx_start = time(NULL); |
dudmuck | 18:9530d682fd9a | 2753 | fsk.start_rx(); |
dudmuck | 18:9530d682fd9a | 2754 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to syncadrs |
dudmuck | 18:9530d682fd9a | 2755 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 2756 | if (radio.HF) { |
dudmuck | 18:9530d682fd9a | 2757 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 2758 | fsk.RegRssiConfig.bits.RssiOffset = FSK_RSSI_OFFSET; |
dudmuck | 18:9530d682fd9a | 2759 | fsk.RegRssiConfig.bits.RssiSmoothing = FSK_RSSI_SMOOTHING; |
dudmuck | 18:9530d682fd9a | 2760 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2761 | } |
dudmuck | 21:b84a77dfb43c | 2762 | |
dudmuck | 21:b84a77dfb43c | 2763 | // sync shadow regsiters |
dudmuck | 21:b84a77dfb43c | 2764 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 2765 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 18:9530d682fd9a | 2766 | } |
dudmuck | 18:9530d682fd9a | 2767 | } |
dudmuck | 18:9530d682fd9a | 2768 | |
dudmuck | 18:9530d682fd9a | 2769 | void cmd_radio_reg_read(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2770 | { |
dudmuck | 18:9530d682fd9a | 2771 | int i; |
dudmuck | 18:9530d682fd9a | 2772 | sscanf(pcbuf+idx, "%x", &i); |
dudmuck | 18:9530d682fd9a | 2773 | printf("%02x: %02x\r\n", i, radio.read_reg(i)); |
dudmuck | 18:9530d682fd9a | 2774 | } |
dudmuck | 18:9530d682fd9a | 2775 | |
dudmuck | 18:9530d682fd9a | 2776 | void cmd_radio_reg_write(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2777 | { |
dudmuck | 18:9530d682fd9a | 2778 | int i, n; |
dudmuck | 18:9530d682fd9a | 2779 | sscanf(pcbuf+idx, "%x %x", &i, &n); |
dudmuck | 18:9530d682fd9a | 2780 | radio.write_reg(i, n); |
dudmuck | 18:9530d682fd9a | 2781 | printf("%02x: %02x\r\n", i, radio.read_reg(i)); |
dudmuck | 18:9530d682fd9a | 2782 | } |
dudmuck | 18:9530d682fd9a | 2783 | |
dudmuck | 18:9530d682fd9a | 2784 | void cmd_mod_shaping(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2785 | { |
dudmuck | 18:9530d682fd9a | 2786 | uint8_t s = fsk.get_modulation_shaping(); |
dudmuck | 18:9530d682fd9a | 2787 | |
dudmuck | 18:9530d682fd9a | 2788 | if (s == 3) |
dudmuck | 18:9530d682fd9a | 2789 | s = 0; |
dudmuck | 18:9530d682fd9a | 2790 | else |
dudmuck | 18:9530d682fd9a | 2791 | s++; |
dudmuck | 18:9530d682fd9a | 2792 | |
dudmuck | 18:9530d682fd9a | 2793 | fsk.set_modulation_shaping(s); |
dudmuck | 18:9530d682fd9a | 2794 | |
dudmuck | 18:9530d682fd9a | 2795 | if (radio.RegOpMode.bits.ModulationType == 0) { |
dudmuck | 18:9530d682fd9a | 2796 | printf("FSK "); |
dudmuck | 18:9530d682fd9a | 2797 | switch (s) { |
dudmuck | 18:9530d682fd9a | 2798 | case 0: printf("off"); break; |
dudmuck | 18:9530d682fd9a | 2799 | case 1: printf("BT1.0 "); break; |
dudmuck | 18:9530d682fd9a | 2800 | case 2: printf("BT0.5 "); break; |
dudmuck | 18:9530d682fd9a | 2801 | case 3: printf("BT0.3 "); break; |
dudmuck | 18:9530d682fd9a | 2802 | } |
dudmuck | 18:9530d682fd9a | 2803 | } else if (radio.RegOpMode.bits.ModulationType == 1) { |
dudmuck | 18:9530d682fd9a | 2804 | printf("OOK "); |
dudmuck | 18:9530d682fd9a | 2805 | switch (s) { |
dudmuck | 18:9530d682fd9a | 2806 | case 0: printf("off"); break; |
dudmuck | 18:9530d682fd9a | 2807 | case 1: printf("Fcutoff=bitrate"); break; |
dudmuck | 18:9530d682fd9a | 2808 | case 2: printf("Fcutoff=2*bitrate"); break; |
dudmuck | 18:9530d682fd9a | 2809 | case 3: printf("?"); break; |
dudmuck | 18:9530d682fd9a | 2810 | } |
dudmuck | 18:9530d682fd9a | 2811 | } |
dudmuck | 18:9530d682fd9a | 2812 | |
dudmuck | 18:9530d682fd9a | 2813 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2814 | } |
dudmuck | 18:9530d682fd9a | 2815 | |
dudmuck | 18:9530d682fd9a | 2816 | void cmd_MapPreambleDetect(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2817 | { |
dudmuck | 18:9530d682fd9a | 2818 | radio.RegDioMapping2.bits.MapPreambleDetect ^= 1; |
dudmuck | 18:9530d682fd9a | 2819 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 18:9530d682fd9a | 2820 | printf("MapPreambleDetect:"); |
dudmuck | 18:9530d682fd9a | 2821 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 18:9530d682fd9a | 2822 | printf("preamble\r\n"); |
dudmuck | 18:9530d682fd9a | 2823 | else |
dudmuck | 18:9530d682fd9a | 2824 | printf("rssi\r\n"); |
dudmuck | 18:9530d682fd9a | 2825 | } |
dudmuck | 18:9530d682fd9a | 2826 | |
dudmuck | 18:9530d682fd9a | 2827 | void cmd_bgr(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2828 | { |
dudmuck | 18:9530d682fd9a | 2829 | RegPdsTrim1_t pds_trim; |
dudmuck | 18:9530d682fd9a | 2830 | uint8_t adr; |
dudmuck | 18:9530d682fd9a | 2831 | if (radio.type == SX1276) |
dudmuck | 18:9530d682fd9a | 2832 | adr = REG_PDSTRIM1_SX1276; |
dudmuck | 18:9530d682fd9a | 2833 | else |
dudmuck | 18:9530d682fd9a | 2834 | adr = REG_PDSTRIM1_SX1272; |
dudmuck | 18:9530d682fd9a | 2835 | |
dudmuck | 18:9530d682fd9a | 2836 | pds_trim.octet = radio.read_reg(adr); |
dudmuck | 18:9530d682fd9a | 2837 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2838 | int i; |
dudmuck | 18:9530d682fd9a | 2839 | sscanf(&pcbuf[idx], "%d", &i); |
dudmuck | 18:9530d682fd9a | 2840 | pds_trim.bits.prog_txdac = i; |
dudmuck | 18:9530d682fd9a | 2841 | } |
dudmuck | 18:9530d682fd9a | 2842 | radio.write_reg(adr, pds_trim.octet); |
dudmuck | 18:9530d682fd9a | 2843 | printf("prog_txdac:%.1fuA\r\n", 2.5 + (pds_trim.bits.prog_txdac * 0.625)); |
dudmuck | 18:9530d682fd9a | 2844 | /* increase OCP threshold to allow more power */ |
dudmuck | 18:9530d682fd9a | 2845 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 18:9530d682fd9a | 2846 | if (radio.RegOcp.bits.OcpTrim < 16) { |
dudmuck | 18:9530d682fd9a | 2847 | radio.RegOcp.bits.OcpTrim = 16; |
dudmuck | 18:9530d682fd9a | 2848 | radio.write_reg(REG_OCP, radio.RegOcp.octet); |
dudmuck | 18:9530d682fd9a | 2849 | } |
dudmuck | 18:9530d682fd9a | 2850 | } |
dudmuck | 18:9530d682fd9a | 2851 | |
dudmuck | 18:9530d682fd9a | 2852 | void cmd_ook(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2853 | { |
dudmuck | 18:9530d682fd9a | 2854 | fsk.set_bitrate(32768); |
dudmuck | 18:9530d682fd9a | 2855 | radio.write_u16(REG_FSK_PREAMBLEMSB, 0); // zero preamble length |
dudmuck | 18:9530d682fd9a | 2856 | radio.RegOpMode.bits.ModulationType = 1; // to ook mode |
dudmuck | 18:9530d682fd9a | 2857 | radio.write_reg(REG_OPMODE, radio.RegOpMode.octet); |
dudmuck | 18:9530d682fd9a | 2858 | fsk.RegSyncConfig.bits.SyncOn = 0; |
dudmuck | 18:9530d682fd9a | 2859 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 2860 | ook_test_en = true; |
dudmuck | 18:9530d682fd9a | 2861 | printf("OOK\r\n"); |
dudmuck | 18:9530d682fd9a | 2862 | } |
dudmuck | 18:9530d682fd9a | 2863 | |
dudmuck | 18:9530d682fd9a | 2864 | void cmd_ocp(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2865 | { |
dudmuck | 18:9530d682fd9a | 2866 | int i; |
dudmuck | 18:9530d682fd9a | 2867 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2868 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2869 | if (i < 130) |
dudmuck | 18:9530d682fd9a | 2870 | radio.RegOcp.bits.OcpTrim = (i - 45) / 5; |
dudmuck | 18:9530d682fd9a | 2871 | else |
dudmuck | 18:9530d682fd9a | 2872 | radio.RegOcp.bits.OcpTrim = (i + 30) / 10; |
dudmuck | 18:9530d682fd9a | 2873 | radio.write_reg(REG_OCP, radio.RegOcp.octet); |
dudmuck | 18:9530d682fd9a | 2874 | } |
dudmuck | 18:9530d682fd9a | 2875 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 18:9530d682fd9a | 2876 | if (radio.RegOcp.bits.OcpTrim < 16) |
dudmuck | 18:9530d682fd9a | 2877 | i = 45 + (5 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 18:9530d682fd9a | 2878 | else if (radio.RegOcp.bits.OcpTrim < 28) |
dudmuck | 18:9530d682fd9a | 2879 | i = (10 * radio.RegOcp.bits.OcpTrim) - 30; |
dudmuck | 18:9530d682fd9a | 2880 | else |
dudmuck | 18:9530d682fd9a | 2881 | i = 240; |
dudmuck | 18:9530d682fd9a | 2882 | printf("Ocp: %dmA\r\n", i); |
dudmuck | 18:9530d682fd9a | 2883 | } |
dudmuck | 18:9530d682fd9a | 2884 | |
dudmuck | 18:9530d682fd9a | 2885 | void cmd_op(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2886 | { |
dudmuck | 18:9530d682fd9a | 2887 | int i, dbm; |
dudmuck | 18:9530d682fd9a | 2888 | RegPdsTrim1_t pds_trim; |
dudmuck | 18:9530d682fd9a | 2889 | uint8_t adr; |
dudmuck | 18:9530d682fd9a | 2890 | if (radio.type == SX1276) |
dudmuck | 18:9530d682fd9a | 2891 | adr = REG_PDSTRIM1_SX1276; |
dudmuck | 18:9530d682fd9a | 2892 | else |
dudmuck | 18:9530d682fd9a | 2893 | adr = REG_PDSTRIM1_SX1272; |
dudmuck | 18:9530d682fd9a | 2894 | |
dudmuck | 18:9530d682fd9a | 2895 | pds_trim.octet = radio.read_reg(adr); |
dudmuck | 18:9530d682fd9a | 2896 | |
dudmuck | 19:be8a8b0e7320 | 2897 | if (pcbuf[idx] >= '0' && (pcbuf[idx] <= '9' || pcbuf[idx] == '-')) { |
dudmuck | 18:9530d682fd9a | 2898 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2899 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 18:9530d682fd9a | 2900 | /* PABOOST used: +2dbm to +17, or +20 */ |
dudmuck | 18:9530d682fd9a | 2901 | if (i == 20) { |
dudmuck | 18:9530d682fd9a | 2902 | printf("+20dBm PADAC bias\r\n"); |
dudmuck | 18:9530d682fd9a | 2903 | i -= 3; |
dudmuck | 18:9530d682fd9a | 2904 | pds_trim.bits.prog_txdac = 7; |
dudmuck | 21:b84a77dfb43c | 2905 | radio.write_reg(adr, pds_trim.octet); |
dudmuck | 13:c73caaee93a5 | 2906 | } |
dudmuck | 18:9530d682fd9a | 2907 | if (i > 1) |
dudmuck | 18:9530d682fd9a | 2908 | radio.RegPaConfig.bits.OutputPower = i - 2; |
dudmuck | 18:9530d682fd9a | 2909 | } else { |
dudmuck | 18:9530d682fd9a | 2910 | /* RFO used: -1 to +14dbm */ |
dudmuck | 18:9530d682fd9a | 2911 | if (i < 15) |
dudmuck | 18:9530d682fd9a | 2912 | radio.RegPaConfig.bits.OutputPower = i + 1; |
dudmuck | 18:9530d682fd9a | 2913 | } |
dudmuck | 18:9530d682fd9a | 2914 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 18:9530d682fd9a | 2915 | } |
dudmuck | 18:9530d682fd9a | 2916 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 18:9530d682fd9a | 2917 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 18:9530d682fd9a | 2918 | printf("PA_BOOST "); |
dudmuck | 18:9530d682fd9a | 2919 | dbm = radio.RegPaConfig.bits.OutputPower + pds_trim.bits.prog_txdac - 2; |
dudmuck | 18:9530d682fd9a | 2920 | } else { |
dudmuck | 18:9530d682fd9a | 2921 | printf("RFO "); |
dudmuck | 18:9530d682fd9a | 2922 | dbm = radio.RegPaConfig.bits.OutputPower - 1; |
dudmuck | 18:9530d682fd9a | 2923 | } |
dudmuck | 18:9530d682fd9a | 2924 | printf("OutputPower:%ddBm\r\n", dbm); |
dudmuck | 18:9530d682fd9a | 2925 | } |
dudmuck | 18:9530d682fd9a | 2926 | |
dudmuck | 18:9530d682fd9a | 2927 | |
dudmuck | 18:9530d682fd9a | 2928 | |
dudmuck | 18:9530d682fd9a | 2929 | void cmd_fsk_agcauto(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2930 | { |
dudmuck | 18:9530d682fd9a | 2931 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 18:9530d682fd9a | 2932 | fsk.RegRxConfig.bits.AgcAutoOn ^= 1; |
dudmuck | 18:9530d682fd9a | 2933 | printf("AgcAuto:"); |
dudmuck | 18:9530d682fd9a | 2934 | if (fsk.RegRxConfig.bits.AgcAutoOn) |
dudmuck | 18:9530d682fd9a | 2935 | printf("On\r\n"); |
dudmuck | 18:9530d682fd9a | 2936 | else |
dudmuck | 18:9530d682fd9a | 2937 | printf("OFF\r\n"); |
dudmuck | 18:9530d682fd9a | 2938 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 2939 | } |
dudmuck | 18:9530d682fd9a | 2940 | |
dudmuck | 18:9530d682fd9a | 2941 | void cmd_fs |