UART console application for testing SX1272/SX1276
This is a UART console test application for using SX127x library driver for SX1272/SX1276 radio transceivers. Serial console is provided at 57600bps. Refer to Serial Communication with a PC for information about using the serial port with your PC.
Using this command interface, you can exercise the functionality of radio chip without needing specialized software application for your PC.
Commands which can be used include ?
to list available commands, or .
to query status from radio chip, for example.
The serial console allows you to configure the radio chip, such as setting spreading factor, bandwidth, operating frequency, etc.
A simple chat application is provided to try communications between two boards. The SX127x library object is instantiated with pin assignments generic arduino headers, but can be easily reassigned for any mbed board.
The same driver library can operate for both SX1272 and SX1276. Upon starting, the driver auto-detects whether SX1272 or SX1276 transceiver chip is connected by attempting to change the LowFrequencyModeOn
bit in RegOpMode
register. If this bit can be changed, then the radio device is SX1276. This bit is not implemented in SX1272. A few of the radio driver functions select behavior based on this detection. The differences between these two devices is small, from a software perspective.
Using with SX1276MB1xAS Shield
This component plugs into any board with arduino uno headers.
There are two different version of this shield. European version (MAS), and North American (LAS). The LAS shield uses PA_BOOST transmit pin to permit +20dBm power. The MAS version uses RFO transmit pin in Europe. This software reads RF switch pin (A4 pin) pulling resistor to determine which type of shield is installed.
Using with your own production board
This software is useful for validating RF performance your own LoRa board design, because only two external pins needs to be provided to PC (UART TX/RX). You can select an mbed platform which matches the CPU on your own board. If the memory size doesnt match exactly, you can export the program to an offline toolchain and edit the target type or linker file there.
Transmitter Test Guidelines
FSK mode is used for transmitter testing, because an unmodulated carrier can be sent, permitting easy measurement of TX power and frequency error.
commands used for transmitter testing:
frf915.0
change to your desired RF center frequency (in this case 915MHz)L
to toggle the radio chip into FSK mode.fdev0
to configure TX frequency deviation to zero, to put the transmitted carrier on the center frequency.pas
to select which TX pin is connected to antenna matching (RFO vs PA_BOOST).op<dBm>
to configure TX power.- If you desire to test higher power PA_BOOST, use
ocp<mA>
w 01 03
put radio chip into transmit mode (skips writing to FIFO). This will cause radio to transmit preamble, because the FIFO is empty in TX mode. Since Fdev is zero, an unmodulated carrier is sent.- Spectrum analyzer can now be used to to observe TX power, harmonics, power consumption, or frequency error.
stby
to end transmission, or useh
to reset radio chip to default condition.- Use period
.
command at any time to review current radio configuration.
LoRa transmitter testing
- use
L
command to toggle radio into LoRa, if necessary. - Normally the
tx
command is used to manually send single packets. txc
will toggleTxContinuousMode
in LoRa modem to send continuous modulated transmission.- Useful for checking adjacent channel power.
- enter
txc
again to end transmission.
Receiver Test Guidelines
FSK mode is used for receiver sensitivity testing, allowing the use of a BERT signal generator (such as R/S SMIQ03B). Using this method provides real-time indication of receiver sensitivity, useful for tuning and impedance matching. The radio chip outputs DCLK and DATA digital signals which are connected back to BERT signal generator.
commands used for receiver testing:
L
to toggle the radio chip into FSK mode.datam
to toggle FSK modem into continuous mode. This disables packet engine and gives direct access to demodulator.- configure DIO1 pin to DCLK function, and DIO2 pin to DATA function:
dio
command to list current DIO pin asignmentsd1
to cycle DIO1 function untilDclk
is selectedd2
for DIO2, onlyData
function is available in FSK continuous mode
frf915.0
change to your desired RF center frequency (in this case 915MHz)rx
to start receiverstby
to disable receiver
Full command list
Arguments shown in square brackets []
indicate required. <>
are optional, where leaving off the argument usually causes a read of the item, and providing the value causes a write operation. You should always have the radio chip datasheet on-hand when using these commands.
Hitting <enter> key by itself will repeat last command.
<Ctrl-C> will cancel an operation in progress.
command list: common commands (both LoRa and FSK)
command | description |
---|---|
. (period) | print current radio status |
? | list available commands |
L | toggle active radio modem (LoRa vs FSK) |
h | hardware reset, put radio into default power-on condition |
frf<MHz> | get/set RF operating frequency |
rx | start radio receiver (any received packets are printed onto your serial terminal) |
rssi | read instantaneous RSSI (level read at the time command is issued) |
tx<%d> | transmit test packet. Packet length value can be provided as argument, or uses last value if not provided |
payl<%d> | get/set payload length |
bw<KHz> | get/set bandwidth. In LoRa mode, both receive and transmit bandwidth are changed. For FSK, only receive bandwidth is affected. bwa accesses AFC bandwidth in FSK |
pas | toggle RFO / PA_BOOST transmit pin output selection |
op<dBm> | get/set TX output power. Value is provided in dBm. Special case is value of 20dBm (on PA_BOOST), which causes increase in TX DAC voltage |
ocp<mA> | get/set TX current limit, in milliamps. Necessary adjustment when +20dBm is used |
dio | show DIO pin assignments |
d<0-5> | change DIO pin assignment, the pin number is given as arguement. Each pin has up to 4 possible functions |
pres<%d> | set preamble length. LoRa: number of symbols. FSK: number of bytes |
crcon | toggle crcOn |
lnab | cycle LNA-boost setting (receiver performance adjustment) |
R | read all radio registers (use only while reading chip datasheet) |
r[%x] | read single radio register (use only while reading chip datasheet) |
w[%x %x] | write single radio register (use only while reading chip datasheet) |
pllbw | change PLL bandwidth |
stby | set chip mode to standby |
sleep | set chip mode to sleep |
fstx | set chip mode to fstx |
fsrx | set chip mode to fsrx |
Eiger range test commands | description |
pid<%d> | get set ID number in range test payload |
pertx<%d> | start Eiger PER transmit. The count of packets to send is provided as arguement |
perrx | start Eiger PER receive |
txpd<%d> | get/set tx delay between PER packets transmitted |
command list: LoRa modem commands
LoRa command | LoRa description |
---|---|
iqinv | toggle RX IQ invert |
cin | toggle TX IQ invert |
lhp<%d> | (RX) get/set hop period |
sync<%x> | get/set sync (post-preamble gap, single byte) |
cr<1-4> | get/set codingRate |
lhm | toggle explicit/implicit (explicit mode sends payload length with each packet) |
sf<%d> | get/set spreadingFactor (SF7 to SF12) |
ldr | toggle LowDataRateOptimize (changes payload encoding, for long packets) |
txc | toggle TxContinuousMode |
rxt<%d> | get/set SymbTimeout |
rxs | start RX_SINGLE (receives only for SymbTimeout symbols) |
cad<%d num tries> | run channel activity detection |
command list: FSK modem commands
FSK command | FSK description |
---|---|
c<%d> | get/set test cases. Several FSK bitrates/bandwidths pre-configured to give optimal performance. |
fdev<kHz> | (TX) get/set frequency deviation |
mods | (TX) increment modulation shaping |
par | (TX) increment paRamp |
datam | toggle DataMode (packet/continuous) |
fifot | toggle TxStartCondition (FifoThreshold level vs FifoNotEmpty) |
br<%f kbps> | get/set bitrate |
dcf | increment DcFree (manchester / whitening) |
pktf | toggle PacketFormat fixed/variable length |
syncon | toggle SyncOn (frame sync, SFD enable) |
bitsync | toggle BitSyncOn (continuous mode only) |
syncw<hex bytes> | get/set syncword. Sync bytes are provided by hex octects separated by spaces. |
fei | (RX) read FEI |
rxt | (RX) increment RxTrigger (RX start on rssi vs. preamble detect) |
rssit<-dBm> | (RX) get/set rssi threshold (trigger level for RSSI interrupt) |
rssis<%d> | (RX) get/set rssi smoothing |
rssio<%d> | (RX) get/set rssi offset |
agcauto | (RX) toggle AgcAutoOn (true = LNA gain set automatically) |
afcauto | (RX) toggle AfcAutoOn |
ac | (RX) AfcClear |
ar | (RX) increment AutoRestartRxMode |
alc | (RX) toggle AfcAutoClearOn (only if AfcAutoOn is set) |
prep | (RX) toggle PreamblePolarity (0xAA vs 0x55) |
pde | (RX) toggle PreambleDetectorOn |
pds<%d> | (RX) get/set PreambleDetectorSize |
pdt<%d> | (RX) get/set PreambleDetectorTol |
mp | (RX) toggle MapPreambleDetect (DIO function RSSI vs PreambleDetect) |
thr<%d> | get/set FifoThreshold (triggers FifoLevel interrupt) |
poll | toggle poll_irq_en. Radio events read from DIO pins vs polling of IrqFlags register |
E | empty out FIFO |
clkout | increment ClkOut divider |
ook | enter OOK mode |
ookt | increment OokThreshType |
ooks | increment OokPeakTheshStep |
sqlch<%d> | get/set OokFixedThresh |
main.cpp@21:b84a77dfb43c, 2017-02-05 (annotated)
- Committer:
- dudmuck
- Date:
- Sun Feb 05 23:34:30 2017 +0000
- Revision:
- 21:b84a77dfb43c
- Parent:
- 20:b11592c9ba5f
- Child:
- 22:2005df80c8a8
added fsk back-to-back packet demonstration
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dudmuck | 1:1cd0afbed23c | 1 | #include "sx127x_lora.h" |
dudmuck | 1:1cd0afbed23c | 2 | #include "sx127x_fsk.h" |
dudmuck | 19:be8a8b0e7320 | 3 | #define __STDC_FORMAT_MACROS |
dudmuck | 19:be8a8b0e7320 | 4 | #include <inttypes.h> |
dudmuck | 18:9530d682fd9a | 5 | //#include "kermit.h" |
dudmuck | 0:be215de91a68 | 6 | |
dudmuck | 13:c73caaee93a5 | 7 | //#define FSK_PER |
dudmuck | 10:d9bb2ce57f05 | 8 | //#define START_EIGER_RX |
dudmuck | 10:d9bb2ce57f05 | 9 | //#define START_EIGER_TX |
dudmuck | 21:b84a77dfb43c | 10 | //#define START_OOK_TX_TEST |
dudmuck | 10:d9bb2ce57f05 | 11 | |
dudmuck | 10:d9bb2ce57f05 | 12 | DigitalOut led1(LED1); |
dudmuck | 0:be215de91a68 | 13 | Serial pc(USBTX, USBRX); |
dudmuck | 0:be215de91a68 | 14 | |
dudmuck | 0:be215de91a68 | 15 | uint8_t tx_cnt; |
dudmuck | 0:be215de91a68 | 16 | char pcbuf[64]; |
dudmuck | 5:360069ec9953 | 17 | int pcbuf_len; |
dudmuck | 0:be215de91a68 | 18 | |
dudmuck | 0:be215de91a68 | 19 | typedef enum { |
dudmuck | 0:be215de91a68 | 20 | APP_NONE = 0, |
dudmuck | 0:be215de91a68 | 21 | APP_CHAT |
dudmuck | 0:be215de91a68 | 22 | } app_e; |
dudmuck | 0:be215de91a68 | 23 | |
dudmuck | 0:be215de91a68 | 24 | app_e app = APP_NONE; |
dudmuck | 0:be215de91a68 | 25 | |
dudmuck | 18:9530d682fd9a | 26 | #define FSK_LARGE_PKT_THRESHOLD 0x3f |
dudmuck | 7:c3c54f222ced | 27 | |
dudmuck | 21:b84a77dfb43c | 28 | bool crc32_en; // ethcrc |
dudmuck | 21:b84a77dfb43c | 29 | |
dudmuck | 21:b84a77dfb43c | 30 | /*********** cmd_ulrx()... ************/ |
dudmuck | 21:b84a77dfb43c | 31 | typedef enum { |
dudmuck | 21:b84a77dfb43c | 32 | ULRX_STATE_OFF = 0, |
dudmuck | 21:b84a77dfb43c | 33 | ULRX_STATE_NEED_LENGTH, |
dudmuck | 21:b84a77dfb43c | 34 | ULRX_STATE_PAYLOAD, |
dudmuck | 21:b84a77dfb43c | 35 | ULRX_STATE_SYNC1 |
dudmuck | 21:b84a77dfb43c | 36 | } ulrx_state_e; |
dudmuck | 21:b84a77dfb43c | 37 | ulrx_state_e ulrx_state = ULRX_STATE_OFF; |
dudmuck | 21:b84a77dfb43c | 38 | bool ulrx_enable; |
dudmuck | 21:b84a77dfb43c | 39 | /*********** ...cmd_ulrx() ************/ |
dudmuck | 21:b84a77dfb43c | 40 | |
dudmuck | 21:b84a77dfb43c | 41 | uint8_t rx_payload_idx; |
dudmuck | 21:b84a77dfb43c | 42 | |
dudmuck | 21:b84a77dfb43c | 43 | /************** fsk modeReady isr... **********/ |
dudmuck | 21:b84a77dfb43c | 44 | bool rx_payloadReady_int_en; // cmd_prrx() |
dudmuck | 21:b84a77dfb43c | 45 | #define N_RX_PKTS 32 |
dudmuck | 21:b84a77dfb43c | 46 | #define RX_PKT_SIZE_LIMIT 32 |
dudmuck | 21:b84a77dfb43c | 47 | uint8_t rx_pkts[N_RX_PKTS][RX_PKT_SIZE_LIMIT]; |
dudmuck | 21:b84a77dfb43c | 48 | uint8_t n_rx_pkts; |
dudmuck | 21:b84a77dfb43c | 49 | /************** ...fsk modeReady isr **********/ |
dudmuck | 21:b84a77dfb43c | 50 | |
dudmuck | 21:b84a77dfb43c | 51 | #ifdef TARGET_STM |
dudmuck | 21:b84a77dfb43c | 52 | CRC_HandleTypeDef CrcHandle; |
dudmuck | 21:b84a77dfb43c | 53 | #endif /* TARGET_STM */ |
dudmuck | 21:b84a77dfb43c | 54 | |
dudmuck | 21:b84a77dfb43c | 55 | int rssi_polling_thresh; // 0 = polling off |
dudmuck | 18:9530d682fd9a | 56 | bool ook_test_en; |
dudmuck | 18:9530d682fd9a | 57 | bool poll_irq_en; |
dudmuck | 20:b11592c9ba5f | 58 | volatile RegIrqFlags2_t fsk_RegIrqFlags2_prev; |
dudmuck | 20:b11592c9ba5f | 59 | volatile RegIrqFlags1_t fsk_RegIrqFlags1_prev; |
dudmuck | 20:b11592c9ba5f | 60 | Timer rx_start_timer; |
dudmuck | 20:b11592c9ba5f | 61 | uint32_t secs_rx_start; |
dudmuck | 1:1cd0afbed23c | 62 | |
dudmuck | 8:227605e4a760 | 63 | /***************************** eiger per: *************************************************/ |
dudmuck | 8:227605e4a760 | 64 | |
dudmuck | 18:9530d682fd9a | 65 | uint32_t num_cads; |
dudmuck | 18:9530d682fd9a | 66 | bool cadper_enable; |
dudmuck | 8:227605e4a760 | 67 | bool per_en; |
dudmuck | 8:227605e4a760 | 68 | float per_tx_delay = 0.1; |
dudmuck | 8:227605e4a760 | 69 | int per_id; |
dudmuck | 18:9530d682fd9a | 70 | uint32_t PacketTxCnt, PacketTxCntEnd; |
dudmuck | 8:227605e4a760 | 71 | uint32_t PacketPerOkCnt; |
dudmuck | 8:227605e4a760 | 72 | int PacketRxSequencePrev; |
dudmuck | 8:227605e4a760 | 73 | uint32_t PacketPerKoCnt; |
dudmuck | 8:227605e4a760 | 74 | uint32_t PacketNormalCnt; |
dudmuck | 8:227605e4a760 | 75 | Timeout per_timeout; |
dudmuck | 8:227605e4a760 | 76 | |
dudmuck | 18:9530d682fd9a | 77 | |
dudmuck | 18:9530d682fd9a | 78 | |
dudmuck | 0:be215de91a68 | 79 | /******************************************************************************/ |
dudmuck | 9:2f13a9ef27b4 | 80 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 9:2f13a9ef27b4 | 81 | // mosi, miso, sclk, cs, rst, dio0, dio1 |
dudmuck | 9:2f13a9ef27b4 | 82 | SX127x radio(LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1); |
dudmuck | 9:2f13a9ef27b4 | 83 | |
dudmuck | 9:2f13a9ef27b4 | 84 | DigitalOut txctl(LORA_TXCTL); |
dudmuck | 9:2f13a9ef27b4 | 85 | DigitalOut rxctl(LORA_RXCTL); |
dudmuck | 9:2f13a9ef27b4 | 86 | |
dudmuck | 9:2f13a9ef27b4 | 87 | void rfsw_callback() |
dudmuck | 9:2f13a9ef27b4 | 88 | { |
dudmuck | 9:2f13a9ef27b4 | 89 | /* SKY13350 */ |
dudmuck | 9:2f13a9ef27b4 | 90 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { // start of transmission |
dudmuck | 9:2f13a9ef27b4 | 91 | txctl = 1; |
dudmuck | 9:2f13a9ef27b4 | 92 | rxctl = 0; |
dudmuck | 9:2f13a9ef27b4 | 93 | } else { // reception: |
dudmuck | 9:2f13a9ef27b4 | 94 | txctl = 0; |
dudmuck | 9:2f13a9ef27b4 | 95 | rxctl = 1; |
dudmuck | 9:2f13a9ef27b4 | 96 | } |
dudmuck | 9:2f13a9ef27b4 | 97 | } |
dudmuck | 9:2f13a9ef27b4 | 98 | |
dudmuck | 15:c69b942685ea | 99 | #define FSK_RSSI_OFFSET 0 |
dudmuck | 15:c69b942685ea | 100 | #define FSK_RSSI_SMOOTHING 2 |
dudmuck | 20:b11592c9ba5f | 101 | DigitalIn dio2(LORA_DIO2); |
dudmuck | 20:b11592c9ba5f | 102 | DigitalIn dio4(LORA_DIO4); |
dudmuck | 15:c69b942685ea | 103 | |
dudmuck | 9:2f13a9ef27b4 | 104 | #else /********************* ...mDot **********************/ |
dudmuck | 0:be215de91a68 | 105 | |
dudmuck | 5:360069ec9953 | 106 | // pin: 3 8 1 7 10 12 5 |
dudmuck | 5:360069ec9953 | 107 | // mosi, miso, sclk, cs, rst, dio0, dio1 |
dudmuck | 6:fe16f96ee335 | 108 | SX127x radio(D11, D12, D13, D10, A0, D2, D3); // sx1276 arduino shield |
dudmuck | 0:be215de91a68 | 109 | |
dudmuck | 15:c69b942685ea | 110 | // for SX1276 arduino shield: |
dudmuck | 7:c3c54f222ced | 111 | #ifdef TARGET_LPC11U6X |
dudmuck | 15:c69b942685ea | 112 | //DigitalOut rfsw(P0_23); |
dudmuck | 15:c69b942685ea | 113 | DigitalInOut rfsw(P0_23); |
dudmuck | 7:c3c54f222ced | 114 | #else |
dudmuck | 15:c69b942685ea | 115 | //DigitalOut rfsw(A4); |
dudmuck | 15:c69b942685ea | 116 | DigitalInOut rfsw(A4); |
dudmuck | 7:c3c54f222ced | 117 | #endif |
dudmuck | 6:fe16f96ee335 | 118 | |
dudmuck | 21:b84a77dfb43c | 119 | InterruptIn dio0int(D2); |
dudmuck | 21:b84a77dfb43c | 120 | InterruptIn dio1int(D3); |
dudmuck | 21:b84a77dfb43c | 121 | InterruptIn dio2int(D4); |
dudmuck | 21:b84a77dfb43c | 122 | InterruptIn dio4int(D8); |
dudmuck | 14:c57ea544dc18 | 123 | DigitalIn dio2(D4); |
dudmuck | 21:b84a77dfb43c | 124 | DigitalIn dio3(D5); |
dudmuck | 20:b11592c9ba5f | 125 | DigitalIn dio4(D8); |
dudmuck | 14:c57ea544dc18 | 126 | |
dudmuck | 21:b84a77dfb43c | 127 | #ifdef TARGET_STM |
dudmuck | 21:b84a77dfb43c | 128 | DigitalOut pc3(PC_3); // nucleo corner pin for misc indication |
dudmuck | 21:b84a77dfb43c | 129 | #endif |
dudmuck | 21:b84a77dfb43c | 130 | |
dudmuck | 6:fe16f96ee335 | 131 | void rfsw_callback() |
dudmuck | 6:fe16f96ee335 | 132 | { |
dudmuck | 6:fe16f96ee335 | 133 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) |
dudmuck | 6:fe16f96ee335 | 134 | rfsw = 1; |
dudmuck | 6:fe16f96ee335 | 135 | else |
dudmuck | 6:fe16f96ee335 | 136 | rfsw = 0; |
dudmuck | 6:fe16f96ee335 | 137 | } |
dudmuck | 6:fe16f96ee335 | 138 | |
dudmuck | 15:c69b942685ea | 139 | #define FSK_RSSI_OFFSET 5 |
dudmuck | 15:c69b942685ea | 140 | #define FSK_RSSI_SMOOTHING 2 |
dudmuck | 15:c69b942685ea | 141 | |
dudmuck | 15:c69b942685ea | 142 | typedef enum { |
dudmuck | 15:c69b942685ea | 143 | SHIELD_TYPE_NONE = 0, |
dudmuck | 15:c69b942685ea | 144 | SHIELD_TYPE_LAS, |
dudmuck | 15:c69b942685ea | 145 | SHIELD_TYPE_MAS, |
dudmuck | 15:c69b942685ea | 146 | } shield_type_e; |
dudmuck | 15:c69b942685ea | 147 | shield_type_e shield_type; |
dudmuck | 15:c69b942685ea | 148 | |
dudmuck | 9:2f13a9ef27b4 | 149 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 9:2f13a9ef27b4 | 150 | |
dudmuck | 9:2f13a9ef27b4 | 151 | SX127x_fsk fsk(radio); |
dudmuck | 9:2f13a9ef27b4 | 152 | SX127x_lora lora(radio); |
dudmuck | 18:9530d682fd9a | 153 | //Kermit kermit(lora); |
dudmuck | 9:2f13a9ef27b4 | 154 | |
dudmuck | 20:b11592c9ba5f | 155 | volatile bool saved_dio4; |
dudmuck | 20:b11592c9ba5f | 156 | |
dudmuck | 21:b84a77dfb43c | 157 | uint32_t crcTable[256]; |
dudmuck | 21:b84a77dfb43c | 158 | void make_crc_table() |
dudmuck | 21:b84a77dfb43c | 159 | { |
dudmuck | 21:b84a77dfb43c | 160 | const uint32_t POLYNOMIAL = 0xEDB88320; |
dudmuck | 21:b84a77dfb43c | 161 | uint32_t remainder; |
dudmuck | 21:b84a77dfb43c | 162 | uint8_t b = 0; |
dudmuck | 21:b84a77dfb43c | 163 | do{ |
dudmuck | 21:b84a77dfb43c | 164 | // Start with the data byte |
dudmuck | 21:b84a77dfb43c | 165 | remainder = b; |
dudmuck | 21:b84a77dfb43c | 166 | for (unsigned long bit = 8; bit > 0; --bit) |
dudmuck | 21:b84a77dfb43c | 167 | { |
dudmuck | 21:b84a77dfb43c | 168 | if (remainder & 1) |
dudmuck | 21:b84a77dfb43c | 169 | remainder = (remainder >> 1) ^ POLYNOMIAL; |
dudmuck | 21:b84a77dfb43c | 170 | else |
dudmuck | 21:b84a77dfb43c | 171 | remainder = (remainder >> 1); |
dudmuck | 21:b84a77dfb43c | 172 | } |
dudmuck | 21:b84a77dfb43c | 173 | crcTable[(size_t)b] = remainder; |
dudmuck | 21:b84a77dfb43c | 174 | } while(0 != ++b); |
dudmuck | 21:b84a77dfb43c | 175 | } |
dudmuck | 21:b84a77dfb43c | 176 | |
dudmuck | 21:b84a77dfb43c | 177 | uint32_t gen_crc(const uint8_t *p, size_t n) |
dudmuck | 21:b84a77dfb43c | 178 | { |
dudmuck | 21:b84a77dfb43c | 179 | uint32_t crc = 0xffffffff; |
dudmuck | 21:b84a77dfb43c | 180 | size_t i; |
dudmuck | 21:b84a77dfb43c | 181 | for(i = 0; i < n; i++) { |
dudmuck | 21:b84a77dfb43c | 182 | crc = crcTable[*p++ ^ (crc&0xff)] ^ (crc>>8); |
dudmuck | 21:b84a77dfb43c | 183 | } |
dudmuck | 21:b84a77dfb43c | 184 | |
dudmuck | 21:b84a77dfb43c | 185 | return(~crc); |
dudmuck | 21:b84a77dfb43c | 186 | } |
dudmuck | 21:b84a77dfb43c | 187 | |
dudmuck | 21:b84a77dfb43c | 188 | |
dudmuck | 0:be215de91a68 | 189 | void printLoraIrqs_(bool clear) |
dudmuck | 0:be215de91a68 | 190 | { |
dudmuck | 0:be215de91a68 | 191 | //in radio class -- RegIrqFlags_t RegIrqFlags; |
dudmuck | 0:be215de91a68 | 192 | |
dudmuck | 0:be215de91a68 | 193 | //already read RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 0:be215de91a68 | 194 | printf("\r\nIrqFlags:"); |
dudmuck | 1:1cd0afbed23c | 195 | if (lora.RegIrqFlags.bits.CadDetected) |
dudmuck | 0:be215de91a68 | 196 | printf("CadDetected "); |
dudmuck | 1:1cd0afbed23c | 197 | if (lora.RegIrqFlags.bits.FhssChangeChannel) { |
dudmuck | 0:be215de91a68 | 198 | //radio.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); |
dudmuck | 1:1cd0afbed23c | 199 | printf("FhssChangeChannel:%d ", lora.RegHopChannel.bits.FhssPresentChannel); |
dudmuck | 0:be215de91a68 | 200 | } |
dudmuck | 1:1cd0afbed23c | 201 | if (lora.RegIrqFlags.bits.CadDone) |
dudmuck | 0:be215de91a68 | 202 | printf("CadDone "); |
dudmuck | 1:1cd0afbed23c | 203 | if (lora.RegIrqFlags.bits.TxDone) |
dudmuck | 0:be215de91a68 | 204 | printf("TxDone "); |
dudmuck | 1:1cd0afbed23c | 205 | if (lora.RegIrqFlags.bits.ValidHeader) |
dudmuck | 0:be215de91a68 | 206 | printf("[42mValidHeader[0m "); |
dudmuck | 1:1cd0afbed23c | 207 | if (lora.RegIrqFlags.bits.PayloadCrcError) |
dudmuck | 0:be215de91a68 | 208 | printf("[41mPayloadCrcError[0m "); |
dudmuck | 1:1cd0afbed23c | 209 | if (lora.RegIrqFlags.bits.RxDone) |
dudmuck | 0:be215de91a68 | 210 | printf("[42mRxDone[0m "); |
dudmuck | 1:1cd0afbed23c | 211 | if (lora.RegIrqFlags.bits.RxTimeout) |
dudmuck | 0:be215de91a68 | 212 | printf("RxTimeout "); |
dudmuck | 0:be215de91a68 | 213 | |
dudmuck | 0:be215de91a68 | 214 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 215 | |
dudmuck | 0:be215de91a68 | 216 | if (clear) |
dudmuck | 1:1cd0afbed23c | 217 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 0:be215de91a68 | 218 | |
dudmuck | 0:be215de91a68 | 219 | } |
dudmuck | 0:be215de91a68 | 220 | |
dudmuck | 1:1cd0afbed23c | 221 | void lora_printCodingRate(bool from_rx) |
dudmuck | 0:be215de91a68 | 222 | { |
dudmuck | 1:1cd0afbed23c | 223 | uint8_t d = lora.getCodingRate(from_rx); |
dudmuck | 0:be215de91a68 | 224 | printf("CodingRate:"); |
dudmuck | 0:be215de91a68 | 225 | switch (d) { |
dudmuck | 0:be215de91a68 | 226 | case 1: printf("4/5 "); break; |
dudmuck | 0:be215de91a68 | 227 | case 2: printf("4/6 "); break; |
dudmuck | 0:be215de91a68 | 228 | case 3: printf("4/7 "); break; |
dudmuck | 0:be215de91a68 | 229 | case 4: printf("4/8 "); break; |
dudmuck | 0:be215de91a68 | 230 | default: |
dudmuck | 0:be215de91a68 | 231 | printf("%d ", d); |
dudmuck | 0:be215de91a68 | 232 | break; |
dudmuck | 0:be215de91a68 | 233 | } |
dudmuck | 0:be215de91a68 | 234 | } |
dudmuck | 0:be215de91a68 | 235 | |
dudmuck | 1:1cd0afbed23c | 236 | void lora_printHeaderMode() |
dudmuck | 0:be215de91a68 | 237 | { |
dudmuck | 1:1cd0afbed23c | 238 | if (lora.getHeaderMode()) |
dudmuck | 0:be215de91a68 | 239 | printf("implicit "); |
dudmuck | 0:be215de91a68 | 240 | else |
dudmuck | 0:be215de91a68 | 241 | printf("explicit "); |
dudmuck | 0:be215de91a68 | 242 | } |
dudmuck | 0:be215de91a68 | 243 | |
dudmuck | 1:1cd0afbed23c | 244 | void lora_printBw() |
dudmuck | 0:be215de91a68 | 245 | { |
dudmuck | 19:be8a8b0e7320 | 246 | (void)lora.getBw(); |
dudmuck | 0:be215de91a68 | 247 | |
dudmuck | 0:be215de91a68 | 248 | printf("Bw:"); |
dudmuck | 0:be215de91a68 | 249 | if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 250 | switch (lora.RegModemConfig.sx1276bits.Bw) { |
dudmuck | 0:be215de91a68 | 251 | case 0: printf("7.8KHz "); break; |
dudmuck | 0:be215de91a68 | 252 | case 1: printf("10.4KHz "); break; |
dudmuck | 0:be215de91a68 | 253 | case 2: printf("15.6KHz "); break; |
dudmuck | 0:be215de91a68 | 254 | case 3: printf("20.8KHz "); break; |
dudmuck | 0:be215de91a68 | 255 | case 4: printf("31.25KHz "); break; |
dudmuck | 0:be215de91a68 | 256 | case 5: printf("41.7KHz "); break; |
dudmuck | 0:be215de91a68 | 257 | case 6: printf("62.5KHz "); break; |
dudmuck | 0:be215de91a68 | 258 | case 7: printf("125KHz "); break; |
dudmuck | 0:be215de91a68 | 259 | case 8: printf("250KHz "); break; |
dudmuck | 0:be215de91a68 | 260 | case 9: printf("500KHz "); break; |
dudmuck | 1:1cd0afbed23c | 261 | default: printf("%x ", lora.RegModemConfig.sx1276bits.Bw); break; |
dudmuck | 0:be215de91a68 | 262 | } |
dudmuck | 0:be215de91a68 | 263 | } else if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 264 | switch (lora.RegModemConfig.sx1272bits.Bw) { |
dudmuck | 0:be215de91a68 | 265 | case 0: printf("125KHz "); break; |
dudmuck | 0:be215de91a68 | 266 | case 1: printf("250KHz "); break; |
dudmuck | 0:be215de91a68 | 267 | case 2: printf("500KHz "); break; |
dudmuck | 0:be215de91a68 | 268 | case 3: printf("11b "); break; |
dudmuck | 0:be215de91a68 | 269 | } |
dudmuck | 0:be215de91a68 | 270 | } |
dudmuck | 0:be215de91a68 | 271 | } |
dudmuck | 0:be215de91a68 | 272 | |
dudmuck | 1:1cd0afbed23c | 273 | void lora_printAllBw() |
dudmuck | 0:be215de91a68 | 274 | { |
dudmuck | 0:be215de91a68 | 275 | int i, s; |
dudmuck | 0:be215de91a68 | 276 | |
dudmuck | 0:be215de91a68 | 277 | if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 278 | s = lora.RegModemConfig.sx1276bits.Bw; |
dudmuck | 0:be215de91a68 | 279 | for (i = 0; i < 10; i++ ) { |
dudmuck | 1:1cd0afbed23c | 280 | lora.RegModemConfig.sx1276bits.Bw = i; |
dudmuck | 0:be215de91a68 | 281 | printf("%d ", i); |
dudmuck | 1:1cd0afbed23c | 282 | lora_printBw(); |
dudmuck | 0:be215de91a68 | 283 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 284 | } |
dudmuck | 1:1cd0afbed23c | 285 | lora.RegModemConfig.sx1276bits.Bw = s; |
dudmuck | 0:be215de91a68 | 286 | } else if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 287 | s = lora.RegModemConfig.sx1272bits.Bw; |
dudmuck | 0:be215de91a68 | 288 | for (i = 0; i < 3; i++ ) { |
dudmuck | 1:1cd0afbed23c | 289 | lora.RegModemConfig.sx1272bits.Bw = i; |
dudmuck | 0:be215de91a68 | 290 | printf("%d ", i); |
dudmuck | 1:1cd0afbed23c | 291 | lora_printBw(); |
dudmuck | 0:be215de91a68 | 292 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 293 | } |
dudmuck | 1:1cd0afbed23c | 294 | lora.RegModemConfig.sx1272bits.Bw = s; |
dudmuck | 0:be215de91a68 | 295 | } |
dudmuck | 0:be215de91a68 | 296 | } |
dudmuck | 0:be215de91a68 | 297 | |
dudmuck | 1:1cd0afbed23c | 298 | void lora_printSf() |
dudmuck | 0:be215de91a68 | 299 | { |
dudmuck | 0:be215de91a68 | 300 | // spreading factor same between sx127[26] |
dudmuck | 1:1cd0afbed23c | 301 | printf("sf:%d ", lora.getSf()); |
dudmuck | 0:be215de91a68 | 302 | } |
dudmuck | 0:be215de91a68 | 303 | |
dudmuck | 1:1cd0afbed23c | 304 | void lora_printRxPayloadCrcOn() |
dudmuck | 0:be215de91a68 | 305 | { |
dudmuck | 1:1cd0afbed23c | 306 | bool on = lora.getRxPayloadCrcOn(); |
dudmuck | 18:9530d682fd9a | 307 | printf("RxPayloadCrcOn:%d = ", on); |
dudmuck | 18:9530d682fd9a | 308 | if (lora.getHeaderMode()) |
dudmuck | 18:9530d682fd9a | 309 | printf("Rx/"); // implicit mode |
dudmuck | 18:9530d682fd9a | 310 | |
dudmuck | 0:be215de91a68 | 311 | if (on) |
dudmuck | 18:9530d682fd9a | 312 | printf("Tx CRC Enabled\r\n"); |
dudmuck | 0:be215de91a68 | 313 | else |
dudmuck | 18:9530d682fd9a | 314 | printf("Tx CRC disabled\r\n"); |
dudmuck | 0:be215de91a68 | 315 | } |
dudmuck | 0:be215de91a68 | 316 | |
dudmuck | 1:1cd0afbed23c | 317 | void lora_printTxContinuousMode() |
dudmuck | 0:be215de91a68 | 318 | { |
dudmuck | 1:1cd0afbed23c | 319 | printf("TxContinuousMode:%d ", lora.RegModemConfig2.sx1276bits.TxContinuousMode); // same for sx1272 and sx1276 |
dudmuck | 0:be215de91a68 | 320 | } |
dudmuck | 0:be215de91a68 | 321 | |
dudmuck | 1:1cd0afbed23c | 322 | void lora_printAgcAutoOn() |
dudmuck | 0:be215de91a68 | 323 | { |
dudmuck | 1:1cd0afbed23c | 324 | printf("AgcAutoOn:%d", lora.getAgcAutoOn()); |
dudmuck | 0:be215de91a68 | 325 | } |
dudmuck | 0:be215de91a68 | 326 | |
dudmuck | 1:1cd0afbed23c | 327 | void lora_print_dio() |
dudmuck | 0:be215de91a68 | 328 | { |
dudmuck | 1:1cd0afbed23c | 329 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 0:be215de91a68 | 330 | printf("DIO5:"); |
dudmuck | 0:be215de91a68 | 331 | switch (radio.RegDioMapping2.bits.Dio5Mapping) { |
dudmuck | 0:be215de91a68 | 332 | case 0: printf("ModeReady"); break; |
dudmuck | 0:be215de91a68 | 333 | case 1: printf("ClkOut"); break; |
dudmuck | 0:be215de91a68 | 334 | case 2: printf("ClkOut"); break; |
dudmuck | 0:be215de91a68 | 335 | } |
dudmuck | 0:be215de91a68 | 336 | printf(" DIO4:"); |
dudmuck | 0:be215de91a68 | 337 | switch (radio.RegDioMapping2.bits.Dio4Mapping) { |
dudmuck | 0:be215de91a68 | 338 | case 0: printf("CadDetected"); break; |
dudmuck | 0:be215de91a68 | 339 | case 1: printf("PllLock"); break; |
dudmuck | 0:be215de91a68 | 340 | case 2: printf("PllLock"); break; |
dudmuck | 0:be215de91a68 | 341 | } |
dudmuck | 0:be215de91a68 | 342 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 0:be215de91a68 | 343 | printf(" DIO3:"); |
dudmuck | 0:be215de91a68 | 344 | switch (radio.RegDioMapping1.bits.Dio3Mapping) { |
dudmuck | 0:be215de91a68 | 345 | case 0: printf("CadDone"); break; |
dudmuck | 0:be215de91a68 | 346 | case 1: printf("ValidHeader"); break; |
dudmuck | 0:be215de91a68 | 347 | case 2: printf("PayloadCrcError"); break; |
dudmuck | 0:be215de91a68 | 348 | } |
dudmuck | 0:be215de91a68 | 349 | printf(" DIO2:"); |
dudmuck | 0:be215de91a68 | 350 | switch (radio.RegDioMapping1.bits.Dio2Mapping) { |
dudmuck | 0:be215de91a68 | 351 | case 0: |
dudmuck | 0:be215de91a68 | 352 | case 1: |
dudmuck | 0:be215de91a68 | 353 | case 2: |
dudmuck | 0:be215de91a68 | 354 | printf("FhssChangeChannel"); |
dudmuck | 0:be215de91a68 | 355 | break; |
dudmuck | 0:be215de91a68 | 356 | } |
dudmuck | 0:be215de91a68 | 357 | printf(" DIO1:"); |
dudmuck | 0:be215de91a68 | 358 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 0:be215de91a68 | 359 | case 0: printf("RxTimeout"); break; |
dudmuck | 0:be215de91a68 | 360 | case 1: printf("FhssChangeChannel"); break; |
dudmuck | 0:be215de91a68 | 361 | case 2: printf("CadDetected"); break; |
dudmuck | 0:be215de91a68 | 362 | } |
dudmuck | 0:be215de91a68 | 363 | printf(" DIO0:"); |
dudmuck | 0:be215de91a68 | 364 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 0:be215de91a68 | 365 | case 0: printf("RxDone"); break; |
dudmuck | 0:be215de91a68 | 366 | case 1: printf("TxDone"); break; |
dudmuck | 0:be215de91a68 | 367 | case 2: printf("CadDone"); break; |
dudmuck | 0:be215de91a68 | 368 | } |
dudmuck | 0:be215de91a68 | 369 | |
dudmuck | 0:be215de91a68 | 370 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 371 | } |
dudmuck | 0:be215de91a68 | 372 | |
dudmuck | 1:1cd0afbed23c | 373 | void fsk_print_dio() |
dudmuck | 1:1cd0afbed23c | 374 | { |
dudmuck | 1:1cd0afbed23c | 375 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 1:1cd0afbed23c | 376 | |
dudmuck | 2:c6b23a43a9d9 | 377 | printf("DIO5:"); |
dudmuck | 1:1cd0afbed23c | 378 | switch (radio.RegDioMapping2.bits.Dio5Mapping) { |
dudmuck | 1:1cd0afbed23c | 379 | case 0: printf("ClkOut"); break; |
dudmuck | 1:1cd0afbed23c | 380 | case 1: printf("PllLock"); break; |
dudmuck | 1:1cd0afbed23c | 381 | case 2: |
dudmuck | 1:1cd0afbed23c | 382 | if (fsk.RegPktConfig2.bits.DataModePacket) |
dudmuck | 1:1cd0afbed23c | 383 | printf("data"); |
dudmuck | 1:1cd0afbed23c | 384 | else { |
dudmuck | 1:1cd0afbed23c | 385 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 386 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 387 | else |
dudmuck | 1:1cd0afbed23c | 388 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 389 | } |
dudmuck | 1:1cd0afbed23c | 390 | break; |
dudmuck | 1:1cd0afbed23c | 391 | case 3: printf("ModeReady"); break; |
dudmuck | 1:1cd0afbed23c | 392 | } |
dudmuck | 1:1cd0afbed23c | 393 | |
dudmuck | 2:c6b23a43a9d9 | 394 | printf(" DIO4:"); |
dudmuck | 1:1cd0afbed23c | 395 | switch (radio.RegDioMapping2.bits.Dio4Mapping) { |
dudmuck | 1:1cd0afbed23c | 396 | case 0: printf("temp/eol"); break; |
dudmuck | 1:1cd0afbed23c | 397 | case 1: printf("PllLock"); break; |
dudmuck | 1:1cd0afbed23c | 398 | case 2: printf("TimeOut"); break; |
dudmuck | 1:1cd0afbed23c | 399 | case 3: |
dudmuck | 1:1cd0afbed23c | 400 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 401 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 402 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 403 | else |
dudmuck | 1:1cd0afbed23c | 404 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 405 | } else |
dudmuck | 1:1cd0afbed23c | 406 | printf("ModeReady"); |
dudmuck | 1:1cd0afbed23c | 407 | break; |
dudmuck | 1:1cd0afbed23c | 408 | } |
dudmuck | 1:1cd0afbed23c | 409 | |
dudmuck | 1:1cd0afbed23c | 410 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 1:1cd0afbed23c | 411 | |
dudmuck | 2:c6b23a43a9d9 | 412 | printf(" DIO3:"); |
dudmuck | 21:b84a77dfb43c | 413 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 21:b84a77dfb43c | 414 | if (radio.RegDioMapping1.bits.Dio3Mapping == 1) |
dudmuck | 21:b84a77dfb43c | 415 | printf("TxReady"); |
dudmuck | 21:b84a77dfb43c | 416 | else |
dudmuck | 21:b84a77dfb43c | 417 | printf("FifoEmpty"); |
dudmuck | 21:b84a77dfb43c | 418 | } else { |
dudmuck | 21:b84a77dfb43c | 419 | switch (radio.RegDioMapping1.bits.Dio3Mapping) { |
dudmuck | 21:b84a77dfb43c | 420 | case 0: printf("Timeout"); break; |
dudmuck | 21:b84a77dfb43c | 421 | case 1: |
dudmuck | 21:b84a77dfb43c | 422 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 21:b84a77dfb43c | 423 | printf("preamble"); |
dudmuck | 21:b84a77dfb43c | 424 | else |
dudmuck | 21:b84a77dfb43c | 425 | printf("rssi"); |
dudmuck | 21:b84a77dfb43c | 426 | break; |
dudmuck | 21:b84a77dfb43c | 427 | case 2: printf("?automode_status?"); break; |
dudmuck | 21:b84a77dfb43c | 428 | case 3: printf("TempChange/LowBat"); break; |
dudmuck | 21:b84a77dfb43c | 429 | } |
dudmuck | 1:1cd0afbed23c | 430 | } |
dudmuck | 1:1cd0afbed23c | 431 | |
dudmuck | 2:c6b23a43a9d9 | 432 | printf(" DIO2:"); |
dudmuck | 1:1cd0afbed23c | 433 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 434 | switch (radio.RegDioMapping1.bits.Dio2Mapping) { |
dudmuck | 1:1cd0afbed23c | 435 | case 0: printf("FifoFull"); break; |
dudmuck | 1:1cd0afbed23c | 436 | case 1: printf("RxReady"); break; |
dudmuck | 1:1cd0afbed23c | 437 | case 2: printf("FifoFull/rx-timeout"); break; |
dudmuck | 1:1cd0afbed23c | 438 | case 3: printf("FifoFull/rx-syncadrs"); break; |
dudmuck | 1:1cd0afbed23c | 439 | } |
dudmuck | 1:1cd0afbed23c | 440 | } else { |
dudmuck | 1:1cd0afbed23c | 441 | printf("Data"); |
dudmuck | 1:1cd0afbed23c | 442 | } |
dudmuck | 1:1cd0afbed23c | 443 | |
dudmuck | 2:c6b23a43a9d9 | 444 | printf(" DIO1:"); |
dudmuck | 1:1cd0afbed23c | 445 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 446 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 1:1cd0afbed23c | 447 | case 0: printf("FifoThresh"); break; |
dudmuck | 1:1cd0afbed23c | 448 | case 1: printf("FifoEmpty"); break; |
dudmuck | 1:1cd0afbed23c | 449 | case 2: printf("FifoFull"); break; |
dudmuck | 1:1cd0afbed23c | 450 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 451 | } |
dudmuck | 1:1cd0afbed23c | 452 | } else { |
dudmuck | 1:1cd0afbed23c | 453 | switch (radio.RegDioMapping1.bits.Dio1Mapping) { |
dudmuck | 1:1cd0afbed23c | 454 | case 0: printf("Dclk"); break; |
dudmuck | 1:1cd0afbed23c | 455 | case 1: |
dudmuck | 1:1cd0afbed23c | 456 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 457 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 458 | else |
dudmuck | 1:1cd0afbed23c | 459 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 460 | break; |
dudmuck | 1:1cd0afbed23c | 461 | case 2: printf("[41m-2-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 462 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 463 | } |
dudmuck | 1:1cd0afbed23c | 464 | } |
dudmuck | 1:1cd0afbed23c | 465 | |
dudmuck | 2:c6b23a43a9d9 | 466 | printf(" DIO0:"); |
dudmuck | 1:1cd0afbed23c | 467 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 468 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 1:1cd0afbed23c | 469 | case 0: printf("PayloadReady/PacketSent"); break; |
dudmuck | 1:1cd0afbed23c | 470 | case 1: printf("CrcOk"); break; |
dudmuck | 1:1cd0afbed23c | 471 | case 2: printf("[41m-2-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 472 | case 3: printf("TempChange/LowBat"); break; |
dudmuck | 1:1cd0afbed23c | 473 | } |
dudmuck | 1:1cd0afbed23c | 474 | } else { |
dudmuck | 1:1cd0afbed23c | 475 | switch (radio.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 1:1cd0afbed23c | 476 | case 0: printf("SyncAdrs/TxReady"); break; |
dudmuck | 1:1cd0afbed23c | 477 | case 1: |
dudmuck | 1:1cd0afbed23c | 478 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 1:1cd0afbed23c | 479 | printf("preamble"); |
dudmuck | 1:1cd0afbed23c | 480 | else |
dudmuck | 1:1cd0afbed23c | 481 | printf("rssi"); |
dudmuck | 1:1cd0afbed23c | 482 | break; |
dudmuck | 1:1cd0afbed23c | 483 | case 2: printf("RxReady"); break; |
dudmuck | 1:1cd0afbed23c | 484 | case 3: printf("[41m-3-[0m"); break; |
dudmuck | 1:1cd0afbed23c | 485 | } |
dudmuck | 1:1cd0afbed23c | 486 | } |
dudmuck | 1:1cd0afbed23c | 487 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 488 | } |
dudmuck | 1:1cd0afbed23c | 489 | |
dudmuck | 0:be215de91a68 | 490 | void lora_print_status() |
dudmuck | 15:c69b942685ea | 491 | { |
dudmuck | 0:be215de91a68 | 492 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 0:be215de91a68 | 493 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 0:be215de91a68 | 494 | printf("FSK\r\n"); |
dudmuck | 0:be215de91a68 | 495 | return; |
dudmuck | 0:be215de91a68 | 496 | } |
dudmuck | 0:be215de91a68 | 497 | |
dudmuck | 1:1cd0afbed23c | 498 | lora_print_dio(); |
dudmuck | 0:be215de91a68 | 499 | printf("LoRa "); |
dudmuck | 0:be215de91a68 | 500 | |
dudmuck | 0:be215de91a68 | 501 | // printing LoRa registers at 0x0d -> 0x3f |
dudmuck | 0:be215de91a68 | 502 | |
dudmuck | 1:1cd0afbed23c | 503 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 1:1cd0afbed23c | 504 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 0:be215de91a68 | 505 | |
dudmuck | 1:1cd0afbed23c | 506 | lora_printCodingRate(false); // false: transmitted coding rate |
dudmuck | 1:1cd0afbed23c | 507 | lora_printHeaderMode(); |
dudmuck | 1:1cd0afbed23c | 508 | lora_printBw(); |
dudmuck | 1:1cd0afbed23c | 509 | lora_printSf(); |
dudmuck | 1:1cd0afbed23c | 510 | lora_printRxPayloadCrcOn(); |
dudmuck | 0:be215de91a68 | 511 | // RegModemStat |
dudmuck | 0:be215de91a68 | 512 | printf("ModemStat:0x%02x\r\n", radio.read_reg(REG_LR_MODEMSTAT)); |
dudmuck | 0:be215de91a68 | 513 | |
dudmuck | 0:be215de91a68 | 514 | // fifo ptrs: |
dudmuck | 1:1cd0afbed23c | 515 | lora.RegPayloadLength = radio.read_reg(REG_LR_PAYLOADLENGTH); |
dudmuck | 1:1cd0afbed23c | 516 | lora.RegRxMaxPayloadLength = radio.read_reg(REG_LR_RX_MAX_PAYLOADLENGTH); |
dudmuck | 0:be215de91a68 | 517 | printf("fifoptr=0x%02x txbase=0x%02x rxbase=0x%02x payloadLength=0x%02x maxlen=0x%02x", |
dudmuck | 0:be215de91a68 | 518 | radio.read_reg(REG_LR_FIFOADDRPTR), |
dudmuck | 0:be215de91a68 | 519 | radio.read_reg(REG_LR_FIFOTXBASEADDR), |
dudmuck | 0:be215de91a68 | 520 | radio.read_reg(REG_LR_FIFORXBASEADDR), |
dudmuck | 1:1cd0afbed23c | 521 | lora.RegPayloadLength, |
dudmuck | 1:1cd0afbed23c | 522 | lora.RegRxMaxPayloadLength |
dudmuck | 0:be215de91a68 | 523 | ); |
dudmuck | 0:be215de91a68 | 524 | |
dudmuck | 1:1cd0afbed23c | 525 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 0:be215de91a68 | 526 | printLoraIrqs_(false); |
dudmuck | 0:be215de91a68 | 527 | |
dudmuck | 1:1cd0afbed23c | 528 | lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); |
dudmuck | 1:1cd0afbed23c | 529 | if (lora.RegHopPeriod != 0) { |
dudmuck | 1:1cd0afbed23c | 530 | printf("\r\nHopPeriod:0x%02x\r\n", lora.RegHopPeriod); |
dudmuck | 0:be215de91a68 | 531 | } |
dudmuck | 0:be215de91a68 | 532 | |
dudmuck | 18:9530d682fd9a | 533 | printf("SymbTimeout:%d ", radio.read_u16(REG_LR_MODEMCONFIG2) & 0x3ff); |
dudmuck | 0:be215de91a68 | 534 | |
dudmuck | 1:1cd0afbed23c | 535 | lora.RegPreamble = radio.read_u16(REG_LR_PREAMBLEMSB); |
dudmuck | 4:7a9007dfc0e5 | 536 | printf("PreambleLength:%d ", lora.RegPreamble); |
dudmuck | 0:be215de91a68 | 537 | |
dudmuck | 0:be215de91a68 | 538 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER_SINGLE) { |
dudmuck | 15:c69b942685ea | 539 | printf("rssi:%ddBm ", lora.get_current_rssi()); |
dudmuck | 0:be215de91a68 | 540 | } |
dudmuck | 0:be215de91a68 | 541 | |
dudmuck | 1:1cd0afbed23c | 542 | lora_printTxContinuousMode(); |
dudmuck | 0:be215de91a68 | 543 | |
dudmuck | 0:be215de91a68 | 544 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 545 | lora_printAgcAutoOn(); |
dudmuck | 0:be215de91a68 | 546 | if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 547 | printf(" LowDataRateOptimize:%d\r\n", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 548 | } |
dudmuck | 0:be215de91a68 | 549 | |
dudmuck | 0:be215de91a68 | 550 | printf("\r\nHeaderCount:%d PacketCount:%d, ", |
dudmuck | 0:be215de91a68 | 551 | radio.read_u16(REG_LR_RXHEADERCNTVALUE_MSB), radio.read_u16(REG_LR_RXPACKETCNTVALUE_MSB)); |
dudmuck | 0:be215de91a68 | 552 | |
dudmuck | 0:be215de91a68 | 553 | printf("Lora detection threshold:%02x\r\n", radio.read_reg(REG_LR_DETECTION_THRESHOLD)); |
dudmuck | 1:1cd0afbed23c | 554 | lora.RegTest31.octet = radio.read_reg(REG_LR_TEST31); |
dudmuck | 1:1cd0afbed23c | 555 | printf("detect_trig_same_peaks_nb:%d\r\n", lora.RegTest31.bits.detect_trig_same_peaks_nb); |
dudmuck | 0:be215de91a68 | 556 | |
dudmuck | 0:be215de91a68 | 557 | if (radio.type == SX1272) { |
dudmuck | 1:1cd0afbed23c | 558 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 6:fe16f96ee335 | 559 | printf("LowDataRateOptimize:%d ", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 560 | } else if (radio.type == SX1276) { |
dudmuck | 1:1cd0afbed23c | 561 | lora.RegModemConfig3.octet = radio.read_reg(REG_LR_MODEMCONFIG3); |
dudmuck | 6:fe16f96ee335 | 562 | printf("LowDataRateOptimize:%d ", lora.RegModemConfig3.sx1276bits.LowDataRateOptimize); |
dudmuck | 0:be215de91a68 | 563 | } |
dudmuck | 0:be215de91a68 | 564 | |
dudmuck | 6:fe16f96ee335 | 565 | printf(" invert: rx=%d tx=%d\r\n", lora.RegTest33.bits.invert_i_q, !lora.RegTest33.bits.chirp_invert_tx); |
dudmuck | 6:fe16f96ee335 | 566 | |
dudmuck | 0:be215de91a68 | 567 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 568 | //printf("A %02x\r\n", radio.RegModemConfig2.octet); |
dudmuck | 0:be215de91a68 | 569 | } |
dudmuck | 0:be215de91a68 | 570 | |
dudmuck | 1:1cd0afbed23c | 571 | uint16_t |
dudmuck | 1:1cd0afbed23c | 572 | fsk_get_PayloadLength(void) |
dudmuck | 1:1cd0afbed23c | 573 | { |
dudmuck | 1:1cd0afbed23c | 574 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 1:1cd0afbed23c | 575 | |
dudmuck | 1:1cd0afbed23c | 576 | return fsk.RegPktConfig2.bits.PayloadLength; |
dudmuck | 1:1cd0afbed23c | 577 | } |
dudmuck | 1:1cd0afbed23c | 578 | |
dudmuck | 1:1cd0afbed23c | 579 | void fsk_printAddressFiltering() |
dudmuck | 1:1cd0afbed23c | 580 | { |
dudmuck | 1:1cd0afbed23c | 581 | uint8_t FSKRegNodeAdrs, FSKRegBroadcastAdrs; |
dudmuck | 1:1cd0afbed23c | 582 | |
dudmuck | 1:1cd0afbed23c | 583 | printf(" AddressFiltering:"); |
dudmuck | 1:1cd0afbed23c | 584 | switch (fsk.RegPktConfig1.bits.AddressFiltering) { |
dudmuck | 1:1cd0afbed23c | 585 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 586 | case 1: // NodeAddress |
dudmuck | 1:1cd0afbed23c | 587 | FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); |
dudmuck | 6:fe16f96ee335 | 588 | printf("NodeAdrs:%02x\r\n", FSKRegNodeAdrs); |
dudmuck | 1:1cd0afbed23c | 589 | break; |
dudmuck | 1:1cd0afbed23c | 590 | case 2: // NodeAddress & BroadcastAddress |
dudmuck | 1:1cd0afbed23c | 591 | FSKRegNodeAdrs = radio.read_reg(REG_FSK_NODEADRS); |
dudmuck | 1:1cd0afbed23c | 592 | printf("NodeAdrs:%02x ", FSKRegNodeAdrs); |
dudmuck | 1:1cd0afbed23c | 593 | FSKRegBroadcastAdrs = radio.read_reg(REG_FSK_BROADCASTADRS); |
dudmuck | 6:fe16f96ee335 | 594 | printf("BroadcastAdrs:%02x\r\n", FSKRegBroadcastAdrs ); |
dudmuck | 1:1cd0afbed23c | 595 | break; |
dudmuck | 1:1cd0afbed23c | 596 | default: |
dudmuck | 1:1cd0afbed23c | 597 | printf("%d", fsk.RegPktConfig1.bits.AddressFiltering); |
dudmuck | 1:1cd0afbed23c | 598 | break; |
dudmuck | 1:1cd0afbed23c | 599 | } |
dudmuck | 1:1cd0afbed23c | 600 | } |
dudmuck | 1:1cd0afbed23c | 601 | |
dudmuck | 1:1cd0afbed23c | 602 | void fsk_print_IrqFlags2() |
dudmuck | 1:1cd0afbed23c | 603 | { |
dudmuck | 2:c6b23a43a9d9 | 604 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 1:1cd0afbed23c | 605 | |
dudmuck | 1:1cd0afbed23c | 606 | printf("IrqFlags2: "); |
dudmuck | 2:c6b23a43a9d9 | 607 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 2:c6b23a43a9d9 | 608 | if (RegIrqFlags2.bits.FifoFull) |
dudmuck | 1:1cd0afbed23c | 609 | printf("FifoFull "); |
dudmuck | 2:c6b23a43a9d9 | 610 | if (RegIrqFlags2.bits.FifoEmpty) |
dudmuck | 1:1cd0afbed23c | 611 | printf("FifoEmpty "); |
dudmuck | 2:c6b23a43a9d9 | 612 | if (RegIrqFlags2.bits.FifoLevel) |
dudmuck | 1:1cd0afbed23c | 613 | printf("FifoLevel "); |
dudmuck | 2:c6b23a43a9d9 | 614 | if (RegIrqFlags2.bits.FifoOverrun) |
dudmuck | 1:1cd0afbed23c | 615 | printf("FifoOverrun "); |
dudmuck | 2:c6b23a43a9d9 | 616 | if (RegIrqFlags2.bits.PacketSent) |
dudmuck | 1:1cd0afbed23c | 617 | printf("PacketSent "); |
dudmuck | 2:c6b23a43a9d9 | 618 | if (RegIrqFlags2.bits.PayloadReady) |
dudmuck | 1:1cd0afbed23c | 619 | printf("PayloadReady "); |
dudmuck | 2:c6b23a43a9d9 | 620 | if (RegIrqFlags2.bits.CrcOk) |
dudmuck | 1:1cd0afbed23c | 621 | printf("CrcOk "); |
dudmuck | 2:c6b23a43a9d9 | 622 | if (RegIrqFlags2.bits.LowBat) |
dudmuck | 1:1cd0afbed23c | 623 | printf("LowBat "); |
dudmuck | 2:c6b23a43a9d9 | 624 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 625 | } |
dudmuck | 1:1cd0afbed23c | 626 | |
dudmuck | 1:1cd0afbed23c | 627 | void |
dudmuck | 1:1cd0afbed23c | 628 | fsk_print_status() |
dudmuck | 1:1cd0afbed23c | 629 | { |
dudmuck | 1:1cd0afbed23c | 630 | //uint16_t s; |
dudmuck | 2:c6b23a43a9d9 | 631 | RegIrqFlags1_t RegIrqFlags1; |
dudmuck | 1:1cd0afbed23c | 632 | |
dudmuck | 1:1cd0afbed23c | 633 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 1:1cd0afbed23c | 634 | printf("LoRa\r\n"); |
dudmuck | 1:1cd0afbed23c | 635 | return; |
dudmuck | 1:1cd0afbed23c | 636 | } |
dudmuck | 1:1cd0afbed23c | 637 | |
dudmuck | 1:1cd0afbed23c | 638 | if (radio.RegOpMode.bits.ModulationType == 0) { |
dudmuck | 1:1cd0afbed23c | 639 | printf("FSK "); |
dudmuck | 1:1cd0afbed23c | 640 | switch (radio.RegOpMode.bits.ModulationShaping) { |
dudmuck | 1:1cd0afbed23c | 641 | case 1: printf("BT1.0 "); break; |
dudmuck | 1:1cd0afbed23c | 642 | case 2: printf("BT0.5 "); break; |
dudmuck | 1:1cd0afbed23c | 643 | case 3: printf("BT0.3 "); break; |
dudmuck | 1:1cd0afbed23c | 644 | } |
dudmuck | 1:1cd0afbed23c | 645 | } else if (radio.RegOpMode.bits.ModulationType == 1) { |
dudmuck | 1:1cd0afbed23c | 646 | printf("OOK "); |
dudmuck | 18:9530d682fd9a | 647 | switch (radio.RegOpMode.bits.ModulationShaping) { |
dudmuck | 18:9530d682fd9a | 648 | case 1: printf("Fcutoff=bitrate"); break; |
dudmuck | 18:9530d682fd9a | 649 | case 2: printf("Fcutoff=2*bitrate"); break; |
dudmuck | 18:9530d682fd9a | 650 | case 3: printf("?"); break; |
dudmuck | 18:9530d682fd9a | 651 | } |
dudmuck | 1:1cd0afbed23c | 652 | } |
dudmuck | 1:1cd0afbed23c | 653 | |
dudmuck | 19:be8a8b0e7320 | 654 | printf("%" PRIu32 "bps fdev:%" PRIu32 "Hz\r\n", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 1:1cd0afbed23c | 655 | |
dudmuck | 1:1cd0afbed23c | 656 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 1:1cd0afbed23c | 657 | |
dudmuck | 1:1cd0afbed23c | 658 | fsk_print_dio(); |
dudmuck | 1:1cd0afbed23c | 659 | |
dudmuck | 19:be8a8b0e7320 | 660 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 19:be8a8b0e7320 | 661 | printf("afcbw:%" PRIu32 "Hz\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW)); |
dudmuck | 1:1cd0afbed23c | 662 | |
dudmuck | 1:1cd0afbed23c | 663 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 1:1cd0afbed23c | 664 | printf("RssiOffset:%ddB smoothing:%dsamples\r\n", fsk.RegRssiConfig.bits.RssiOffset, 1 << (fsk.RegRssiConfig.bits.RssiSmoothing+1)); |
dudmuck | 1:1cd0afbed23c | 665 | |
dudmuck | 1:1cd0afbed23c | 666 | |
dudmuck | 1:1cd0afbed23c | 667 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 1:1cd0afbed23c | 668 | |
dudmuck | 1:1cd0afbed23c | 669 | if (fsk.RegPktConfig2.bits.DataModePacket) { |
dudmuck | 1:1cd0afbed23c | 670 | uint16_t len; |
dudmuck | 1:1cd0afbed23c | 671 | /* packet mode */ |
dudmuck | 1:1cd0afbed23c | 672 | len = fsk_get_PayloadLength(); |
dudmuck | 1:1cd0afbed23c | 673 | printf("packet RegPayloadLength:0x%03x ", len); |
dudmuck | 1:1cd0afbed23c | 674 | |
dudmuck | 1:1cd0afbed23c | 675 | if (fsk.RegPktConfig2.bits.BeaconOn) |
dudmuck | 1:1cd0afbed23c | 676 | printf("BeaconOn "); |
dudmuck | 1:1cd0afbed23c | 677 | |
dudmuck | 1:1cd0afbed23c | 678 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 1:1cd0afbed23c | 679 | printf("FifoThreshold:%d TxStartCondition:", fsk.RegFifoThreshold.bits.FifoThreshold); |
dudmuck | 1:1cd0afbed23c | 680 | if (fsk.RegFifoThreshold.bits.TxStartCondition) |
dudmuck | 1:1cd0afbed23c | 681 | printf("!FifoEmpty"); |
dudmuck | 1:1cd0afbed23c | 682 | else |
dudmuck | 1:1cd0afbed23c | 683 | printf("FifoLevel"); |
dudmuck | 1:1cd0afbed23c | 684 | |
dudmuck | 1:1cd0afbed23c | 685 | printf("\r\nAutoRestartRxMode:"); |
dudmuck | 1:1cd0afbed23c | 686 | switch (fsk.RegSyncConfig.bits.AutoRestartRxMode) { |
dudmuck | 1:1cd0afbed23c | 687 | case 0: printf("off "); break; |
dudmuck | 1:1cd0afbed23c | 688 | case 1: printf("no-pll-wait "); break; |
dudmuck | 1:1cd0afbed23c | 689 | case 2: printf("pll-wait "); break; |
dudmuck | 1:1cd0afbed23c | 690 | case 3: printf("3 "); break; |
dudmuck | 1:1cd0afbed23c | 691 | } |
dudmuck | 1:1cd0afbed23c | 692 | //...todo |
dudmuck | 1:1cd0afbed23c | 693 | |
dudmuck | 1:1cd0afbed23c | 694 | printf("PreambleSize:%d ", radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 1:1cd0afbed23c | 695 | |
dudmuck | 1:1cd0afbed23c | 696 | fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); |
dudmuck | 1:1cd0afbed23c | 697 | if (fsk.RegOokPeak.bits.barker_en) |
dudmuck | 1:1cd0afbed23c | 698 | printf("barker "); |
dudmuck | 1:1cd0afbed23c | 699 | if (!fsk.RegOokPeak.bits.BitSyncOn) |
dudmuck | 1:1cd0afbed23c | 700 | printf("BitSyncOff "); |
dudmuck | 1:1cd0afbed23c | 701 | //...todo |
dudmuck | 1:1cd0afbed23c | 702 | |
dudmuck | 1:1cd0afbed23c | 703 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 1:1cd0afbed23c | 704 | if (fsk.RegPktConfig1.bits.PacketFormatVariable) |
dudmuck | 1:1cd0afbed23c | 705 | printf("variable"); |
dudmuck | 1:1cd0afbed23c | 706 | else |
dudmuck | 1:1cd0afbed23c | 707 | printf("fixed"); |
dudmuck | 1:1cd0afbed23c | 708 | printf("-length\r\ncrc"); |
dudmuck | 1:1cd0afbed23c | 709 | if (fsk.RegPktConfig1.bits.CrcOn) { |
dudmuck | 1:1cd0afbed23c | 710 | printf("On"); |
dudmuck | 1:1cd0afbed23c | 711 | } else |
dudmuck | 1:1cd0afbed23c | 712 | printf("Off"); |
dudmuck | 1:1cd0afbed23c | 713 | printf(" crctype:"); |
dudmuck | 1:1cd0afbed23c | 714 | if (fsk.RegPktConfig1.bits.CrCWhiteningType) |
dudmuck | 1:1cd0afbed23c | 715 | printf("IBM"); |
dudmuck | 1:1cd0afbed23c | 716 | else |
dudmuck | 1:1cd0afbed23c | 717 | printf("CCITT"); |
dudmuck | 1:1cd0afbed23c | 718 | printf(" dcFree:"); |
dudmuck | 1:1cd0afbed23c | 719 | switch (fsk.RegPktConfig1.bits.DcFree) { |
dudmuck | 1:1cd0afbed23c | 720 | case 0: printf("none "); break; |
dudmuck | 1:1cd0afbed23c | 721 | case 1: printf("Manchester "); break; |
dudmuck | 1:1cd0afbed23c | 722 | case 2: printf("Whitening "); break; |
dudmuck | 1:1cd0afbed23c | 723 | case 3: printf("[41mreserved[0m "); break; |
dudmuck | 1:1cd0afbed23c | 724 | } |
dudmuck | 1:1cd0afbed23c | 725 | fsk_printAddressFiltering(); |
dudmuck | 1:1cd0afbed23c | 726 | |
dudmuck | 1:1cd0afbed23c | 727 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 728 | fsk_print_IrqFlags2(); |
dudmuck | 1:1cd0afbed23c | 729 | } else { |
dudmuck | 1:1cd0afbed23c | 730 | /* continuous mode */ |
dudmuck | 1:1cd0afbed23c | 731 | printf("[7mcontinuous[27m "); |
dudmuck | 1:1cd0afbed23c | 732 | } |
dudmuck | 1:1cd0afbed23c | 733 | |
dudmuck | 1:1cd0afbed23c | 734 | fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); |
dudmuck | 1:1cd0afbed23c | 735 | printf("PreambleDetect:"); |
dudmuck | 1:1cd0afbed23c | 736 | if (fsk.RegPreambleDetect.bits.PreambleDetectorOn) { |
dudmuck | 1:1cd0afbed23c | 737 | printf("size=%d,tol=%d ", |
dudmuck | 1:1cd0afbed23c | 738 | fsk.RegPreambleDetect.bits.PreambleDetectorSize, |
dudmuck | 1:1cd0afbed23c | 739 | fsk.RegPreambleDetect.bits.PreambleDetectorTol); |
dudmuck | 1:1cd0afbed23c | 740 | } else |
dudmuck | 1:1cd0afbed23c | 741 | printf("Off "); |
dudmuck | 1:1cd0afbed23c | 742 | |
dudmuck | 18:9530d682fd9a | 743 | if (fsk.RegSyncConfig.bits.SyncOn) { |
dudmuck | 18:9530d682fd9a | 744 | printf(" syncsize:%d ", fsk.RegSyncConfig.bits.SyncSize); |
dudmuck | 18:9530d682fd9a | 745 | printf(" : %02x ", radio.read_reg(REG_FSK_SYNCVALUE1)); |
dudmuck | 18:9530d682fd9a | 746 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE2)); |
dudmuck | 18:9530d682fd9a | 747 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE3)); |
dudmuck | 18:9530d682fd9a | 748 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE4)); |
dudmuck | 18:9530d682fd9a | 749 | } else |
dudmuck | 18:9530d682fd9a | 750 | printf("Sync Off"); |
dudmuck | 1:1cd0afbed23c | 751 | printf("\r\n"); // end sync config |
dudmuck | 1:1cd0afbed23c | 752 | |
dudmuck | 1:1cd0afbed23c | 753 | fsk.RegAfcFei.octet = radio.read_reg(REG_FSK_AFCFEI); |
dudmuck | 1:1cd0afbed23c | 754 | printf("afcAutoClear:"); |
dudmuck | 1:1cd0afbed23c | 755 | if (fsk.RegAfcFei.bits.AfcAutoClearOn) |
dudmuck | 1:1cd0afbed23c | 756 | printf("On"); |
dudmuck | 1:1cd0afbed23c | 757 | else |
dudmuck | 1:1cd0afbed23c | 758 | printf("OFF"); |
dudmuck | 1:1cd0afbed23c | 759 | printf(" afc:%dHz ", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); |
dudmuck | 1:1cd0afbed23c | 760 | |
dudmuck | 1:1cd0afbed23c | 761 | printf("fei:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_FEIMSB))); |
dudmuck | 1:1cd0afbed23c | 762 | |
dudmuck | 1:1cd0afbed23c | 763 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 1:1cd0afbed23c | 764 | printf("RxTrigger:"); |
dudmuck | 1:1cd0afbed23c | 765 | switch (fsk.RegRxConfig.bits.RxTrigger) { |
dudmuck | 1:1cd0afbed23c | 766 | case 0: printf("none "); break; |
dudmuck | 1:1cd0afbed23c | 767 | case 1: printf("rssi "); break; |
dudmuck | 1:1cd0afbed23c | 768 | case 6: printf("preamble "); break; |
dudmuck | 1:1cd0afbed23c | 769 | case 7: printf("both "); break; |
dudmuck | 1:1cd0afbed23c | 770 | default: printf("-%d- ", fsk.RegRxConfig.bits.RxTrigger); break; |
dudmuck | 1:1cd0afbed23c | 771 | } |
dudmuck | 1:1cd0afbed23c | 772 | printf("AfcAuto:"); |
dudmuck | 1:1cd0afbed23c | 773 | if (fsk.RegRxConfig.bits.AfcAutoOn) |
dudmuck | 1:1cd0afbed23c | 774 | printf("On "); |
dudmuck | 1:1cd0afbed23c | 775 | else |
dudmuck | 1:1cd0afbed23c | 776 | printf("OFF "); |
dudmuck | 15:c69b942685ea | 777 | |
dudmuck | 15:c69b942685ea | 778 | radio.RegLna.octet = radio.read_reg(REG_LNA); |
dudmuck | 1:1cd0afbed23c | 779 | if (!fsk.RegRxConfig.bits.AgcAutoOn) { |
dudmuck | 1:1cd0afbed23c | 780 | printf("AgcAutoOff:G%d ", radio.RegLna.bits.LnaGain); |
dudmuck | 1:1cd0afbed23c | 781 | } |
dudmuck | 15:c69b942685ea | 782 | printf("LnaBoostHF:%d ", radio.RegLna.bits.LnaBoostHF); |
dudmuck | 1:1cd0afbed23c | 783 | |
dudmuck | 1:1cd0afbed23c | 784 | fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); |
dudmuck | 1:1cd0afbed23c | 785 | if (fsk.RegTimerResol.bits.hlm_started) |
dudmuck | 1:1cd0afbed23c | 786 | printf("[35mhlm_started[0m "); |
dudmuck | 1:1cd0afbed23c | 787 | else |
dudmuck | 1:1cd0afbed23c | 788 | printf("hlm_stopped "); |
dudmuck | 1:1cd0afbed23c | 789 | |
dudmuck | 1:1cd0afbed23c | 790 | fsk.RegRssiThresh = radio.read_reg(REG_FSK_RSSITHRESH); |
dudmuck | 1:1cd0afbed23c | 791 | printf("rssiThreshold:-%.1f@%02x ", fsk.RegRssiThresh / 2.0, REG_FSK_RSSITHRESH); |
dudmuck | 1:1cd0afbed23c | 792 | |
dudmuck | 1:1cd0afbed23c | 793 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 1:1cd0afbed23c | 794 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || |
dudmuck | 1:1cd0afbed23c | 795 | radio.RegOpMode.bits.Mode == RF_OPMODE_SYNTHESIZER_RX) |
dudmuck | 1:1cd0afbed23c | 796 | { |
dudmuck | 1:1cd0afbed23c | 797 | printf("rssi:-%.1f ", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 1:1cd0afbed23c | 798 | } |
dudmuck | 1:1cd0afbed23c | 799 | |
dudmuck | 1:1cd0afbed23c | 800 | fsk.RegSeqConfig1.octet = radio.read_reg(REG_FSK_SEQCONFIG1); |
dudmuck | 1:1cd0afbed23c | 801 | printf("\r\nsequencer: "); |
dudmuck | 1:1cd0afbed23c | 802 | printf("FromStart:"); |
dudmuck | 1:1cd0afbed23c | 803 | switch (fsk.RegSeqConfig1.bits.FromStart) { |
dudmuck | 1:1cd0afbed23c | 804 | case 0: |
dudmuck | 1:1cd0afbed23c | 805 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 806 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 807 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 808 | else |
dudmuck | 1:1cd0afbed23c | 809 | printf("sequencerOff"); |
dudmuck | 1:1cd0afbed23c | 810 | break; |
dudmuck | 1:1cd0afbed23c | 811 | case 1: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 812 | case 2: printf("tx"); break; |
dudmuck | 1:1cd0afbed23c | 813 | case 3: printf("tx on fifolevel"); break; |
dudmuck | 1:1cd0afbed23c | 814 | } |
dudmuck | 1:1cd0afbed23c | 815 | printf(" lowPowerSelection:"); |
dudmuck | 1:1cd0afbed23c | 816 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 817 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 818 | else |
dudmuck | 1:1cd0afbed23c | 819 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 820 | if (fsk.RegSeqConfig1.bits.FromStart != 0 && |
dudmuck | 1:1cd0afbed23c | 821 | fsk.RegSeqConfig1.bits.LowPowerSelection != 0) |
dudmuck | 1:1cd0afbed23c | 822 | { // if sequencer enabled: |
dudmuck | 1:1cd0afbed23c | 823 | printf("\r\nsequencer: IdleMode:"); |
dudmuck | 1:1cd0afbed23c | 824 | if (fsk.RegSeqConfig1.bits.IdleMode) |
dudmuck | 1:1cd0afbed23c | 825 | printf("Sleep"); |
dudmuck | 1:1cd0afbed23c | 826 | else |
dudmuck | 1:1cd0afbed23c | 827 | printf("standby"); |
dudmuck | 1:1cd0afbed23c | 828 | printf("\r\nsequencer: FromIdle to:"); |
dudmuck | 1:1cd0afbed23c | 829 | if (fsk.RegSeqConfig1.bits.FromIdle) |
dudmuck | 1:1cd0afbed23c | 830 | printf("rx"); |
dudmuck | 1:1cd0afbed23c | 831 | else |
dudmuck | 1:1cd0afbed23c | 832 | printf("tx"); |
dudmuck | 1:1cd0afbed23c | 833 | printf("\r\nsequencer: FromTransmit to:"); |
dudmuck | 1:1cd0afbed23c | 834 | if (fsk.RegSeqConfig1.bits.FromTransmit) |
dudmuck | 1:1cd0afbed23c | 835 | printf("rx-on-PacketSent"); |
dudmuck | 1:1cd0afbed23c | 836 | else { |
dudmuck | 1:1cd0afbed23c | 837 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 838 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 839 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 840 | else |
dudmuck | 1:1cd0afbed23c | 841 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 842 | printf("-on-PacketSent"); |
dudmuck | 1:1cd0afbed23c | 843 | } |
dudmuck | 1:1cd0afbed23c | 844 | fsk.RegSeqConfig2.octet = radio.read_reg(REG_FSK_SEQCONFIG2); |
dudmuck | 1:1cd0afbed23c | 845 | printf("\r\nsequencer: FromReceive:"); |
dudmuck | 1:1cd0afbed23c | 846 | switch (fsk.RegSeqConfig2.bits.FromReceive) { |
dudmuck | 1:1cd0afbed23c | 847 | case 1: printf("PacketRecevied on PayloadReady"); break; |
dudmuck | 1:1cd0afbed23c | 848 | case 2: |
dudmuck | 1:1cd0afbed23c | 849 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 850 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 851 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 852 | else |
dudmuck | 1:1cd0afbed23c | 853 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 854 | printf("-on-payloadReady"); |
dudmuck | 1:1cd0afbed23c | 855 | break; |
dudmuck | 1:1cd0afbed23c | 856 | case 3: printf("PacketRecevied-on-CrcOk"); break; |
dudmuck | 1:1cd0afbed23c | 857 | case 4: printf("SequencerOff-on-Rssi"); break; |
dudmuck | 1:1cd0afbed23c | 858 | case 5: printf("SequencerOff-on-SyncAddress"); break; |
dudmuck | 1:1cd0afbed23c | 859 | case 6: printf("SequencerOff-PreambleDetect"); break; |
dudmuck | 1:1cd0afbed23c | 860 | default: printf("-%d-", fsk.RegSeqConfig2.bits.FromReceive); break; |
dudmuck | 1:1cd0afbed23c | 861 | } |
dudmuck | 1:1cd0afbed23c | 862 | printf("\r\nsequencer: FromRxTimeout:"); |
dudmuck | 1:1cd0afbed23c | 863 | switch (fsk.RegSeqConfig2.bits.FromRxTimeout) { |
dudmuck | 1:1cd0afbed23c | 864 | case 0: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 865 | case 1: printf("tx"); break; |
dudmuck | 1:1cd0afbed23c | 866 | case 2: |
dudmuck | 1:1cd0afbed23c | 867 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 868 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 869 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 870 | else |
dudmuck | 1:1cd0afbed23c | 871 | printf("SequencerOff"); |
dudmuck | 1:1cd0afbed23c | 872 | break; |
dudmuck | 1:1cd0afbed23c | 873 | case 3: printf("SequencerOff"); break; |
dudmuck | 1:1cd0afbed23c | 874 | } |
dudmuck | 1:1cd0afbed23c | 875 | printf("\r\nsequencer: FromPacketReceived to:"); |
dudmuck | 1:1cd0afbed23c | 876 | switch (fsk.RegSeqConfig2.bits.FromPacketReceived) { |
dudmuck | 1:1cd0afbed23c | 877 | case 0: printf("SequencerOff"); break; |
dudmuck | 1:1cd0afbed23c | 878 | case 1: printf("tx on FifoEmpty"); break; |
dudmuck | 1:1cd0afbed23c | 879 | case 2: |
dudmuck | 1:1cd0afbed23c | 880 | printf("lowPowerSelection-"); |
dudmuck | 1:1cd0afbed23c | 881 | if (fsk.RegSeqConfig1.bits.LowPowerSelection) |
dudmuck | 1:1cd0afbed23c | 882 | printf("idle"); |
dudmuck | 1:1cd0afbed23c | 883 | else |
dudmuck | 1:1cd0afbed23c | 884 | printf("sequencerOff"); |
dudmuck | 1:1cd0afbed23c | 885 | break; |
dudmuck | 1:1cd0afbed23c | 886 | case 3: printf("rx via fs"); break; |
dudmuck | 1:1cd0afbed23c | 887 | case 4: printf("rx"); break; |
dudmuck | 1:1cd0afbed23c | 888 | } |
dudmuck | 1:1cd0afbed23c | 889 | |
dudmuck | 1:1cd0afbed23c | 890 | fsk.RegTimerResol.octet = radio.read_reg(REG_FSK_TIMERRESOL); |
dudmuck | 1:1cd0afbed23c | 891 | printf("\r\nsequencer: timer1:"); |
dudmuck | 1:1cd0afbed23c | 892 | switch (fsk.RegTimerResol.bits.timer1_resol) { |
dudmuck | 1:1cd0afbed23c | 893 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 894 | case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER1COEF) * 64); break; |
dudmuck | 1:1cd0afbed23c | 895 | case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER1COEF) * 4.1); break; |
dudmuck | 1:1cd0afbed23c | 896 | case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER1COEF) * 0.262); break; |
dudmuck | 1:1cd0afbed23c | 897 | } |
dudmuck | 1:1cd0afbed23c | 898 | |
dudmuck | 1:1cd0afbed23c | 899 | printf(" timer2:"); |
dudmuck | 1:1cd0afbed23c | 900 | switch (fsk.RegTimerResol.bits.timer2_resol) { |
dudmuck | 1:1cd0afbed23c | 901 | case 0: printf("off"); break; |
dudmuck | 1:1cd0afbed23c | 902 | case 1: printf("%dus", radio.read_reg(REG_FSK_TIMER2COEF) * 64); break; |
dudmuck | 1:1cd0afbed23c | 903 | case 2: printf("%.1fms", radio.read_reg(REG_FSK_TIMER2COEF) * 4.1); break; |
dudmuck | 1:1cd0afbed23c | 904 | case 3: printf("%.1fs", radio.read_reg(REG_FSK_TIMER2COEF) * 0.262); break; |
dudmuck | 1:1cd0afbed23c | 905 | } |
dudmuck | 1:1cd0afbed23c | 906 | } // ..if sequencer enabled |
dudmuck | 1:1cd0afbed23c | 907 | |
dudmuck | 1:1cd0afbed23c | 908 | printf("\r\nIrqFlags1:"); |
dudmuck | 2:c6b23a43a9d9 | 909 | RegIrqFlags1.octet = radio.read_reg(REG_FSK_IRQFLAGS1); |
dudmuck | 2:c6b23a43a9d9 | 910 | if (RegIrqFlags1.bits.ModeReady) |
dudmuck | 1:1cd0afbed23c | 911 | printf("ModeReady "); |
dudmuck | 2:c6b23a43a9d9 | 912 | if (RegIrqFlags1.bits.RxReady) |
dudmuck | 1:1cd0afbed23c | 913 | printf("RxReady "); |
dudmuck | 2:c6b23a43a9d9 | 914 | if (RegIrqFlags1.bits.TxReady) |
dudmuck | 1:1cd0afbed23c | 915 | printf("TxReady "); |
dudmuck | 2:c6b23a43a9d9 | 916 | if (RegIrqFlags1.bits.PllLock) |
dudmuck | 1:1cd0afbed23c | 917 | printf("PllLock "); |
dudmuck | 2:c6b23a43a9d9 | 918 | if (RegIrqFlags1.bits.Rssi) |
dudmuck | 1:1cd0afbed23c | 919 | printf("Rssi "); |
dudmuck | 2:c6b23a43a9d9 | 920 | if (RegIrqFlags1.bits.Timeout) |
dudmuck | 1:1cd0afbed23c | 921 | printf("Timeout "); |
dudmuck | 2:c6b23a43a9d9 | 922 | if (RegIrqFlags1.bits.PreambleDetect) |
dudmuck | 1:1cd0afbed23c | 923 | printf("PreambleDetect "); |
dudmuck | 2:c6b23a43a9d9 | 924 | if (RegIrqFlags1.bits.SyncAddressMatch) |
dudmuck | 1:1cd0afbed23c | 925 | printf("SyncAddressMatch "); |
dudmuck | 1:1cd0afbed23c | 926 | |
dudmuck | 1:1cd0afbed23c | 927 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 928 | |
dudmuck | 1:1cd0afbed23c | 929 | /* TODO if (!SX1272FSK->RegPktConfig1.bits.PacketFormatVariable) { // if fixed-length packet format: |
dudmuck | 1:1cd0afbed23c | 930 | s = fsk_get_PayloadLength(); |
dudmuck | 1:1cd0afbed23c | 931 | if (s > FSK_LARGE_PKT_THRESHOLD) |
dudmuck | 1:1cd0afbed23c | 932 | flags.fifo_flow_ctl = 1; |
dudmuck | 1:1cd0afbed23c | 933 | else |
dudmuck | 1:1cd0afbed23c | 934 | flags.fifo_flow_ctl = 0; |
dudmuck | 1:1cd0afbed23c | 935 | }*/ |
dudmuck | 1:1cd0afbed23c | 936 | |
dudmuck | 1:1cd0afbed23c | 937 | fsk.RegImageCal.octet = radio.read_reg(REG_FSK_IMAGECAL); |
dudmuck | 1:1cd0afbed23c | 938 | if (fsk.RegImageCal.bits.TempMonitorOff) { |
dudmuck | 1:1cd0afbed23c | 939 | printf("[42mTempMonitorOff[\r0m\n"); |
dudmuck | 1:1cd0afbed23c | 940 | } else { |
dudmuck | 1:1cd0afbed23c | 941 | printf("TempThreshold:"); |
dudmuck | 1:1cd0afbed23c | 942 | switch (fsk.RegImageCal.bits.TempThreshold) { |
dudmuck | 1:1cd0afbed23c | 943 | case 0: printf("5C"); break; |
dudmuck | 1:1cd0afbed23c | 944 | case 1: printf("10C"); break; |
dudmuck | 1:1cd0afbed23c | 945 | case 2: printf("15C"); break; |
dudmuck | 1:1cd0afbed23c | 946 | case 3: printf("20C"); break; |
dudmuck | 1:1cd0afbed23c | 947 | } |
dudmuck | 1:1cd0afbed23c | 948 | printf("\r\n"); |
dudmuck | 1:1cd0afbed23c | 949 | } |
dudmuck | 1:1cd0afbed23c | 950 | if (fsk.RegImageCal.bits.ImageCalRunning) |
dudmuck | 1:1cd0afbed23c | 951 | printf("[33mImageCalRunning[\r0m\n"); |
dudmuck | 21:b84a77dfb43c | 952 | |
dudmuck | 21:b84a77dfb43c | 953 | if (rx_payloadReady_int_en) { |
dudmuck | 21:b84a77dfb43c | 954 | printf("n_rx_pkts:%u, dio:%u,%u,%u,%u,%u\r\n", n_rx_pkts, dio4.read(), dio3.read(), dio2.read(), radio.dio1.read(), radio.dio0.read()); |
dudmuck | 21:b84a77dfb43c | 955 | } |
dudmuck | 1:1cd0afbed23c | 956 | } |
dudmuck | 1:1cd0afbed23c | 957 | |
dudmuck | 0:be215de91a68 | 958 | void printOpMode() |
dudmuck | 0:be215de91a68 | 959 | { |
dudmuck | 0:be215de91a68 | 960 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 0:be215de91a68 | 961 | switch (radio.RegOpMode.bits.Mode) { |
dudmuck | 0:be215de91a68 | 962 | case RF_OPMODE_SLEEP: printf("[7msleep[0m"); break; |
dudmuck | 0:be215de91a68 | 963 | case RF_OPMODE_STANDBY: printf("[7mstby[0m"); break; |
dudmuck | 0:be215de91a68 | 964 | case RF_OPMODE_SYNTHESIZER_TX: printf("[33mfstx[0m"); break; |
dudmuck | 0:be215de91a68 | 965 | case RF_OPMODE_TRANSMITTER: printf("[31mtx[0m"); break; |
dudmuck | 0:be215de91a68 | 966 | case RF_OPMODE_SYNTHESIZER_RX: printf("[33mfsrx[0m"); break; |
dudmuck | 0:be215de91a68 | 967 | case RF_OPMODE_RECEIVER: printf("[32mrx[0m"); break; |
dudmuck | 0:be215de91a68 | 968 | case 6: |
dudmuck | 0:be215de91a68 | 969 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 0:be215de91a68 | 970 | printf("[42mrxs[0m"); |
dudmuck | 0:be215de91a68 | 971 | else |
dudmuck | 0:be215de91a68 | 972 | printf("-6-"); |
dudmuck | 0:be215de91a68 | 973 | break; // todo: different lora/fsk |
dudmuck | 0:be215de91a68 | 974 | case 7: |
dudmuck | 0:be215de91a68 | 975 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 0:be215de91a68 | 976 | printf("[45mcad[0m"); |
dudmuck | 0:be215de91a68 | 977 | else |
dudmuck | 0:be215de91a68 | 978 | printf("-7-"); |
dudmuck | 0:be215de91a68 | 979 | break; // todo: different lora/fsk |
dudmuck | 0:be215de91a68 | 980 | } |
dudmuck | 0:be215de91a68 | 981 | } |
dudmuck | 0:be215de91a68 | 982 | |
dudmuck | 0:be215de91a68 | 983 | void |
dudmuck | 0:be215de91a68 | 984 | printPa() |
dudmuck | 0:be215de91a68 | 985 | { |
dudmuck | 0:be215de91a68 | 986 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 0:be215de91a68 | 987 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 0:be215de91a68 | 988 | float output_dBm = 17 - (15-radio.RegPaConfig.bits.OutputPower); |
dudmuck | 0:be215de91a68 | 989 | printf(" PABOOST OutputPower=%.1fdBm", output_dBm); |
dudmuck | 0:be215de91a68 | 990 | } else { |
dudmuck | 0:be215de91a68 | 991 | float pmax = (0.6*radio.RegPaConfig.bits.MaxPower) + 10.8; |
dudmuck | 0:be215de91a68 | 992 | float output_dBm = pmax - (15-radio.RegPaConfig.bits.OutputPower); |
dudmuck | 20:b11592c9ba5f | 993 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 20:b11592c9ba5f | 994 | printf(" \x1b[31mRFO pmax=%.1fdBm OutputPower=%.1fdBm\x1b[0m", pmax, output_dBm); // not connected |
dudmuck | 20:b11592c9ba5f | 995 | #else |
dudmuck | 0:be215de91a68 | 996 | printf(" RFO pmax=%.1fdBm OutputPower=%.1fdBm", pmax, output_dBm); |
dudmuck | 20:b11592c9ba5f | 997 | #endif |
dudmuck | 0:be215de91a68 | 998 | } |
dudmuck | 0:be215de91a68 | 999 | } |
dudmuck | 0:be215de91a68 | 1000 | |
dudmuck | 0:be215de91a68 | 1001 | void /* things always present, whether lora or fsk */ |
dudmuck | 0:be215de91a68 | 1002 | common_print_status() |
dudmuck | 0:be215de91a68 | 1003 | { |
dudmuck | 0:be215de91a68 | 1004 | printf("version:0x%02x %.3fMHz ", radio.read_reg(REG_VERSION), radio.get_frf_MHz()); |
dudmuck | 0:be215de91a68 | 1005 | printOpMode(); |
dudmuck | 0:be215de91a68 | 1006 | |
dudmuck | 0:be215de91a68 | 1007 | printPa(); |
dudmuck | 0:be215de91a68 | 1008 | |
dudmuck | 0:be215de91a68 | 1009 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 0:be215de91a68 | 1010 | if (radio.RegOcp.bits.OcpOn) { |
dudmuck | 0:be215de91a68 | 1011 | int imax = 0; |
dudmuck | 0:be215de91a68 | 1012 | if (radio.RegOcp.bits.OcpTrim < 16) |
dudmuck | 0:be215de91a68 | 1013 | imax = 45 + (5 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 0:be215de91a68 | 1014 | else if (radio.RegOcp.bits.OcpTrim < 28) |
dudmuck | 0:be215de91a68 | 1015 | imax = -30 + (10 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 0:be215de91a68 | 1016 | else |
dudmuck | 0:be215de91a68 | 1017 | imax = 240; |
dudmuck | 0:be215de91a68 | 1018 | printf(" OcpOn %dmA ", imax); |
dudmuck | 0:be215de91a68 | 1019 | } else |
dudmuck | 0:be215de91a68 | 1020 | printf(" OcpOFF "); |
dudmuck | 0:be215de91a68 | 1021 | |
dudmuck | 0:be215de91a68 | 1022 | printf("\r\n"); |
dudmuck | 8:227605e4a760 | 1023 | |
dudmuck | 8:227605e4a760 | 1024 | if (per_en) { |
dudmuck | 18:9530d682fd9a | 1025 | if (cadper_enable) { |
dudmuck | 19:be8a8b0e7320 | 1026 | printf("cadper %" PRIu32 ", ", num_cads); |
dudmuck | 18:9530d682fd9a | 1027 | } |
dudmuck | 8:227605e4a760 | 1028 | printf("per_tx_delay:%f\r\n", per_tx_delay); |
dudmuck | 8:227605e4a760 | 1029 | printf("PER device ID:%d\r\n", per_id); |
dudmuck | 8:227605e4a760 | 1030 | } |
dudmuck | 18:9530d682fd9a | 1031 | |
dudmuck | 20:b11592c9ba5f | 1032 | if (poll_irq_en) { |
dudmuck | 18:9530d682fd9a | 1033 | printf("poll_irq_en\r\n"); |
dudmuck | 20:b11592c9ba5f | 1034 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 20:b11592c9ba5f | 1035 | printf("saved irqs: %02x %02x\r\n", fsk_RegIrqFlags1_prev.octet, fsk_RegIrqFlags2_prev.octet); |
dudmuck | 20:b11592c9ba5f | 1036 | } |
dudmuck | 20:b11592c9ba5f | 1037 | } |
dudmuck | 0:be215de91a68 | 1038 | |
dudmuck | 0:be215de91a68 | 1039 | } |
dudmuck | 0:be215de91a68 | 1040 | |
dudmuck | 0:be215de91a68 | 1041 | void print_rx_buf(int len) |
dudmuck | 0:be215de91a68 | 1042 | { |
dudmuck | 0:be215de91a68 | 1043 | int i; |
dudmuck | 0:be215de91a68 | 1044 | |
dudmuck | 0:be215de91a68 | 1045 | printf("000:"); |
dudmuck | 0:be215de91a68 | 1046 | for (i = 0; i < len; i++) { |
dudmuck | 0:be215de91a68 | 1047 | //printf("(%d)%02x ", i % 16, rx_buf[i]); |
dudmuck | 0:be215de91a68 | 1048 | printf("%02x ", radio.rx_buf[i]); |
dudmuck | 0:be215de91a68 | 1049 | if (i % 16 == 15 && i != len-1) |
dudmuck | 0:be215de91a68 | 1050 | printf("\r\n%03d:", i+1); |
dudmuck | 0:be215de91a68 | 1051 | |
dudmuck | 0:be215de91a68 | 1052 | } |
dudmuck | 0:be215de91a68 | 1053 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 1054 | } |
dudmuck | 0:be215de91a68 | 1055 | |
dudmuck | 21:b84a77dfb43c | 1056 | void lora_print_rx_verbose(uint8_t dlen) |
dudmuck | 7:c3c54f222ced | 1057 | { |
dudmuck | 7:c3c54f222ced | 1058 | float dbm; |
dudmuck | 7:c3c54f222ced | 1059 | printLoraIrqs_(false); |
dudmuck | 7:c3c54f222ced | 1060 | if (lora.RegHopPeriod > 0) { |
dudmuck | 7:c3c54f222ced | 1061 | lora.RegHopChannel.octet = radio.read_reg(REG_LR_HOPCHANNEL); |
dudmuck | 7:c3c54f222ced | 1062 | printf("HopCH:%d ", lora.RegHopChannel.bits.FhssPresentChannel); |
dudmuck | 7:c3c54f222ced | 1063 | } |
dudmuck | 7:c3c54f222ced | 1064 | printf("%dHz ", lora.get_freq_error_Hz()); |
dudmuck | 7:c3c54f222ced | 1065 | lora_printCodingRate(true); // true: of received packet |
dudmuck | 7:c3c54f222ced | 1066 | dbm = lora.get_pkt_rssi(); |
dudmuck | 7:c3c54f222ced | 1067 | printf(" crc%s %.1fdB %.1fdBm\r\n", |
dudmuck | 7:c3c54f222ced | 1068 | lora.RegHopChannel.bits.RxPayloadCrcOn ? "On" : "OFF", |
dudmuck | 7:c3c54f222ced | 1069 | lora.RegPktSnrValue / 4.0, |
dudmuck | 7:c3c54f222ced | 1070 | dbm |
dudmuck | 7:c3c54f222ced | 1071 | ); |
dudmuck | 7:c3c54f222ced | 1072 | print_rx_buf(dlen); |
dudmuck | 18:9530d682fd9a | 1073 | } |
dudmuck | 7:c3c54f222ced | 1074 | |
dudmuck | 18:9530d682fd9a | 1075 | void set_per_en(bool en) |
dudmuck | 18:9530d682fd9a | 1076 | { |
dudmuck | 18:9530d682fd9a | 1077 | if (en) { |
dudmuck | 18:9530d682fd9a | 1078 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 1079 | if (radio.type == SX1272) { |
dudmuck | 18:9530d682fd9a | 1080 | lora.RegModemConfig.sx1272bits.LowDataRateOptimize = 1; |
dudmuck | 18:9530d682fd9a | 1081 | radio.write_reg(REG_LR_MODEMCONFIG, lora.RegModemConfig.octet); |
dudmuck | 18:9530d682fd9a | 1082 | } else if (radio.type == SX1276) { |
dudmuck | 18:9530d682fd9a | 1083 | lora.RegModemConfig3.sx1276bits.LowDataRateOptimize = 1; |
dudmuck | 18:9530d682fd9a | 1084 | radio.write_reg(REG_LR_MODEMCONFIG3, lora.RegModemConfig3.octet); |
dudmuck | 18:9530d682fd9a | 1085 | } |
dudmuck | 18:9530d682fd9a | 1086 | lora.RegPayloadLength = 9; |
dudmuck | 18:9530d682fd9a | 1087 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1088 | radio.RegDioMapping1.bits.Dio3Mapping = 1; // to ValidHeader |
dudmuck | 18:9530d682fd9a | 1089 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 1090 | } else { // fsk.. |
dudmuck | 18:9530d682fd9a | 1091 | //fsk_tx_length = 9; |
dudmuck | 7:c3c54f222ced | 1092 | } |
dudmuck | 20:b11592c9ba5f | 1093 | PacketRxSequencePrev = 0; // transmitter side PacketTxCnt is 1 at first TX |
dudmuck | 18:9530d682fd9a | 1094 | //PacketRxSequence = 0; |
dudmuck | 18:9530d682fd9a | 1095 | PacketPerKoCnt = 0; |
dudmuck | 18:9530d682fd9a | 1096 | PacketPerOkCnt = 0; |
dudmuck | 18:9530d682fd9a | 1097 | PacketNormalCnt = 0; |
dudmuck | 18:9530d682fd9a | 1098 | } // ..if (per_en) |
dudmuck | 18:9530d682fd9a | 1099 | else { |
dudmuck | 18:9530d682fd9a | 1100 | per_timeout.detach(); |
dudmuck | 18:9530d682fd9a | 1101 | } |
dudmuck | 18:9530d682fd9a | 1102 | |
dudmuck | 18:9530d682fd9a | 1103 | per_en = en; |
dudmuck | 18:9530d682fd9a | 1104 | } |
dudmuck | 7:c3c54f222ced | 1105 | |
dudmuck | 8:227605e4a760 | 1106 | void per_cb() |
dudmuck | 8:227605e4a760 | 1107 | { |
dudmuck | 8:227605e4a760 | 1108 | int i; |
dudmuck | 8:227605e4a760 | 1109 | |
dudmuck | 8:227605e4a760 | 1110 | PacketTxCnt++; |
dudmuck | 8:227605e4a760 | 1111 | |
dudmuck | 8:227605e4a760 | 1112 | radio.tx_buf[0] = per_id; |
dudmuck | 8:227605e4a760 | 1113 | radio.tx_buf[1] = PacketTxCnt >> 24; |
dudmuck | 8:227605e4a760 | 1114 | radio.tx_buf[2] = PacketTxCnt >> 16; |
dudmuck | 8:227605e4a760 | 1115 | radio.tx_buf[3] = PacketTxCnt >> 8; |
dudmuck | 8:227605e4a760 | 1116 | radio.tx_buf[4] = PacketTxCnt; |
dudmuck | 8:227605e4a760 | 1117 | radio.tx_buf[5] = 'P'; |
dudmuck | 8:227605e4a760 | 1118 | radio.tx_buf[6] = 'E'; |
dudmuck | 8:227605e4a760 | 1119 | radio.tx_buf[7] = 'R'; |
dudmuck | 8:227605e4a760 | 1120 | radio.tx_buf[8] = 0; |
dudmuck | 8:227605e4a760 | 1121 | for (i = 0; i < 8; i++) |
dudmuck | 8:227605e4a760 | 1122 | radio.tx_buf[8] += radio.tx_buf[i]; |
dudmuck | 8:227605e4a760 | 1123 | |
dudmuck | 13:c73caaee93a5 | 1124 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 13:c73caaee93a5 | 1125 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 13:c73caaee93a5 | 1126 | } else { |
dudmuck | 13:c73caaee93a5 | 1127 | fsk.start_tx(9); |
dudmuck | 13:c73caaee93a5 | 1128 | } |
dudmuck | 10:d9bb2ce57f05 | 1129 | |
dudmuck | 10:d9bb2ce57f05 | 1130 | led1 = !led1.read(); |
dudmuck | 18:9530d682fd9a | 1131 | |
dudmuck | 18:9530d682fd9a | 1132 | if (PacketTxCnt == PacketTxCntEnd) { |
dudmuck | 18:9530d682fd9a | 1133 | set_per_en(false); |
dudmuck | 18:9530d682fd9a | 1134 | return; |
dudmuck | 18:9530d682fd9a | 1135 | } |
dudmuck | 8:227605e4a760 | 1136 | } |
dudmuck | 8:227605e4a760 | 1137 | |
dudmuck | 13:c73caaee93a5 | 1138 | int per_parse_rx(uint8_t len) |
dudmuck | 13:c73caaee93a5 | 1139 | { |
dudmuck | 13:c73caaee93a5 | 1140 | if (len > 8 && radio.rx_buf[5] == 'P' && radio.rx_buf[6] == 'E' && radio.rx_buf[7] == 'R') { |
dudmuck | 13:c73caaee93a5 | 1141 | int i; |
dudmuck | 13:c73caaee93a5 | 1142 | float per; |
dudmuck | 13:c73caaee93a5 | 1143 | |
dudmuck | 13:c73caaee93a5 | 1144 | /* this is PER packet */ |
dudmuck | 19:be8a8b0e7320 | 1145 | int PacketRxSequence = (radio.rx_buf[1] << 24) | (radio.rx_buf[2] << 16) | (radio.rx_buf[3] << 8) | radio.rx_buf[4]; |
dudmuck | 13:c73caaee93a5 | 1146 | PacketPerOkCnt++; |
dudmuck | 13:c73caaee93a5 | 1147 | |
dudmuck | 13:c73caaee93a5 | 1148 | if( PacketRxSequence <= PacketRxSequencePrev ) |
dudmuck | 13:c73caaee93a5 | 1149 | { // Sequence went back => resynchronization |
dudmuck | 13:c73caaee93a5 | 1150 | // dont count missed packets this time |
dudmuck | 13:c73caaee93a5 | 1151 | i = 0; |
dudmuck | 13:c73caaee93a5 | 1152 | } |
dudmuck | 13:c73caaee93a5 | 1153 | else |
dudmuck | 13:c73caaee93a5 | 1154 | { |
dudmuck | 13:c73caaee93a5 | 1155 | // determine number of missed packets |
dudmuck | 13:c73caaee93a5 | 1156 | i = PacketRxSequence - PacketRxSequencePrev - 1; |
dudmuck | 13:c73caaee93a5 | 1157 | } |
dudmuck | 13:c73caaee93a5 | 1158 | |
dudmuck | 13:c73caaee93a5 | 1159 | led1 = !led1.read(); |
dudmuck | 13:c73caaee93a5 | 1160 | // be ready for the next |
dudmuck | 13:c73caaee93a5 | 1161 | PacketRxSequencePrev = PacketRxSequence; |
dudmuck | 13:c73caaee93a5 | 1162 | // increment 'missed' counter for the RX session |
dudmuck | 13:c73caaee93a5 | 1163 | PacketPerKoCnt += i; |
dudmuck | 18:9530d682fd9a | 1164 | per = ( (float)1.0 - ( float )PacketPerOkCnt / ( float )( PacketPerOkCnt + PacketPerKoCnt ) ) * (float)100.0; |
dudmuck | 19:be8a8b0e7320 | 1165 | printf("%d, ok=%" PRIu32 " missed=%" PRIu32 " normal=%" PRIu32 " per:%.3f ", PacketRxSequence, PacketPerOkCnt, PacketPerKoCnt, PacketNormalCnt, per); |
dudmuck | 15:c69b942685ea | 1166 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 15:c69b942685ea | 1167 | printf("pkt:%ddBm, snr:%.1fdB, %ddBm\r\n", lora.get_pkt_rssi(), lora.RegPktSnrValue / 4.0, lora.get_current_rssi()); |
dudmuck | 15:c69b942685ea | 1168 | else { |
dudmuck | 16:b9d36c60f2d3 | 1169 | wait_us(10000); |
dudmuck | 15:c69b942685ea | 1170 | printf(" -%.1fdBm\r\n", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 15:c69b942685ea | 1171 | } |
dudmuck | 15:c69b942685ea | 1172 | |
dudmuck | 13:c73caaee93a5 | 1173 | return 1; |
dudmuck | 13:c73caaee93a5 | 1174 | } else { |
dudmuck | 13:c73caaee93a5 | 1175 | return 0; |
dudmuck | 13:c73caaee93a5 | 1176 | } |
dudmuck | 13:c73caaee93a5 | 1177 | } |
dudmuck | 13:c73caaee93a5 | 1178 | |
dudmuck | 18:9530d682fd9a | 1179 | typedef enum { |
dudmuck | 18:9530d682fd9a | 1180 | ON_TXDONE_STATE_NONE = 0, |
dudmuck | 18:9530d682fd9a | 1181 | ON_TXDONE_STATE_SYNC_HI_NIBBLE, |
dudmuck | 18:9530d682fd9a | 1182 | ON_TXDONE_STATE_SYNC_LO_NIBBLE, |
dudmuck | 18:9530d682fd9a | 1183 | ON_TXDONE_STATE_PAYLOAD_LENGTH, |
dudmuck | 18:9530d682fd9a | 1184 | } on_txdone_state_e; |
dudmuck | 18:9530d682fd9a | 1185 | |
dudmuck | 18:9530d682fd9a | 1186 | on_txdone_state_e on_txdone_state; |
dudmuck | 18:9530d682fd9a | 1187 | |
dudmuck | 18:9530d682fd9a | 1188 | uint8_t lora_sync_byte; |
dudmuck | 18:9530d682fd9a | 1189 | float on_txdone_delay; |
dudmuck | 18:9530d682fd9a | 1190 | Timeout on_txdone_timeout; |
dudmuck | 18:9530d682fd9a | 1191 | uint8_t on_txdone_repeat_cnt; |
dudmuck | 18:9530d682fd9a | 1192 | |
dudmuck | 18:9530d682fd9a | 1193 | void txdone_timeout_cb() |
dudmuck | 18:9530d682fd9a | 1194 | { |
dudmuck | 18:9530d682fd9a | 1195 | uint8_t nib; |
dudmuck | 18:9530d682fd9a | 1196 | |
dudmuck | 18:9530d682fd9a | 1197 | switch (on_txdone_state) { |
dudmuck | 18:9530d682fd9a | 1198 | case ON_TXDONE_STATE_SYNC_HI_NIBBLE: |
dudmuck | 18:9530d682fd9a | 1199 | nib = lora_sync_byte >> 4; |
dudmuck | 18:9530d682fd9a | 1200 | if (nib >= 15) { |
dudmuck | 18:9530d682fd9a | 1201 | on_txdone_state = ON_TXDONE_STATE_SYNC_LO_NIBBLE; |
dudmuck | 18:9530d682fd9a | 1202 | lora_sync_byte = 0x00; |
dudmuck | 18:9530d682fd9a | 1203 | } else |
dudmuck | 18:9530d682fd9a | 1204 | nib++; |
dudmuck | 18:9530d682fd9a | 1205 | |
dudmuck | 18:9530d682fd9a | 1206 | lora_sync_byte = nib << 4; |
dudmuck | 18:9530d682fd9a | 1207 | |
dudmuck | 18:9530d682fd9a | 1208 | radio.write_reg(REG_LR_SYNC_BYTE, lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1209 | printf("upper %02x\r\n", lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1210 | break; |
dudmuck | 18:9530d682fd9a | 1211 | case ON_TXDONE_STATE_SYNC_LO_NIBBLE: |
dudmuck | 18:9530d682fd9a | 1212 | nib = lora_sync_byte & 0x0f; |
dudmuck | 18:9530d682fd9a | 1213 | if (nib >= 15) { |
dudmuck | 18:9530d682fd9a | 1214 | on_txdone_state = ON_TXDONE_STATE_SYNC_LO_NIBBLE; |
dudmuck | 18:9530d682fd9a | 1215 | lora_sync_byte = 0x00; |
dudmuck | 18:9530d682fd9a | 1216 | } else |
dudmuck | 18:9530d682fd9a | 1217 | nib++; |
dudmuck | 18:9530d682fd9a | 1218 | |
dudmuck | 18:9530d682fd9a | 1219 | lora_sync_byte = nib & 0x0f; |
dudmuck | 18:9530d682fd9a | 1220 | |
dudmuck | 18:9530d682fd9a | 1221 | radio.write_reg(REG_LR_SYNC_BYTE, lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1222 | printf("lower %02x\r\n", lora_sync_byte); |
dudmuck | 18:9530d682fd9a | 1223 | break; |
dudmuck | 18:9530d682fd9a | 1224 | case ON_TXDONE_STATE_PAYLOAD_LENGTH: |
dudmuck | 18:9530d682fd9a | 1225 | if (++on_txdone_repeat_cnt >= 10) { |
dudmuck | 18:9530d682fd9a | 1226 | on_txdone_repeat_cnt = 0; |
dudmuck | 18:9530d682fd9a | 1227 | if (lora.RegPayloadLength == 255) { |
dudmuck | 18:9530d682fd9a | 1228 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 1229 | printf("done\r\n"); |
dudmuck | 18:9530d682fd9a | 1230 | on_txdone_state = ON_TXDONE_STATE_NONE; |
dudmuck | 18:9530d682fd9a | 1231 | return; |
dudmuck | 18:9530d682fd9a | 1232 | } |
dudmuck | 18:9530d682fd9a | 1233 | lora.RegPayloadLength++; |
dudmuck | 18:9530d682fd9a | 1234 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1235 | printf("pl %d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1236 | } |
dudmuck | 18:9530d682fd9a | 1237 | tx_cnt++; |
dudmuck | 18:9530d682fd9a | 1238 | radio.tx_buf[0] = tx_cnt; |
dudmuck | 18:9530d682fd9a | 1239 | radio.tx_buf[1] = ~tx_cnt; |
dudmuck | 18:9530d682fd9a | 1240 | break; |
dudmuck | 18:9530d682fd9a | 1241 | default: |
dudmuck | 18:9530d682fd9a | 1242 | return; |
dudmuck | 18:9530d682fd9a | 1243 | } // ..switch (on_txdone_state) |
dudmuck | 18:9530d682fd9a | 1244 | |
dudmuck | 18:9530d682fd9a | 1245 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1246 | } |
dudmuck | 18:9530d682fd9a | 1247 | |
dudmuck | 20:b11592c9ba5f | 1248 | |
dudmuck | 18:9530d682fd9a | 1249 | void |
dudmuck | 18:9530d682fd9a | 1250 | poll_service_radio() |
dudmuck | 18:9530d682fd9a | 1251 | { |
dudmuck | 18:9530d682fd9a | 1252 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 1253 | } else { // fsk: |
dudmuck | 21:b84a77dfb43c | 1254 | if (rx_payloadReady_int_en) |
dudmuck | 21:b84a77dfb43c | 1255 | return; |
dudmuck | 21:b84a77dfb43c | 1256 | |
dudmuck | 20:b11592c9ba5f | 1257 | /*RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 18:9530d682fd9a | 1258 | if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { |
dudmuck | 18:9530d682fd9a | 1259 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 1260 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 18:9530d682fd9a | 1261 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 18:9530d682fd9a | 1262 | printf("poll mode fsk tx done\r\n"); |
dudmuck | 18:9530d682fd9a | 1263 | } |
dudmuck | 20:b11592c9ba5f | 1264 | }*/ |
dudmuck | 20:b11592c9ba5f | 1265 | static uint8_t rssi; |
dudmuck | 20:b11592c9ba5f | 1266 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 20:b11592c9ba5f | 1267 | RegIrqFlags1_t RegIrqFlags1; |
dudmuck | 20:b11592c9ba5f | 1268 | RegIrqFlags1.octet = radio.read_reg(REG_FSK_IRQFLAGS1); |
dudmuck | 20:b11592c9ba5f | 1269 | if (RegIrqFlags1.octet != fsk_RegIrqFlags1_prev.octet) { |
dudmuck | 20:b11592c9ba5f | 1270 | printf("iF1:"); |
dudmuck | 20:b11592c9ba5f | 1271 | if (RegIrqFlags1.bits.ModeReady ^ fsk_RegIrqFlags1_prev.bits.ModeReady) { |
dudmuck | 20:b11592c9ba5f | 1272 | printf("ModeReady-"); |
dudmuck | 20:b11592c9ba5f | 1273 | if (RegIrqFlags1.bits.ModeReady) |
dudmuck | 20:b11592c9ba5f | 1274 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1275 | else |
dudmuck | 20:b11592c9ba5f | 1276 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1277 | } |
dudmuck | 20:b11592c9ba5f | 1278 | if (RegIrqFlags1.bits.RxReady ^ fsk_RegIrqFlags1_prev.bits.RxReady) { |
dudmuck | 20:b11592c9ba5f | 1279 | printf("RxReady-"); |
dudmuck | 20:b11592c9ba5f | 1280 | if (RegIrqFlags1.bits.RxReady) |
dudmuck | 20:b11592c9ba5f | 1281 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1282 | else |
dudmuck | 20:b11592c9ba5f | 1283 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1284 | } |
dudmuck | 20:b11592c9ba5f | 1285 | if (RegIrqFlags1.bits.TxReady ^ fsk_RegIrqFlags1_prev.bits.TxReady) { |
dudmuck | 20:b11592c9ba5f | 1286 | printf("TxReady-"); |
dudmuck | 20:b11592c9ba5f | 1287 | if (RegIrqFlags1.bits.TxReady) |
dudmuck | 20:b11592c9ba5f | 1288 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1289 | else |
dudmuck | 20:b11592c9ba5f | 1290 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1291 | } |
dudmuck | 20:b11592c9ba5f | 1292 | if (RegIrqFlags1.bits.PllLock ^ fsk_RegIrqFlags1_prev.bits.PllLock) { |
dudmuck | 20:b11592c9ba5f | 1293 | printf("PllLock-"); |
dudmuck | 20:b11592c9ba5f | 1294 | if (RegIrqFlags1.bits.PllLock) |
dudmuck | 20:b11592c9ba5f | 1295 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1296 | else |
dudmuck | 20:b11592c9ba5f | 1297 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1298 | } |
dudmuck | 20:b11592c9ba5f | 1299 | if (RegIrqFlags1.bits.Rssi ^ fsk_RegIrqFlags1_prev.bits.Rssi) { |
dudmuck | 20:b11592c9ba5f | 1300 | printf("Rssi-"); |
dudmuck | 20:b11592c9ba5f | 1301 | if (RegIrqFlags1.bits.Rssi) |
dudmuck | 20:b11592c9ba5f | 1302 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1303 | else |
dudmuck | 20:b11592c9ba5f | 1304 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1305 | } |
dudmuck | 20:b11592c9ba5f | 1306 | if (RegIrqFlags1.bits.Timeout ^ fsk_RegIrqFlags1_prev.bits.Timeout) { |
dudmuck | 20:b11592c9ba5f | 1307 | printf("Timeout-"); |
dudmuck | 20:b11592c9ba5f | 1308 | if (RegIrqFlags1.bits.Timeout) |
dudmuck | 20:b11592c9ba5f | 1309 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1310 | else |
dudmuck | 20:b11592c9ba5f | 1311 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1312 | } |
dudmuck | 20:b11592c9ba5f | 1313 | if (RegIrqFlags1.bits.PreambleDetect ^ fsk_RegIrqFlags1_prev.bits.PreambleDetect) { |
dudmuck | 20:b11592c9ba5f | 1314 | printf("PreambleDetect-"); |
dudmuck | 20:b11592c9ba5f | 1315 | if (RegIrqFlags1.bits.PreambleDetect) |
dudmuck | 20:b11592c9ba5f | 1316 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1317 | else |
dudmuck | 20:b11592c9ba5f | 1318 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1319 | } |
dudmuck | 20:b11592c9ba5f | 1320 | if (RegIrqFlags1.bits.SyncAddressMatch ^ fsk_RegIrqFlags1_prev.bits.SyncAddressMatch) { |
dudmuck | 20:b11592c9ba5f | 1321 | printf("SyncAddressMatch-"); |
dudmuck | 20:b11592c9ba5f | 1322 | if (RegIrqFlags1.bits.SyncAddressMatch) |
dudmuck | 20:b11592c9ba5f | 1323 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1324 | else |
dudmuck | 20:b11592c9ba5f | 1325 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1326 | } |
dudmuck | 20:b11592c9ba5f | 1327 | fsk_RegIrqFlags1_prev.octet = RegIrqFlags1.octet; |
dudmuck | 20:b11592c9ba5f | 1328 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1329 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1330 | } |
dudmuck | 20:b11592c9ba5f | 1331 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 20:b11592c9ba5f | 1332 | if (RegIrqFlags2.octet != fsk_RegIrqFlags2_prev.octet) { |
dudmuck | 20:b11592c9ba5f | 1333 | printf("iF2:"); |
dudmuck | 20:b11592c9ba5f | 1334 | if (RegIrqFlags2.bits.FifoFull ^ fsk_RegIrqFlags2_prev.bits.FifoFull) { |
dudmuck | 20:b11592c9ba5f | 1335 | printf("FifoFull-"); |
dudmuck | 20:b11592c9ba5f | 1336 | if (RegIrqFlags2.bits.FifoFull) |
dudmuck | 20:b11592c9ba5f | 1337 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1338 | else |
dudmuck | 20:b11592c9ba5f | 1339 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1340 | } |
dudmuck | 20:b11592c9ba5f | 1341 | if (RegIrqFlags2.bits.FifoEmpty ^ fsk_RegIrqFlags2_prev.bits.FifoEmpty) { |
dudmuck | 20:b11592c9ba5f | 1342 | printf("FifoEmpty-"); |
dudmuck | 20:b11592c9ba5f | 1343 | if (RegIrqFlags2.bits.FifoEmpty) |
dudmuck | 20:b11592c9ba5f | 1344 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1345 | else { |
dudmuck | 20:b11592c9ba5f | 1346 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1347 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 20:b11592c9ba5f | 1348 | } |
dudmuck | 20:b11592c9ba5f | 1349 | } |
dudmuck | 20:b11592c9ba5f | 1350 | if (RegIrqFlags2.bits.FifoLevel ^ fsk_RegIrqFlags2_prev.bits.FifoLevel) { |
dudmuck | 20:b11592c9ba5f | 1351 | printf("FifoLevel-"); |
dudmuck | 20:b11592c9ba5f | 1352 | if (RegIrqFlags2.bits.FifoLevel) |
dudmuck | 20:b11592c9ba5f | 1353 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1354 | else |
dudmuck | 20:b11592c9ba5f | 1355 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1356 | } |
dudmuck | 20:b11592c9ba5f | 1357 | if (RegIrqFlags2.bits.FifoOverrun ^ fsk_RegIrqFlags2_prev.bits.FifoOverrun) { |
dudmuck | 20:b11592c9ba5f | 1358 | printf("FifoOverrun-"); |
dudmuck | 20:b11592c9ba5f | 1359 | if (RegIrqFlags2.bits.FifoOverrun) |
dudmuck | 20:b11592c9ba5f | 1360 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1361 | else |
dudmuck | 20:b11592c9ba5f | 1362 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1363 | } |
dudmuck | 20:b11592c9ba5f | 1364 | if (RegIrqFlags2.bits.PacketSent ^ fsk_RegIrqFlags2_prev.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1365 | printf("PacketSent-"); |
dudmuck | 20:b11592c9ba5f | 1366 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1367 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1368 | } else |
dudmuck | 20:b11592c9ba5f | 1369 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1370 | } |
dudmuck | 20:b11592c9ba5f | 1371 | if (RegIrqFlags2.bits.PayloadReady ^ fsk_RegIrqFlags2_prev.bits.PayloadReady) { |
dudmuck | 20:b11592c9ba5f | 1372 | printf("PayloadReady-"); |
dudmuck | 20:b11592c9ba5f | 1373 | if (RegIrqFlags2.bits.PayloadReady) |
dudmuck | 20:b11592c9ba5f | 1374 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1375 | else |
dudmuck | 20:b11592c9ba5f | 1376 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1377 | } |
dudmuck | 20:b11592c9ba5f | 1378 | if (RegIrqFlags2.bits.CrcOk ^ fsk_RegIrqFlags2_prev.bits.CrcOk) { |
dudmuck | 20:b11592c9ba5f | 1379 | printf("CrcOk-"); |
dudmuck | 20:b11592c9ba5f | 1380 | if (RegIrqFlags2.bits.CrcOk) |
dudmuck | 20:b11592c9ba5f | 1381 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1382 | else |
dudmuck | 20:b11592c9ba5f | 1383 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1384 | } |
dudmuck | 20:b11592c9ba5f | 1385 | if (RegIrqFlags2.bits.LowBat ^ fsk_RegIrqFlags2_prev.bits.LowBat) { |
dudmuck | 20:b11592c9ba5f | 1386 | printf("LowBat-"); |
dudmuck | 20:b11592c9ba5f | 1387 | if (RegIrqFlags2.bits.LowBat) |
dudmuck | 20:b11592c9ba5f | 1388 | printf("on "); |
dudmuck | 20:b11592c9ba5f | 1389 | else |
dudmuck | 20:b11592c9ba5f | 1390 | printf("off "); |
dudmuck | 20:b11592c9ba5f | 1391 | } |
dudmuck | 20:b11592c9ba5f | 1392 | fsk_RegIrqFlags2_prev.octet = RegIrqFlags2.octet; |
dudmuck | 20:b11592c9ba5f | 1393 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1394 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1395 | |
dudmuck | 20:b11592c9ba5f | 1396 | if (RegIrqFlags2.bits.PacketSent) { |
dudmuck | 20:b11592c9ba5f | 1397 | if (fsk.tx_done_sleep) |
dudmuck | 20:b11592c9ba5f | 1398 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 20:b11592c9ba5f | 1399 | else |
dudmuck | 20:b11592c9ba5f | 1400 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 20:b11592c9ba5f | 1401 | } |
dudmuck | 20:b11592c9ba5f | 1402 | |
dudmuck | 20:b11592c9ba5f | 1403 | if (RegIrqFlags2.bits.CrcOk || RegIrqFlags2.bits.PayloadReady) { |
dudmuck | 20:b11592c9ba5f | 1404 | if (fsk.RegRxConfig.bits.AfcAutoOn) { |
dudmuck | 20:b11592c9ba5f | 1405 | fsk.RegAfcValue = radio.read_s16(REG_FSK_AFCMSB); |
dudmuck | 20:b11592c9ba5f | 1406 | printf("%dHz ", (int)(FREQ_STEP_HZ * fsk.RegAfcValue)); |
dudmuck | 20:b11592c9ba5f | 1407 | if (rssi != 0) { |
dudmuck | 20:b11592c9ba5f | 1408 | printf("pkt:-%.1fdBm ", rssi / 2.0); |
dudmuck | 20:b11592c9ba5f | 1409 | rssi = 0; |
dudmuck | 20:b11592c9ba5f | 1410 | } |
dudmuck | 20:b11592c9ba5f | 1411 | } |
dudmuck | 20:b11592c9ba5f | 1412 | if (fsk.RegPktConfig1.bits.PacketFormatVariable) { |
dudmuck | 20:b11592c9ba5f | 1413 | fsk.rx_buf_length = radio.read_reg(REG_FIFO); |
dudmuck | 20:b11592c9ba5f | 1414 | } else { |
dudmuck | 20:b11592c9ba5f | 1415 | fsk.rx_buf_length = fsk.RegPktConfig2.bits.PayloadLength; |
dudmuck | 20:b11592c9ba5f | 1416 | } |
dudmuck | 20:b11592c9ba5f | 1417 | |
dudmuck | 20:b11592c9ba5f | 1418 | radio.m_cs = 0; |
dudmuck | 20:b11592c9ba5f | 1419 | radio.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 20:b11592c9ba5f | 1420 | for (int i = 0; i < fsk.rx_buf_length; i++) { |
dudmuck | 20:b11592c9ba5f | 1421 | radio.rx_buf[i] = radio.m_spi.write(0); |
dudmuck | 20:b11592c9ba5f | 1422 | } |
dudmuck | 20:b11592c9ba5f | 1423 | radio.m_cs = 1; |
dudmuck | 20:b11592c9ba5f | 1424 | /****/ |
dudmuck | 20:b11592c9ba5f | 1425 | if (per_en) { |
dudmuck | 20:b11592c9ba5f | 1426 | if (!per_parse_rx(fsk.rx_buf_length)) { |
dudmuck | 20:b11592c9ba5f | 1427 | PacketNormalCnt++; |
dudmuck | 20:b11592c9ba5f | 1428 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 20:b11592c9ba5f | 1429 | } |
dudmuck | 20:b11592c9ba5f | 1430 | } else { |
dudmuck | 20:b11592c9ba5f | 1431 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 20:b11592c9ba5f | 1432 | } |
dudmuck | 20:b11592c9ba5f | 1433 | fflush(stdout); |
dudmuck | 20:b11592c9ba5f | 1434 | } // ..if CrcOk or PayloadReady |
dudmuck | 20:b11592c9ba5f | 1435 | } // ..if RegIrqFlags2 changed |
dudmuck | 20:b11592c9ba5f | 1436 | } // ...fsk |
dudmuck | 18:9530d682fd9a | 1437 | } |
dudmuck | 18:9530d682fd9a | 1438 | |
dudmuck | 18:9530d682fd9a | 1439 | void cadper_service() |
dudmuck | 18:9530d682fd9a | 1440 | { |
dudmuck | 18:9530d682fd9a | 1441 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1442 | |
dudmuck | 18:9530d682fd9a | 1443 | |
dudmuck | 18:9530d682fd9a | 1444 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 1445 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 1446 | do { |
dudmuck | 18:9530d682fd9a | 1447 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1448 | if (lora.RegIrqFlags.bits.RxDone) { |
dudmuck | 18:9530d682fd9a | 1449 | service_action_e act = lora.service(); |
dudmuck | 18:9530d682fd9a | 1450 | if (act == SERVICE_READ_FIFO) { |
dudmuck | 18:9530d682fd9a | 1451 | if (!per_parse_rx(lora.RegRxNbBytes)) { |
dudmuck | 18:9530d682fd9a | 1452 | PacketNormalCnt++; |
dudmuck | 21:b84a77dfb43c | 1453 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 18:9530d682fd9a | 1454 | } |
dudmuck | 18:9530d682fd9a | 1455 | } |
dudmuck | 18:9530d682fd9a | 1456 | break; |
dudmuck | 18:9530d682fd9a | 1457 | } |
dudmuck | 18:9530d682fd9a | 1458 | } while (!lora.RegIrqFlags.bits.RxTimeout); |
dudmuck | 18:9530d682fd9a | 1459 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 1460 | } |
dudmuck | 18:9530d682fd9a | 1461 | |
dudmuck | 18:9530d682fd9a | 1462 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 1463 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 1464 | num_cads++; |
dudmuck | 18:9530d682fd9a | 1465 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 1466 | } |
dudmuck | 18:9530d682fd9a | 1467 | |
dudmuck | 18:9530d682fd9a | 1468 | } |
dudmuck | 18:9530d682fd9a | 1469 | |
dudmuck | 20:b11592c9ba5f | 1470 | void cmd_restart_rx(uint8_t); |
dudmuck | 20:b11592c9ba5f | 1471 | Timeout timeout_syncAddress; |
dudmuck | 20:b11592c9ba5f | 1472 | int preamble_to_sync_us; |
dudmuck | 20:b11592c9ba5f | 1473 | bool get_syncAddress; |
dudmuck | 20:b11592c9ba5f | 1474 | float preamble_detect_at; |
dudmuck | 20:b11592c9ba5f | 1475 | |
dudmuck | 20:b11592c9ba5f | 1476 | void callback_sa_timeout() |
dudmuck | 20:b11592c9ba5f | 1477 | { |
dudmuck | 20:b11592c9ba5f | 1478 | printf("syncAddress timeout "); |
dudmuck | 20:b11592c9ba5f | 1479 | if (dio2.read() == 0) { |
dudmuck | 20:b11592c9ba5f | 1480 | //cmd_restart_rx(0); |
dudmuck | 20:b11592c9ba5f | 1481 | rx_start_timer.reset(); |
dudmuck | 20:b11592c9ba5f | 1482 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 20:b11592c9ba5f | 1483 | printf("(false preamble detect at %f, secs:%u)\r\n", preamble_detect_at, time(NULL) - secs_rx_start); |
dudmuck | 20:b11592c9ba5f | 1484 | secs_rx_start = time(NULL); |
dudmuck | 20:b11592c9ba5f | 1485 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 20:b11592c9ba5f | 1486 | } else |
dudmuck | 20:b11592c9ba5f | 1487 | printf("\r\n"); |
dudmuck | 20:b11592c9ba5f | 1488 | } |
dudmuck | 20:b11592c9ba5f | 1489 | |
dudmuck | 0:be215de91a68 | 1490 | void |
dudmuck | 0:be215de91a68 | 1491 | service_radio() |
dudmuck | 0:be215de91a68 | 1492 | { |
dudmuck | 1:1cd0afbed23c | 1493 | service_action_e act; |
dudmuck | 14:c57ea544dc18 | 1494 | static uint8_t rssi = 0; |
dudmuck | 1:1cd0afbed23c | 1495 | |
dudmuck | 1:1cd0afbed23c | 1496 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 21:b84a77dfb43c | 1497 | if (rssi_polling_thresh != 0 && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 21:b84a77dfb43c | 1498 | int rssi = lora.get_current_rssi(); // dBm returned, negative value |
dudmuck | 21:b84a77dfb43c | 1499 | #ifdef TARGET_STM |
dudmuck | 21:b84a77dfb43c | 1500 | if (rssi < rssi_polling_thresh) |
dudmuck | 21:b84a77dfb43c | 1501 | pc3 = 0; // signal weaker than threshold |
dudmuck | 21:b84a77dfb43c | 1502 | else |
dudmuck | 21:b84a77dfb43c | 1503 | pc3 = 1; // signal stronger than threshold |
dudmuck | 21:b84a77dfb43c | 1504 | #endif |
dudmuck | 21:b84a77dfb43c | 1505 | } |
dudmuck | 21:b84a77dfb43c | 1506 | |
dudmuck | 18:9530d682fd9a | 1507 | if (cadper_enable) { |
dudmuck | 18:9530d682fd9a | 1508 | cadper_service(); |
dudmuck | 18:9530d682fd9a | 1509 | } |
dudmuck | 4:7a9007dfc0e5 | 1510 | |
dudmuck | 1:1cd0afbed23c | 1511 | act = lora.service(); |
dudmuck | 0:be215de91a68 | 1512 | |
dudmuck | 1:1cd0afbed23c | 1513 | switch (act) { |
dudmuck | 1:1cd0afbed23c | 1514 | case SERVICE_READ_FIFO: |
dudmuck | 8:227605e4a760 | 1515 | if (app == APP_NONE) { |
dudmuck | 8:227605e4a760 | 1516 | if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1517 | if (!per_parse_rx(lora.RegRxNbBytes)) { |
dudmuck | 8:227605e4a760 | 1518 | PacketNormalCnt++; |
dudmuck | 21:b84a77dfb43c | 1519 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 8:227605e4a760 | 1520 | } |
dudmuck | 8:227605e4a760 | 1521 | } else |
dudmuck | 21:b84a77dfb43c | 1522 | lora_print_rx_verbose(lora.RegRxNbBytes); |
dudmuck | 15:c69b942685ea | 1523 | fflush(stdout); |
dudmuck | 1:1cd0afbed23c | 1524 | } else if (app == APP_CHAT) { |
dudmuck | 1:1cd0afbed23c | 1525 | if (lora.RegHopChannel.bits.RxPayloadCrcOn) { |
dudmuck | 1:1cd0afbed23c | 1526 | if (lora.RegIrqFlags.bits.PayloadCrcError) |
dudmuck | 1:1cd0afbed23c | 1527 | printf("crcError\r\n"); |
dudmuck | 1:1cd0afbed23c | 1528 | else { |
dudmuck | 1:1cd0afbed23c | 1529 | int n = lora.RegRxNbBytes; |
dudmuck | 1:1cd0afbed23c | 1530 | radio.rx_buf[n++] = '\r'; |
dudmuck | 1:1cd0afbed23c | 1531 | radio.rx_buf[n++] = '\n'; |
dudmuck | 1:1cd0afbed23c | 1532 | radio.rx_buf[n] = 0; // null terminate |
dudmuck | 1:1cd0afbed23c | 1533 | printf((char *)radio.rx_buf); |
dudmuck | 1:1cd0afbed23c | 1534 | } |
dudmuck | 1:1cd0afbed23c | 1535 | } else |
dudmuck | 1:1cd0afbed23c | 1536 | printf("crcOff\r\n"); |
dudmuck | 1:1cd0afbed23c | 1537 | |
dudmuck | 1:1cd0afbed23c | 1538 | // clear Irq flags |
dudmuck | 1:1cd0afbed23c | 1539 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 1:1cd0afbed23c | 1540 | // should still be in receive mode |
dudmuck | 0:be215de91a68 | 1541 | } |
dudmuck | 1:1cd0afbed23c | 1542 | break; |
dudmuck | 1:1cd0afbed23c | 1543 | case SERVICE_TX_DONE: |
dudmuck | 1:1cd0afbed23c | 1544 | if (app == APP_CHAT) { |
dudmuck | 18:9530d682fd9a | 1545 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 8:227605e4a760 | 1546 | } else if (per_en) { |
dudmuck | 18:9530d682fd9a | 1547 | per_timeout.attach(&per_cb, per_tx_delay); // start next TX |
dudmuck | 18:9530d682fd9a | 1548 | } else if (on_txdone_state != ON_TXDONE_STATE_NONE) { |
dudmuck | 18:9530d682fd9a | 1549 | on_txdone_timeout.attach(&txdone_timeout_cb, on_txdone_delay); |
dudmuck | 1:1cd0afbed23c | 1550 | } |
dudmuck | 1:1cd0afbed23c | 1551 | break; |
dudmuck | 1:1cd0afbed23c | 1552 | case SERVICE_ERROR: |
dudmuck | 1:1cd0afbed23c | 1553 | printf("error\r\n"); |
dudmuck | 1:1cd0afbed23c | 1554 | break; |
dudmuck | 19:be8a8b0e7320 | 1555 | case SERVICE_NONE: |
dudmuck | 19:be8a8b0e7320 | 1556 | break; |
dudmuck | 1:1cd0afbed23c | 1557 | } // ...switch (act) |
dudmuck | 1:1cd0afbed23c | 1558 | } else { |
dudmuck | 1:1cd0afbed23c | 1559 | /* FSK: */ |
dudmuck | 21:b84a77dfb43c | 1560 | |
dudmuck | 21:b84a77dfb43c | 1561 | if (rx_payloadReady_int_en) |
dudmuck | 21:b84a77dfb43c | 1562 | return; // radio service by ISR only |
dudmuck | 21:b84a77dfb43c | 1563 | |
dudmuck | 21:b84a77dfb43c | 1564 | if (ulrx_enable) |
dudmuck | 21:b84a77dfb43c | 1565 | return; |
dudmuck | 21:b84a77dfb43c | 1566 | |
dudmuck | 1:1cd0afbed23c | 1567 | act = fsk.service(); |
dudmuck | 1:1cd0afbed23c | 1568 | |
dudmuck | 1:1cd0afbed23c | 1569 | switch (act) { |
dudmuck | 1:1cd0afbed23c | 1570 | case SERVICE_READ_FIFO: |
dudmuck | 2:c6b23a43a9d9 | 1571 | if (app == APP_CHAT) { |
dudmuck | 2:c6b23a43a9d9 | 1572 | int n = fsk.rx_buf_length; |
dudmuck | 2:c6b23a43a9d9 | 1573 | radio.rx_buf[n++] = '\r'; |
dudmuck | 2:c6b23a43a9d9 | 1574 | radio.rx_buf[n++] = '\n'; |
dudmuck | 2:c6b23a43a9d9 | 1575 | radio.rx_buf[n] = 0; // null terminate |
dudmuck | 2:c6b23a43a9d9 | 1576 | printf((char *)radio.rx_buf); |
dudmuck | 2:c6b23a43a9d9 | 1577 | } else { |
dudmuck | 21:b84a77dfb43c | 1578 | if (fsk.RegRxConfig.bits.AfcAutoOn) { |
dudmuck | 14:c57ea544dc18 | 1579 | printf("%dHz ", (int)(FREQ_STEP_HZ * fsk.RegAfcValue)); |
dudmuck | 14:c57ea544dc18 | 1580 | if (rssi != 0) { |
dudmuck | 15:c69b942685ea | 1581 | printf("pkt:-%.1fdBm ", rssi / 2.0); |
dudmuck | 14:c57ea544dc18 | 1582 | rssi = 0; |
dudmuck | 15:c69b942685ea | 1583 | } |
dudmuck | 21:b84a77dfb43c | 1584 | } |
dudmuck | 13:c73caaee93a5 | 1585 | if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1586 | if (!per_parse_rx(fsk.rx_buf_length)) { |
dudmuck | 13:c73caaee93a5 | 1587 | PacketNormalCnt++; |
dudmuck | 13:c73caaee93a5 | 1588 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 13:c73caaee93a5 | 1589 | } |
dudmuck | 13:c73caaee93a5 | 1590 | } else { |
dudmuck | 13:c73caaee93a5 | 1591 | print_rx_buf(fsk.rx_buf_length); |
dudmuck | 13:c73caaee93a5 | 1592 | } |
dudmuck | 21:b84a77dfb43c | 1593 | |
dudmuck | 2:c6b23a43a9d9 | 1594 | } |
dudmuck | 21:b84a77dfb43c | 1595 | if (crc32_en) { |
dudmuck | 21:b84a77dfb43c | 1596 | uint32_t c, *u32_ptr = (uint32_t*)&radio.rx_buf[fsk.rx_buf_length-4]; |
dudmuck | 21:b84a77dfb43c | 1597 | printf("rx crc:%08x, ", *u32_ptr); |
dudmuck | 21:b84a77dfb43c | 1598 | c = gen_crc(radio.rx_buf, fsk.rx_buf_length-4); |
dudmuck | 21:b84a77dfb43c | 1599 | printf("calc crc:%08x\r\n", c); |
dudmuck | 21:b84a77dfb43c | 1600 | } |
dudmuck | 21:b84a77dfb43c | 1601 | fflush(stdout); |
dudmuck | 1:1cd0afbed23c | 1602 | break; |
dudmuck | 2:c6b23a43a9d9 | 1603 | case SERVICE_TX_DONE: |
dudmuck | 18:9530d682fd9a | 1604 | if (ook_test_en) |
dudmuck | 18:9530d682fd9a | 1605 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 2:c6b23a43a9d9 | 1606 | if (app == APP_CHAT) { |
dudmuck | 2:c6b23a43a9d9 | 1607 | fsk.start_rx(); |
dudmuck | 13:c73caaee93a5 | 1608 | } else if (per_en) { |
dudmuck | 13:c73caaee93a5 | 1609 | per_timeout.attach(&per_cb, per_tx_delay); // start next TX |
dudmuck | 13:c73caaee93a5 | 1610 | } |
dudmuck | 2:c6b23a43a9d9 | 1611 | break; |
dudmuck | 19:be8a8b0e7320 | 1612 | case SERVICE_ERROR: |
dudmuck | 19:be8a8b0e7320 | 1613 | case SERVICE_NONE: |
dudmuck | 19:be8a8b0e7320 | 1614 | break; |
dudmuck | 20:b11592c9ba5f | 1615 | } // ...switch (act) |
dudmuck | 14:c57ea544dc18 | 1616 | |
dudmuck | 20:b11592c9ba5f | 1617 | /* FSK receiver handling of preamble detection */ |
dudmuck | 20:b11592c9ba5f | 1618 | if (radio.RegDioMapping2.bits.MapPreambleDetect && radio.RegDioMapping2.bits.Dio4Mapping == 3) { |
dudmuck | 20:b11592c9ba5f | 1619 | if (saved_dio4 != dio4.read()) { |
dudmuck | 20:b11592c9ba5f | 1620 | //printf("predet-dio4:%d\r\n", dio4.read()); |
dudmuck | 20:b11592c9ba5f | 1621 | /* FSK: preamble detect state change */ |
dudmuck | 20:b11592c9ba5f | 1622 | if (dio4.read()) { |
dudmuck | 20:b11592c9ba5f | 1623 | if (radio.RegDioMapping1.bits.Dio2Mapping == 3) { // if we can see SyncAddress |
dudmuck | 20:b11592c9ba5f | 1624 | get_syncAddress = true; |
dudmuck | 20:b11592c9ba5f | 1625 | timeout_syncAddress.attach_us(callback_sa_timeout, preamble_to_sync_us); |
dudmuck | 20:b11592c9ba5f | 1626 | } |
dudmuck | 20:b11592c9ba5f | 1627 | /* how long after RX start is preamble detection occuring? */ |
dudmuck | 20:b11592c9ba5f | 1628 | //printf("preamble detect at %f\r\n", rx_start_timer.read()); |
dudmuck | 20:b11592c9ba5f | 1629 | preamble_detect_at = rx_start_timer.read(); |
dudmuck | 20:b11592c9ba5f | 1630 | } else { |
dudmuck | 20:b11592c9ba5f | 1631 | get_syncAddress = false; |
dudmuck | 20:b11592c9ba5f | 1632 | //printf("preamble detect clear\r\n"); |
dudmuck | 20:b11592c9ba5f | 1633 | } |
dudmuck | 20:b11592c9ba5f | 1634 | saved_dio4 = dio4.read(); |
dudmuck | 20:b11592c9ba5f | 1635 | } |
dudmuck | 20:b11592c9ba5f | 1636 | } // ..if dio4 is |
dudmuck | 20:b11592c9ba5f | 1637 | |
dudmuck | 20:b11592c9ba5f | 1638 | if (radio.RegDioMapping1.bits.Dio2Mapping == 3) { |
dudmuck | 20:b11592c9ba5f | 1639 | if (dio2.read()) { |
dudmuck | 20:b11592c9ba5f | 1640 | if (get_syncAddress) { |
dudmuck | 20:b11592c9ba5f | 1641 | timeout_syncAddress.detach(); |
dudmuck | 20:b11592c9ba5f | 1642 | get_syncAddress = false; |
dudmuck | 20:b11592c9ba5f | 1643 | } |
dudmuck | 15:c69b942685ea | 1644 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 14:c57ea544dc18 | 1645 | } |
dudmuck | 14:c57ea544dc18 | 1646 | } |
dudmuck | 14:c57ea544dc18 | 1647 | |
dudmuck | 20:b11592c9ba5f | 1648 | /*if (radio.RegDioMapping1.bits.Dio1Mapping == 1 && radio.dio1) { |
dudmuck | 20:b11592c9ba5f | 1649 | = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 20:b11592c9ba5f | 1650 | }*/ |
dudmuck | 20:b11592c9ba5f | 1651 | |
dudmuck | 21:b84a77dfb43c | 1652 | if (rssi_polling_thresh != 0 && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 21:b84a77dfb43c | 1653 | rssi = radio.read_reg(REG_FSK_RSSIVALUE); |
dudmuck | 21:b84a77dfb43c | 1654 | rssi = -rssi; |
dudmuck | 21:b84a77dfb43c | 1655 | #ifdef TARGET_STM |
dudmuck | 21:b84a77dfb43c | 1656 | if (rssi < rssi_polling_thresh) |
dudmuck | 21:b84a77dfb43c | 1657 | pc3 = 0; // signal weaker than threshold |
dudmuck | 21:b84a77dfb43c | 1658 | else |
dudmuck | 21:b84a77dfb43c | 1659 | pc3 = 1; // signal stronger than threshold |
dudmuck | 21:b84a77dfb43c | 1660 | } |
dudmuck | 21:b84a77dfb43c | 1661 | #endif |
dudmuck | 14:c57ea544dc18 | 1662 | } // ...!radio.RegOpMode.bits.LongRangeMode |
dudmuck | 0:be215de91a68 | 1663 | } |
dudmuck | 0:be215de91a68 | 1664 | |
dudmuck | 5:360069ec9953 | 1665 | /*int get_kbd_str(char* buf, int size) |
dudmuck | 0:be215de91a68 | 1666 | { |
dudmuck | 0:be215de91a68 | 1667 | char c; |
dudmuck | 0:be215de91a68 | 1668 | int i; |
dudmuck | 0:be215de91a68 | 1669 | static int prev_len; |
dudmuck | 0:be215de91a68 | 1670 | |
dudmuck | 0:be215de91a68 | 1671 | for (i = 0;;) { |
dudmuck | 0:be215de91a68 | 1672 | if (pc.readable()) { |
dudmuck | 0:be215de91a68 | 1673 | c = pc.getc(); |
dudmuck | 0:be215de91a68 | 1674 | if (c == 8 && i > 0) { |
dudmuck | 0:be215de91a68 | 1675 | pc.putc(8); |
dudmuck | 0:be215de91a68 | 1676 | pc.putc(' '); |
dudmuck | 0:be215de91a68 | 1677 | pc.putc(8); |
dudmuck | 0:be215de91a68 | 1678 | i--; |
dudmuck | 0:be215de91a68 | 1679 | } else if (c == '\r') { |
dudmuck | 0:be215de91a68 | 1680 | if (i == 0) { |
dudmuck | 0:be215de91a68 | 1681 | return prev_len; // repeat previous |
dudmuck | 0:be215de91a68 | 1682 | } else { |
dudmuck | 0:be215de91a68 | 1683 | buf[i] = 0; // null terminate |
dudmuck | 0:be215de91a68 | 1684 | prev_len = i; |
dudmuck | 0:be215de91a68 | 1685 | return i; |
dudmuck | 0:be215de91a68 | 1686 | } |
dudmuck | 0:be215de91a68 | 1687 | } else if (c == 3) { |
dudmuck | 0:be215de91a68 | 1688 | // ctrl-C abort |
dudmuck | 0:be215de91a68 | 1689 | return -1; |
dudmuck | 0:be215de91a68 | 1690 | } else if (i < size) { |
dudmuck | 0:be215de91a68 | 1691 | buf[i++] = c; |
dudmuck | 0:be215de91a68 | 1692 | pc.putc(c); |
dudmuck | 0:be215de91a68 | 1693 | } |
dudmuck | 4:7a9007dfc0e5 | 1694 | } else { |
dudmuck | 0:be215de91a68 | 1695 | service_radio(); |
dudmuck | 4:7a9007dfc0e5 | 1696 | } |
dudmuck | 0:be215de91a68 | 1697 | } // ...for() |
dudmuck | 5:360069ec9953 | 1698 | }*/ |
dudmuck | 0:be215de91a68 | 1699 | |
dudmuck | 0:be215de91a68 | 1700 | void |
dudmuck | 0:be215de91a68 | 1701 | console_chat() |
dudmuck | 0:be215de91a68 | 1702 | { |
dudmuck | 5:360069ec9953 | 1703 | //int i, len = get_kbd_str(pcbuf, sizeof(pcbuf)); |
dudmuck | 5:360069ec9953 | 1704 | |
dudmuck | 5:360069ec9953 | 1705 | service_radio(); |
dudmuck | 5:360069ec9953 | 1706 | |
dudmuck | 5:360069ec9953 | 1707 | if (pcbuf_len < 0) { |
dudmuck | 0:be215de91a68 | 1708 | printf("chat abort\r\n"); |
dudmuck | 5:360069ec9953 | 1709 | pcbuf_len = 0; |
dudmuck | 0:be215de91a68 | 1710 | app = APP_NONE; |
dudmuck | 0:be215de91a68 | 1711 | return; |
dudmuck | 5:360069ec9953 | 1712 | } else if (pcbuf_len == 0) { |
dudmuck | 5:360069ec9953 | 1713 | return; |
dudmuck | 0:be215de91a68 | 1714 | } else { |
dudmuck | 5:360069ec9953 | 1715 | int i; |
dudmuck | 5:360069ec9953 | 1716 | for (i = 0; i < pcbuf_len; i++) |
dudmuck | 0:be215de91a68 | 1717 | radio.tx_buf[i] = pcbuf[i]; |
dudmuck | 1:1cd0afbed23c | 1718 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 5:360069ec9953 | 1719 | lora.RegPayloadLength = pcbuf_len; |
dudmuck | 1:1cd0afbed23c | 1720 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 5:360069ec9953 | 1721 | lora.start_tx(pcbuf_len); |
dudmuck | 2:c6b23a43a9d9 | 1722 | } else { |
dudmuck | 5:360069ec9953 | 1723 | fsk.start_tx(pcbuf_len); |
dudmuck | 2:c6b23a43a9d9 | 1724 | } |
dudmuck | 5:360069ec9953 | 1725 | pcbuf_len = 0; |
dudmuck | 0:be215de91a68 | 1726 | printf("\r\n"); |
dudmuck | 0:be215de91a68 | 1727 | } |
dudmuck | 0:be215de91a68 | 1728 | } |
dudmuck | 0:be215de91a68 | 1729 | |
dudmuck | 21:b84a77dfb43c | 1730 | const uint8_t ookt_tx_payload[] = { |
dudmuck | 21:b84a77dfb43c | 1731 | 0x55, 0x55, 0x55, 0x55, 0xA9, 0x66, 0x69, 0x65, |
dudmuck | 21:b84a77dfb43c | 1732 | 0x39, 0x53, 0xAA, 0xC3, 0xA6, 0x95, 0xC6, 0x3C, |
dudmuck | 21:b84a77dfb43c | 1733 | 0x6A, 0x33, 0x33, 0xC6, 0xCA, 0xA6, 0x33, 0x33, |
dudmuck | 21:b84a77dfb43c | 1734 | 0x55, 0x6A, 0xA6, 0xAA, 0x53 |
dudmuck | 21:b84a77dfb43c | 1735 | }; |
dudmuck | 21:b84a77dfb43c | 1736 | volatile uint32_t ook_tx_cnt = 0; |
dudmuck | 21:b84a77dfb43c | 1737 | |
dudmuck | 21:b84a77dfb43c | 1738 | void callback_ook_tx_test() |
dudmuck | 21:b84a77dfb43c | 1739 | { |
dudmuck | 21:b84a77dfb43c | 1740 | int i; |
dudmuck | 21:b84a77dfb43c | 1741 | |
dudmuck | 21:b84a77dfb43c | 1742 | //radio.write_reg(REG_FSK_SYNCCONFIG, 0); |
dudmuck | 21:b84a77dfb43c | 1743 | |
dudmuck | 21:b84a77dfb43c | 1744 | printf("%u ookTx: ", ook_tx_cnt++); |
dudmuck | 21:b84a77dfb43c | 1745 | for (i = 0; i < sizeof(ookt_tx_payload); i++) { |
dudmuck | 21:b84a77dfb43c | 1746 | radio.tx_buf[i] = ookt_tx_payload[i]; |
dudmuck | 21:b84a77dfb43c | 1747 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 21:b84a77dfb43c | 1748 | } |
dudmuck | 21:b84a77dfb43c | 1749 | printf("\r\n"); |
dudmuck | 21:b84a77dfb43c | 1750 | |
dudmuck | 21:b84a77dfb43c | 1751 | //printf("syncConf:%x\r\n", radio.read_reg(REG_FSK_SYNCCONFIG)); |
dudmuck | 21:b84a77dfb43c | 1752 | fsk.start_tx(sizeof(ookt_tx_payload)); |
dudmuck | 21:b84a77dfb43c | 1753 | } |
dudmuck | 21:b84a77dfb43c | 1754 | |
dudmuck | 18:9530d682fd9a | 1755 | typedef enum { |
dudmuck | 18:9530d682fd9a | 1756 | TXTICKER_STATE_OFF = 0, |
dudmuck | 18:9530d682fd9a | 1757 | TXTICKER_STATE_TOGGLE_PAYLOAD_BIT, |
dudmuck | 18:9530d682fd9a | 1758 | TXTICKER_STATE_CYCLE_PAYLOAD_LENGTH, |
dudmuck | 18:9530d682fd9a | 1759 | TXTICKER_STATE_CYCLE_CODING_RATE, |
dudmuck | 18:9530d682fd9a | 1760 | TXTICKER_STATE_TOG_HEADER_MODE, |
dudmuck | 18:9530d682fd9a | 1761 | TXTICKER_STATE_TOG_CRC_ON, |
dudmuck | 18:9530d682fd9a | 1762 | TXTICKER_STATE_CYCLE_SYNC_1, |
dudmuck | 18:9530d682fd9a | 1763 | TXTICKER_STATE_CYCLE_SYNC_2, |
dudmuck | 18:9530d682fd9a | 1764 | TXTICKER_STATE_RAMP_PAYLOAD_DATA_START, |
dudmuck | 18:9530d682fd9a | 1765 | TXTICKER_STATE_RAMP_PAYLOAD_DATA, |
dudmuck | 18:9530d682fd9a | 1766 | TXTICKER_STATE_SYMBOL_SWEEP, |
dudmuck | 18:9530d682fd9a | 1767 | TXTICKER_STATE_TOGGLE_ALL_BITS_START, |
dudmuck | 18:9530d682fd9a | 1768 | TXTICKER_STATE_TOGGLE_ALL_BITS, |
dudmuck | 18:9530d682fd9a | 1769 | } txticker_state_e; |
dudmuck | 18:9530d682fd9a | 1770 | |
dudmuck | 18:9530d682fd9a | 1771 | txticker_state_e txticker_state; |
dudmuck | 18:9530d682fd9a | 1772 | float tx_ticker_rate = 0.5; |
dudmuck | 18:9530d682fd9a | 1773 | Ticker tx_ticker; |
dudmuck | 18:9530d682fd9a | 1774 | |
dudmuck | 18:9530d682fd9a | 1775 | uint8_t txticker_sync_byte; |
dudmuck | 18:9530d682fd9a | 1776 | uint8_t payload_length_stop; |
dudmuck | 18:9530d682fd9a | 1777 | uint8_t symbol_num; |
dudmuck | 18:9530d682fd9a | 1778 | uint32_t symbol_sweep_bit_counter = 0; |
dudmuck | 18:9530d682fd9a | 1779 | unsigned int symbol_sweep_bit_counter_stop; |
dudmuck | 18:9530d682fd9a | 1780 | uint8_t symbol_sweep_nbits; |
dudmuck | 18:9530d682fd9a | 1781 | uint8_t byte_pad_length; |
dudmuck | 18:9530d682fd9a | 1782 | |
dudmuck | 18:9530d682fd9a | 1783 | uint8_t tab_current_byte_num; |
dudmuck | 18:9530d682fd9a | 1784 | uint8_t tab_current_bit_in_byte; |
dudmuck | 18:9530d682fd9a | 1785 | |
dudmuck | 18:9530d682fd9a | 1786 | void fp_cb() |
dudmuck | 18:9530d682fd9a | 1787 | { |
dudmuck | 18:9530d682fd9a | 1788 | int i; |
dudmuck | 18:9530d682fd9a | 1789 | if (!radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 1790 | return; |
dudmuck | 18:9530d682fd9a | 1791 | |
dudmuck | 18:9530d682fd9a | 1792 | switch (txticker_state) { |
dudmuck | 18:9530d682fd9a | 1793 | case TXTICKER_STATE_TOGGLE_PAYLOAD_BIT: |
dudmuck | 18:9530d682fd9a | 1794 | /* |
dudmuck | 18:9530d682fd9a | 1795 | { |
dudmuck | 18:9530d682fd9a | 1796 | if (fp_tog_bit_ < 32) { |
dudmuck | 18:9530d682fd9a | 1797 | uint32_t bp = 1 << fp_tog_bit_; |
dudmuck | 18:9530d682fd9a | 1798 | fp_data ^= bp; |
dudmuck | 18:9530d682fd9a | 1799 | //printf("bp%02x ", bp); |
dudmuck | 18:9530d682fd9a | 1800 | } |
dudmuck | 18:9530d682fd9a | 1801 | memcpy(radio.tx_buf, &fp_data, fp_data_length); |
dudmuck | 18:9530d682fd9a | 1802 | printf("TX "); |
dudmuck | 18:9530d682fd9a | 1803 | for (i = 0; i < fp_data_length; i++) |
dudmuck | 18:9530d682fd9a | 1804 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1805 | |
dudmuck | 18:9530d682fd9a | 1806 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1807 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1808 | break; |
dudmuck | 18:9530d682fd9a | 1809 | } |
dudmuck | 18:9530d682fd9a | 1810 | */ |
dudmuck | 18:9530d682fd9a | 1811 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1812 | break; |
dudmuck | 18:9530d682fd9a | 1813 | case TXTICKER_STATE_CYCLE_PAYLOAD_LENGTH: |
dudmuck | 18:9530d682fd9a | 1814 | { |
dudmuck | 18:9530d682fd9a | 1815 | if (lora.RegPayloadLength > payload_length_stop) |
dudmuck | 18:9530d682fd9a | 1816 | lora.RegPayloadLength = 0; |
dudmuck | 18:9530d682fd9a | 1817 | else |
dudmuck | 18:9530d682fd9a | 1818 | lora.RegPayloadLength++; |
dudmuck | 18:9530d682fd9a | 1819 | |
dudmuck | 18:9530d682fd9a | 1820 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1821 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1822 | printf("RegPayloadLength:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1823 | break; |
dudmuck | 18:9530d682fd9a | 1824 | } |
dudmuck | 18:9530d682fd9a | 1825 | case TXTICKER_STATE_CYCLE_CODING_RATE: |
dudmuck | 18:9530d682fd9a | 1826 | { |
dudmuck | 18:9530d682fd9a | 1827 | uint8_t cr = lora.getCodingRate(false); // false: TX coding rate |
dudmuck | 18:9530d682fd9a | 1828 | if (cr == 4) |
dudmuck | 18:9530d682fd9a | 1829 | cr = 0; |
dudmuck | 18:9530d682fd9a | 1830 | else |
dudmuck | 18:9530d682fd9a | 1831 | cr++; |
dudmuck | 18:9530d682fd9a | 1832 | |
dudmuck | 18:9530d682fd9a | 1833 | lora.setCodingRate(cr); |
dudmuck | 18:9530d682fd9a | 1834 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1835 | printf("tx cr:%d\r\n", cr); |
dudmuck | 18:9530d682fd9a | 1836 | break; |
dudmuck | 18:9530d682fd9a | 1837 | } |
dudmuck | 18:9530d682fd9a | 1838 | case TXTICKER_STATE_TOG_HEADER_MODE: |
dudmuck | 18:9530d682fd9a | 1839 | { |
dudmuck | 18:9530d682fd9a | 1840 | lora.setHeaderMode(!lora.getHeaderMode()); |
dudmuck | 18:9530d682fd9a | 1841 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1842 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 1843 | lora_printHeaderMode(); |
dudmuck | 18:9530d682fd9a | 1844 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1845 | break; |
dudmuck | 18:9530d682fd9a | 1846 | } |
dudmuck | 18:9530d682fd9a | 1847 | case TXTICKER_STATE_TOG_CRC_ON: |
dudmuck | 18:9530d682fd9a | 1848 | { |
dudmuck | 18:9530d682fd9a | 1849 | lora.setRxPayloadCrcOn(!lora.getRxPayloadCrcOn()); |
dudmuck | 18:9530d682fd9a | 1850 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1851 | printf("crc on:%d\r\n", lora.getRxPayloadCrcOn()); |
dudmuck | 18:9530d682fd9a | 1852 | break; |
dudmuck | 18:9530d682fd9a | 1853 | } |
dudmuck | 18:9530d682fd9a | 1854 | case TXTICKER_STATE_CYCLE_SYNC_1: |
dudmuck | 18:9530d682fd9a | 1855 | { |
dudmuck | 18:9530d682fd9a | 1856 | /* cycle hi nibble of 0x39 register */ |
dudmuck | 18:9530d682fd9a | 1857 | if ((txticker_sync_byte & 0xf0) == 0xf0) |
dudmuck | 18:9530d682fd9a | 1858 | txticker_sync_byte &= 0x0f; |
dudmuck | 18:9530d682fd9a | 1859 | else |
dudmuck | 18:9530d682fd9a | 1860 | txticker_sync_byte += 0x10; |
dudmuck | 18:9530d682fd9a | 1861 | radio.write_reg(REG_LR_SYNC_BYTE, txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1862 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1863 | printf("0x39: %02x\r\n", txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1864 | break; |
dudmuck | 18:9530d682fd9a | 1865 | } |
dudmuck | 18:9530d682fd9a | 1866 | case TXTICKER_STATE_CYCLE_SYNC_2: |
dudmuck | 18:9530d682fd9a | 1867 | { |
dudmuck | 18:9530d682fd9a | 1868 | /* cycle lo nibble of 0x39 register */ |
dudmuck | 18:9530d682fd9a | 1869 | if ((txticker_sync_byte & 0x0f) == 0x0f) |
dudmuck | 18:9530d682fd9a | 1870 | txticker_sync_byte &= 0xf0; |
dudmuck | 18:9530d682fd9a | 1871 | else |
dudmuck | 18:9530d682fd9a | 1872 | txticker_sync_byte += 0x01; |
dudmuck | 18:9530d682fd9a | 1873 | radio.write_reg(REG_LR_SYNC_BYTE, txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1874 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1875 | printf("0x39: %02x\r\n", txticker_sync_byte); |
dudmuck | 18:9530d682fd9a | 1876 | break; |
dudmuck | 18:9530d682fd9a | 1877 | } |
dudmuck | 18:9530d682fd9a | 1878 | case TXTICKER_STATE_RAMP_PAYLOAD_DATA_START: |
dudmuck | 18:9530d682fd9a | 1879 | txticker_state = TXTICKER_STATE_RAMP_PAYLOAD_DATA; |
dudmuck | 18:9530d682fd9a | 1880 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1881 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1882 | |
dudmuck | 18:9530d682fd9a | 1883 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1884 | printf("payload start, len:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1885 | break; |
dudmuck | 18:9530d682fd9a | 1886 | case TXTICKER_STATE_RAMP_PAYLOAD_DATA: |
dudmuck | 18:9530d682fd9a | 1887 | for (i = lora.RegPayloadLength-1; i >= 0; i--) { |
dudmuck | 18:9530d682fd9a | 1888 | //printf("i:%d ", i); |
dudmuck | 18:9530d682fd9a | 1889 | if (radio.tx_buf[i] == 255) { |
dudmuck | 18:9530d682fd9a | 1890 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1891 | } else { |
dudmuck | 18:9530d682fd9a | 1892 | radio.tx_buf[i]++; |
dudmuck | 18:9530d682fd9a | 1893 | break; |
dudmuck | 18:9530d682fd9a | 1894 | } |
dudmuck | 18:9530d682fd9a | 1895 | } |
dudmuck | 18:9530d682fd9a | 1896 | //printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1897 | printf("send:"); |
dudmuck | 18:9530d682fd9a | 1898 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 1899 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1900 | } |
dudmuck | 18:9530d682fd9a | 1901 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1902 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1903 | if (radio.tx_buf[0] == 255) { |
dudmuck | 18:9530d682fd9a | 1904 | printf("payload ramp done\r\n"); |
dudmuck | 18:9530d682fd9a | 1905 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1906 | } |
dudmuck | 18:9530d682fd9a | 1907 | break; |
dudmuck | 18:9530d682fd9a | 1908 | case TXTICKER_STATE_SYMBOL_SWEEP: // fpsNL command, where N=symbol num, L=nbytes |
dudmuck | 18:9530d682fd9a | 1909 | { |
dudmuck | 18:9530d682fd9a | 1910 | uint32_t mask; |
dudmuck | 18:9530d682fd9a | 1911 | /*for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1912 | radio.tx_buf[i] = 0;*/ |
dudmuck | 18:9530d682fd9a | 1913 | i = byte_pad_length; |
dudmuck | 19:be8a8b0e7320 | 1914 | printf("bit_counter 0x%" PRIx32 " : ", symbol_sweep_bit_counter); |
dudmuck | 18:9530d682fd9a | 1915 | for (int bn = 0; bn < symbol_sweep_nbits; bn += 2) { |
dudmuck | 18:9530d682fd9a | 1916 | /* 2 lsbits going into first byte */ |
dudmuck | 18:9530d682fd9a | 1917 | mask = 1 << bn; |
dudmuck | 18:9530d682fd9a | 1918 | if (symbol_sweep_bit_counter & mask) |
dudmuck | 18:9530d682fd9a | 1919 | radio.tx_buf[i] |= 1 << symbol_num; |
dudmuck | 18:9530d682fd9a | 1920 | else |
dudmuck | 18:9530d682fd9a | 1921 | radio.tx_buf[i] &= ~(1 << symbol_num); |
dudmuck | 18:9530d682fd9a | 1922 | mask = 2 << bn; |
dudmuck | 18:9530d682fd9a | 1923 | if (symbol_sweep_bit_counter & mask) |
dudmuck | 18:9530d682fd9a | 1924 | radio.tx_buf[i] |= 0x10 << symbol_num; |
dudmuck | 18:9530d682fd9a | 1925 | else |
dudmuck | 18:9530d682fd9a | 1926 | radio.tx_buf[i] &= ~(0x10 << symbol_num); |
dudmuck | 18:9530d682fd9a | 1927 | //printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1928 | i++; |
dudmuck | 18:9530d682fd9a | 1929 | } |
dudmuck | 18:9530d682fd9a | 1930 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 18:9530d682fd9a | 1931 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1932 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1933 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1934 | if (++symbol_sweep_bit_counter == symbol_sweep_bit_counter_stop) { |
dudmuck | 18:9530d682fd9a | 1935 | printf("stop\r\n"); |
dudmuck | 18:9530d682fd9a | 1936 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1937 | } |
dudmuck | 18:9530d682fd9a | 1938 | } |
dudmuck | 18:9530d682fd9a | 1939 | break; |
dudmuck | 18:9530d682fd9a | 1940 | case TXTICKER_STATE_TOGGLE_ALL_BITS_START: |
dudmuck | 18:9530d682fd9a | 1941 | tab_current_byte_num = byte_pad_length; |
dudmuck | 18:9530d682fd9a | 1942 | tab_current_bit_in_byte = 0; |
dudmuck | 18:9530d682fd9a | 1943 | printf("tx "); |
dudmuck | 18:9530d682fd9a | 1944 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 1945 | radio.tx_buf[i] = 0; |
dudmuck | 18:9530d682fd9a | 1946 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1947 | } |
dudmuck | 18:9530d682fd9a | 1948 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1949 | txticker_state = TXTICKER_STATE_TOGGLE_ALL_BITS; |
dudmuck | 18:9530d682fd9a | 1950 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1951 | break; |
dudmuck | 18:9530d682fd9a | 1952 | case TXTICKER_STATE_TOGGLE_ALL_BITS: |
dudmuck | 18:9530d682fd9a | 1953 | { |
dudmuck | 18:9530d682fd9a | 1954 | uint8_t mask = 1 << tab_current_bit_in_byte; |
dudmuck | 18:9530d682fd9a | 1955 | radio.tx_buf[tab_current_byte_num] = mask; |
dudmuck | 18:9530d682fd9a | 1956 | printf("bit%d in [%d]: tx ", tab_current_bit_in_byte, tab_current_byte_num); |
dudmuck | 18:9530d682fd9a | 1957 | for (i = 0; i < lora.RegPayloadLength; i++) { |
dudmuck | 18:9530d682fd9a | 1958 | printf("%02x ", radio.tx_buf[i]); |
dudmuck | 18:9530d682fd9a | 1959 | } |
dudmuck | 18:9530d682fd9a | 1960 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1961 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 1962 | if (++tab_current_bit_in_byte == 8) { |
dudmuck | 18:9530d682fd9a | 1963 | radio.tx_buf[tab_current_byte_num] = 0; |
dudmuck | 18:9530d682fd9a | 1964 | tab_current_bit_in_byte = 0; |
dudmuck | 18:9530d682fd9a | 1965 | if (++tab_current_byte_num == lora.RegPayloadLength) { |
dudmuck | 18:9530d682fd9a | 1966 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1967 | } |
dudmuck | 18:9530d682fd9a | 1968 | } |
dudmuck | 18:9530d682fd9a | 1969 | } |
dudmuck | 18:9530d682fd9a | 1970 | break; |
dudmuck | 18:9530d682fd9a | 1971 | default: |
dudmuck | 18:9530d682fd9a | 1972 | tx_ticker.detach(); |
dudmuck | 18:9530d682fd9a | 1973 | break; |
dudmuck | 18:9530d682fd9a | 1974 | } // ...switch (txticker_state) |
dudmuck | 18:9530d682fd9a | 1975 | } |
dudmuck | 18:9530d682fd9a | 1976 | |
dudmuck | 18:9530d682fd9a | 1977 | void ook_test_tx(int len) |
dudmuck | 18:9530d682fd9a | 1978 | { |
dudmuck | 18:9530d682fd9a | 1979 | int i; |
dudmuck | 18:9530d682fd9a | 1980 | /* |
dudmuck | 18:9530d682fd9a | 1981 | fsk.RegPktConfig2.bits.PayloadLength = i; |
dudmuck | 18:9530d682fd9a | 1982 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word);fsk.RegPktConfig2.bits.PayloadLength = i; |
dudmuck | 18:9530d682fd9a | 1983 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 18:9530d682fd9a | 1984 | */ |
dudmuck | 18:9530d682fd9a | 1985 | for (i = 0; i < 4; i++) { |
dudmuck | 18:9530d682fd9a | 1986 | radio.tx_buf[i] = 0xaa; |
dudmuck | 18:9530d682fd9a | 1987 | } |
dudmuck | 18:9530d682fd9a | 1988 | |
dudmuck | 18:9530d682fd9a | 1989 | printf("ooktx:"); |
dudmuck | 18:9530d682fd9a | 1990 | for (i = 0; i < len; i++) { |
dudmuck | 18:9530d682fd9a | 1991 | radio.tx_buf[i+4] = rand() & 0xff; |
dudmuck | 18:9530d682fd9a | 1992 | printf("%02x ", radio.tx_buf[i+4]); |
dudmuck | 18:9530d682fd9a | 1993 | } |
dudmuck | 18:9530d682fd9a | 1994 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 1995 | fsk.start_tx(len+4); |
dudmuck | 18:9530d682fd9a | 1996 | |
dudmuck | 18:9530d682fd9a | 1997 | while (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { |
dudmuck | 18:9530d682fd9a | 1998 | if (poll_irq_en) |
dudmuck | 18:9530d682fd9a | 1999 | poll_service_radio(); |
dudmuck | 18:9530d682fd9a | 2000 | else |
dudmuck | 18:9530d682fd9a | 2001 | service_radio(); |
dudmuck | 18:9530d682fd9a | 2002 | } |
dudmuck | 18:9530d682fd9a | 2003 | } |
dudmuck | 18:9530d682fd9a | 2004 | |
dudmuck | 18:9530d682fd9a | 2005 | void cmd_init(uint8_t args_at) |
dudmuck | 10:d9bb2ce57f05 | 2006 | { |
dudmuck | 18:9530d682fd9a | 2007 | printf("init\r\n"); |
dudmuck | 18:9530d682fd9a | 2008 | radio.init(); |
dudmuck | 18:9530d682fd9a | 2009 | if (!radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 2010 | fsk.init(); // put FSK modem to some functioning default |
dudmuck | 18:9530d682fd9a | 2011 | } else { |
dudmuck | 18:9530d682fd9a | 2012 | // lora configuration is more simple |
dudmuck | 18:9530d682fd9a | 2013 | } |
dudmuck | 18:9530d682fd9a | 2014 | } |
dudmuck | 18:9530d682fd9a | 2015 | |
dudmuck | 18:9530d682fd9a | 2016 | void cmd_per_tx_delay(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2017 | { |
dudmuck | 18:9530d682fd9a | 2018 | int i; |
dudmuck | 18:9530d682fd9a | 2019 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2020 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2021 | per_tx_delay = i / 1000.0; |
dudmuck | 18:9530d682fd9a | 2022 | } |
dudmuck | 18:9530d682fd9a | 2023 | printf("per_tx_delay:%dms\r\n", (int)(per_tx_delay * 1000)); |
dudmuck | 18:9530d682fd9a | 2024 | } |
dudmuck | 18:9530d682fd9a | 2025 | |
dudmuck | 21:b84a77dfb43c | 2026 | const uint8_t test_payload_A[7] = { |
dudmuck | 21:b84a77dfb43c | 2027 | 0x80, 0x02, 0x58, 0xF5, 0xDF, 0xB8, 0x9E |
dudmuck | 21:b84a77dfb43c | 2028 | }; |
dudmuck | 21:b84a77dfb43c | 2029 | |
dudmuck | 21:b84a77dfb43c | 2030 | const uint8_t test_payload_B[] = { |
dudmuck | 21:b84a77dfb43c | 2031 | 0xca, 0xfe, 0xba, 0xbe |
dudmuck | 21:b84a77dfb43c | 2032 | }; |
dudmuck | 21:b84a77dfb43c | 2033 | |
dudmuck | 21:b84a77dfb43c | 2034 | const uint8_t test_payload_C[0x1a] = { |
dudmuck | 21:b84a77dfb43c | 2035 | 0x88, 0x39, 0x1F, 0xC6, 0xD3, 0xEB, 0xA4, 0xAC, |
dudmuck | 21:b84a77dfb43c | 2036 | 0xFB, 0xB9, 0xBA, 0xB9, 0xBE, 0x13, 0x61, 0x4C, |
dudmuck | 21:b84a77dfb43c | 2037 | 0x43, 0x83, 0x00, 0x92, 0x84, 0x00, 0x6F, 0x87, |
dudmuck | 21:b84a77dfb43c | 2038 | 0x7C, 0xB2 |
dudmuck | 21:b84a77dfb43c | 2039 | }; |
dudmuck | 21:b84a77dfb43c | 2040 | |
dudmuck | 18:9530d682fd9a | 2041 | void cmd_tx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2042 | { |
dudmuck | 18:9530d682fd9a | 2043 | int i; |
dudmuck | 18:9530d682fd9a | 2044 | static uint16_t fsk_tx_length; |
dudmuck | 18:9530d682fd9a | 2045 | |
dudmuck | 18:9530d682fd9a | 2046 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 2047 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2048 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2049 | lora.RegPayloadLength = i; |
dudmuck | 18:9530d682fd9a | 2050 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2051 | } |
dudmuck | 18:9530d682fd9a | 2052 | |
dudmuck | 21:b84a77dfb43c | 2053 | if (pcbuf[idx] == 'A') { |
dudmuck | 21:b84a77dfb43c | 2054 | } else if (pcbuf[idx] == 'B') { |
dudmuck | 21:b84a77dfb43c | 2055 | } else if (pcbuf[idx] == 'C') { |
dudmuck | 21:b84a77dfb43c | 2056 | } else { |
dudmuck | 21:b84a77dfb43c | 2057 | tx_cnt++; |
dudmuck | 21:b84a77dfb43c | 2058 | printf("payload:%02x\r\n", tx_cnt); |
dudmuck | 21:b84a77dfb43c | 2059 | |
dudmuck | 21:b84a77dfb43c | 2060 | for (i = 0; i < lora.RegPayloadLength; i++) |
dudmuck | 21:b84a77dfb43c | 2061 | radio.tx_buf[i] = tx_cnt; |
dudmuck | 21:b84a77dfb43c | 2062 | } |
dudmuck | 21:b84a77dfb43c | 2063 | |
dudmuck | 18:9530d682fd9a | 2064 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 2065 | } else { // FSK: |
dudmuck | 21:b84a77dfb43c | 2066 | |
dudmuck | 21:b84a77dfb43c | 2067 | /* always variable-length format */ |
dudmuck | 21:b84a77dfb43c | 2068 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2069 | if (!fsk.RegPktConfig1.bits.PacketFormatVariable) { |
dudmuck | 21:b84a77dfb43c | 2070 | printf("fsk fixed->variable\r\n"); |
dudmuck | 21:b84a77dfb43c | 2071 | fsk.RegPktConfig1.bits.PacketFormatVariable = 1; |
dudmuck | 21:b84a77dfb43c | 2072 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2073 | } |
dudmuck | 21:b84a77dfb43c | 2074 | |
dudmuck | 18:9530d682fd9a | 2075 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2076 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2077 | fsk_tx_length = i; |
dudmuck | 18:9530d682fd9a | 2078 | } |
dudmuck | 18:9530d682fd9a | 2079 | if (ook_test_en) { |
dudmuck | 18:9530d682fd9a | 2080 | ook_test_tx(fsk_tx_length); |
dudmuck | 18:9530d682fd9a | 2081 | } else { |
dudmuck | 18:9530d682fd9a | 2082 | if (radio.RegOpMode.bits.Mode != RF_OPMODE_TRANSMITTER) { // if not already busy transmitting |
dudmuck | 21:b84a77dfb43c | 2083 | if (pcbuf[idx] == 'A') { |
dudmuck | 21:b84a77dfb43c | 2084 | fsk_tx_length = sizeof(test_payload_A); |
dudmuck | 21:b84a77dfb43c | 2085 | memcpy(radio.tx_buf, test_payload_A, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2086 | } else if (pcbuf[idx] == 'B') { |
dudmuck | 21:b84a77dfb43c | 2087 | fsk_tx_length = sizeof(test_payload_B); |
dudmuck | 21:b84a77dfb43c | 2088 | memcpy(radio.tx_buf, test_payload_B, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2089 | } else if (pcbuf[idx] == 'C') { |
dudmuck | 21:b84a77dfb43c | 2090 | fsk_tx_length = sizeof(test_payload_C); |
dudmuck | 21:b84a77dfb43c | 2091 | memcpy(radio.tx_buf, test_payload_C, fsk_tx_length); |
dudmuck | 21:b84a77dfb43c | 2092 | } else { |
dudmuck | 21:b84a77dfb43c | 2093 | tx_cnt++; |
dudmuck | 21:b84a77dfb43c | 2094 | printf("payload:%02x\r\n", tx_cnt); |
dudmuck | 21:b84a77dfb43c | 2095 | for (i = 0; i < fsk_tx_length; i++) { |
dudmuck | 21:b84a77dfb43c | 2096 | radio.tx_buf[i] = tx_cnt; |
dudmuck | 21:b84a77dfb43c | 2097 | } |
dudmuck | 18:9530d682fd9a | 2098 | } |
dudmuck | 21:b84a77dfb43c | 2099 | |
dudmuck | 18:9530d682fd9a | 2100 | fsk.start_tx(fsk_tx_length); |
dudmuck | 18:9530d682fd9a | 2101 | } |
dudmuck | 18:9530d682fd9a | 2102 | } |
dudmuck | 18:9530d682fd9a | 2103 | } // !LoRa |
dudmuck | 18:9530d682fd9a | 2104 | |
dudmuck | 18:9530d682fd9a | 2105 | } |
dudmuck | 18:9530d682fd9a | 2106 | |
dudmuck | 21:b84a77dfb43c | 2107 | volatile uint16_t long_byte_count, long_byte_count_at_full; |
dudmuck | 21:b84a77dfb43c | 2108 | |
dudmuck | 21:b84a77dfb43c | 2109 | const uint8_t test_preamble_sync[] = { |
dudmuck | 21:b84a77dfb43c | 2110 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xcb, 0x82 |
dudmuck | 21:b84a77dfb43c | 2111 | }; |
dudmuck | 21:b84a77dfb43c | 2112 | |
dudmuck | 21:b84a77dfb43c | 2113 | void _ulm_write_fifo(uint8_t len) |
dudmuck | 21:b84a77dfb43c | 2114 | { |
dudmuck | 21:b84a77dfb43c | 2115 | uint8_t i; |
dudmuck | 21:b84a77dfb43c | 2116 | |
dudmuck | 21:b84a77dfb43c | 2117 | //dio2 is FifoFull |
dudmuck | 21:b84a77dfb43c | 2118 | radio.m_cs = 0; |
dudmuck | 21:b84a77dfb43c | 2119 | radio.m_spi.write(REG_FIFO | 0x80); // bit7 is high for writing to radio |
dudmuck | 21:b84a77dfb43c | 2120 | |
dudmuck | 21:b84a77dfb43c | 2121 | for (i = 0; i < len; ) { |
dudmuck | 21:b84a77dfb43c | 2122 | //printf("_%02x\r\n", radio.tx_buf[i]); |
dudmuck | 21:b84a77dfb43c | 2123 | radio.m_spi.write(radio.tx_buf[i++]); |
dudmuck | 21:b84a77dfb43c | 2124 | long_byte_count++; |
dudmuck | 21:b84a77dfb43c | 2125 | if (dio2) { |
dudmuck | 21:b84a77dfb43c | 2126 | long_byte_count_at_full = long_byte_count; |
dudmuck | 21:b84a77dfb43c | 2127 | while (radio.dio1) |
dudmuck | 21:b84a77dfb43c | 2128 | ; |
dudmuck | 21:b84a77dfb43c | 2129 | } |
dudmuck | 21:b84a77dfb43c | 2130 | } |
dudmuck | 21:b84a77dfb43c | 2131 | radio.m_cs = 1; |
dudmuck | 21:b84a77dfb43c | 2132 | } |
dudmuck | 21:b84a77dfb43c | 2133 | |
dudmuck | 21:b84a77dfb43c | 2134 | int write_buf_to_fifo(const uint8_t* send_buf, uint8_t target_length) |
dudmuck | 21:b84a77dfb43c | 2135 | { |
dudmuck | 21:b84a77dfb43c | 2136 | /* block until all is written */ |
dudmuck | 21:b84a77dfb43c | 2137 | uint8_t total_sent = 0; |
dudmuck | 21:b84a77dfb43c | 2138 | |
dudmuck | 21:b84a77dfb43c | 2139 | //printf("wbtf %u\r\n", target_length); |
dudmuck | 21:b84a77dfb43c | 2140 | while (target_length > total_sent) { |
dudmuck | 21:b84a77dfb43c | 2141 | uint8_t this_length = target_length - total_sent; |
dudmuck | 21:b84a77dfb43c | 2142 | memcpy(radio.tx_buf+total_sent, send_buf+total_sent, this_length); |
dudmuck | 21:b84a77dfb43c | 2143 | _ulm_write_fifo(this_length); |
dudmuck | 21:b84a77dfb43c | 2144 | total_sent += this_length; |
dudmuck | 21:b84a77dfb43c | 2145 | } |
dudmuck | 21:b84a77dfb43c | 2146 | return total_sent; |
dudmuck | 21:b84a77dfb43c | 2147 | } |
dudmuck | 21:b84a77dfb43c | 2148 | |
dudmuck | 21:b84a77dfb43c | 2149 | #define TEST_PAYLOAD test_payload_C |
dudmuck | 21:b84a77dfb43c | 2150 | //#define TEST_PAYLOAD test_payload_A |
dudmuck | 21:b84a77dfb43c | 2151 | void cmd_long_tx(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2152 | { |
dudmuck | 21:b84a77dfb43c | 2153 | unsigned int pkt_cnt = 0; |
dudmuck | 21:b84a77dfb43c | 2154 | bool first_pkt; |
dudmuck | 21:b84a77dfb43c | 2155 | /* transmit multipe packets without any time between packets (back to back) */ |
dudmuck | 21:b84a77dfb43c | 2156 | |
dudmuck | 21:b84a77dfb43c | 2157 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 21:b84a77dfb43c | 2158 | sscanf(pcbuf+idx, "%u", &pkt_cnt); |
dudmuck | 21:b84a77dfb43c | 2159 | } |
dudmuck | 21:b84a77dfb43c | 2160 | |
dudmuck | 21:b84a77dfb43c | 2161 | printf("tx %u pkts\r\n", pkt_cnt); |
dudmuck | 21:b84a77dfb43c | 2162 | if (pkt_cnt < 1) |
dudmuck | 21:b84a77dfb43c | 2163 | return; |
dudmuck | 21:b84a77dfb43c | 2164 | |
dudmuck | 21:b84a77dfb43c | 2165 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 21:b84a77dfb43c | 2166 | radio.RegDioMapping2.bits.Dio5Mapping = 2; // data output to observation |
dudmuck | 21:b84a77dfb43c | 2167 | radio.RegDioMapping2.bits.Dio4Mapping = 3; // output preamble detect indication |
dudmuck | 21:b84a77dfb43c | 2168 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; |
dudmuck | 21:b84a77dfb43c | 2169 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 21:b84a77dfb43c | 2170 | |
dudmuck | 21:b84a77dfb43c | 2171 | //unlimited packet length mode |
dudmuck | 21:b84a77dfb43c | 2172 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2173 | fsk.RegPktConfig1.bits.PacketFormatVariable = 0; // fixed length format |
dudmuck | 21:b84a77dfb43c | 2174 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2175 | |
dudmuck | 21:b84a77dfb43c | 2176 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 21:b84a77dfb43c | 2177 | fsk.RegPktConfig2.bits.PayloadLength = 0; |
dudmuck | 21:b84a77dfb43c | 2178 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 21:b84a77dfb43c | 2179 | //DIO3 to FifoEmpty (for end of tx) |
dudmuck | 21:b84a77dfb43c | 2180 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 2181 | radio.RegDioMapping1.bits.Dio3Mapping = 0; // FifoEmpty |
dudmuck | 21:b84a77dfb43c | 2182 | //DIO2 to FifoFull |
dudmuck | 21:b84a77dfb43c | 2183 | radio.RegDioMapping1.bits.Dio2Mapping = 0; // FIfoFull |
dudmuck | 21:b84a77dfb43c | 2184 | //DIO1 to FifoLevel |
dudmuck | 21:b84a77dfb43c | 2185 | radio.RegDioMapping1.bits.Dio1Mapping = 0; // FifoLevel |
dudmuck | 21:b84a77dfb43c | 2186 | radio.RegDioMapping1.bits.Dio0Mapping = 0; // PacketSent |
dudmuck | 21:b84a77dfb43c | 2187 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 21:b84a77dfb43c | 2188 | //FifoThreshold to approx 1/5th full |
dudmuck | 21:b84a77dfb43c | 2189 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 21:b84a77dfb43c | 2190 | fsk.RegFifoThreshold.bits.FifoThreshold = sizeof(TEST_PAYLOAD)-1; // allow single packet |
dudmuck | 21:b84a77dfb43c | 2191 | // tx start condition to FifoLevel |
dudmuck | 21:b84a77dfb43c | 2192 | fsk.RegFifoThreshold.bits.TxStartCondition = 0; // start on FifoLevel |
dudmuck | 21:b84a77dfb43c | 2193 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 21:b84a77dfb43c | 2194 | |
dudmuck | 21:b84a77dfb43c | 2195 | long_byte_count = 0; |
dudmuck | 21:b84a77dfb43c | 2196 | long_byte_count_at_full = 0xffff; |
dudmuck | 21:b84a77dfb43c | 2197 | |
dudmuck | 21:b84a77dfb43c | 2198 | radio.set_opmode(RF_OPMODE_TRANSMITTER); |
dudmuck | 21:b84a77dfb43c | 2199 | first_pkt = true; // preamble+sync sent by packet engine only for first packet |
dudmuck | 21:b84a77dfb43c | 2200 | for (; pkt_cnt > 0; pkt_cnt--) { |
dudmuck | 21:b84a77dfb43c | 2201 | uint8_t len; |
dudmuck | 21:b84a77dfb43c | 2202 | if (first_pkt) |
dudmuck | 21:b84a77dfb43c | 2203 | first_pkt = false; |
dudmuck | 21:b84a77dfb43c | 2204 | else { |
dudmuck | 21:b84a77dfb43c | 2205 | if (dio3) { |
dudmuck | 21:b84a77dfb43c | 2206 | printf("fail-empty\r\n"); |
dudmuck | 21:b84a77dfb43c | 2207 | } |
dudmuck | 21:b84a77dfb43c | 2208 | write_buf_to_fifo(test_preamble_sync, sizeof(test_preamble_sync)); |
dudmuck | 21:b84a77dfb43c | 2209 | } |
dudmuck | 21:b84a77dfb43c | 2210 | |
dudmuck | 21:b84a77dfb43c | 2211 | len = sizeof(TEST_PAYLOAD); //TEST_PAYLOAD doesnt start with length |
dudmuck | 21:b84a77dfb43c | 2212 | write_buf_to_fifo(&len, 1); |
dudmuck | 21:b84a77dfb43c | 2213 | write_buf_to_fifo(TEST_PAYLOAD, sizeof(TEST_PAYLOAD)); |
dudmuck | 21:b84a77dfb43c | 2214 | } // .. |
dudmuck | 21:b84a77dfb43c | 2215 | |
dudmuck | 21:b84a77dfb43c | 2216 | rx_start_timer.reset(); |
dudmuck | 21:b84a77dfb43c | 2217 | rx_start_timer.start(); |
dudmuck | 21:b84a77dfb43c | 2218 | while (!dio3) { |
dudmuck | 21:b84a77dfb43c | 2219 | if (rx_start_timer.read() > 1) { |
dudmuck | 21:b84a77dfb43c | 2220 | printf("fifoEmpty fail\r\n"); |
dudmuck | 21:b84a77dfb43c | 2221 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2222 | return; |
dudmuck | 21:b84a77dfb43c | 2223 | } |
dudmuck | 21:b84a77dfb43c | 2224 | } |
dudmuck | 21:b84a77dfb43c | 2225 | |
dudmuck | 21:b84a77dfb43c | 2226 | rx_start_timer.reset(); |
dudmuck | 21:b84a77dfb43c | 2227 | rx_start_timer.start(); |
dudmuck | 21:b84a77dfb43c | 2228 | while (!radio.dio0) { |
dudmuck | 21:b84a77dfb43c | 2229 | if (rx_start_timer.read() > 3) { |
dudmuck | 21:b84a77dfb43c | 2230 | printf("PacketSent fail\r\n"); |
dudmuck | 21:b84a77dfb43c | 2231 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2232 | return; |
dudmuck | 21:b84a77dfb43c | 2233 | } |
dudmuck | 21:b84a77dfb43c | 2234 | } |
dudmuck | 21:b84a77dfb43c | 2235 | wait_us(100); |
dudmuck | 21:b84a77dfb43c | 2236 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2237 | printf("done ok %u, %u\r\n", long_byte_count, long_byte_count_at_full); |
dudmuck | 21:b84a77dfb43c | 2238 | |
dudmuck | 21:b84a77dfb43c | 2239 | } |
dudmuck | 21:b84a77dfb43c | 2240 | |
dudmuck | 18:9530d682fd9a | 2241 | void cmd_hw_reset(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2242 | { |
dudmuck | 18:9530d682fd9a | 2243 | printf("hw_reset()\r\n"); |
dudmuck | 18:9530d682fd9a | 2244 | radio.hw_reset(); |
dudmuck | 18:9530d682fd9a | 2245 | ook_test_en = false; |
dudmuck | 18:9530d682fd9a | 2246 | poll_irq_en = false; |
dudmuck | 18:9530d682fd9a | 2247 | } |
dudmuck | 18:9530d682fd9a | 2248 | |
dudmuck | 18:9530d682fd9a | 2249 | void cmd_read_all_regs(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2250 | { |
dudmuck | 18:9530d682fd9a | 2251 | uint8_t a, d; |
dudmuck | 18:9530d682fd9a | 2252 | |
dudmuck | 18:9530d682fd9a | 2253 | // read all registers |
dudmuck | 18:9530d682fd9a | 2254 | for (a = 1; a < 0x71; a++) { |
dudmuck | 18:9530d682fd9a | 2255 | d = radio.read_reg(a); |
dudmuck | 18:9530d682fd9a | 2256 | printf("%02x: %02x\r\n", a, d); |
dudmuck | 18:9530d682fd9a | 2257 | } |
dudmuck | 18:9530d682fd9a | 2258 | } |
dudmuck | 18:9530d682fd9a | 2259 | |
dudmuck | 18:9530d682fd9a | 2260 | void cmd_read_current_rssi(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2261 | { |
dudmuck | 18:9530d682fd9a | 2262 | if (radio.RegOpMode.bits.Mode != RF_OPMODE_RECEIVER) { |
dudmuck | 18:9530d682fd9a | 2263 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 18:9530d682fd9a | 2264 | wait_us(10000); |
dudmuck | 18:9530d682fd9a | 2265 | } |
dudmuck | 18:9530d682fd9a | 2266 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2267 | printf("rssi:%ddBm\r\n", lora.get_current_rssi()); |
dudmuck | 18:9530d682fd9a | 2268 | else |
dudmuck | 18:9530d682fd9a | 2269 | printf("rssi:-%.1f\r\n", radio.read_reg(REG_FSK_RSSIVALUE) / 2.0); |
dudmuck | 18:9530d682fd9a | 2270 | } |
dudmuck | 18:9530d682fd9a | 2271 | |
dudmuck | 21:b84a77dfb43c | 2272 | void cmd_rssi_polling(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2273 | { |
dudmuck | 21:b84a77dfb43c | 2274 | if ((pcbuf[idx] >= '0' && pcbuf[idx] <= '9') || pcbuf[idx] == '-') { |
dudmuck | 21:b84a77dfb43c | 2275 | sscanf(pcbuf+idx, "%d", &rssi_polling_thresh); |
dudmuck | 21:b84a77dfb43c | 2276 | } |
dudmuck | 21:b84a77dfb43c | 2277 | printf("rssi_polling_thresh:%d\r\n", rssi_polling_thresh); |
dudmuck | 21:b84a77dfb43c | 2278 | } |
dudmuck | 21:b84a77dfb43c | 2279 | |
dudmuck | 18:9530d682fd9a | 2280 | void cmd_lora_continuous_tx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2281 | { |
dudmuck | 18:9530d682fd9a | 2282 | /* TxContinuousMode same for sx1272 and sx1276 */ |
dudmuck | 18:9530d682fd9a | 2283 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2284 | lora.RegModemConfig2.sx1276bits.TxContinuousMode ^= 1; |
dudmuck | 18:9530d682fd9a | 2285 | radio.write_reg(REG_LR_MODEMCONFIG2, lora.RegModemConfig2.octet); |
dudmuck | 18:9530d682fd9a | 2286 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 13:c73caaee93a5 | 2287 | |
dudmuck | 18:9530d682fd9a | 2288 | lora_printTxContinuousMode(); |
dudmuck | 18:9530d682fd9a | 2289 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2290 | } |
dudmuck | 18:9530d682fd9a | 2291 | |
dudmuck | 18:9530d682fd9a | 2292 | void cmd_fsk_test_case(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2293 | { |
dudmuck | 18:9530d682fd9a | 2294 | if (pcbuf[idx] < '0' || pcbuf[idx] > '9') { |
dudmuck | 19:be8a8b0e7320 | 2295 | printf("%" PRIu32 "bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 19:be8a8b0e7320 | 2296 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 19:be8a8b0e7320 | 2297 | printf("afcbw:%" PRIu32 "Hz preambleLen:%" PRIu16 "\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 18:9530d682fd9a | 2298 | } else { |
dudmuck | 18:9530d682fd9a | 2299 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 2300 | per_tx_delay = 0.3; |
dudmuck | 18:9530d682fd9a | 2301 | |
dudmuck | 18:9530d682fd9a | 2302 | if (radio.read_reg(REG_FSK_SYNCVALUE1) == 0x55 && radio.read_reg(REG_FSK_SYNCVALUE2)) { |
dudmuck | 18:9530d682fd9a | 2303 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 18:9530d682fd9a | 2304 | fsk.RegSyncConfig.bits.SyncSize = 2; |
dudmuck | 18:9530d682fd9a | 2305 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 2306 | radio.write_reg(REG_FSK_SYNCVALUE3, 0x90); |
dudmuck | 18:9530d682fd9a | 2307 | radio.write_reg(REG_FSK_SYNCVALUE2, 0x4e); |
dudmuck | 18:9530d682fd9a | 2308 | radio.write_reg(REG_FSK_SYNCVALUE1, 0x63); |
dudmuck | 18:9530d682fd9a | 2309 | } |
dudmuck | 18:9530d682fd9a | 2310 | |
dudmuck | 18:9530d682fd9a | 2311 | fsk.RegPreambleDetect.octet = radio.read_reg(REG_FSK_PREAMBLEDETECT); |
dudmuck | 18:9530d682fd9a | 2312 | fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 18:9530d682fd9a | 2313 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 2314 | |
dudmuck | 18:9530d682fd9a | 2315 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 18:9530d682fd9a | 2316 | fsk.RegRxConfig.bits.AfcAutoOn = 1; |
dudmuck | 18:9530d682fd9a | 2317 | fsk.RegRxConfig.bits.AgcAutoOn = 1; |
dudmuck | 20:b11592c9ba5f | 2318 | fsk.RegRxConfig.bits.RxTrigger = 7; // both |
dudmuck | 18:9530d682fd9a | 2319 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 2320 | |
dudmuck | 18:9530d682fd9a | 2321 | fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 18:9530d682fd9a | 2322 | fsk.RegPreambleDetect.bits.PreambleDetectorSize = 1; |
dudmuck | 18:9530d682fd9a | 2323 | fsk.RegPreambleDetect.bits.PreambleDetectorTol = 10; |
dudmuck | 18:9530d682fd9a | 2324 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 2325 | |
dudmuck | 18:9530d682fd9a | 2326 | switch (pcbuf[idx]) { |
dudmuck | 18:9530d682fd9a | 2327 | case '0': |
dudmuck | 18:9530d682fd9a | 2328 | fsk.set_bitrate(4800); |
dudmuck | 18:9530d682fd9a | 2329 | fsk.set_tx_fdev_hz(5005); |
dudmuck | 18:9530d682fd9a | 2330 | fsk.set_rx_dcc_bw_hz(10417, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2331 | fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2332 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2333 | break; |
dudmuck | 18:9530d682fd9a | 2334 | case '1': |
dudmuck | 18:9530d682fd9a | 2335 | fsk.set_bitrate(50000); |
dudmuck | 18:9530d682fd9a | 2336 | fsk.set_tx_fdev_hz(25000); |
dudmuck | 18:9530d682fd9a | 2337 | fsk.set_rx_dcc_bw_hz(62500, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2338 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2339 | radio.write_u16(REG_FSK_PREAMBLEMSB, 9); |
dudmuck | 18:9530d682fd9a | 2340 | break; |
dudmuck | 18:9530d682fd9a | 2341 | case '2': |
dudmuck | 18:9530d682fd9a | 2342 | fsk.set_bitrate(38400); |
dudmuck | 18:9530d682fd9a | 2343 | fsk.set_tx_fdev_hz(20020); |
dudmuck | 18:9530d682fd9a | 2344 | fsk.set_rx_dcc_bw_hz(50000, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2345 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2346 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2347 | break; |
dudmuck | 18:9530d682fd9a | 2348 | case '3': |
dudmuck | 18:9530d682fd9a | 2349 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2350 | fsk.set_tx_fdev_hz(20020); |
dudmuck | 18:9530d682fd9a | 2351 | fsk.set_rx_dcc_bw_hz(25000, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2352 | fsk.set_rx_dcc_bw_hz(50000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2353 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2354 | break; |
dudmuck | 18:9530d682fd9a | 2355 | case '4': |
dudmuck | 18:9530d682fd9a | 2356 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2357 | fsk.set_tx_fdev_hz(4028); |
dudmuck | 18:9530d682fd9a | 2358 | fsk.set_rx_dcc_bw_hz(7813, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2359 | fsk.set_rx_dcc_bw_hz(25000, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2360 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 18:9530d682fd9a | 2361 | break; |
dudmuck | 18:9530d682fd9a | 2362 | case '5': |
dudmuck | 18:9530d682fd9a | 2363 | fsk.set_bitrate(1201); |
dudmuck | 18:9530d682fd9a | 2364 | fsk.set_tx_fdev_hz(4028); |
dudmuck | 18:9530d682fd9a | 2365 | fsk.set_rx_dcc_bw_hz(5208, 0); // rxbw |
dudmuck | 18:9530d682fd9a | 2366 | fsk.set_rx_dcc_bw_hz(10417, 1); // afcbw |
dudmuck | 18:9530d682fd9a | 2367 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 20:b11592c9ba5f | 2368 | break; |
dudmuck | 20:b11592c9ba5f | 2369 | case '6': |
dudmuck | 20:b11592c9ba5f | 2370 | fsk.set_bitrate(65536); |
dudmuck | 20:b11592c9ba5f | 2371 | fsk.set_tx_fdev_hz(16384); |
dudmuck | 20:b11592c9ba5f | 2372 | fsk.set_rx_dcc_bw_hz(62500, 0); // rxbw |
dudmuck | 20:b11592c9ba5f | 2373 | fsk.set_rx_dcc_bw_hz(100000, 1); // afcbw |
dudmuck | 21:b84a77dfb43c | 2374 | |
dudmuck | 21:b84a77dfb43c | 2375 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2376 | fsk.RegPktConfig1.bits.CrcOn = 0; |
dudmuck | 21:b84a77dfb43c | 2377 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2378 | |
dudmuck | 20:b11592c9ba5f | 2379 | radio.write_u16(REG_FSK_PREAMBLEMSB, 5); |
dudmuck | 20:b11592c9ba5f | 2380 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 20:b11592c9ba5f | 2381 | fsk.RegSyncConfig.bits.SyncSize = 2; |
dudmuck | 21:b84a77dfb43c | 2382 | fsk.RegSyncConfig.bits.SyncOn = 1; |
dudmuck | 20:b11592c9ba5f | 2383 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2384 | radio.write_reg(REG_FSK_SYNCVALUE1, 0x33); |
dudmuck | 20:b11592c9ba5f | 2385 | radio.write_reg(REG_FSK_SYNCVALUE2, 0xcb); |
dudmuck | 21:b84a77dfb43c | 2386 | radio.write_reg(REG_FSK_SYNCVALUE3, 0x82); |
dudmuck | 21:b84a77dfb43c | 2387 | |
dudmuck | 21:b84a77dfb43c | 2388 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 21:b84a77dfb43c | 2389 | radio.RegOpMode.bits.ModulationType = 0; // 0 = FSK |
dudmuck | 21:b84a77dfb43c | 2390 | radio.RegOpMode.bits.ModulationShaping = 2; // 2=BT0.5 |
dudmuck | 21:b84a77dfb43c | 2391 | radio.write_reg(REG_OPMODE, radio.RegOpMode.octet); |
dudmuck | 21:b84a77dfb43c | 2392 | |
dudmuck | 21:b84a77dfb43c | 2393 | fsk.RegAfcFei.octet = radio.read_reg(REG_FSK_AFCFEI); |
dudmuck | 21:b84a77dfb43c | 2394 | fsk.RegAfcFei.bits.AfcAutoClearOn = 0; |
dudmuck | 21:b84a77dfb43c | 2395 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 20:b11592c9ba5f | 2396 | |
dudmuck | 20:b11592c9ba5f | 2397 | fsk.RegRxConfig.bits.RxTrigger = 6; // preamble |
dudmuck | 20:b11592c9ba5f | 2398 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 20:b11592c9ba5f | 2399 | radio.RegDioMapping2.bits.Dio4Mapping = 3; |
dudmuck | 20:b11592c9ba5f | 2400 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; // dio4 to preambleDetect in RX |
dudmuck | 20:b11592c9ba5f | 2401 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 20:b11592c9ba5f | 2402 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to SyncAddress in RX |
dudmuck | 20:b11592c9ba5f | 2403 | radio.RegDioMapping1.bits.Dio1Mapping = 1; // to FifoEmpty |
dudmuck | 20:b11592c9ba5f | 2404 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 20:b11592c9ba5f | 2405 | break; |
dudmuck | 18:9530d682fd9a | 2406 | } // ...switch (pcbuf[idx]) |
dudmuck | 19:be8a8b0e7320 | 2407 | printf("%" PRIu32 "bps fdev:%" PRIu32 "hz ", fsk.get_bitrate(), fsk.get_tx_fdev_hz()); |
dudmuck | 19:be8a8b0e7320 | 2408 | printf("rxbw:%" PRIu32 "Hz ", fsk.get_rx_bw_hz(REG_FSK_RXBW)); |
dudmuck | 20:b11592c9ba5f | 2409 | printf("afcbw:%" PRIu32 "Hz preambleLen:%" PRIu16 "\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW), radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 20:b11592c9ba5f | 2410 | |
dudmuck | 20:b11592c9ba5f | 2411 | /* time between preamble occurring and syncAddress occuring |
dudmuck | 20:b11592c9ba5f | 2412 | * = bitrate in microseconds * 8 * (preamble bytes + sync bytes) |
dudmuck | 20:b11592c9ba5f | 2413 | */ |
dudmuck | 20:b11592c9ba5f | 2414 | preamble_to_sync_us = (1.0 / fsk.get_bitrate())*1e6 * 8 * (radio.read_u16(REG_FSK_PREAMBLEMSB)+1 + fsk.RegSyncConfig.bits.SyncSize+2); |
dudmuck | 20:b11592c9ba5f | 2415 | //printf("bitrate:%d, %f\r\n", fsk.get_bitrate(), 1.0 / fsk.get_bitrate()*1e6); |
dudmuck | 20:b11592c9ba5f | 2416 | printf("preamble_to_sync_us:%d\r\n", preamble_to_sync_us); |
dudmuck | 18:9530d682fd9a | 2417 | } |
dudmuck | 18:9530d682fd9a | 2418 | } |
dudmuck | 18:9530d682fd9a | 2419 | |
dudmuck | 20:b11592c9ba5f | 2420 | void cmd_restart_rx(uint8_t idx) |
dudmuck | 20:b11592c9ba5f | 2421 | { |
dudmuck | 20:b11592c9ba5f | 2422 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 20:b11592c9ba5f | 2423 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 20:b11592c9ba5f | 2424 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 20:b11592c9ba5f | 2425 | rx_start_timer.reset(); |
dudmuck | 20:b11592c9ba5f | 2426 | secs_rx_start = time(NULL); |
dudmuck | 20:b11592c9ba5f | 2427 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 0; |
dudmuck | 20:b11592c9ba5f | 2428 | printf("RestartRxWithoutPllLock\r\n"); |
dudmuck | 20:b11592c9ba5f | 2429 | } |
dudmuck | 20:b11592c9ba5f | 2430 | |
dudmuck | 18:9530d682fd9a | 2431 | void cmd_toggle_modem(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2432 | { |
dudmuck | 18:9530d682fd9a | 2433 | ook_test_en = false; |
dudmuck | 18:9530d682fd9a | 2434 | poll_irq_en = false; |
dudmuck | 18:9530d682fd9a | 2435 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2436 | fsk.enable(false); |
dudmuck | 18:9530d682fd9a | 2437 | else |
dudmuck | 18:9530d682fd9a | 2438 | lora.enable(); |
dudmuck | 18:9530d682fd9a | 2439 | |
dudmuck | 18:9530d682fd9a | 2440 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 18:9530d682fd9a | 2441 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2442 | printf("LoRa\r\n"); |
dudmuck | 18:9530d682fd9a | 2443 | else |
dudmuck | 18:9530d682fd9a | 2444 | printf("FSK\r\n"); |
dudmuck | 18:9530d682fd9a | 2445 | } |
dudmuck | 18:9530d682fd9a | 2446 | |
dudmuck | 18:9530d682fd9a | 2447 | void cmd_empty_fifo(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2448 | { |
dudmuck | 18:9530d682fd9a | 2449 | RegIrqFlags2_t RegIrqFlags2; |
dudmuck | 18:9530d682fd9a | 2450 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 2451 | while (!RegIrqFlags2.bits.FifoEmpty) { |
dudmuck | 18:9530d682fd9a | 2452 | if (pc.readable()) |
dudmuck | 18:9530d682fd9a | 2453 | break; |
dudmuck | 18:9530d682fd9a | 2454 | printf("%02x\r\n", radio.read_reg(REG_FIFO)); |
dudmuck | 18:9530d682fd9a | 2455 | RegIrqFlags2.octet = radio.read_reg(REG_FSK_IRQFLAGS2); |
dudmuck | 18:9530d682fd9a | 2456 | } |
dudmuck | 18:9530d682fd9a | 2457 | } |
dudmuck | 18:9530d682fd9a | 2458 | |
dudmuck | 18:9530d682fd9a | 2459 | void cmd_print_status(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2460 | { |
dudmuck | 18:9530d682fd9a | 2461 | if (radio.type == SX1276) { |
dudmuck | 18:9530d682fd9a | 2462 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 18:9530d682fd9a | 2463 | printf("\r\nSX1276 "); |
dudmuck | 18:9530d682fd9a | 2464 | #else |
dudmuck | 18:9530d682fd9a | 2465 | if (shield_type == SHIELD_TYPE_LAS) |
dudmuck | 18:9530d682fd9a | 2466 | printf("\r\nSX1276LAS "); |
dudmuck | 18:9530d682fd9a | 2467 | if (shield_type == SHIELD_TYPE_MAS) |
dudmuck | 18:9530d682fd9a | 2468 | printf("\r\nSX1276MAS "); |
dudmuck | 18:9530d682fd9a | 2469 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 18:9530d682fd9a | 2470 | } else if (radio.type == SX1272) |
dudmuck | 18:9530d682fd9a | 2471 | printf("\r\nSX1272 "); |
dudmuck | 18:9530d682fd9a | 2472 | |
dudmuck | 18:9530d682fd9a | 2473 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 18:9530d682fd9a | 2474 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2475 | lora_print_status(); |
dudmuck | 18:9530d682fd9a | 2476 | else |
dudmuck | 18:9530d682fd9a | 2477 | fsk_print_status(); |
dudmuck | 18:9530d682fd9a | 2478 | common_print_status(); |
dudmuck | 18:9530d682fd9a | 2479 | } |
dudmuck | 18:9530d682fd9a | 2480 | |
dudmuck | 18:9530d682fd9a | 2481 | void cmd_hop_period(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2482 | { |
dudmuck | 18:9530d682fd9a | 2483 | int i; |
dudmuck | 18:9530d682fd9a | 2484 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2485 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2486 | lora.RegHopPeriod = i; |
dudmuck | 18:9530d682fd9a | 2487 | radio.write_reg(REG_LR_HOPPERIOD, lora.RegHopPeriod); |
dudmuck | 18:9530d682fd9a | 2488 | if (radio.RegDioMapping1.bits.Dio1Mapping != 1) { |
dudmuck | 18:9530d682fd9a | 2489 | radio.RegDioMapping1.bits.Dio1Mapping = 1; |
dudmuck | 18:9530d682fd9a | 2490 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 2491 | } |
dudmuck | 18:9530d682fd9a | 2492 | } |
dudmuck | 18:9530d682fd9a | 2493 | lora.RegHopPeriod = radio.read_reg(REG_LR_HOPPERIOD); |
dudmuck | 18:9530d682fd9a | 2494 | printf("HopPeriod:0x%02x\r\n", lora.RegHopPeriod); |
dudmuck | 18:9530d682fd9a | 2495 | } |
dudmuck | 18:9530d682fd9a | 2496 | |
dudmuck | 18:9530d682fd9a | 2497 | void cmd_lora_ppg(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2498 | { |
dudmuck | 18:9530d682fd9a | 2499 | int i; |
dudmuck | 18:9530d682fd9a | 2500 | if (pcbuf[idx] != 0) { |
dudmuck | 18:9530d682fd9a | 2501 | sscanf(pcbuf+idx, "%x", &i); |
dudmuck | 18:9530d682fd9a | 2502 | radio.write_reg(REG_LR_SYNC_BYTE, i); |
dudmuck | 18:9530d682fd9a | 2503 | } |
dudmuck | 18:9530d682fd9a | 2504 | printf("lora sync:0x%02x\r\n", radio.read_reg(REG_LR_SYNC_BYTE)); |
dudmuck | 18:9530d682fd9a | 2505 | } |
dudmuck | 18:9530d682fd9a | 2506 | |
dudmuck | 18:9530d682fd9a | 2507 | void cmd_rssi_offset(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2508 | { |
dudmuck | 18:9530d682fd9a | 2509 | int i; |
dudmuck | 18:9530d682fd9a | 2510 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2511 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2512 | fsk.RegRssiConfig.bits.RssiOffset = i; |
dudmuck | 18:9530d682fd9a | 2513 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 18:9530d682fd9a | 2514 | } |
dudmuck | 18:9530d682fd9a | 2515 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 2516 | printf("RssiOffset:%d\r\n", fsk.RegRssiConfig.bits.RssiOffset); |
dudmuck | 18:9530d682fd9a | 2517 | } |
dudmuck | 18:9530d682fd9a | 2518 | |
dudmuck | 18:9530d682fd9a | 2519 | void cmd_rssi_smoothing(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2520 | { |
dudmuck | 18:9530d682fd9a | 2521 | int i; |
dudmuck | 18:9530d682fd9a | 2522 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2523 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 2524 | fsk.RegRssiConfig.bits.RssiSmoothing = i; |
dudmuck | 18:9530d682fd9a | 2525 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 18:9530d682fd9a | 2526 | } |
dudmuck | 18:9530d682fd9a | 2527 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 2528 | printf("RssiSmoothing:%d\r\n", fsk.RegRssiConfig.bits.RssiSmoothing); |
dudmuck | 18:9530d682fd9a | 2529 | } |
dudmuck | 18:9530d682fd9a | 2530 | |
dudmuck | 18:9530d682fd9a | 2531 | void cmd_rssi_threshold(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2532 | { |
dudmuck | 19:be8a8b0e7320 | 2533 | if ((pcbuf[idx] >= '0' && pcbuf[idx] <= '9') || pcbuf[idx] == '-') { |
dudmuck | 18:9530d682fd9a | 2534 | float dbm; |
dudmuck | 18:9530d682fd9a | 2535 | sscanf(pcbuf+idx, "%f", &dbm); |
dudmuck | 18:9530d682fd9a | 2536 | dbm *= (float)2.0; |
dudmuck | 18:9530d682fd9a | 2537 | fsk.RegRssiThresh = (int)fabs(dbm); |
dudmuck | 18:9530d682fd9a | 2538 | radio.write_reg(REG_FSK_RSSITHRESH, fsk.RegRssiThresh); |
dudmuck | 18:9530d682fd9a | 2539 | } |
dudmuck | 18:9530d682fd9a | 2540 | fsk.RegRssiThresh = radio.read_reg(REG_FSK_RSSITHRESH); |
dudmuck | 18:9530d682fd9a | 2541 | printf("rssiThreshold:-%.1f\r\n", fsk.RegRssiThresh / 2.0); |
dudmuck | 18:9530d682fd9a | 2542 | } |
dudmuck | 18:9530d682fd9a | 2543 | |
dudmuck | 18:9530d682fd9a | 2544 | void cmd_rx_trigger(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2545 | { |
dudmuck | 18:9530d682fd9a | 2546 | printf("RxTrigger:"); |
dudmuck | 18:9530d682fd9a | 2547 | switch (fsk.RegRxConfig.bits.RxTrigger) { |
dudmuck | 18:9530d682fd9a | 2548 | case 0: fsk.RegRxConfig.bits.RxTrigger = 1; |
dudmuck | 18:9530d682fd9a | 2549 | printf("rssi\r\n"); |
dudmuck | 18:9530d682fd9a | 2550 | break; |
dudmuck | 18:9530d682fd9a | 2551 | case 1: fsk.RegRxConfig.bits.RxTrigger = 6; |
dudmuck | 18:9530d682fd9a | 2552 | printf("preamble\r\n"); |
dudmuck | 18:9530d682fd9a | 2553 | break; |
dudmuck | 18:9530d682fd9a | 2554 | case 6: fsk.RegRxConfig.bits.RxTrigger = 7; |
dudmuck | 18:9530d682fd9a | 2555 | printf("both\r\n"); |
dudmuck | 18:9530d682fd9a | 2556 | break; |
dudmuck | 18:9530d682fd9a | 2557 | case 7: fsk.RegRxConfig.bits.RxTrigger = 0; |
dudmuck | 18:9530d682fd9a | 2558 | printf("none\r\n"); |
dudmuck | 18:9530d682fd9a | 2559 | break; |
dudmuck | 18:9530d682fd9a | 2560 | default: fsk.RegRxConfig.bits.RxTrigger = 0; |
dudmuck | 18:9530d682fd9a | 2561 | printf("none\r\n"); |
dudmuck | 18:9530d682fd9a | 2562 | break; |
dudmuck | 18:9530d682fd9a | 2563 | } |
dudmuck | 18:9530d682fd9a | 2564 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 2565 | } |
dudmuck | 18:9530d682fd9a | 2566 | |
dudmuck | 18:9530d682fd9a | 2567 | void cmd_cadper(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2568 | { |
dudmuck | 18:9530d682fd9a | 2569 | set_per_en(true); |
dudmuck | 18:9530d682fd9a | 2570 | |
dudmuck | 18:9530d682fd9a | 2571 | PacketNormalCnt = 0; |
dudmuck | 20:b11592c9ba5f | 2572 | PacketRxSequencePrev = 0; // transmitter side PacketTxCnt is 1 at first TX |
dudmuck | 18:9530d682fd9a | 2573 | PacketPerKoCnt = 0; |
dudmuck | 18:9530d682fd9a | 2574 | PacketPerOkCnt = 0; |
dudmuck | 18:9530d682fd9a | 2575 | |
dudmuck | 18:9530d682fd9a | 2576 | cadper_enable = true; |
dudmuck | 18:9530d682fd9a | 2577 | |
dudmuck | 18:9530d682fd9a | 2578 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2579 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2580 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2581 | |
dudmuck | 18:9530d682fd9a | 2582 | /* start first CAD */ |
dudmuck | 18:9530d682fd9a | 2583 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2584 | num_cads = 0; |
dudmuck | 18:9530d682fd9a | 2585 | } |
dudmuck | 18:9530d682fd9a | 2586 | |
dudmuck | 18:9530d682fd9a | 2587 | #if 0 |
dudmuck | 18:9530d682fd9a | 2588 | void cmd_cadrx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2589 | { |
dudmuck | 18:9530d682fd9a | 2590 | int n_tries = 1; |
dudmuck | 18:9530d682fd9a | 2591 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2592 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2593 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2594 | |
dudmuck | 18:9530d682fd9a | 2595 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2596 | sscanf(pcbuf+idx, "%d", &n_tries); |
dudmuck | 18:9530d682fd9a | 2597 | } |
dudmuck | 18:9530d682fd9a | 2598 | |
dudmuck | 18:9530d682fd9a | 2599 | while (n_tries > 0) { |
dudmuck | 18:9530d682fd9a | 2600 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2601 | |
dudmuck | 18:9530d682fd9a | 2602 | do { |
dudmuck | 18:9530d682fd9a | 2603 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2604 | } while (!lora.RegIrqFlags.bits.CadDetected && !lora.RegIrqFlags.bits.CadDone); |
dudmuck | 18:9530d682fd9a | 2605 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 2606 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 2607 | n_tries = 1; // end |
dudmuck | 18:9530d682fd9a | 2608 | printf("CadDetected "); |
dudmuck | 18:9530d682fd9a | 2609 | } |
dudmuck | 18:9530d682fd9a | 2610 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 2611 | printf("CadDone "); |
dudmuck | 18:9530d682fd9a | 2612 | } |
dudmuck | 18:9530d682fd9a | 2613 | |
dudmuck | 18:9530d682fd9a | 2614 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2615 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2616 | n_tries--; |
dudmuck | 18:9530d682fd9a | 2617 | } |
dudmuck | 18:9530d682fd9a | 2618 | } |
dudmuck | 18:9530d682fd9a | 2619 | #endif /* #if 0 */ |
dudmuck | 18:9530d682fd9a | 2620 | |
dudmuck | 18:9530d682fd9a | 2621 | void cmd_cad(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2622 | { |
dudmuck | 18:9530d682fd9a | 2623 | int n_tries = 1; |
dudmuck | 18:9530d682fd9a | 2624 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2625 | /* clear any stale flag */ |
dudmuck | 18:9530d682fd9a | 2626 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2627 | |
dudmuck | 18:9530d682fd9a | 2628 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2629 | sscanf(pcbuf+idx, "%d", &n_tries); |
dudmuck | 18:9530d682fd9a | 2630 | } |
dudmuck | 18:9530d682fd9a | 2631 | |
dudmuck | 18:9530d682fd9a | 2632 | while (n_tries > 0) { |
dudmuck | 18:9530d682fd9a | 2633 | radio.set_opmode(RF_OPMODE_CAD); |
dudmuck | 18:9530d682fd9a | 2634 | |
dudmuck | 18:9530d682fd9a | 2635 | do { |
dudmuck | 18:9530d682fd9a | 2636 | lora.RegIrqFlags.octet = radio.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 18:9530d682fd9a | 2637 | } while (!lora.RegIrqFlags.bits.CadDetected && !lora.RegIrqFlags.bits.CadDone); |
dudmuck | 18:9530d682fd9a | 2638 | if (lora.RegIrqFlags.bits.CadDetected) { |
dudmuck | 18:9530d682fd9a | 2639 | n_tries = 1; // end |
dudmuck | 18:9530d682fd9a | 2640 | printf("CadDetected "); |
dudmuck | 18:9530d682fd9a | 2641 | } |
dudmuck | 18:9530d682fd9a | 2642 | if (lora.RegIrqFlags.bits.CadDone) { |
dudmuck | 18:9530d682fd9a | 2643 | if (n_tries == 1) // print on last try |
dudmuck | 18:9530d682fd9a | 2644 | printf("CadDone "); |
dudmuck | 18:9530d682fd9a | 2645 | } |
dudmuck | 18:9530d682fd9a | 2646 | |
dudmuck | 18:9530d682fd9a | 2647 | radio.write_reg(REG_LR_IRQFLAGS, lora.RegIrqFlags.octet); |
dudmuck | 18:9530d682fd9a | 2648 | n_tries--; |
dudmuck | 18:9530d682fd9a | 2649 | } |
dudmuck | 18:9530d682fd9a | 2650 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 2651 | } |
dudmuck | 18:9530d682fd9a | 2652 | |
dudmuck | 18:9530d682fd9a | 2653 | void cmd_rx_timeout(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2654 | { |
dudmuck | 18:9530d682fd9a | 2655 | int symb_timeout; |
dudmuck | 18:9530d682fd9a | 2656 | uint16_t reg_u16 = radio.read_u16(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2657 | |
dudmuck | 18:9530d682fd9a | 2658 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 2659 | sscanf(pcbuf+idx, "%d", &symb_timeout); |
dudmuck | 18:9530d682fd9a | 2660 | reg_u16 &= 0xfc00; |
dudmuck | 18:9530d682fd9a | 2661 | reg_u16 |= symb_timeout; |
dudmuck | 18:9530d682fd9a | 2662 | } |
dudmuck | 18:9530d682fd9a | 2663 | reg_u16 = radio.read_u16(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 2664 | printf("SymbTimeout:%d\r\n", reg_u16 & 0x3ff); |
dudmuck | 18:9530d682fd9a | 2665 | } |
dudmuck | 18:9530d682fd9a | 2666 | |
dudmuck | 18:9530d682fd9a | 2667 | void cmd_rx_single(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2668 | { |
dudmuck | 18:9530d682fd9a | 2669 | lora.start_rx(RF_OPMODE_RECEIVER_SINGLE); |
dudmuck | 18:9530d682fd9a | 2670 | } |
dudmuck | 18:9530d682fd9a | 2671 | |
dudmuck | 21:b84a77dfb43c | 2672 | void preamble_without_sync() |
dudmuck | 21:b84a77dfb43c | 2673 | { |
dudmuck | 21:b84a77dfb43c | 2674 | printf("preamble_without_sync Afc:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); |
dudmuck | 21:b84a77dfb43c | 2675 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 21:b84a77dfb43c | 2676 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2677 | } |
dudmuck | 21:b84a77dfb43c | 2678 | |
dudmuck | 21:b84a77dfb43c | 2679 | Timeout pd_timeout; |
dudmuck | 21:b84a77dfb43c | 2680 | Timeout sync_timeout; |
dudmuck | 21:b84a77dfb43c | 2681 | void preamble_detect_isr() |
dudmuck | 21:b84a77dfb43c | 2682 | { |
dudmuck | 21:b84a77dfb43c | 2683 | // only used between frames, on background noise |
dudmuck | 21:b84a77dfb43c | 2684 | pd_timeout.attach_us(&preamble_without_sync, 1500); // 122us per byte |
dudmuck | 21:b84a77dfb43c | 2685 | } |
dudmuck | 21:b84a77dfb43c | 2686 | |
dudmuck | 21:b84a77dfb43c | 2687 | void prrx_end() |
dudmuck | 21:b84a77dfb43c | 2688 | { |
dudmuck | 21:b84a77dfb43c | 2689 | uint8_t n, i; |
dudmuck | 21:b84a77dfb43c | 2690 | |
dudmuck | 21:b84a77dfb43c | 2691 | for (n = 0; n < n_rx_pkts; n++) { |
dudmuck | 21:b84a77dfb43c | 2692 | printf("%d) %d: ", n, rx_pkts[n][0]); |
dudmuck | 21:b84a77dfb43c | 2693 | for (i = 0; i < rx_pkts[n][0]; i++) { |
dudmuck | 21:b84a77dfb43c | 2694 | if (i < RX_PKT_SIZE_LIMIT) |
dudmuck | 21:b84a77dfb43c | 2695 | printf("%02x ", rx_pkts[n][i+1]); |
dudmuck | 21:b84a77dfb43c | 2696 | } |
dudmuck | 21:b84a77dfb43c | 2697 | printf("\r\n"); |
dudmuck | 21:b84a77dfb43c | 2698 | } |
dudmuck | 21:b84a77dfb43c | 2699 | |
dudmuck | 21:b84a77dfb43c | 2700 | n_rx_pkts = 0; // done with rx packets, clear for next time |
dudmuck | 21:b84a77dfb43c | 2701 | |
dudmuck | 21:b84a77dfb43c | 2702 | /* end of this reception, prepare for next super-packet */ |
dudmuck | 21:b84a77dfb43c | 2703 | fsk.RegRxConfig.bits.AgcAutoOn = 1; |
dudmuck | 21:b84a77dfb43c | 2704 | fsk.RegRxConfig.bits.AfcAutoOn = 1; |
dudmuck | 21:b84a77dfb43c | 2705 | fsk.RegRxConfig.bits.RxTrigger = 6; // preamble |
dudmuck | 21:b84a77dfb43c | 2706 | fsk.RegAfcFei.bits.AfcAutoClearOn = 1; |
dudmuck | 21:b84a77dfb43c | 2707 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 21:b84a77dfb43c | 2708 | |
dudmuck | 21:b84a77dfb43c | 2709 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 21:b84a77dfb43c | 2710 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2711 | |
dudmuck | 21:b84a77dfb43c | 2712 | dio4int.rise(&preamble_detect_isr); // detect preamble without sync on background noise |
dudmuck | 21:b84a77dfb43c | 2713 | dio4int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2714 | |
dudmuck | 21:b84a77dfb43c | 2715 | dio0int.disable_irq(); // disable packet end detection |
dudmuck | 21:b84a77dfb43c | 2716 | } |
dudmuck | 21:b84a77dfb43c | 2717 | |
dudmuck | 21:b84a77dfb43c | 2718 | volatile bool length_byte; |
dudmuck | 21:b84a77dfb43c | 2719 | void syncadrs_dio2_isr(void); |
dudmuck | 21:b84a77dfb43c | 2720 | |
dudmuck | 21:b84a77dfb43c | 2721 | void payloadReady_isr() |
dudmuck | 21:b84a77dfb43c | 2722 | { |
dudmuck | 21:b84a77dfb43c | 2723 | uint8_t i; |
dudmuck | 21:b84a77dfb43c | 2724 | |
dudmuck | 21:b84a77dfb43c | 2725 | dio0int.disable_irq(); // disable ourselves, enabled at syncadrs detection |
dudmuck | 21:b84a77dfb43c | 2726 | dio1int.disable_irq(); // disable prrx_fifoLevel_isr() while handling end-of-packet |
dudmuck | 21:b84a77dfb43c | 2727 | |
dudmuck | 21:b84a77dfb43c | 2728 | if (!rx_payloadReady_int_en) { |
dudmuck | 21:b84a77dfb43c | 2729 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2730 | dio2int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2731 | dio4int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2732 | printf("payloadReady_isr() not enabled\r\n"); |
dudmuck | 21:b84a77dfb43c | 2733 | return; |
dudmuck | 21:b84a77dfb43c | 2734 | } |
dudmuck | 21:b84a77dfb43c | 2735 | |
dudmuck | 21:b84a77dfb43c | 2736 | if (radio.RegOpMode.bits.Mode != RF_OPMODE_RECEIVER && radio.RegOpMode.bits.Mode != RF_OPMODE_SYNTHESIZER_RX) { |
dudmuck | 21:b84a77dfb43c | 2737 | rx_payloadReady_int_en = false; |
dudmuck | 21:b84a77dfb43c | 2738 | printf("payloadReady_isr() not-rx\r\n"); |
dudmuck | 21:b84a77dfb43c | 2739 | return; |
dudmuck | 21:b84a77dfb43c | 2740 | } |
dudmuck | 21:b84a77dfb43c | 2741 | |
dudmuck | 21:b84a77dfb43c | 2742 | //Simultaneously write AgcAutoOn = 0, AgcAutoOn = 0, RXTrigger = Rssi, LnaGain value = read above (i.e. AGC is fixed from reception of first packet) |
dudmuck | 21:b84a77dfb43c | 2743 | if (fsk.RegRxConfig.bits.AgcAutoOn) { |
dudmuck | 21:b84a77dfb43c | 2744 | fsk.RegRxConfig.bits.AgcAutoOn = 0; |
dudmuck | 21:b84a77dfb43c | 2745 | fsk.RegRxConfig.bits.AfcAutoOn = 0; |
dudmuck | 21:b84a77dfb43c | 2746 | fsk.RegRxConfig.bits.RxTrigger = 1; // rssi |
dudmuck | 21:b84a77dfb43c | 2747 | fsk.RegAfcFei.bits.AfcAutoClearOn = 0; |
dudmuck | 21:b84a77dfb43c | 2748 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 21:b84a77dfb43c | 2749 | } |
dudmuck | 21:b84a77dfb43c | 2750 | |
dudmuck | 21:b84a77dfb43c | 2751 | fsk.RegRxConfig.bits.RestartRxWithoutPllLock = 1; |
dudmuck | 21:b84a77dfb43c | 2752 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 21:b84a77dfb43c | 2753 | |
dudmuck | 21:b84a77dfb43c | 2754 | radio.m_cs = 0; |
dudmuck | 21:b84a77dfb43c | 2755 | radio.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 21:b84a77dfb43c | 2756 | |
dudmuck | 21:b84a77dfb43c | 2757 | if (length_byte) { |
dudmuck | 21:b84a77dfb43c | 2758 | /* none of the packet has been retrieved */ |
dudmuck | 21:b84a77dfb43c | 2759 | rx_pkts[n_rx_pkts][0] = radio.m_spi.write(0); // read length byte |
dudmuck | 21:b84a77dfb43c | 2760 | for (i = 0; i < rx_pkts[n_rx_pkts][0]; i++) { |
dudmuck | 21:b84a77dfb43c | 2761 | uint8_t o, idx = i + 1; |
dudmuck | 21:b84a77dfb43c | 2762 | o = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2763 | if (idx < RX_PKT_SIZE_LIMIT) |
dudmuck | 21:b84a77dfb43c | 2764 | rx_pkts[n_rx_pkts][idx] = o; |
dudmuck | 21:b84a77dfb43c | 2765 | else { |
dudmuck | 21:b84a77dfb43c | 2766 | printf("L-prrx-overflow %u %u %u\r\n", n_rx_pkts, idx, rx_pkts[n_rx_pkts][0]); |
dudmuck | 21:b84a77dfb43c | 2767 | break; |
dudmuck | 21:b84a77dfb43c | 2768 | } |
dudmuck | 21:b84a77dfb43c | 2769 | } |
dudmuck | 21:b84a77dfb43c | 2770 | } else { |
dudmuck | 21:b84a77dfb43c | 2771 | /* last packet bytes havent been retrieved? */ |
dudmuck | 21:b84a77dfb43c | 2772 | while (rx_payload_idx < rx_pkts[n_rx_pkts][0]) { |
dudmuck | 21:b84a77dfb43c | 2773 | if (rx_payload_idx < RX_PKT_SIZE_LIMIT) |
dudmuck | 21:b84a77dfb43c | 2774 | rx_pkts[n_rx_pkts][++rx_payload_idx] = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2775 | else { |
dudmuck | 21:b84a77dfb43c | 2776 | printf("R-prrx-overflow %u %u %u\r\n", n_rx_pkts, rx_payload_idx, rx_pkts[n_rx_pkts][0]); |
dudmuck | 21:b84a77dfb43c | 2777 | break; |
dudmuck | 21:b84a77dfb43c | 2778 | } |
dudmuck | 21:b84a77dfb43c | 2779 | } |
dudmuck | 21:b84a77dfb43c | 2780 | } |
dudmuck | 21:b84a77dfb43c | 2781 | radio.m_cs = 1; |
dudmuck | 21:b84a77dfb43c | 2782 | |
dudmuck | 21:b84a77dfb43c | 2783 | if (++n_rx_pkts >= N_RX_PKTS) { |
dudmuck | 21:b84a77dfb43c | 2784 | /* overflow, stop */ |
dudmuck | 21:b84a77dfb43c | 2785 | prrx_end(); |
dudmuck | 21:b84a77dfb43c | 2786 | rx_payloadReady_int_en = false; |
dudmuck | 21:b84a77dfb43c | 2787 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2788 | dio2int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2789 | dio4int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2790 | printf("n_rx_pkts overflow\r\n"); |
dudmuck | 21:b84a77dfb43c | 2791 | return; |
dudmuck | 21:b84a77dfb43c | 2792 | } |
dudmuck | 21:b84a77dfb43c | 2793 | |
dudmuck | 21:b84a77dfb43c | 2794 | // timeout occurs if next syncadrs doesnt come |
dudmuck | 21:b84a77dfb43c | 2795 | sync_timeout.attach_us(&prrx_end, 2000); // 122us per byte |
dudmuck | 21:b84a77dfb43c | 2796 | |
dudmuck | 21:b84a77dfb43c | 2797 | dio2int.rise(&syncadrs_dio2_isr); // timeout for detecting last packet |
dudmuck | 21:b84a77dfb43c | 2798 | dio2int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2799 | } |
dudmuck | 21:b84a77dfb43c | 2800 | |
dudmuck | 21:b84a77dfb43c | 2801 | void prrx_fifoLevel_isr() |
dudmuck | 21:b84a77dfb43c | 2802 | { |
dudmuck | 21:b84a77dfb43c | 2803 | bool fail = false; |
dudmuck | 21:b84a77dfb43c | 2804 | |
dudmuck | 21:b84a77dfb43c | 2805 | if (dio0int.read()) { |
dudmuck | 21:b84a77dfb43c | 2806 | printf("fifolevel_isr: dio0 set\r\n"); |
dudmuck | 21:b84a77dfb43c | 2807 | return; |
dudmuck | 21:b84a77dfb43c | 2808 | } |
dudmuck | 21:b84a77dfb43c | 2809 | |
dudmuck | 21:b84a77dfb43c | 2810 | radio.m_cs = 0; |
dudmuck | 21:b84a77dfb43c | 2811 | radio.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 21:b84a77dfb43c | 2812 | |
dudmuck | 21:b84a77dfb43c | 2813 | while (!dio3) { // while fifo has something |
dudmuck | 21:b84a77dfb43c | 2814 | if (length_byte) { |
dudmuck | 21:b84a77dfb43c | 2815 | rx_pkts[n_rx_pkts][0] = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2816 | length_byte = false; |
dudmuck | 21:b84a77dfb43c | 2817 | rx_payload_idx = 0; |
dudmuck | 21:b84a77dfb43c | 2818 | } else { |
dudmuck | 21:b84a77dfb43c | 2819 | if (rx_payload_idx < RX_PKT_SIZE_LIMIT) |
dudmuck | 21:b84a77dfb43c | 2820 | rx_pkts[n_rx_pkts][++rx_payload_idx] = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2821 | else { |
dudmuck | 21:b84a77dfb43c | 2822 | printf("isr-prrx-overflow %u %u %u, dio3:%d\r\n", n_rx_pkts, rx_payload_idx, rx_pkts[n_rx_pkts][0], dio3.read()); |
dudmuck | 21:b84a77dfb43c | 2823 | fail = true; |
dudmuck | 21:b84a77dfb43c | 2824 | break; |
dudmuck | 21:b84a77dfb43c | 2825 | } |
dudmuck | 21:b84a77dfb43c | 2826 | } |
dudmuck | 21:b84a77dfb43c | 2827 | } |
dudmuck | 21:b84a77dfb43c | 2828 | radio.m_cs = 1; |
dudmuck | 21:b84a77dfb43c | 2829 | |
dudmuck | 21:b84a77dfb43c | 2830 | if (fail) |
dudmuck | 21:b84a77dfb43c | 2831 | fsk_print_IrqFlags2(); |
dudmuck | 21:b84a77dfb43c | 2832 | } |
dudmuck | 21:b84a77dfb43c | 2833 | |
dudmuck | 21:b84a77dfb43c | 2834 | void syncadrs_dio2_isr() |
dudmuck | 21:b84a77dfb43c | 2835 | { |
dudmuck | 21:b84a77dfb43c | 2836 | pc3 = !pc3; |
dudmuck | 21:b84a77dfb43c | 2837 | /* syncadrs match, disable end-timeout */ |
dudmuck | 21:b84a77dfb43c | 2838 | if (!dio3.read()) { |
dudmuck | 21:b84a77dfb43c | 2839 | printf("syncadrs: fifo not empty\r\n"); |
dudmuck | 21:b84a77dfb43c | 2840 | rx_payloadReady_int_en = false; |
dudmuck | 21:b84a77dfb43c | 2841 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2842 | dio0int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2843 | dio1int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2844 | dio2int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2845 | dio4int.disable_irq(); |
dudmuck | 21:b84a77dfb43c | 2846 | return; |
dudmuck | 21:b84a77dfb43c | 2847 | } |
dudmuck | 21:b84a77dfb43c | 2848 | |
dudmuck | 21:b84a77dfb43c | 2849 | sync_timeout.detach(); |
dudmuck | 21:b84a77dfb43c | 2850 | pd_timeout.detach(); |
dudmuck | 21:b84a77dfb43c | 2851 | dio4int.disable_irq(); // inhibit preamble_detect_isr() until end |
dudmuck | 21:b84a77dfb43c | 2852 | |
dudmuck | 21:b84a77dfb43c | 2853 | if (dio0int.read()) { |
dudmuck | 21:b84a77dfb43c | 2854 | printf("syncadrs_dio2_isr: dio0 set\r\n"); |
dudmuck | 21:b84a77dfb43c | 2855 | return; |
dudmuck | 21:b84a77dfb43c | 2856 | } |
dudmuck | 21:b84a77dfb43c | 2857 | if (dio1int.read()) { |
dudmuck | 21:b84a77dfb43c | 2858 | printf("syncadrs_dio2_isr: dio1 set\r\n"); |
dudmuck | 21:b84a77dfb43c | 2859 | return; |
dudmuck | 21:b84a77dfb43c | 2860 | } |
dudmuck | 21:b84a77dfb43c | 2861 | |
dudmuck | 21:b84a77dfb43c | 2862 | dio0int.rise(&payloadReady_isr); // end of packet detection |
dudmuck | 21:b84a77dfb43c | 2863 | dio0int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2864 | |
dudmuck | 21:b84a77dfb43c | 2865 | dio1int.rise(&prrx_fifoLevel_isr); // flow control during packet |
dudmuck | 21:b84a77dfb43c | 2866 | dio1int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2867 | |
dudmuck | 21:b84a77dfb43c | 2868 | length_byte = true; // first byte is length |
dudmuck | 21:b84a77dfb43c | 2869 | } |
dudmuck | 21:b84a77dfb43c | 2870 | |
dudmuck | 21:b84a77dfb43c | 2871 | void cmd_prrx(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2872 | { |
dudmuck | 21:b84a77dfb43c | 2873 | radio.m_spi.frequency(10000000); // max speed |
dudmuck | 21:b84a77dfb43c | 2874 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2875 | |
dudmuck | 21:b84a77dfb43c | 2876 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2877 | fsk.RegPktConfig1.bits.PacketFormatVariable = 1; // varible length format |
dudmuck | 21:b84a77dfb43c | 2878 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2879 | |
dudmuck | 21:b84a77dfb43c | 2880 | // DIO0 to payloadReady |
dudmuck | 21:b84a77dfb43c | 2881 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 2882 | radio.RegDioMapping1.bits.Dio0Mapping = 0; // PayloadReady |
dudmuck | 21:b84a77dfb43c | 2883 | radio.RegDioMapping1.bits.Dio1Mapping = 0; // FifoLevel |
dudmuck | 21:b84a77dfb43c | 2884 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to SyncAddress in RX |
dudmuck | 21:b84a77dfb43c | 2885 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 21:b84a77dfb43c | 2886 | |
dudmuck | 21:b84a77dfb43c | 2887 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 21:b84a77dfb43c | 2888 | radio.RegDioMapping2.bits.Dio4Mapping = 3; |
dudmuck | 21:b84a77dfb43c | 2889 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; // dio4 to preambleDetect in RX |
dudmuck | 21:b84a77dfb43c | 2890 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 21:b84a77dfb43c | 2891 | |
dudmuck | 21:b84a77dfb43c | 2892 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); // update shadow |
dudmuck | 21:b84a77dfb43c | 2893 | |
dudmuck | 21:b84a77dfb43c | 2894 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 21:b84a77dfb43c | 2895 | fsk.RegFifoThreshold.bits.FifoThreshold = 6; // fifoLevel_isr threshold |
dudmuck | 21:b84a77dfb43c | 2896 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 21:b84a77dfb43c | 2897 | |
dudmuck | 21:b84a77dfb43c | 2898 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 21:b84a77dfb43c | 2899 | n_rx_pkts = 0; |
dudmuck | 21:b84a77dfb43c | 2900 | |
dudmuck | 21:b84a77dfb43c | 2901 | rx_payloadReady_int_en = true; |
dudmuck | 21:b84a77dfb43c | 2902 | |
dudmuck | 21:b84a77dfb43c | 2903 | dio2int.rise(&syncadrs_dio2_isr); // timeout for detecting last packet |
dudmuck | 21:b84a77dfb43c | 2904 | dio2int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2905 | |
dudmuck | 21:b84a77dfb43c | 2906 | dio4int.rise(&preamble_detect_isr); // detect preamble without sync on background noise |
dudmuck | 21:b84a77dfb43c | 2907 | dio4int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2908 | } |
dudmuck | 21:b84a77dfb43c | 2909 | |
dudmuck | 21:b84a77dfb43c | 2910 | void ulrx_fifoLevel_isr() |
dudmuck | 21:b84a77dfb43c | 2911 | { |
dudmuck | 21:b84a77dfb43c | 2912 | uint8_t o; |
dudmuck | 21:b84a77dfb43c | 2913 | |
dudmuck | 21:b84a77dfb43c | 2914 | radio.m_cs = 0; |
dudmuck | 21:b84a77dfb43c | 2915 | radio.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 21:b84a77dfb43c | 2916 | |
dudmuck | 21:b84a77dfb43c | 2917 | while (!dio3) { // while FifoEmpty is not asserted |
dudmuck | 21:b84a77dfb43c | 2918 | switch (ulrx_state) { |
dudmuck | 21:b84a77dfb43c | 2919 | case ULRX_STATE_NEED_LENGTH: |
dudmuck | 21:b84a77dfb43c | 2920 | rx_pkts[n_rx_pkts][0] = radio.m_spi.write(0); // read length byte |
dudmuck | 21:b84a77dfb43c | 2921 | ulrx_state = ULRX_STATE_PAYLOAD; |
dudmuck | 21:b84a77dfb43c | 2922 | rx_payload_idx = 0; |
dudmuck | 21:b84a77dfb43c | 2923 | break; |
dudmuck | 21:b84a77dfb43c | 2924 | case ULRX_STATE_PAYLOAD: |
dudmuck | 21:b84a77dfb43c | 2925 | o = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2926 | if (rx_payload_idx < rx_pkts[n_rx_pkts][0]) { |
dudmuck | 21:b84a77dfb43c | 2927 | if (rx_payload_idx < RX_PKT_SIZE_LIMIT) |
dudmuck | 21:b84a77dfb43c | 2928 | rx_pkts[n_rx_pkts][rx_payload_idx++] = o; |
dudmuck | 21:b84a77dfb43c | 2929 | } else { |
dudmuck | 21:b84a77dfb43c | 2930 | /* first byte after payload */ |
dudmuck | 21:b84a77dfb43c | 2931 | if (++n_rx_pkts >= N_RX_PKTS) { |
dudmuck | 21:b84a77dfb43c | 2932 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2933 | ulrx_state = ULRX_STATE_OFF; |
dudmuck | 21:b84a77dfb43c | 2934 | printf("n_rx_pkts overflow\r\n"); |
dudmuck | 21:b84a77dfb43c | 2935 | return; |
dudmuck | 21:b84a77dfb43c | 2936 | } |
dudmuck | 21:b84a77dfb43c | 2937 | ulrx_state = ULRX_STATE_SYNC1; |
dudmuck | 21:b84a77dfb43c | 2938 | } |
dudmuck | 21:b84a77dfb43c | 2939 | break; |
dudmuck | 21:b84a77dfb43c | 2940 | case ULRX_STATE_SYNC1: |
dudmuck | 21:b84a77dfb43c | 2941 | o = radio.m_spi.write(0); |
dudmuck | 21:b84a77dfb43c | 2942 | /* TODO */ |
dudmuck | 21:b84a77dfb43c | 2943 | break; |
dudmuck | 21:b84a77dfb43c | 2944 | } |
dudmuck | 21:b84a77dfb43c | 2945 | } // ..while fifo has something |
dudmuck | 21:b84a77dfb43c | 2946 | |
dudmuck | 21:b84a77dfb43c | 2947 | radio.m_cs = 1; |
dudmuck | 21:b84a77dfb43c | 2948 | } |
dudmuck | 21:b84a77dfb43c | 2949 | |
dudmuck | 21:b84a77dfb43c | 2950 | void cmd_ulrx(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 2951 | { |
dudmuck | 21:b84a77dfb43c | 2952 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 21:b84a77dfb43c | 2953 | |
dudmuck | 21:b84a77dfb43c | 2954 | //unlimited packet length mode |
dudmuck | 21:b84a77dfb43c | 2955 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 2956 | fsk.RegPktConfig1.bits.PacketFormatVariable = 0; // fixed length format |
dudmuck | 21:b84a77dfb43c | 2957 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 2958 | |
dudmuck | 21:b84a77dfb43c | 2959 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 21:b84a77dfb43c | 2960 | fsk.RegPktConfig2.bits.PayloadLength = 0; |
dudmuck | 21:b84a77dfb43c | 2961 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 21:b84a77dfb43c | 2962 | |
dudmuck | 21:b84a77dfb43c | 2963 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 2964 | radio.RegDioMapping1.bits.Dio3Mapping = 0; // FifoEmpty |
dudmuck | 21:b84a77dfb43c | 2965 | //DIO2 to FifoFull |
dudmuck | 21:b84a77dfb43c | 2966 | radio.RegDioMapping1.bits.Dio2Mapping = 0; // FIfoFull |
dudmuck | 21:b84a77dfb43c | 2967 | //DIO1 to FifoLevel |
dudmuck | 21:b84a77dfb43c | 2968 | radio.RegDioMapping1.bits.Dio1Mapping = 0; // FifoLevel |
dudmuck | 21:b84a77dfb43c | 2969 | //radio.RegDioMapping1.bits.Dio0Mapping = 0; // useful? |
dudmuck | 21:b84a77dfb43c | 2970 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 21:b84a77dfb43c | 2971 | //FifoThreshold to approx 1/5th full |
dudmuck | 21:b84a77dfb43c | 2972 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 21:b84a77dfb43c | 2973 | fsk.RegFifoThreshold.bits.FifoThreshold = 48; // 75% full |
dudmuck | 21:b84a77dfb43c | 2974 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 21:b84a77dfb43c | 2975 | |
dudmuck | 21:b84a77dfb43c | 2976 | ulrx_enable = true; |
dudmuck | 21:b84a77dfb43c | 2977 | ulrx_state = ULRX_STATE_NEED_LENGTH; |
dudmuck | 21:b84a77dfb43c | 2978 | dio1int.rise(&ulrx_fifoLevel_isr); |
dudmuck | 21:b84a77dfb43c | 2979 | dio1int.enable_irq(); |
dudmuck | 21:b84a77dfb43c | 2980 | n_rx_pkts = 0; |
dudmuck | 21:b84a77dfb43c | 2981 | radio.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 21:b84a77dfb43c | 2982 | } |
dudmuck | 21:b84a77dfb43c | 2983 | |
dudmuck | 18:9530d682fd9a | 2984 | void cmd_rx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 2985 | { |
dudmuck | 18:9530d682fd9a | 2986 | set_per_en(false); |
dudmuck | 18:9530d682fd9a | 2987 | |
dudmuck | 18:9530d682fd9a | 2988 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 2989 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 18:9530d682fd9a | 2990 | else { |
dudmuck | 20:b11592c9ba5f | 2991 | if (poll_irq_en) { |
dudmuck | 20:b11592c9ba5f | 2992 | fsk_RegIrqFlags2_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 2993 | fsk_RegIrqFlags1_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 2994 | } |
dudmuck | 20:b11592c9ba5f | 2995 | |
dudmuck | 20:b11592c9ba5f | 2996 | rx_start_timer.start(); |
dudmuck | 20:b11592c9ba5f | 2997 | secs_rx_start = time(NULL); |
dudmuck | 18:9530d682fd9a | 2998 | fsk.start_rx(); |
dudmuck | 18:9530d682fd9a | 2999 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to syncadrs |
dudmuck | 18:9530d682fd9a | 3000 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3001 | if (radio.HF) { |
dudmuck | 18:9530d682fd9a | 3002 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 3003 | fsk.RegRssiConfig.bits.RssiOffset = FSK_RSSI_OFFSET; |
dudmuck | 18:9530d682fd9a | 3004 | fsk.RegRssiConfig.bits.RssiSmoothing = FSK_RSSI_SMOOTHING; |
dudmuck | 18:9530d682fd9a | 3005 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 21:b84a77dfb43c | 3006 | } |
dudmuck | 21:b84a77dfb43c | 3007 | |
dudmuck | 21:b84a77dfb43c | 3008 | // sync shadow regsiters |
dudmuck | 21:b84a77dfb43c | 3009 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 3010 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 18:9530d682fd9a | 3011 | } |
dudmuck | 18:9530d682fd9a | 3012 | } |
dudmuck | 18:9530d682fd9a | 3013 | |
dudmuck | 18:9530d682fd9a | 3014 | void cmd_radio_reg_read(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3015 | { |
dudmuck | 18:9530d682fd9a | 3016 | int i; |
dudmuck | 18:9530d682fd9a | 3017 | sscanf(pcbuf+idx, "%x", &i); |
dudmuck | 18:9530d682fd9a | 3018 | printf("%02x: %02x\r\n", i, radio.read_reg(i)); |
dudmuck | 18:9530d682fd9a | 3019 | } |
dudmuck | 18:9530d682fd9a | 3020 | |
dudmuck | 18:9530d682fd9a | 3021 | void cmd_radio_reg_write(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3022 | { |
dudmuck | 18:9530d682fd9a | 3023 | int i, n; |
dudmuck | 18:9530d682fd9a | 3024 | sscanf(pcbuf+idx, "%x %x", &i, &n); |
dudmuck | 18:9530d682fd9a | 3025 | radio.write_reg(i, n); |
dudmuck | 18:9530d682fd9a | 3026 | printf("%02x: %02x\r\n", i, radio.read_reg(i)); |
dudmuck | 18:9530d682fd9a | 3027 | } |
dudmuck | 18:9530d682fd9a | 3028 | |
dudmuck | 18:9530d682fd9a | 3029 | void cmd_mod_shaping(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3030 | { |
dudmuck | 18:9530d682fd9a | 3031 | uint8_t s = fsk.get_modulation_shaping(); |
dudmuck | 18:9530d682fd9a | 3032 | |
dudmuck | 18:9530d682fd9a | 3033 | if (s == 3) |
dudmuck | 18:9530d682fd9a | 3034 | s = 0; |
dudmuck | 18:9530d682fd9a | 3035 | else |
dudmuck | 18:9530d682fd9a | 3036 | s++; |
dudmuck | 18:9530d682fd9a | 3037 | |
dudmuck | 18:9530d682fd9a | 3038 | fsk.set_modulation_shaping(s); |
dudmuck | 18:9530d682fd9a | 3039 | |
dudmuck | 18:9530d682fd9a | 3040 | if (radio.RegOpMode.bits.ModulationType == 0) { |
dudmuck | 18:9530d682fd9a | 3041 | printf("FSK "); |
dudmuck | 18:9530d682fd9a | 3042 | switch (s) { |
dudmuck | 18:9530d682fd9a | 3043 | case 0: printf("off"); break; |
dudmuck | 18:9530d682fd9a | 3044 | case 1: printf("BT1.0 "); break; |
dudmuck | 18:9530d682fd9a | 3045 | case 2: printf("BT0.5 "); break; |
dudmuck | 18:9530d682fd9a | 3046 | case 3: printf("BT0.3 "); break; |
dudmuck | 18:9530d682fd9a | 3047 | } |
dudmuck | 18:9530d682fd9a | 3048 | } else if (radio.RegOpMode.bits.ModulationType == 1) { |
dudmuck | 18:9530d682fd9a | 3049 | printf("OOK "); |
dudmuck | 18:9530d682fd9a | 3050 | switch (s) { |
dudmuck | 18:9530d682fd9a | 3051 | case 0: printf("off"); break; |
dudmuck | 18:9530d682fd9a | 3052 | case 1: printf("Fcutoff=bitrate"); break; |
dudmuck | 18:9530d682fd9a | 3053 | case 2: printf("Fcutoff=2*bitrate"); break; |
dudmuck | 18:9530d682fd9a | 3054 | case 3: printf("?"); break; |
dudmuck | 18:9530d682fd9a | 3055 | } |
dudmuck | 18:9530d682fd9a | 3056 | } |
dudmuck | 18:9530d682fd9a | 3057 | |
dudmuck | 18:9530d682fd9a | 3058 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3059 | } |
dudmuck | 18:9530d682fd9a | 3060 | |
dudmuck | 18:9530d682fd9a | 3061 | void cmd_MapPreambleDetect(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3062 | { |
dudmuck | 18:9530d682fd9a | 3063 | radio.RegDioMapping2.bits.MapPreambleDetect ^= 1; |
dudmuck | 18:9530d682fd9a | 3064 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 18:9530d682fd9a | 3065 | printf("MapPreambleDetect:"); |
dudmuck | 18:9530d682fd9a | 3066 | if (radio.RegDioMapping2.bits.MapPreambleDetect) |
dudmuck | 18:9530d682fd9a | 3067 | printf("preamble\r\n"); |
dudmuck | 18:9530d682fd9a | 3068 | else |
dudmuck | 18:9530d682fd9a | 3069 | printf("rssi\r\n"); |
dudmuck | 18:9530d682fd9a | 3070 | } |
dudmuck | 18:9530d682fd9a | 3071 | |
dudmuck | 18:9530d682fd9a | 3072 | void cmd_bgr(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3073 | { |
dudmuck | 18:9530d682fd9a | 3074 | RegPdsTrim1_t pds_trim; |
dudmuck | 18:9530d682fd9a | 3075 | uint8_t adr; |
dudmuck | 18:9530d682fd9a | 3076 | if (radio.type == SX1276) |
dudmuck | 18:9530d682fd9a | 3077 | adr = REG_PDSTRIM1_SX1276; |
dudmuck | 18:9530d682fd9a | 3078 | else |
dudmuck | 18:9530d682fd9a | 3079 | adr = REG_PDSTRIM1_SX1272; |
dudmuck | 18:9530d682fd9a | 3080 | |
dudmuck | 18:9530d682fd9a | 3081 | pds_trim.octet = radio.read_reg(adr); |
dudmuck | 18:9530d682fd9a | 3082 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3083 | int i; |
dudmuck | 18:9530d682fd9a | 3084 | sscanf(&pcbuf[idx], "%d", &i); |
dudmuck | 18:9530d682fd9a | 3085 | pds_trim.bits.prog_txdac = i; |
dudmuck | 18:9530d682fd9a | 3086 | } |
dudmuck | 18:9530d682fd9a | 3087 | radio.write_reg(adr, pds_trim.octet); |
dudmuck | 18:9530d682fd9a | 3088 | printf("prog_txdac:%.1fuA\r\n", 2.5 + (pds_trim.bits.prog_txdac * 0.625)); |
dudmuck | 18:9530d682fd9a | 3089 | /* increase OCP threshold to allow more power */ |
dudmuck | 18:9530d682fd9a | 3090 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 18:9530d682fd9a | 3091 | if (radio.RegOcp.bits.OcpTrim < 16) { |
dudmuck | 18:9530d682fd9a | 3092 | radio.RegOcp.bits.OcpTrim = 16; |
dudmuck | 18:9530d682fd9a | 3093 | radio.write_reg(REG_OCP, radio.RegOcp.octet); |
dudmuck | 18:9530d682fd9a | 3094 | } |
dudmuck | 18:9530d682fd9a | 3095 | } |
dudmuck | 18:9530d682fd9a | 3096 | |
dudmuck | 18:9530d682fd9a | 3097 | void cmd_ook(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3098 | { |
dudmuck | 18:9530d682fd9a | 3099 | fsk.set_bitrate(32768); |
dudmuck | 18:9530d682fd9a | 3100 | radio.write_u16(REG_FSK_PREAMBLEMSB, 0); // zero preamble length |
dudmuck | 18:9530d682fd9a | 3101 | radio.RegOpMode.bits.ModulationType = 1; // to ook mode |
dudmuck | 18:9530d682fd9a | 3102 | radio.write_reg(REG_OPMODE, radio.RegOpMode.octet); |
dudmuck | 18:9530d682fd9a | 3103 | fsk.RegSyncConfig.bits.SyncOn = 0; |
dudmuck | 18:9530d682fd9a | 3104 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 3105 | ook_test_en = true; |
dudmuck | 18:9530d682fd9a | 3106 | printf("OOK\r\n"); |
dudmuck | 18:9530d682fd9a | 3107 | } |
dudmuck | 18:9530d682fd9a | 3108 | |
dudmuck | 18:9530d682fd9a | 3109 | void cmd_ocp(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3110 | { |
dudmuck | 18:9530d682fd9a | 3111 | int i; |
dudmuck | 18:9530d682fd9a | 3112 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3113 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3114 | if (i < 130) |
dudmuck | 18:9530d682fd9a | 3115 | radio.RegOcp.bits.OcpTrim = (i - 45) / 5; |
dudmuck | 18:9530d682fd9a | 3116 | else |
dudmuck | 18:9530d682fd9a | 3117 | radio.RegOcp.bits.OcpTrim = (i + 30) / 10; |
dudmuck | 18:9530d682fd9a | 3118 | radio.write_reg(REG_OCP, radio.RegOcp.octet); |
dudmuck | 18:9530d682fd9a | 3119 | } |
dudmuck | 18:9530d682fd9a | 3120 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 18:9530d682fd9a | 3121 | if (radio.RegOcp.bits.OcpTrim < 16) |
dudmuck | 18:9530d682fd9a | 3122 | i = 45 + (5 * radio.RegOcp.bits.OcpTrim); |
dudmuck | 18:9530d682fd9a | 3123 | else if (radio.RegOcp.bits.OcpTrim < 28) |
dudmuck | 18:9530d682fd9a | 3124 | i = (10 * radio.RegOcp.bits.OcpTrim) - 30; |
dudmuck | 18:9530d682fd9a | 3125 | else |
dudmuck | 18:9530d682fd9a | 3126 | i = 240; |
dudmuck | 18:9530d682fd9a | 3127 | printf("Ocp: %dmA\r\n", i); |
dudmuck | 18:9530d682fd9a | 3128 | } |
dudmuck | 18:9530d682fd9a | 3129 | |
dudmuck | 18:9530d682fd9a | 3130 | void cmd_op(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3131 | { |
dudmuck | 18:9530d682fd9a | 3132 | int i, dbm; |
dudmuck | 18:9530d682fd9a | 3133 | RegPdsTrim1_t pds_trim; |
dudmuck | 18:9530d682fd9a | 3134 | uint8_t adr; |
dudmuck | 18:9530d682fd9a | 3135 | if (radio.type == SX1276) |
dudmuck | 18:9530d682fd9a | 3136 | adr = REG_PDSTRIM1_SX1276; |
dudmuck | 18:9530d682fd9a | 3137 | else |
dudmuck | 18:9530d682fd9a | 3138 | adr = REG_PDSTRIM1_SX1272; |
dudmuck | 18:9530d682fd9a | 3139 | |
dudmuck | 18:9530d682fd9a | 3140 | pds_trim.octet = radio.read_reg(adr); |
dudmuck | 18:9530d682fd9a | 3141 | |
dudmuck | 19:be8a8b0e7320 | 3142 | if (pcbuf[idx] >= '0' && (pcbuf[idx] <= '9' || pcbuf[idx] == '-')) { |
dudmuck | 18:9530d682fd9a | 3143 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3144 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 18:9530d682fd9a | 3145 | /* PABOOST used: +2dbm to +17, or +20 */ |
dudmuck | 18:9530d682fd9a | 3146 | if (i == 20) { |
dudmuck | 18:9530d682fd9a | 3147 | printf("+20dBm PADAC bias\r\n"); |
dudmuck | 18:9530d682fd9a | 3148 | i -= 3; |
dudmuck | 18:9530d682fd9a | 3149 | pds_trim.bits.prog_txdac = 7; |
dudmuck | 21:b84a77dfb43c | 3150 | radio.write_reg(adr, pds_trim.octet); |
dudmuck | 13:c73caaee93a5 | 3151 | } |
dudmuck | 18:9530d682fd9a | 3152 | if (i > 1) |
dudmuck | 18:9530d682fd9a | 3153 | radio.RegPaConfig.bits.OutputPower = i - 2; |
dudmuck | 18:9530d682fd9a | 3154 | } else { |
dudmuck | 18:9530d682fd9a | 3155 | /* RFO used: -1 to +14dbm */ |
dudmuck | 18:9530d682fd9a | 3156 | if (i < 15) |
dudmuck | 18:9530d682fd9a | 3157 | radio.RegPaConfig.bits.OutputPower = i + 1; |
dudmuck | 18:9530d682fd9a | 3158 | } |
dudmuck | 18:9530d682fd9a | 3159 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 18:9530d682fd9a | 3160 | } |
dudmuck | 18:9530d682fd9a | 3161 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 18:9530d682fd9a | 3162 | if (radio.RegPaConfig.bits.PaSelect) { |
dudmuck | 18:9530d682fd9a | 3163 | printf("PA_BOOST "); |
dudmuck | 18:9530d682fd9a | 3164 | dbm = radio.RegPaConfig.bits.OutputPower + pds_trim.bits.prog_txdac - 2; |
dudmuck | 18:9530d682fd9a | 3165 | } else { |
dudmuck | 18:9530d682fd9a | 3166 | printf("RFO "); |
dudmuck | 18:9530d682fd9a | 3167 | dbm = radio.RegPaConfig.bits.OutputPower - 1; |
dudmuck | 18:9530d682fd9a | 3168 | } |
dudmuck | 18:9530d682fd9a | 3169 | printf("OutputPower:%ddBm\r\n", dbm); |
dudmuck | 18:9530d682fd9a | 3170 | } |
dudmuck | 18:9530d682fd9a | 3171 | |
dudmuck | 18:9530d682fd9a | 3172 | |
dudmuck | 18:9530d682fd9a | 3173 | |
dudmuck | 18:9530d682fd9a | 3174 | void cmd_fsk_agcauto(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3175 | { |
dudmuck | 18:9530d682fd9a | 3176 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 18:9530d682fd9a | 3177 | fsk.RegRxConfig.bits.AgcAutoOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3178 | printf("AgcAuto:"); |
dudmuck | 18:9530d682fd9a | 3179 | if (fsk.RegRxConfig.bits.AgcAutoOn) |
dudmuck | 18:9530d682fd9a | 3180 | printf("On\r\n"); |
dudmuck | 18:9530d682fd9a | 3181 | else |
dudmuck | 18:9530d682fd9a | 3182 | printf("OFF\r\n"); |
dudmuck | 18:9530d682fd9a | 3183 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 3184 | } |
dudmuck | 18:9530d682fd9a | 3185 | |
dudmuck | 18:9530d682fd9a | 3186 | void cmd_fsk_afcauto(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3187 | { |
dudmuck | 18:9530d682fd9a | 3188 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 18:9530d682fd9a | 3189 | fsk.RegRxConfig.bits.AfcAutoOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3190 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 18:9530d682fd9a | 3191 | printf("AfcAuto:"); |
dudmuck | 18:9530d682fd9a | 3192 | if (fsk.RegRxConfig.bits.AfcAutoOn) |
dudmuck | 18:9530d682fd9a | 3193 | printf("On\r\n"); |
dudmuck | 18:9530d682fd9a | 3194 | else |
dudmuck | 18:9530d682fd9a | 3195 | printf("OFF\r\n"); |
dudmuck | 18:9530d682fd9a | 3196 | } |
dudmuck | 18:9530d682fd9a | 3197 | |
dudmuck | 21:b84a77dfb43c | 3198 | void cmd_crc32(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 3199 | { |
dudmuck | 21:b84a77dfb43c | 3200 | crc32_en ^= true; |
dudmuck | 21:b84a77dfb43c | 3201 | printf("crc32_en:%u\r\n", crc32_en); |
dudmuck | 21:b84a77dfb43c | 3202 | } |
dudmuck | 21:b84a77dfb43c | 3203 | |
dudmuck | 18:9530d682fd9a | 3204 | void cmd_crcOn(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3205 | { |
dudmuck | 18:9530d682fd9a | 3206 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 3207 | lora.setRxPayloadCrcOn(!lora.getRxPayloadCrcOn()); |
dudmuck | 18:9530d682fd9a | 3208 | lora_printRxPayloadCrcOn(); |
dudmuck | 18:9530d682fd9a | 3209 | } else { |
dudmuck | 18:9530d682fd9a | 3210 | printf("CrcOn:"); |
dudmuck | 18:9530d682fd9a | 3211 | fsk.RegPktConfig1.bits.CrcOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3212 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 18:9530d682fd9a | 3213 | if (fsk.RegPktConfig1.bits.CrcOn) |
dudmuck | 18:9530d682fd9a | 3214 | printf("On\r\n"); |
dudmuck | 18:9530d682fd9a | 3215 | else |
dudmuck | 18:9530d682fd9a | 3216 | printf("Off\r\n"); |
dudmuck | 18:9530d682fd9a | 3217 | if (fsk.RegPktConfig2.bits.DataModePacket && radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 18:9530d682fd9a | 3218 | fsk.config_dio0_for_pktmode_rx(); |
dudmuck | 18:9530d682fd9a | 3219 | } |
dudmuck | 18:9530d682fd9a | 3220 | } |
dudmuck | 18:9530d682fd9a | 3221 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3222 | } |
dudmuck | 18:9530d682fd9a | 3223 | |
dudmuck | 18:9530d682fd9a | 3224 | #ifdef LORA_TX_TEST |
dudmuck | 18:9530d682fd9a | 3225 | void cmd_lora_fixed_payload_symbol(uint8_t idx) // fixed payload, symbol test |
dudmuck | 18:9530d682fd9a | 3226 | { |
dudmuck | 18:9530d682fd9a | 3227 | int n, i; |
dudmuck | 18:9530d682fd9a | 3228 | |
dudmuck | 18:9530d682fd9a | 3229 | symbol_num = pcbuf[idx] - '0'; |
dudmuck | 18:9530d682fd9a | 3230 | sscanf(pcbuf+idx+2, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3231 | n = i >> 2; // num nibbles |
dudmuck | 18:9530d682fd9a | 3232 | printf("%d nibbles: ", n); |
dudmuck | 18:9530d682fd9a | 3233 | lora.RegPayloadLength = byte_pad_length; |
dudmuck | 18:9530d682fd9a | 3234 | while (n > 0) { |
dudmuck | 18:9530d682fd9a | 3235 | lora.RegPayloadLength++; |
dudmuck | 18:9530d682fd9a | 3236 | n -= 2; // one byte = two nibbles |
dudmuck | 18:9530d682fd9a | 3237 | } |
dudmuck | 18:9530d682fd9a | 3238 | printf("%d bytes\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3239 | symbol_sweep_nbits = i >> 2; |
dudmuck | 18:9530d682fd9a | 3240 | symbol_sweep_bit_counter = 0; |
dudmuck | 18:9530d682fd9a | 3241 | symbol_sweep_bit_counter_stop = 1 << symbol_sweep_nbits; // one bit per nibble used in symbol (2bits per byte) |
dudmuck | 18:9530d682fd9a | 3242 | printf("sweep symbol %d, length bytes:%d nbits:%d stop:0x%x\r\n", symbol_num, lora.RegPayloadLength, symbol_sweep_nbits, symbol_sweep_bit_counter_stop); |
dudmuck | 18:9530d682fd9a | 3243 | txticker_state = TXTICKER_STATE_SYMBOL_SWEEP; |
dudmuck | 18:9530d682fd9a | 3244 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3245 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3246 | } |
dudmuck | 18:9530d682fd9a | 3247 | |
dudmuck | 18:9530d682fd9a | 3248 | void cmd_fixed_payload_offset(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3249 | { |
dudmuck | 18:9530d682fd9a | 3250 | int i; |
dudmuck | 18:9530d682fd9a | 3251 | if (pcbuf[idx] >='0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3252 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3253 | byte_pad_length = i; |
dudmuck | 18:9530d682fd9a | 3254 | } |
dudmuck | 18:9530d682fd9a | 3255 | printf("byte_pad_length:%d\r\n", byte_pad_length); |
dudmuck | 18:9530d682fd9a | 3256 | } |
dudmuck | 18:9530d682fd9a | 3257 | |
dudmuck | 18:9530d682fd9a | 3258 | void cmd_lora_fixed_payload(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3259 | { |
dudmuck | 18:9530d682fd9a | 3260 | int n, a, i, d = 0; |
dudmuck | 18:9530d682fd9a | 3261 | for (i = idx; i < pcbuf_len; ) { |
dudmuck | 18:9530d682fd9a | 3262 | //printf("scan:\"%s\"\r\n", pcbuf+i); |
dudmuck | 18:9530d682fd9a | 3263 | sscanf(pcbuf+i, "%x", &n); |
dudmuck | 18:9530d682fd9a | 3264 | //printf("n:%x\r\n", n); |
dudmuck | 18:9530d682fd9a | 3265 | radio.tx_buf[d] = n; |
dudmuck | 18:9530d682fd9a | 3266 | printf("%02x ", n); |
dudmuck | 18:9530d682fd9a | 3267 | while (pcbuf[i] == ' ') |
dudmuck | 18:9530d682fd9a | 3268 | i++; |
dudmuck | 18:9530d682fd9a | 3269 | //printf("%d pcbuf[i]:%x\r\n", i, pcbuf[i]); |
dudmuck | 18:9530d682fd9a | 3270 | for (a = i; pcbuf[a] != ' '; a++) |
dudmuck | 18:9530d682fd9a | 3271 | if (a >= pcbuf_len) |
dudmuck | 18:9530d682fd9a | 3272 | break; |
dudmuck | 18:9530d682fd9a | 3273 | i = a; |
dudmuck | 18:9530d682fd9a | 3274 | while (pcbuf[i] == ' ') { |
dudmuck | 18:9530d682fd9a | 3275 | i++; |
dudmuck | 18:9530d682fd9a | 3276 | if (i >= pcbuf_len) |
dudmuck | 18:9530d682fd9a | 3277 | break; |
dudmuck | 18:9530d682fd9a | 3278 | } |
dudmuck | 18:9530d682fd9a | 3279 | d++; |
dudmuck | 18:9530d682fd9a | 3280 | } |
dudmuck | 18:9530d682fd9a | 3281 | lora.RegPayloadLength = d; |
dudmuck | 18:9530d682fd9a | 3282 | printf("\r\nlora.RegPayloadLength:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3283 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3284 | lora.start_tx(lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3285 | } |
dudmuck | 18:9530d682fd9a | 3286 | |
dudmuck | 18:9530d682fd9a | 3287 | void cmd_lora_toggle_crcOn(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3288 | { |
dudmuck | 18:9530d682fd9a | 3289 | /* test lora crc on/off */ |
dudmuck | 18:9530d682fd9a | 3290 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 3291 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3292 | txticker_state = TXTICKER_STATE_TOG_CRC_ON; |
dudmuck | 18:9530d682fd9a | 3293 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3294 | } |
dudmuck | 18:9530d682fd9a | 3295 | |
dudmuck | 18:9530d682fd9a | 3296 | void lora_cycle_payload_length(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3297 | { |
dudmuck | 18:9530d682fd9a | 3298 | int i; |
dudmuck | 18:9530d682fd9a | 3299 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3300 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3301 | payload_length_stop = i; |
dudmuck | 18:9530d682fd9a | 3302 | } |
dudmuck | 18:9530d682fd9a | 3303 | txticker_state = TXTICKER_STATE_CYCLE_PAYLOAD_LENGTH; |
dudmuck | 18:9530d682fd9a | 3304 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3305 | } |
dudmuck | 18:9530d682fd9a | 3306 | |
dudmuck | 18:9530d682fd9a | 3307 | void cmd_lora_data_ramp(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3308 | { |
dudmuck | 18:9530d682fd9a | 3309 | // lora payload data ramping |
dudmuck | 18:9530d682fd9a | 3310 | lora.RegPayloadLength = pcbuf[idx] - '0'; |
dudmuck | 18:9530d682fd9a | 3311 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3312 | txticker_state = TXTICKER_STATE_RAMP_PAYLOAD_DATA_START; |
dudmuck | 18:9530d682fd9a | 3313 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3314 | } |
dudmuck | 18:9530d682fd9a | 3315 | |
dudmuck | 18:9530d682fd9a | 3316 | void cmd_lora_sync_lo_nibble(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3317 | { |
dudmuck | 18:9530d682fd9a | 3318 | lora_sync_byte = 0x00; |
dudmuck | 18:9530d682fd9a | 3319 | on_txdone_state = ON_TXDONE_STATE_SYNC_LO_NIBBLE; |
dudmuck | 18:9530d682fd9a | 3320 | on_txdone_delay = 0.100; |
dudmuck | 18:9530d682fd9a | 3321 | txdone_timeout_cb(); |
dudmuck | 18:9530d682fd9a | 3322 | //sync_sweep_timeout.attach(&txdone_timeout_cb, sync_sweep_delay); |
dudmuck | 18:9530d682fd9a | 3323 | } |
dudmuck | 18:9530d682fd9a | 3324 | |
dudmuck | 18:9530d682fd9a | 3325 | void cmd_lora_toggle_header_mode(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3326 | { |
dudmuck | 18:9530d682fd9a | 3327 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 3328 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3329 | txticker_state = TXTICKER_STATE_TOG_HEADER_MODE; |
dudmuck | 18:9530d682fd9a | 3330 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3331 | } |
dudmuck | 18:9530d682fd9a | 3332 | |
dudmuck | 18:9530d682fd9a | 3333 | void cmd_lora_sync_sweep(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3334 | { |
dudmuck | 18:9530d682fd9a | 3335 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 3336 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3337 | txticker_sync_byte = 0x12; |
dudmuck | 18:9530d682fd9a | 3338 | if (pcbuf[idx] == '1') |
dudmuck | 18:9530d682fd9a | 3339 | txticker_state = TXTICKER_STATE_CYCLE_SYNC_1; |
dudmuck | 18:9530d682fd9a | 3340 | else if (pcbuf[idx] == '2') |
dudmuck | 18:9530d682fd9a | 3341 | txticker_state = TXTICKER_STATE_CYCLE_SYNC_2; |
dudmuck | 18:9530d682fd9a | 3342 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3343 | } |
dudmuck | 18:9530d682fd9a | 3344 | |
dudmuck | 18:9530d682fd9a | 3345 | void cmd_lora_all_payload_lengths(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3346 | { |
dudmuck | 18:9530d682fd9a | 3347 | on_txdone_repeat_cnt = 0; |
dudmuck | 18:9530d682fd9a | 3348 | on_txdone_state = ON_TXDONE_STATE_PAYLOAD_LENGTH; |
dudmuck | 18:9530d682fd9a | 3349 | on_txdone_delay = 0.200; |
dudmuck | 18:9530d682fd9a | 3350 | txdone_timeout_cb(); |
dudmuck | 18:9530d682fd9a | 3351 | lora.RegPayloadLength = 0; |
dudmuck | 18:9530d682fd9a | 3352 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3353 | } |
dudmuck | 18:9530d682fd9a | 3354 | |
dudmuck | 18:9530d682fd9a | 3355 | void cmd_lora_toggle_all_bits(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3356 | { |
dudmuck | 18:9530d682fd9a | 3357 | lora.RegPayloadLength = (pcbuf[idx] - '0') + byte_pad_length; |
dudmuck | 18:9530d682fd9a | 3358 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3359 | txticker_state = TXTICKER_STATE_TOGGLE_ALL_BITS_START; |
dudmuck | 18:9530d682fd9a | 3360 | printf("tab byte length:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3361 | |
dudmuck | 18:9530d682fd9a | 3362 | if (lora.RegPayloadLength > 0) |
dudmuck | 18:9530d682fd9a | 3363 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3364 | } |
dudmuck | 18:9530d682fd9a | 3365 | |
dudmuck | 18:9530d682fd9a | 3366 | void cmd_lora_cycle_codingrates(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3367 | { |
dudmuck | 18:9530d682fd9a | 3368 | lora.RegPayloadLength = 1; |
dudmuck | 18:9530d682fd9a | 3369 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3370 | txticker_state = TXTICKER_STATE_CYCLE_CODING_RATE; |
dudmuck | 18:9530d682fd9a | 3371 | tx_ticker.attach(&fp_cb, tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3372 | } |
dudmuck | 18:9530d682fd9a | 3373 | #endif /* LORA_TX_TEST */ |
dudmuck | 18:9530d682fd9a | 3374 | |
dudmuck | 18:9530d682fd9a | 3375 | void cmd_codingRate(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3376 | { |
dudmuck | 18:9530d682fd9a | 3377 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') |
dudmuck | 18:9530d682fd9a | 3378 | lora.setCodingRate(pcbuf[idx] - '0'); |
dudmuck | 18:9530d682fd9a | 3379 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 3380 | lora_printCodingRate(false); // false: transmitted |
dudmuck | 18:9530d682fd9a | 3381 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3382 | } |
dudmuck | 18:9530d682fd9a | 3383 | |
dudmuck | 18:9530d682fd9a | 3384 | void cmd_lora_header_mode(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3385 | { |
dudmuck | 18:9530d682fd9a | 3386 | lora.setHeaderMode(!lora.getHeaderMode()); |
dudmuck | 18:9530d682fd9a | 3387 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 3388 | lora_printHeaderMode(); |
dudmuck | 18:9530d682fd9a | 3389 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3390 | } |
dudmuck | 18:9530d682fd9a | 3391 | |
dudmuck | 18:9530d682fd9a | 3392 | void cmd_fsk_AfcAutoClearOn(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3393 | { |
dudmuck | 18:9530d682fd9a | 3394 | fsk.RegAfcFei.bits.AfcAutoClearOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3395 | printf("AfcAutoClearOn: "); |
dudmuck | 18:9530d682fd9a | 3396 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 18:9530d682fd9a | 3397 | if (fsk.RegAfcFei.bits.AfcAutoClearOn) |
dudmuck | 18:9530d682fd9a | 3398 | printf("ON\r\n"); |
dudmuck | 18:9530d682fd9a | 3399 | else |
dudmuck | 18:9530d682fd9a | 3400 | printf("off\r\n"); |
dudmuck | 18:9530d682fd9a | 3401 | } |
dudmuck | 18:9530d682fd9a | 3402 | |
dudmuck | 18:9530d682fd9a | 3403 | void cmd_fsk_AutoRestartRxMode(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3404 | { |
dudmuck | 18:9530d682fd9a | 3405 | fsk.RegSyncConfig.bits.AutoRestartRxMode++; |
dudmuck | 18:9530d682fd9a | 3406 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 3407 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 18:9530d682fd9a | 3408 | printf("AutoRestartRxMode:"); |
dudmuck | 18:9530d682fd9a | 3409 | switch (fsk.RegSyncConfig.bits.AutoRestartRxMode) { |
dudmuck | 18:9530d682fd9a | 3410 | case 0: printf("off "); break; |
dudmuck | 18:9530d682fd9a | 3411 | case 1: printf("no-pll-wait "); break; |
dudmuck | 18:9530d682fd9a | 3412 | case 2: printf("pll-wait "); break; |
dudmuck | 18:9530d682fd9a | 3413 | case 3: printf("3 "); break; |
dudmuck | 18:9530d682fd9a | 3414 | } |
dudmuck | 18:9530d682fd9a | 3415 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3416 | } |
dudmuck | 18:9530d682fd9a | 3417 | |
dudmuck | 18:9530d682fd9a | 3418 | void cmd_AfcClear(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3419 | { |
dudmuck | 18:9530d682fd9a | 3420 | printf("clear afc: "); |
dudmuck | 18:9530d682fd9a | 3421 | fsk.RegAfcFei.bits.AfcClear = 1; |
dudmuck | 18:9530d682fd9a | 3422 | radio.write_reg(REG_FSK_AFCFEI, fsk.RegAfcFei.octet); |
dudmuck | 18:9530d682fd9a | 3423 | fsk.RegAfcFei.bits.AfcClear = 0; |
dudmuck | 18:9530d682fd9a | 3424 | printf("%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_AFCMSB))); |
dudmuck | 18:9530d682fd9a | 3425 | } |
dudmuck | 18:9530d682fd9a | 3426 | |
dudmuck | 18:9530d682fd9a | 3427 | void cmd_fsk_bitrate(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3428 | { |
dudmuck | 18:9530d682fd9a | 3429 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3430 | float kbits; |
dudmuck | 18:9530d682fd9a | 3431 | sscanf(&pcbuf[idx], "%f", &kbits); |
dudmuck | 18:9530d682fd9a | 3432 | fsk.set_bitrate((int)(kbits*1000)); |
dudmuck | 18:9530d682fd9a | 3433 | } |
dudmuck | 18:9530d682fd9a | 3434 | printf("%fkbps\r\n", fsk.get_bitrate()/(float)1000.0); |
dudmuck | 18:9530d682fd9a | 3435 | } |
dudmuck | 18:9530d682fd9a | 3436 | |
dudmuck | 18:9530d682fd9a | 3437 | void cmd_bandwidth(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3438 | { |
dudmuck | 18:9530d682fd9a | 3439 | int i; |
dudmuck | 18:9530d682fd9a | 3440 | float f; |
dudmuck | 18:9530d682fd9a | 3441 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 3442 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3443 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 3444 | sscanf(&pcbuf[idx], "%d", &i); |
dudmuck | 18:9530d682fd9a | 3445 | lora.setBw_KHz(i); |
dudmuck | 18:9530d682fd9a | 3446 | } else |
dudmuck | 18:9530d682fd9a | 3447 | lora_printAllBw(); |
dudmuck | 18:9530d682fd9a | 3448 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 3449 | printf("current "); |
dudmuck | 18:9530d682fd9a | 3450 | lora_printBw(); |
dudmuck | 18:9530d682fd9a | 3451 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3452 | } else { // FSK: |
dudmuck | 18:9530d682fd9a | 3453 | if (pcbuf[idx] == 'a') { |
dudmuck | 18:9530d682fd9a | 3454 | idx++; |
dudmuck | 18:9530d682fd9a | 3455 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3456 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 3457 | sscanf(&pcbuf[idx], "%f", &f); |
dudmuck | 18:9530d682fd9a | 3458 | fsk.set_rx_dcc_bw_hz((int)(f*(float)1000.0), 1); |
dudmuck | 18:9530d682fd9a | 3459 | } |
dudmuck | 18:9530d682fd9a | 3460 | printf("afcbw:%.3fkHz\r\n", fsk.get_rx_bw_hz(REG_FSK_AFCBW)/1000.0); |
dudmuck | 18:9530d682fd9a | 3461 | } else { |
dudmuck | 18:9530d682fd9a | 3462 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3463 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 3464 | sscanf(&pcbuf[idx], "%f", &f); |
dudmuck | 18:9530d682fd9a | 3465 | fsk.set_rx_dcc_bw_hz((int)(f*(float)1000.0), 0); |
dudmuck | 18:9530d682fd9a | 3466 | } |
dudmuck | 18:9530d682fd9a | 3467 | printf("rxbw:%.3fkHz\r\n", fsk.get_rx_bw_hz(REG_FSK_RXBW)/1000.0); |
dudmuck | 18:9530d682fd9a | 3468 | } |
dudmuck | 18:9530d682fd9a | 3469 | } |
dudmuck | 18:9530d682fd9a | 3470 | } |
dudmuck | 18:9530d682fd9a | 3471 | |
dudmuck | 18:9530d682fd9a | 3472 | void cmd_lora_poll_validHeader(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3473 | { |
dudmuck | 18:9530d682fd9a | 3474 | lora.poll_vh ^= 1; |
dudmuck | 18:9530d682fd9a | 3475 | printf("poll_vh:%d\r\n", lora.poll_vh); |
dudmuck | 18:9530d682fd9a | 3476 | } |
dudmuck | 18:9530d682fd9a | 3477 | |
dudmuck | 18:9530d682fd9a | 3478 | void cmd_fsk_syncword(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3479 | { |
dudmuck | 18:9530d682fd9a | 3480 | int i, d = 0; |
dudmuck | 18:9530d682fd9a | 3481 | uint8_t reg_addr = REG_FSK_SYNCVALUE1; |
dudmuck | 18:9530d682fd9a | 3482 | |
dudmuck | 18:9530d682fd9a | 3483 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 18:9530d682fd9a | 3484 | |
dudmuck | 18:9530d682fd9a | 3485 | if (pcbuf_len != idx) { // something to write? |
dudmuck | 18:9530d682fd9a | 3486 | for (i = idx; i < pcbuf_len; ) { |
dudmuck | 18:9530d682fd9a | 3487 | int a, n; |
dudmuck | 18:9530d682fd9a | 3488 | sscanf(pcbuf+i, "%x", &n); |
dudmuck | 18:9530d682fd9a | 3489 | radio.write_reg(reg_addr++, n); |
dudmuck | 18:9530d682fd9a | 3490 | //printf("%02x ", n); |
dudmuck | 18:9530d682fd9a | 3491 | while (pcbuf[i] == ' ') |
dudmuck | 18:9530d682fd9a | 3492 | i++; |
dudmuck | 18:9530d682fd9a | 3493 | for (a = i; pcbuf[a] != ' '; a++) |
dudmuck | 18:9530d682fd9a | 3494 | if (a >= pcbuf_len) |
dudmuck | 18:9530d682fd9a | 3495 | break; |
dudmuck | 18:9530d682fd9a | 3496 | i = a; |
dudmuck | 18:9530d682fd9a | 3497 | while (pcbuf[i] == ' ') { |
dudmuck | 18:9530d682fd9a | 3498 | i++; |
dudmuck | 18:9530d682fd9a | 3499 | if (i >= pcbuf_len) |
dudmuck | 18:9530d682fd9a | 3500 | break; |
dudmuck | 18:9530d682fd9a | 3501 | } |
dudmuck | 18:9530d682fd9a | 3502 | d++; |
dudmuck | 18:9530d682fd9a | 3503 | } |
dudmuck | 18:9530d682fd9a | 3504 | |
dudmuck | 18:9530d682fd9a | 3505 | fsk.RegSyncConfig.bits.SyncSize = reg_addr - REG_FSK_SYNCVALUE1 - 1; |
dudmuck | 18:9530d682fd9a | 3506 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 3507 | } |
dudmuck | 18:9530d682fd9a | 3508 | |
dudmuck | 18:9530d682fd9a | 3509 | printf("%d: ", fsk.RegSyncConfig.bits.SyncSize); |
dudmuck | 18:9530d682fd9a | 3510 | for (i = 0; i <= fsk.RegSyncConfig.bits.SyncSize; i++) |
dudmuck | 18:9530d682fd9a | 3511 | printf("%02x ", radio.read_reg(REG_FSK_SYNCVALUE1+i)); |
dudmuck | 18:9530d682fd9a | 3512 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3513 | } |
dudmuck | 18:9530d682fd9a | 3514 | |
dudmuck | 18:9530d682fd9a | 3515 | void cmd_fsk_syncOn(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3516 | { |
dudmuck | 18:9530d682fd9a | 3517 | fsk.RegSyncConfig.bits.SyncOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3518 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 3519 | printf("SyncOn:%d\r\n", fsk.RegSyncConfig.bits.SyncOn); |
dudmuck | 18:9530d682fd9a | 3520 | } |
dudmuck | 18:9530d682fd9a | 3521 | |
dudmuck | 18:9530d682fd9a | 3522 | void cmd_fsk_bitsync(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3523 | { |
dudmuck | 18:9530d682fd9a | 3524 | fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); |
dudmuck | 18:9530d682fd9a | 3525 | fsk.RegOokPeak.bits.BitSyncOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3526 | radio.write_reg(REG_FSK_OOKPEAK, fsk.RegOokPeak.octet); |
dudmuck | 18:9530d682fd9a | 3527 | if (fsk.RegOokPeak.bits.BitSyncOn) |
dudmuck | 18:9530d682fd9a | 3528 | printf("BitSyncOn\r\n"); |
dudmuck | 18:9530d682fd9a | 3529 | else |
dudmuck | 18:9530d682fd9a | 3530 | printf("BitSync Off\r\n"); |
dudmuck | 18:9530d682fd9a | 3531 | } |
dudmuck | 18:9530d682fd9a | 3532 | |
dudmuck | 18:9530d682fd9a | 3533 | void cmd_lora_sf(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3534 | { |
dudmuck | 18:9530d682fd9a | 3535 | int i; |
dudmuck | 18:9530d682fd9a | 3536 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3537 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3538 | lora.setSf(i); |
dudmuck | 18:9530d682fd9a | 3539 | if (i == 6 && !lora.getHeaderMode()) { |
dudmuck | 18:9530d682fd9a | 3540 | printf("SF6: to implicit header mode\r\n"); |
dudmuck | 18:9530d682fd9a | 3541 | lora.setHeaderMode(true); |
dudmuck | 18:9530d682fd9a | 3542 | } |
dudmuck | 18:9530d682fd9a | 3543 | } |
dudmuck | 18:9530d682fd9a | 3544 | lora.RegModemConfig2.octet = radio.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 18:9530d682fd9a | 3545 | lora_printSf(); |
dudmuck | 18:9530d682fd9a | 3546 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3547 | } |
dudmuck | 18:9530d682fd9a | 3548 | |
dudmuck | 18:9530d682fd9a | 3549 | void cmd_fsk_TxStartCondition(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3550 | { |
dudmuck | 18:9530d682fd9a | 3551 | fsk.RegFifoThreshold.bits.TxStartCondition ^= 1; |
dudmuck | 18:9530d682fd9a | 3552 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 18:9530d682fd9a | 3553 | printf("TxStartCondition:"); |
dudmuck | 18:9530d682fd9a | 3554 | if (fsk.RegFifoThreshold.bits.TxStartCondition) |
dudmuck | 18:9530d682fd9a | 3555 | printf("!FifoEmpty\r\n"); |
dudmuck | 18:9530d682fd9a | 3556 | else |
dudmuck | 18:9530d682fd9a | 3557 | printf("FifoLevel\r\n"); |
dudmuck | 18:9530d682fd9a | 3558 | } |
dudmuck | 18:9530d682fd9a | 3559 | |
dudmuck | 18:9530d682fd9a | 3560 | void cmd_fsk_read_fei(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3561 | { |
dudmuck | 18:9530d682fd9a | 3562 | printf("fei:%dHz\r\n", (int)(FREQ_STEP_HZ * radio.read_s16(REG_FSK_FEIMSB))); |
dudmuck | 18:9530d682fd9a | 3563 | } |
dudmuck | 18:9530d682fd9a | 3564 | |
dudmuck | 18:9530d682fd9a | 3565 | void cmd_fsk_fdev(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3566 | { |
dudmuck | 18:9530d682fd9a | 3567 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3568 | float khz; |
dudmuck | 18:9530d682fd9a | 3569 | sscanf(pcbuf+idx, "%f", &khz); |
dudmuck | 18:9530d682fd9a | 3570 | fsk.set_tx_fdev_hz((int)(khz*1000)); |
dudmuck | 18:9530d682fd9a | 3571 | } |
dudmuck | 18:9530d682fd9a | 3572 | printf("fdev:%fKHz\r\n", fsk.get_tx_fdev_hz()/(float)1000.0); |
dudmuck | 18:9530d682fd9a | 3573 | } |
dudmuck | 18:9530d682fd9a | 3574 | |
dudmuck | 21:b84a77dfb43c | 3575 | void cmd_spifreq(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 3576 | { |
dudmuck | 21:b84a77dfb43c | 3577 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 21:b84a77dfb43c | 3578 | int hz, MHz; |
dudmuck | 21:b84a77dfb43c | 3579 | sscanf(pcbuf+idx, "%d", &MHz); |
dudmuck | 21:b84a77dfb43c | 3580 | hz = MHz * 1000000; |
dudmuck | 21:b84a77dfb43c | 3581 | printf("spi hz:%u\r\n", hz); |
dudmuck | 21:b84a77dfb43c | 3582 | radio.m_spi.frequency(hz); |
dudmuck | 21:b84a77dfb43c | 3583 | } |
dudmuck | 21:b84a77dfb43c | 3584 | } |
dudmuck | 21:b84a77dfb43c | 3585 | |
dudmuck | 18:9530d682fd9a | 3586 | void cmd_frf(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3587 | { |
dudmuck | 18:9530d682fd9a | 3588 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3589 | float MHz; |
dudmuck | 18:9530d682fd9a | 3590 | sscanf(pcbuf+idx, "%f", &MHz); |
dudmuck | 18:9530d682fd9a | 3591 | //printf("MHz:%f\r\n", MHz); |
dudmuck | 18:9530d682fd9a | 3592 | radio.set_frf_MHz(MHz); |
dudmuck | 18:9530d682fd9a | 3593 | } |
dudmuck | 18:9530d682fd9a | 3594 | printf("%fMHz\r\n", radio.get_frf_MHz()); |
dudmuck | 18:9530d682fd9a | 3595 | #ifndef TARGET_MTS_MDOT_F411RE |
dudmuck | 18:9530d682fd9a | 3596 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 18:9530d682fd9a | 3597 | if (shield_type == SHIELD_TYPE_LAS) { |
dudmuck | 18:9530d682fd9a | 3598 | // LAS HF=PA_BOOST LF=RFO |
dudmuck | 18:9530d682fd9a | 3599 | if (radio.HF) |
dudmuck | 18:9530d682fd9a | 3600 | radio.RegPaConfig.bits.PaSelect = 1; |
dudmuck | 18:9530d682fd9a | 3601 | else |
dudmuck | 18:9530d682fd9a | 3602 | radio.RegPaConfig.bits.PaSelect = 0; |
dudmuck | 18:9530d682fd9a | 3603 | } |
dudmuck | 18:9530d682fd9a | 3604 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 18:9530d682fd9a | 3605 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 18:9530d682fd9a | 3606 | } |
dudmuck | 18:9530d682fd9a | 3607 | |
dudmuck | 18:9530d682fd9a | 3608 | void cmd_fsk_PacketFormat(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3609 | { |
dudmuck | 18:9530d682fd9a | 3610 | printf("PacketFormat:"); |
dudmuck | 18:9530d682fd9a | 3611 | fsk.RegPktConfig1.bits.PacketFormatVariable ^= 1; |
dudmuck | 18:9530d682fd9a | 3612 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 18:9530d682fd9a | 3613 | if (fsk.RegPktConfig1.bits.PacketFormatVariable) |
dudmuck | 18:9530d682fd9a | 3614 | printf("variable\r\n"); |
dudmuck | 18:9530d682fd9a | 3615 | else |
dudmuck | 18:9530d682fd9a | 3616 | printf("fixed\r\n"); |
dudmuck | 18:9530d682fd9a | 3617 | } |
dudmuck | 18:9530d682fd9a | 3618 | |
dudmuck | 18:9530d682fd9a | 3619 | void cmd_payload_length(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3620 | { |
dudmuck | 18:9530d682fd9a | 3621 | int i; |
dudmuck | 18:9530d682fd9a | 3622 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3623 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3624 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 3625 | lora.RegPayloadLength = i; |
dudmuck | 13:c73caaee93a5 | 3626 | radio.write_reg(REG_LR_PAYLOADLENGTH, lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3627 | } else { |
dudmuck | 18:9530d682fd9a | 3628 | fsk.RegPktConfig2.bits.PayloadLength = i; |
dudmuck | 18:9530d682fd9a | 3629 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 10:d9bb2ce57f05 | 3630 | } |
dudmuck | 18:9530d682fd9a | 3631 | } |
dudmuck | 18:9530d682fd9a | 3632 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 3633 | lora.RegPayloadLength = radio.read_reg(REG_LR_PAYLOADLENGTH); |
dudmuck | 18:9530d682fd9a | 3634 | printf("PayloadLength:%d\r\n", lora.RegPayloadLength); |
dudmuck | 18:9530d682fd9a | 3635 | } else { |
dudmuck | 18:9530d682fd9a | 3636 | printf("PayloadLength:%d\r\n", fsk_get_PayloadLength()); |
dudmuck | 18:9530d682fd9a | 3637 | } |
dudmuck | 18:9530d682fd9a | 3638 | } |
dudmuck | 18:9530d682fd9a | 3639 | |
dudmuck | 18:9530d682fd9a | 3640 | void cmd_paRamp(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3641 | { |
dudmuck | 18:9530d682fd9a | 3642 | int i; |
dudmuck | 18:9530d682fd9a | 3643 | uint8_t reg_par = radio.read_reg(REG_PARAMP); |
dudmuck | 18:9530d682fd9a | 3644 | uint8_t PaRamp = reg_par & 0x0f; |
dudmuck | 18:9530d682fd9a | 3645 | reg_par &= 0xf0; |
dudmuck | 18:9530d682fd9a | 3646 | if (PaRamp == 15) |
dudmuck | 18:9530d682fd9a | 3647 | PaRamp = 0; |
dudmuck | 18:9530d682fd9a | 3648 | else |
dudmuck | 18:9530d682fd9a | 3649 | PaRamp++; |
dudmuck | 18:9530d682fd9a | 3650 | radio.write_reg(REG_PARAMP, reg_par | PaRamp); |
dudmuck | 18:9530d682fd9a | 3651 | printf("PaRamp:"); |
dudmuck | 18:9530d682fd9a | 3652 | switch (PaRamp) { |
dudmuck | 18:9530d682fd9a | 3653 | case 0: i = 3400; break; |
dudmuck | 18:9530d682fd9a | 3654 | case 1: i = 2000; break; |
dudmuck | 18:9530d682fd9a | 3655 | case 2: i = 1000; break; |
dudmuck | 18:9530d682fd9a | 3656 | case 3: i = 500; break; |
dudmuck | 18:9530d682fd9a | 3657 | case 4: i = 250; break; |
dudmuck | 18:9530d682fd9a | 3658 | case 5: i = 125; break; |
dudmuck | 18:9530d682fd9a | 3659 | case 6: i = 100; break; |
dudmuck | 18:9530d682fd9a | 3660 | case 7: i = 62; break; |
dudmuck | 18:9530d682fd9a | 3661 | case 8: i = 50; break; |
dudmuck | 18:9530d682fd9a | 3662 | case 9: i = 40; break; |
dudmuck | 18:9530d682fd9a | 3663 | case 10: i = 31; break; |
dudmuck | 18:9530d682fd9a | 3664 | case 11: i = 25; break; |
dudmuck | 18:9530d682fd9a | 3665 | case 12: i = 20; break; |
dudmuck | 18:9530d682fd9a | 3666 | case 13: i = 15; break; |
dudmuck | 18:9530d682fd9a | 3667 | case 14: i = 12; break; |
dudmuck | 18:9530d682fd9a | 3668 | case 15: i = 10; break; |
dudmuck | 18:9530d682fd9a | 3669 | } |
dudmuck | 18:9530d682fd9a | 3670 | printf("%dus\r\n", i); |
dudmuck | 18:9530d682fd9a | 3671 | } |
dudmuck | 18:9530d682fd9a | 3672 | |
dudmuck | 18:9530d682fd9a | 3673 | void cmd_paSelect(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3674 | { |
dudmuck | 18:9530d682fd9a | 3675 | radio.RegPaConfig.bits.PaSelect ^= 1; |
dudmuck | 18:9530d682fd9a | 3676 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 18:9530d682fd9a | 3677 | printPa(); |
dudmuck | 18:9530d682fd9a | 3678 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3679 | } |
dudmuck | 18:9530d682fd9a | 3680 | |
dudmuck | 18:9530d682fd9a | 3681 | void cmd_poll_irq_en(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3682 | { |
dudmuck | 18:9530d682fd9a | 3683 | poll_irq_en ^= 1; |
dudmuck | 18:9530d682fd9a | 3684 | printf("poll_irq_en:"); |
dudmuck | 20:b11592c9ba5f | 3685 | if (poll_irq_en) { |
dudmuck | 18:9530d682fd9a | 3686 | printf("irqFlags register\r\n"); |
dudmuck | 20:b11592c9ba5f | 3687 | fsk_RegIrqFlags1_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 3688 | fsk_RegIrqFlags2_prev.octet = 0; |
dudmuck | 20:b11592c9ba5f | 3689 | } else |
dudmuck | 18:9530d682fd9a | 3690 | printf("DIO pin interrupt\r\n"); |
dudmuck | 18:9530d682fd9a | 3691 | } |
dudmuck | 18:9530d682fd9a | 3692 | |
dudmuck | 18:9530d682fd9a | 3693 | void cmd_per_id(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3694 | { |
dudmuck | 18:9530d682fd9a | 3695 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3696 | sscanf(pcbuf+idx, "%d", &per_id); |
dudmuck | 18:9530d682fd9a | 3697 | } |
dudmuck | 18:9530d682fd9a | 3698 | printf("PER device ID:%d\r\n", per_id); |
dudmuck | 18:9530d682fd9a | 3699 | } |
dudmuck | 18:9530d682fd9a | 3700 | |
dudmuck | 18:9530d682fd9a | 3701 | void cmd_pertx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3702 | { |
dudmuck | 18:9530d682fd9a | 3703 | int i; |
dudmuck | 18:9530d682fd9a | 3704 | |
dudmuck | 18:9530d682fd9a | 3705 | if (cadper_enable) |
dudmuck | 18:9530d682fd9a | 3706 | cadper_enable = false; |
dudmuck | 18:9530d682fd9a | 3707 | |
dudmuck | 18:9530d682fd9a | 3708 | set_per_en(true); |
dudmuck | 18:9530d682fd9a | 3709 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3710 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3711 | PacketTxCntEnd = i; |
dudmuck | 18:9530d682fd9a | 3712 | } |
dudmuck | 18:9530d682fd9a | 3713 | PacketTxCnt = 0; |
dudmuck | 18:9530d682fd9a | 3714 | per_timeout.attach(&per_cb, per_tx_delay); |
dudmuck | 18:9530d682fd9a | 3715 | } |
dudmuck | 18:9530d682fd9a | 3716 | |
dudmuck | 18:9530d682fd9a | 3717 | void cmd_perrx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3718 | { |
dudmuck | 18:9530d682fd9a | 3719 | set_per_en(true); |
dudmuck | 18:9530d682fd9a | 3720 | |
dudmuck | 18:9530d682fd9a | 3721 | PacketNormalCnt = 0; |
dudmuck | 20:b11592c9ba5f | 3722 | PacketRxSequencePrev = 0; // transmitter side PacketTxCnt is 1 at first TX |
dudmuck | 18:9530d682fd9a | 3723 | PacketPerKoCnt = 0; |
dudmuck | 18:9530d682fd9a | 3724 | PacketPerOkCnt = 0; |
dudmuck | 18:9530d682fd9a | 3725 | //dio3.rise(&dio3_cb); |
dudmuck | 18:9530d682fd9a | 3726 | |
dudmuck | 18:9530d682fd9a | 3727 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 3728 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 13:c73caaee93a5 | 3729 | else { |
dudmuck | 18:9530d682fd9a | 3730 | fsk.start_rx(); |
dudmuck | 18:9530d682fd9a | 3731 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to syncadrs |
dudmuck | 18:9530d682fd9a | 3732 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3733 | if (radio.HF) { |
dudmuck | 18:9530d682fd9a | 3734 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 18:9530d682fd9a | 3735 | fsk.RegRssiConfig.bits.RssiOffset = FSK_RSSI_OFFSET; |
dudmuck | 18:9530d682fd9a | 3736 | fsk.RegRssiConfig.bits.RssiSmoothing = FSK_RSSI_SMOOTHING; |
dudmuck | 18:9530d682fd9a | 3737 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 18:9530d682fd9a | 3738 | } |
dudmuck | 18:9530d682fd9a | 3739 | } |
dudmuck | 18:9530d682fd9a | 3740 | } |
dudmuck | 18:9530d682fd9a | 3741 | |
dudmuck | 18:9530d682fd9a | 3742 | void cmd_fsk_PreambleDetectorOn(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3743 | { |
dudmuck | 18:9530d682fd9a | 3744 | fsk.RegPreambleDetect.bits.PreambleDetectorOn ^= 1; |
dudmuck | 18:9530d682fd9a | 3745 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 3746 | printf("PreambleDetector:"); |
dudmuck | 18:9530d682fd9a | 3747 | if (fsk.RegPreambleDetect.bits.PreambleDetectorOn) |
dudmuck | 18:9530d682fd9a | 3748 | printf("On\r\n"); |
dudmuck | 18:9530d682fd9a | 3749 | else |
dudmuck | 18:9530d682fd9a | 3750 | printf("OFF\r\n"); |
dudmuck | 18:9530d682fd9a | 3751 | } |
dudmuck | 18:9530d682fd9a | 3752 | |
dudmuck | 18:9530d682fd9a | 3753 | void cmd_fsk_PreambleDetectorSize(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3754 | { |
dudmuck | 18:9530d682fd9a | 3755 | int i; |
dudmuck | 18:9530d682fd9a | 3756 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3757 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3758 | fsk.RegPreambleDetect.bits.PreambleDetectorSize = i; |
dudmuck | 18:9530d682fd9a | 3759 | } |
dudmuck | 18:9530d682fd9a | 3760 | printf("PreambleDetectorSize:%d\r\n", fsk.RegPreambleDetect.bits.PreambleDetectorSize); |
dudmuck | 18:9530d682fd9a | 3761 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 3762 | } |
dudmuck | 18:9530d682fd9a | 3763 | |
dudmuck | 18:9530d682fd9a | 3764 | void cmd_fsk_PreambleDetectorTol(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3765 | { |
dudmuck | 18:9530d682fd9a | 3766 | int i; |
dudmuck | 18:9530d682fd9a | 3767 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3768 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3769 | fsk.RegPreambleDetect.bits.PreambleDetectorTol = i; |
dudmuck | 18:9530d682fd9a | 3770 | } |
dudmuck | 18:9530d682fd9a | 3771 | printf("PreambleDetectorTol:%d\r\n", fsk.RegPreambleDetect.bits.PreambleDetectorTol); |
dudmuck | 18:9530d682fd9a | 3772 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 18:9530d682fd9a | 3773 | } |
dudmuck | 18:9530d682fd9a | 3774 | |
dudmuck | 18:9530d682fd9a | 3775 | void cmd_PreambleSize(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3776 | { |
dudmuck | 18:9530d682fd9a | 3777 | int i; |
dudmuck | 18:9530d682fd9a | 3778 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 3779 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3780 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3781 | radio.write_u16(REG_LR_PREAMBLEMSB, i); |
dudmuck | 18:9530d682fd9a | 3782 | } |
dudmuck | 18:9530d682fd9a | 3783 | lora.RegPreamble = radio.read_u16(REG_LR_PREAMBLEMSB); |
dudmuck | 18:9530d682fd9a | 3784 | printf("lora PreambleLength:%d\r\n", lora.RegPreamble); |
dudmuck | 18:9530d682fd9a | 3785 | } else { |
dudmuck | 18:9530d682fd9a | 3786 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3787 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3788 | radio.write_u16(REG_FSK_PREAMBLEMSB, i); |
dudmuck | 18:9530d682fd9a | 3789 | } |
dudmuck | 18:9530d682fd9a | 3790 | printf("PreambleSize:%d\r\n", radio.read_u16(REG_FSK_PREAMBLEMSB)); |
dudmuck | 18:9530d682fd9a | 3791 | } |
dudmuck | 18:9530d682fd9a | 3792 | } |
dudmuck | 18:9530d682fd9a | 3793 | |
dudmuck | 18:9530d682fd9a | 3794 | void cmd_fsk_PreamblePolarity(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3795 | { |
dudmuck | 18:9530d682fd9a | 3796 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 18:9530d682fd9a | 3797 | fsk.RegSyncConfig.bits.PreamblePolarity ^= 1; |
dudmuck | 18:9530d682fd9a | 3798 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 18:9530d682fd9a | 3799 | if (fsk.RegSyncConfig.bits.PreamblePolarity) |
dudmuck | 18:9530d682fd9a | 3800 | printf("0x55\r\n"); |
dudmuck | 18:9530d682fd9a | 3801 | else |
dudmuck | 18:9530d682fd9a | 3802 | printf("0xaa\r\n"); |
dudmuck | 18:9530d682fd9a | 3803 | } |
dudmuck | 18:9530d682fd9a | 3804 | |
dudmuck | 18:9530d682fd9a | 3805 | void cmd_pllbw(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3806 | { |
dudmuck | 18:9530d682fd9a | 3807 | RegPll_t pll; |
dudmuck | 18:9530d682fd9a | 3808 | if (radio.type == SX1272) { |
dudmuck | 18:9530d682fd9a | 3809 | // 0x5c and 0x5e registers |
dudmuck | 18:9530d682fd9a | 3810 | pll.octet = radio.read_reg(REG_PLL_SX1272); |
dudmuck | 18:9530d682fd9a | 3811 | if (pll.bits.PllBandwidth == 3) |
dudmuck | 18:9530d682fd9a | 3812 | pll.bits.PllBandwidth = 0; |
dudmuck | 18:9530d682fd9a | 3813 | else |
dudmuck | 18:9530d682fd9a | 3814 | pll.bits.PllBandwidth++; |
dudmuck | 18:9530d682fd9a | 3815 | radio.write_reg(REG_PLL_SX1272, pll.octet); |
dudmuck | 18:9530d682fd9a | 3816 | pll.octet = radio.read_reg(REG_PLL_LOWPN_SX1272); |
dudmuck | 18:9530d682fd9a | 3817 | if (pll.bits.PllBandwidth == 3) |
dudmuck | 18:9530d682fd9a | 3818 | pll.bits.PllBandwidth = 0; |
dudmuck | 18:9530d682fd9a | 3819 | else |
dudmuck | 18:9530d682fd9a | 3820 | pll.bits.PllBandwidth++; |
dudmuck | 18:9530d682fd9a | 3821 | radio.write_reg(REG_PLL_LOWPN_SX1272, pll.octet); |
dudmuck | 18:9530d682fd9a | 3822 | } else if (radio.type == SX1276) { |
dudmuck | 18:9530d682fd9a | 3823 | // 0x70 register |
dudmuck | 18:9530d682fd9a | 3824 | pll.octet = radio.read_reg(REG_PLL_SX1276); |
dudmuck | 18:9530d682fd9a | 3825 | if (pll.bits.PllBandwidth == 3) |
dudmuck | 18:9530d682fd9a | 3826 | pll.bits.PllBandwidth = 0; |
dudmuck | 18:9530d682fd9a | 3827 | else |
dudmuck | 18:9530d682fd9a | 3828 | pll.bits.PllBandwidth++; |
dudmuck | 18:9530d682fd9a | 3829 | radio.write_reg(REG_PLL_SX1276, pll.octet); |
dudmuck | 18:9530d682fd9a | 3830 | } |
dudmuck | 18:9530d682fd9a | 3831 | switch (pll.bits.PllBandwidth) { |
dudmuck | 18:9530d682fd9a | 3832 | case 0: printf("75"); break; |
dudmuck | 18:9530d682fd9a | 3833 | case 1: printf("150"); break; |
dudmuck | 18:9530d682fd9a | 3834 | case 2: printf("225"); break; |
dudmuck | 18:9530d682fd9a | 3835 | case 3: printf("300"); break; |
dudmuck | 18:9530d682fd9a | 3836 | } |
dudmuck | 18:9530d682fd9a | 3837 | printf("KHz\r\n"); |
dudmuck | 18:9530d682fd9a | 3838 | } |
dudmuck | 18:9530d682fd9a | 3839 | |
dudmuck | 18:9530d682fd9a | 3840 | void cmd_lna_boost(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3841 | { |
dudmuck | 18:9530d682fd9a | 3842 | radio.RegLna.octet = radio.read_reg(REG_LNA); |
dudmuck | 18:9530d682fd9a | 3843 | if (radio.RegLna.bits.LnaBoostHF == 3) |
dudmuck | 18:9530d682fd9a | 3844 | radio.RegLna.bits.LnaBoostHF = 0; |
dudmuck | 18:9530d682fd9a | 3845 | else |
dudmuck | 18:9530d682fd9a | 3846 | radio.RegLna.bits.LnaBoostHF++; |
dudmuck | 18:9530d682fd9a | 3847 | radio.write_reg(REG_LNA, radio.RegLna.octet); |
dudmuck | 18:9530d682fd9a | 3848 | printf("LNA-boost:%d\r\n", radio.RegLna.bits.LnaBoostHF); |
dudmuck | 18:9530d682fd9a | 3849 | } |
dudmuck | 18:9530d682fd9a | 3850 | |
dudmuck | 18:9530d682fd9a | 3851 | void cmd_LowDataRateOptimize(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3852 | { |
dudmuck | 18:9530d682fd9a | 3853 | if (radio.type == SX1272) { |
dudmuck | 18:9530d682fd9a | 3854 | lora.RegModemConfig.octet = radio.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 18:9530d682fd9a | 3855 | lora.RegModemConfig.sx1272bits.LowDataRateOptimize ^= 1; |
dudmuck | 18:9530d682fd9a | 3856 | printf("LowDataRateOptimize:%d\r\n", lora.RegModemConfig.sx1272bits.LowDataRateOptimize); |
dudmuck | 18:9530d682fd9a | 3857 | radio.write_reg(REG_LR_MODEMCONFIG, lora.RegModemConfig.octet); |
dudmuck | 18:9530d682fd9a | 3858 | } else if (radio.type == SX1276) { |
dudmuck | 18:9530d682fd9a | 3859 | lora.RegModemConfig3.octet = radio.read_reg(REG_LR_MODEMCONFIG3); |
dudmuck | 18:9530d682fd9a | 3860 | lora.RegModemConfig3.sx1276bits.LowDataRateOptimize ^= 1; |
dudmuck | 18:9530d682fd9a | 3861 | printf("LowDataRateOptimize:%d\r\n", lora.RegModemConfig3.sx1276bits.LowDataRateOptimize); |
dudmuck | 18:9530d682fd9a | 3862 | radio.write_reg(REG_LR_MODEMCONFIG3, lora.RegModemConfig3.octet); |
dudmuck | 18:9530d682fd9a | 3863 | } |
dudmuck | 18:9530d682fd9a | 3864 | } |
dudmuck | 18:9530d682fd9a | 3865 | |
dudmuck | 18:9530d682fd9a | 3866 | void cmd_fsk_FifoThreshold(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3867 | { |
dudmuck | 18:9530d682fd9a | 3868 | int i; |
dudmuck | 18:9530d682fd9a | 3869 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 18:9530d682fd9a | 3870 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 3871 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 3872 | fsk.RegFifoThreshold.bits.FifoThreshold = i; |
dudmuck | 18:9530d682fd9a | 3873 | } |
dudmuck | 18:9530d682fd9a | 3874 | radio.write_reg(REG_FSK_FIFOTHRESH, fsk.RegFifoThreshold.octet); |
dudmuck | 18:9530d682fd9a | 3875 | printf("FifoThreshold:%d\r\n", fsk.RegFifoThreshold.bits.FifoThreshold); |
dudmuck | 18:9530d682fd9a | 3876 | fsk.RegFifoThreshold.octet = radio.read_reg(REG_FSK_FIFOTHRESH); |
dudmuck | 18:9530d682fd9a | 3877 | } |
dudmuck | 18:9530d682fd9a | 3878 | |
dudmuck | 18:9530d682fd9a | 3879 | void cmd_tx_ticker_rate(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3880 | { |
dudmuck | 18:9530d682fd9a | 3881 | if (pcbuf[idx] != 0) { |
dudmuck | 18:9530d682fd9a | 3882 | sscanf(pcbuf+idx, "%f", &tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3883 | } |
dudmuck | 18:9530d682fd9a | 3884 | printf("tx_ticker_rate:%f\r\n", tx_ticker_rate); |
dudmuck | 18:9530d682fd9a | 3885 | } |
dudmuck | 18:9530d682fd9a | 3886 | |
dudmuck | 18:9530d682fd9a | 3887 | void cmd_lora_tx_invert(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3888 | { |
dudmuck | 18:9530d682fd9a | 3889 | lora.invert_tx(lora.RegTest33.bits.chirp_invert_tx); |
dudmuck | 18:9530d682fd9a | 3890 | printf("chirp_invert_tx :%d\r\n", lora.RegTest33.bits.chirp_invert_tx); |
dudmuck | 18:9530d682fd9a | 3891 | } |
dudmuck | 18:9530d682fd9a | 3892 | |
dudmuck | 18:9530d682fd9a | 3893 | void cmd_lora_rx_invert(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3894 | { |
dudmuck | 18:9530d682fd9a | 3895 | lora.invert_rx(!lora.RegTest33.bits.invert_i_q); |
dudmuck | 18:9530d682fd9a | 3896 | printf("rx invert_i_q:%d\r\n", lora.RegTest33.bits.invert_i_q); |
dudmuck | 18:9530d682fd9a | 3897 | } |
dudmuck | 18:9530d682fd9a | 3898 | |
dudmuck | 18:9530d682fd9a | 3899 | void cmd_fsk_dcfree(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3900 | { |
dudmuck | 18:9530d682fd9a | 3901 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 18:9530d682fd9a | 3902 | if (fsk.RegPktConfig1.bits.DcFree == 3) |
dudmuck | 18:9530d682fd9a | 3903 | fsk.RegPktConfig1.bits.DcFree = 0; |
dudmuck | 18:9530d682fd9a | 3904 | else |
dudmuck | 18:9530d682fd9a | 3905 | fsk.RegPktConfig1.bits.DcFree++; |
dudmuck | 18:9530d682fd9a | 3906 | printf(" dcFree:"); |
dudmuck | 18:9530d682fd9a | 3907 | switch (fsk.RegPktConfig1.bits.DcFree) { |
dudmuck | 18:9530d682fd9a | 3908 | case 0: printf("none "); break; |
dudmuck | 18:9530d682fd9a | 3909 | case 1: printf("Manchester "); break; |
dudmuck | 18:9530d682fd9a | 3910 | case 2: printf("Whitening "); break; |
dudmuck | 18:9530d682fd9a | 3911 | case 3: printf("[41mreserved[0m "); break; |
dudmuck | 18:9530d682fd9a | 3912 | } |
dudmuck | 18:9530d682fd9a | 3913 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 18:9530d682fd9a | 3914 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 3915 | } |
dudmuck | 18:9530d682fd9a | 3916 | |
dudmuck | 21:b84a77dfb43c | 3917 | void cmd_bt(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 3918 | { |
dudmuck | 21:b84a77dfb43c | 3919 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 21:b84a77dfb43c | 3920 | if (radio.RegOpMode.bits.ModulationType != 0) { |
dudmuck | 21:b84a77dfb43c | 3921 | printf("!fsk\r\n"); |
dudmuck | 21:b84a77dfb43c | 3922 | return; |
dudmuck | 21:b84a77dfb43c | 3923 | } |
dudmuck | 21:b84a77dfb43c | 3924 | |
dudmuck | 21:b84a77dfb43c | 3925 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 21:b84a77dfb43c | 3926 | float bt; |
dudmuck | 21:b84a77dfb43c | 3927 | sscanf(pcbuf+idx, "%f", &bt); |
dudmuck | 21:b84a77dfb43c | 3928 | if (bt > 1.0) |
dudmuck | 21:b84a77dfb43c | 3929 | radio.RegOpMode.bits.ModulationShaping = 0; // 0 = no shaping |
dudmuck | 21:b84a77dfb43c | 3930 | else if (bt > 0.6) |
dudmuck | 21:b84a77dfb43c | 3931 | radio.RegOpMode.bits.ModulationShaping = 1; // 1 = BT1.0 |
dudmuck | 21:b84a77dfb43c | 3932 | else if (bt > 0.4) |
dudmuck | 21:b84a77dfb43c | 3933 | radio.RegOpMode.bits.ModulationShaping = 2; // 2 = BT0.5 |
dudmuck | 21:b84a77dfb43c | 3934 | else |
dudmuck | 21:b84a77dfb43c | 3935 | radio.RegOpMode.bits.ModulationShaping = 3; // 3 = BT0.3 |
dudmuck | 21:b84a77dfb43c | 3936 | } |
dudmuck | 21:b84a77dfb43c | 3937 | radio.write_reg(REG_OPMODE, radio.RegOpMode.octet); |
dudmuck | 21:b84a77dfb43c | 3938 | switch (radio.RegOpMode.bits.ModulationShaping) { |
dudmuck | 21:b84a77dfb43c | 3939 | case 0: printf("no-shaping "); break; |
dudmuck | 21:b84a77dfb43c | 3940 | case 1: printf("BT1.0 "); break; |
dudmuck | 21:b84a77dfb43c | 3941 | case 2: printf("BT0.5 "); break; |
dudmuck | 21:b84a77dfb43c | 3942 | case 3: printf("BT0.3 "); break; |
dudmuck | 21:b84a77dfb43c | 3943 | } |
dudmuck | 21:b84a77dfb43c | 3944 | printf("\r\n"); |
dudmuck | 21:b84a77dfb43c | 3945 | } |
dudmuck | 21:b84a77dfb43c | 3946 | |
dudmuck | 18:9530d682fd9a | 3947 | void cmd_fsk_DataMode(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3948 | { |
dudmuck | 18:9530d682fd9a | 3949 | fsk.RegPktConfig2.word = radio.read_u16(REG_FSK_PACKETCONFIG2); |
dudmuck | 18:9530d682fd9a | 3950 | fsk.RegPktConfig2.bits.DataModePacket ^= 1; |
dudmuck | 18:9530d682fd9a | 3951 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 18:9530d682fd9a | 3952 | printf("datamode:"); |
dudmuck | 18:9530d682fd9a | 3953 | if (fsk.RegPktConfig2.bits.DataModePacket) |
dudmuck | 18:9530d682fd9a | 3954 | printf("packet\r\n"); |
dudmuck | 18:9530d682fd9a | 3955 | else |
dudmuck | 18:9530d682fd9a | 3956 | printf("continuous\r\n"); |
dudmuck | 18:9530d682fd9a | 3957 | } |
dudmuck | 18:9530d682fd9a | 3958 | |
dudmuck | 18:9530d682fd9a | 3959 | void cmd_show_dio(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3960 | { |
dudmuck | 18:9530d682fd9a | 3961 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 3962 | lora_print_dio(); |
dudmuck | 18:9530d682fd9a | 3963 | else |
dudmuck | 18:9530d682fd9a | 3964 | fsk_print_dio(); |
dudmuck | 18:9530d682fd9a | 3965 | } |
dudmuck | 18:9530d682fd9a | 3966 | |
dudmuck | 18:9530d682fd9a | 3967 | void cmd_set_dio(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 3968 | { |
dudmuck | 18:9530d682fd9a | 3969 | switch (pcbuf[idx]) { |
dudmuck | 18:9530d682fd9a | 3970 | case '0': |
dudmuck | 18:9530d682fd9a | 3971 | radio.RegDioMapping1.bits.Dio0Mapping++; |
dudmuck | 18:9530d682fd9a | 3972 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3973 | break; |
dudmuck | 18:9530d682fd9a | 3974 | case '1': |
dudmuck | 18:9530d682fd9a | 3975 | radio.RegDioMapping1.bits.Dio1Mapping++; |
dudmuck | 18:9530d682fd9a | 3976 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3977 | break; |
dudmuck | 18:9530d682fd9a | 3978 | case '2': |
dudmuck | 18:9530d682fd9a | 3979 | radio.RegDioMapping1.bits.Dio2Mapping++; |
dudmuck | 18:9530d682fd9a | 3980 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3981 | break; |
dudmuck | 18:9530d682fd9a | 3982 | case '3': |
dudmuck | 18:9530d682fd9a | 3983 | radio.RegDioMapping1.bits.Dio3Mapping++; |
dudmuck | 18:9530d682fd9a | 3984 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 18:9530d682fd9a | 3985 | break; |
dudmuck | 18:9530d682fd9a | 3986 | case '4': |
dudmuck | 18:9530d682fd9a | 3987 | radio.RegDioMapping2.bits.Dio4Mapping++; |
dudmuck | 18:9530d682fd9a | 3988 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 18:9530d682fd9a | 3989 | break; |
dudmuck | 18:9530d682fd9a | 3990 | case '5': |
dudmuck | 18:9530d682fd9a | 3991 | radio.RegDioMapping2.bits.Dio5Mapping++; |
dudmuck | 18:9530d682fd9a | 3992 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 18:9530d682fd9a | 3993 | break; |
dudmuck | 18:9530d682fd9a | 3994 | } // ...switch (pcbuf[idx]) |
dudmuck | 18:9530d682fd9a | 3995 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 18:9530d682fd9a | 3996 | lora_print_dio(); |
dudmuck | 18:9530d682fd9a | 3997 | else |
dudmuck | 18:9530d682fd9a | 3998 | fsk_print_dio(); |
dudmuck | 18:9530d682fd9a | 3999 | } |
dudmuck | 18:9530d682fd9a | 4000 | |
dudmuck | 18:9530d682fd9a | 4001 | void cmd_mode_standby(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4002 | { |
dudmuck | 18:9530d682fd9a | 4003 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 18:9530d682fd9a | 4004 | printf("standby\r\n"); |
dudmuck | 18:9530d682fd9a | 4005 | } |
dudmuck | 18:9530d682fd9a | 4006 | |
dudmuck | 18:9530d682fd9a | 4007 | void cmd_mode_sleep(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4008 | { |
dudmuck | 18:9530d682fd9a | 4009 | radio.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 18:9530d682fd9a | 4010 | printf("sleep\r\n"); |
dudmuck | 18:9530d682fd9a | 4011 | } |
dudmuck | 18:9530d682fd9a | 4012 | |
dudmuck | 18:9530d682fd9a | 4013 | void cmd_mode_fstx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4014 | { |
dudmuck | 18:9530d682fd9a | 4015 | radio.set_opmode(RF_OPMODE_SYNTHESIZER_TX); |
dudmuck | 18:9530d682fd9a | 4016 | printf("fstx\r\n"); |
dudmuck | 18:9530d682fd9a | 4017 | } |
dudmuck | 18:9530d682fd9a | 4018 | |
dudmuck | 18:9530d682fd9a | 4019 | void cmd_mode_fsrx(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4020 | { |
dudmuck | 18:9530d682fd9a | 4021 | radio.set_opmode(RF_OPMODE_SYNTHESIZER_RX); |
dudmuck | 18:9530d682fd9a | 4022 | printf("fsrx\r\n"); |
dudmuck | 18:9530d682fd9a | 4023 | } |
dudmuck | 18:9530d682fd9a | 4024 | |
dudmuck | 18:9530d682fd9a | 4025 | void cmd_chat(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4026 | { |
dudmuck | 18:9530d682fd9a | 4027 | app = APP_CHAT; |
dudmuck | 18:9530d682fd9a | 4028 | lora.start_rx(RF_OPMODE_RECEIVER); |
dudmuck | 18:9530d682fd9a | 4029 | printf("chat start\r\n"); |
dudmuck | 18:9530d682fd9a | 4030 | } |
dudmuck | 18:9530d682fd9a | 4031 | |
dudmuck | 18:9530d682fd9a | 4032 | void cmd_OokThreshType(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4033 | { |
dudmuck | 18:9530d682fd9a | 4034 | fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); |
dudmuck | 18:9530d682fd9a | 4035 | if (fsk.RegOokPeak.bits.OokThreshType == 2) |
dudmuck | 18:9530d682fd9a | 4036 | fsk.RegOokPeak.bits.OokThreshType = 0; |
dudmuck | 18:9530d682fd9a | 4037 | else |
dudmuck | 18:9530d682fd9a | 4038 | fsk.RegOokPeak.bits.OokThreshType++; |
dudmuck | 18:9530d682fd9a | 4039 | |
dudmuck | 18:9530d682fd9a | 4040 | radio.write_reg(REG_FSK_OOKPEAK, fsk.RegOokPeak.octet); |
dudmuck | 18:9530d682fd9a | 4041 | printf("OokThreshType:"); |
dudmuck | 18:9530d682fd9a | 4042 | switch (fsk.RegOokPeak.bits.OokThreshType) { |
dudmuck | 18:9530d682fd9a | 4043 | case 0: printf("fixed"); break; |
dudmuck | 18:9530d682fd9a | 4044 | case 1: printf("peak"); break; |
dudmuck | 18:9530d682fd9a | 4045 | case 2: printf("average"); break; |
dudmuck | 18:9530d682fd9a | 4046 | case 3: printf("?"); break; |
dudmuck | 18:9530d682fd9a | 4047 | } |
dudmuck | 18:9530d682fd9a | 4048 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 4049 | } |
dudmuck | 18:9530d682fd9a | 4050 | |
dudmuck | 18:9530d682fd9a | 4051 | void cmd_OokPeakTheshStep(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4052 | { |
dudmuck | 18:9530d682fd9a | 4053 | float f; |
dudmuck | 18:9530d682fd9a | 4054 | fsk.RegOokPeak.octet = radio.read_reg(REG_FSK_OOKPEAK); |
dudmuck | 18:9530d682fd9a | 4055 | if (fsk.RegOokPeak.bits.OokPeakThreshStep == 7) |
dudmuck | 18:9530d682fd9a | 4056 | fsk.RegOokPeak.bits.OokPeakThreshStep = 0; |
dudmuck | 18:9530d682fd9a | 4057 | else |
dudmuck | 18:9530d682fd9a | 4058 | fsk.RegOokPeak.bits.OokPeakThreshStep++; |
dudmuck | 18:9530d682fd9a | 4059 | |
dudmuck | 18:9530d682fd9a | 4060 | radio.write_reg(REG_FSK_OOKPEAK, fsk.RegOokPeak.octet); |
dudmuck | 18:9530d682fd9a | 4061 | switch (fsk.RegOokPeak.bits.OokPeakThreshStep) { |
dudmuck | 18:9530d682fd9a | 4062 | case 0: f = 0.5; break; |
dudmuck | 18:9530d682fd9a | 4063 | case 1: f = 1; break; |
dudmuck | 18:9530d682fd9a | 4064 | case 2: f = 1.5; break; |
dudmuck | 18:9530d682fd9a | 4065 | case 3: f = 2; break; |
dudmuck | 18:9530d682fd9a | 4066 | case 4: f = 3; break; |
dudmuck | 18:9530d682fd9a | 4067 | case 5: f = 4; break; |
dudmuck | 18:9530d682fd9a | 4068 | case 6: f = 5; break; |
dudmuck | 18:9530d682fd9a | 4069 | case 7: f = 6; break; |
dudmuck | 18:9530d682fd9a | 4070 | } |
dudmuck | 18:9530d682fd9a | 4071 | printf("OokPeakThreshStep:%.1fdB\r\n", f); |
dudmuck | 18:9530d682fd9a | 4072 | } |
dudmuck | 18:9530d682fd9a | 4073 | |
dudmuck | 18:9530d682fd9a | 4074 | void cmd_OokFixedThresh(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4075 | { |
dudmuck | 18:9530d682fd9a | 4076 | int i; |
dudmuck | 18:9530d682fd9a | 4077 | if (pcbuf[idx] >= '0' && pcbuf[idx] <= '9') { |
dudmuck | 18:9530d682fd9a | 4078 | sscanf(pcbuf+idx, "%d", &i); |
dudmuck | 18:9530d682fd9a | 4079 | radio.write_reg(REG_FSK_OOKFIX, i); |
dudmuck | 18:9530d682fd9a | 4080 | } |
dudmuck | 18:9530d682fd9a | 4081 | i = radio.read_reg(REG_FSK_OOKFIX); |
dudmuck | 18:9530d682fd9a | 4082 | printf("OokFixedThreshold:%d\r\n", i); |
dudmuck | 18:9530d682fd9a | 4083 | } |
dudmuck | 18:9530d682fd9a | 4084 | |
dudmuck | 18:9530d682fd9a | 4085 | void cmd_clkout(uint8_t idx) |
dudmuck | 18:9530d682fd9a | 4086 | { |
dudmuck | 18:9530d682fd9a | 4087 | RegOsc_t reg_osc; |
dudmuck | 18:9530d682fd9a | 4088 | reg_osc.octet = radio.read_reg(REG_FSK_OSC); |
dudmuck | 18:9530d682fd9a | 4089 | if (reg_osc.bits.ClkOut == 7) |
dudmuck | 18:9530d682fd9a | 4090 | reg_osc.bits.ClkOut = 0; |
dudmuck | 18:9530d682fd9a | 4091 | else |
dudmuck | 18:9530d682fd9a | 4092 | reg_osc.bits.ClkOut++; |
dudmuck | 18:9530d682fd9a | 4093 | |
dudmuck | 18:9530d682fd9a | 4094 | printf("ClkOut:%d\r\n", reg_osc.bits.ClkOut); |
dudmuck | 18:9530d682fd9a | 4095 | radio.write_reg(REG_FSK_OSC, reg_osc.octet); |
dudmuck | 18:9530d682fd9a | 4096 | } |
dudmuck | 21:b84a77dfb43c | 4097 | |
dudmuck | 21:b84a77dfb43c | 4098 | void cmd_ook_tx_test(uint8_t idx) |
dudmuck | 21:b84a77dfb43c | 4099 | { |
dudmuck | 21:b84a77dfb43c | 4100 | radio.set_frf_MHz(915.0); |
dudmuck | 21:b84a77dfb43c | 4101 | |
dudmuck | 21:b84a77dfb43c | 4102 | radio.RegOpMode.octet = radio.read_reg(REG_OPMODE); |
dudmuck | 21:b84a77dfb43c | 4103 | if (radio.RegOpMode.bits.LongRangeMode) |
dudmuck | 21:b84a77dfb43c | 4104 | cmd_toggle_modem(0); |
dudmuck | 21:b84a77dfb43c | 4105 | |
dudmuck | 21:b84a77dfb43c | 4106 | fsk.RegPktConfig1.octet = radio.read_reg(REG_FSK_PACKETCONFIG1); |
dudmuck | 21:b84a77dfb43c | 4107 | fsk.RegPktConfig1.bits.CrcOn = 0; |
dudmuck | 21:b84a77dfb43c | 4108 | radio.write_reg(REG_FSK_PACKETCONFIG1, fsk.RegPktConfig1.octet); |
dudmuck | 21:b84a77dfb43c | 4109 | |
dudmuck | 21:b84a77dfb43c | 4110 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 21:b84a77dfb43c | 4111 | radio.RegDioMapping2.bits.Dio5Mapping = 2; // Data |
dudmuck | 21:b84a77dfb43c | 4112 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 21:b84a77dfb43c | 4113 | |
dudmuck | 21:b84a77dfb43c | 4114 | radio.RegDioMapping1.octet = radio.read_reg(REG_DIOMAPPING1); |
dudmuck | 21:b84a77dfb43c | 4115 | radio.RegDioMapping1.bits.Dio3Mapping = 1; // TxReady |
dudmuck | 21:b84a77dfb43c | 4116 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 21:b84a77dfb43c | 4117 | |
dudmuck | 21:b84a77dfb43c | 4118 | //radio.write_reg(REG_FSK_SYNCCONFIG, 0); |
dudmuck | 21:b84a77dfb43c | 4119 | cmd_ook(0); |
dudmuck | 21:b84a77dfb43c | 4120 | radio.write_reg(REG_FSK_SYNCCONFIG, 0); |
dudmuck | 21:b84a77dfb43c | 4121 | /* radio.write_u16(REG_FSK_PREAMBLEMSB, 4); // preamble length |
dudmuck | 21:b84a77dfb43c | 4122 | |
dudmuck | 21:b84a77dfb43c | 4123 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 21:b84a77dfb43c | 4124 | fsk.RegSyncConfig.bits.SyncOn = 1; |
dudmuck | 21:b84a77dfb43c | 4125 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 21:b84a77dfb43c | 4126 | |
dudmuck | 21:b84a77dfb43c | 4127 | // 0123456 |
dudmuck | 21:b84a77dfb43c | 4128 | sprintf(pcbuf, "syncw a9 66 69 65"); |
dudmuck | 21:b84a77dfb43c | 4129 | cmd_fsk_syncword(6);*/ |
dudmuck | 21:b84a77dfb43c | 4130 | tx_ticker.attach(&callback_ook_tx_test, tx_ticker_rate); |
dudmuck | 21:b84a77dfb43c | 4131 | } |
dudmuck | 18:9530d682fd9a | 4132 | |
dudmuck | 18:9530d682fd9a | 4133 | void cmd_help(uint8_t args_at); |
dudmuck | 18:9530d682fd9a | 4134 | |
dudmuck | 18:9530d682fd9a | 4135 | typedef enum { |
dudmuck | 18:9530d682fd9a | 4136 | MODEM_BOTH, |
dudmuck | 18:9530d682fd9a | 4137 | MODEM_FSK, |
dudmuck | 18:9530d682fd9a | 4138 | MODEM_LORA |
dudmuck | 18:9530d682fd9a | 4139 | } modem_e; |
dudmuck | 18:9530d682fd9a | 4140 | |
dudmuck | 18:9530d682fd9a | 4141 | typedef struct { |
dudmuck | 18:9530d682fd9a | 4142 | modem_e modem; |
dudmuck | 18:9530d682fd9a | 4143 | const char* const cmd; |
dudmuck | 18:9530d682fd9a | 4144 | void (*handler)(uint8_t args_at); |
dudmuck | 18:9530d682fd9a | 4145 | const char* const arg_descr; |
dudmuck | 18:9530d682fd9a | 4146 | const char* const description; |
dudmuck | 18:9530d682fd9a | 4147 | } menu_item_t; |
dudmuck | 18:9530d682fd9a | 4148 | |
dudmuck | 18:9530d682fd9a | 4149 | const menu_item_t menu_items[] = |
dudmuck | 18:9530d682fd9a | 4150 | { /* after first character, command names must be [A-Za-z] */ |
dudmuck | 18:9530d682fd9a | 4151 | { MODEM_BOTH, "chat", cmd_chat, "","start keyboard chat"}, |
dudmuck | 18:9530d682fd9a | 4152 | { MODEM_BOTH, "rssi", cmd_read_current_rssi, "","(RX) read instantaneous RSSI"}, |
dudmuck | 21:b84a77dfb43c | 4153 | { MODEM_BOTH, "prssi", cmd_rssi_polling, "<%d>","dbm of rssi polling, 0 = off"}, |
dudmuck | 18:9530d682fd9a | 4154 | { MODEM_BOTH, "txpd", cmd_per_tx_delay, "<%d>","get/set PER tx delay (in milliseconds)"}, |
dudmuck | 18:9530d682fd9a | 4155 | { MODEM_BOTH, "pertx", cmd_pertx, "<%d pkt count>","start Eiger PER TX"}, |
dudmuck | 18:9530d682fd9a | 4156 | { MODEM_BOTH, "perrx", cmd_perrx, "","start Eiger PER RX"}, |
dudmuck | 18:9530d682fd9a | 4157 | { MODEM_BOTH, "pres", cmd_PreambleSize, "<%d>", "get/set PreambleSize"}, |
dudmuck | 18:9530d682fd9a | 4158 | { MODEM_BOTH, "pllbw", cmd_pllbw, "", "increment pllbw"}, |
dudmuck | 18:9530d682fd9a | 4159 | { MODEM_BOTH, "lnab", cmd_lna_boost, "", "(RX) increment LNA boost"}, |
dudmuck | 18:9530d682fd9a | 4160 | { MODEM_BOTH, "stby", cmd_mode_standby, "", "set chip mode to standby"}, |
dudmuck | 18:9530d682fd9a | 4161 | { MODEM_BOTH, "sleep", cmd_mode_sleep, "", "set chip mode to sleep"}, |
dudmuck | 18:9530d682fd9a | 4162 | { MODEM_BOTH, "fstx", cmd_mode_fstx, "", "set chip mode to fstx"}, |
dudmuck | 18:9530d682fd9a | 4163 | { MODEM_BOTH, "fsrx", cmd_mode_fsrx, "", "set chip mode to fsrx"}, |
dudmuck | 18:9530d682fd9a | 4164 | { MODEM_BOTH, "crcon", cmd_crcOn, "","toggle crcOn"}, |
dudmuck | 21:b84a77dfb43c | 4165 | { MODEM_BOTH, "ethcrc", cmd_crc32, "","toggle enable software crc32"}, |
dudmuck | 21:b84a77dfb43c | 4166 | { MODEM_BOTH, "spif", cmd_spifreq, "<MHz>","change SPI clock frequency"}, |
dudmuck | 18:9530d682fd9a | 4167 | { MODEM_BOTH, "payl", cmd_payload_length, "<%d>","get/set payload length"}, |
dudmuck | 18:9530d682fd9a | 4168 | { MODEM_BOTH, "bgr", cmd_bgr, "<%d>","(TX) get/set reference for TX DAC"}, |
dudmuck | 18:9530d682fd9a | 4169 | { MODEM_BOTH, "ocp", cmd_ocp, "<%d>","(TX) get/set milliamps current limit"}, |
dudmuck | 18:9530d682fd9a | 4170 | { MODEM_BOTH, "frf", cmd_frf, "<MHz>","get/set RF center frequency"}, |
dudmuck | 18:9530d682fd9a | 4171 | { MODEM_BOTH, "pas", cmd_paSelect, "","(TX) toggle RFO/PA_BOOST"}, |
dudmuck | 18:9530d682fd9a | 4172 | { MODEM_BOTH, "pid", cmd_per_id, "<%d>","get/set ID number in Eiger PER packet"}, |
dudmuck | 18:9530d682fd9a | 4173 | { MODEM_BOTH, "dio", cmd_show_dio, "","print dio mapping"}, |
dudmuck | 18:9530d682fd9a | 4174 | |
dudmuck | 18:9530d682fd9a | 4175 | { MODEM_FSK, "clkout", cmd_clkout, "","increment ClkOut divider"}, |
dudmuck | 18:9530d682fd9a | 4176 | { MODEM_FSK, "ookt", cmd_OokThreshType, "","(RX) increment OokThreshType"}, |
dudmuck | 18:9530d682fd9a | 4177 | { MODEM_FSK, "ooks", cmd_OokPeakTheshStep, "","(RX) increment OokPeakTheshStep"}, |
dudmuck | 18:9530d682fd9a | 4178 | { MODEM_FSK, "sqlch", cmd_OokFixedThresh, "<%d>","(RX) get/set OokFixedThresh"}, |
dudmuck | 18:9530d682fd9a | 4179 | { MODEM_FSK, "rssit", cmd_rssi_threshold, "<-dBm>","(RX) get/set rssi threshold"}, |
dudmuck | 18:9530d682fd9a | 4180 | { MODEM_FSK, "rssis", cmd_rssi_smoothing, "<%d>","(RX) get/set rssi smoothing"}, |
dudmuck | 18:9530d682fd9a | 4181 | { MODEM_FSK, "rssio", cmd_rssi_offset, "<%d>","(RX) get/set rssi offset"}, |
dudmuck | 18:9530d682fd9a | 4182 | { MODEM_FSK, "mods", cmd_mod_shaping, "", "(TX) increment modulation shaping"}, |
dudmuck | 18:9530d682fd9a | 4183 | { MODEM_FSK, "agcauto", cmd_fsk_agcauto, "", "(RX) toggle AgcAutoOn"}, |
dudmuck | 18:9530d682fd9a | 4184 | { MODEM_FSK, "afcauto", cmd_fsk_afcauto, "", "(RX) toggle AfcAutoOn"}, |
dudmuck | 18:9530d682fd9a | 4185 | { MODEM_FSK, "syncw", cmd_fsk_syncword, "<hex bytes>", "get/set syncword"}, |
dudmuck | 18:9530d682fd9a | 4186 | { MODEM_FSK, "syncon", cmd_fsk_syncOn, "", "toggle SyncOn (frame sync, SFD enable)"}, |
dudmuck | 18:9530d682fd9a | 4187 | { MODEM_FSK, "bitsync", cmd_fsk_bitsync, "", "toggle BitSyncOn (continuous mode only)"}, |
dudmuck | 18:9530d682fd9a | 4188 | { MODEM_FSK, "fifot", cmd_fsk_TxStartCondition, "", "(TX) toggle TxStartCondition"}, |
dudmuck | 18:9530d682fd9a | 4189 | { MODEM_FSK, "pktf", cmd_fsk_PacketFormat, "", "toggle PacketFormat fixed/variable length"}, |
dudmuck | 18:9530d682fd9a | 4190 | { MODEM_FSK, "poll", cmd_poll_irq_en, "", "toggle poll_irq_en"}, |
dudmuck | 18:9530d682fd9a | 4191 | { MODEM_FSK, "prep", cmd_fsk_PreamblePolarity, "", "toggle PreamblePolarity"}, |
dudmuck | 18:9530d682fd9a | 4192 | { MODEM_FSK, "datam", cmd_fsk_DataMode, "", "toggle DataMode (packet/continuous)"}, |
dudmuck | 18:9530d682fd9a | 4193 | { MODEM_FSK, "rxt", cmd_rx_trigger, "","(RX) increment RxTrigger"}, |
dudmuck | 18:9530d682fd9a | 4194 | { MODEM_FSK, "ook", cmd_ook, "","enter OOK mode"}, |
dudmuck | 21:b84a77dfb43c | 4195 | { MODEM_FSK, "otx", cmd_ook_tx_test, "","start ook tx repeat"}, |
dudmuck | 18:9530d682fd9a | 4196 | { MODEM_FSK, "fei", cmd_fsk_read_fei, "","(RX) read FEI"}, |
dudmuck | 18:9530d682fd9a | 4197 | { MODEM_FSK, "fdev", cmd_fsk_fdev, "<kHz>","(TX) get/set fdev"}, |
dudmuck | 18:9530d682fd9a | 4198 | { MODEM_FSK, "par", cmd_paRamp, "","(TX) increment paRamp"}, |
dudmuck | 18:9530d682fd9a | 4199 | { MODEM_FSK, "pde", cmd_fsk_PreambleDetectorOn, "","(RX) toggle PreambleDetectorOn"}, |
dudmuck | 18:9530d682fd9a | 4200 | { MODEM_FSK, "pds", cmd_fsk_PreambleDetectorSize, "<%d>","(RX) get/set PreambleDetectorSize"}, |
dudmuck | 18:9530d682fd9a | 4201 | { MODEM_FSK, "pdt", cmd_fsk_PreambleDetectorTol, "<%d>","(RX) get/set PreambleDetectorTol"}, |
dudmuck | 18:9530d682fd9a | 4202 | { MODEM_FSK, "thr", cmd_fsk_FifoThreshold, "<%d>","get/set FifoThreshold"}, |
dudmuck | 18:9530d682fd9a | 4203 | { MODEM_FSK, "dcf", cmd_fsk_dcfree, "","(RX) increment DcFree"}, |
dudmuck | 18:9530d682fd9a | 4204 | { MODEM_FSK, "br", cmd_fsk_bitrate, "<%f kbps>","get/set bitrate"}, |
dudmuck | 18:9530d682fd9a | 4205 | { MODEM_FSK, "ac", cmd_AfcClear, "","(RX) AfcClear"}, |
dudmuck | 18:9530d682fd9a | 4206 | { MODEM_FSK, "ar", cmd_fsk_AutoRestartRxMode, "","(RX) increment AutoRestartRxMode"}, |
dudmuck | 18:9530d682fd9a | 4207 | { MODEM_FSK, "alc", cmd_fsk_AfcAutoClearOn, "","(RX) toggle AfcAutoClearOn"}, |
dudmuck | 18:9530d682fd9a | 4208 | { MODEM_FSK, "mp", cmd_MapPreambleDetect, "","(RX) toggle MapPreambleDetect"}, |
dudmuck | 20:b11592c9ba5f | 4209 | { MODEM_FSK, "rrx", cmd_restart_rx, "","restart RX"}, |
dudmuck | 18:9530d682fd9a | 4210 | { MODEM_BOTH, "op", cmd_op, "<dBm>","(TX) get/set TX power"}, |
dudmuck | 21:b84a77dfb43c | 4211 | { MODEM_FSK, "bt", cmd_bt, "","get/set BT"}, |
dudmuck | 21:b84a77dfb43c | 4212 | { MODEM_FSK, "ltx", cmd_long_tx, "<%d>","long tx"}, |
dudmuck | 21:b84a77dfb43c | 4213 | { MODEM_FSK, "prrx", cmd_prrx, "","start RX with payloadReady isr"}, |
dudmuck | 21:b84a77dfb43c | 4214 | { MODEM_FSK, "ulrx", cmd_ulrx, "","start RX with unlimited length"}, |
dudmuck | 18:9530d682fd9a | 4215 | |
dudmuck | 18:9530d682fd9a | 4216 | #ifdef LORA_TX_TEST |
dudmuck | 18:9530d682fd9a | 4217 | { MODEM_LORA, "apl", cmd_lora_all_payload_lengths, "","(TXTEST) sweep payload lengths 0->255"}, |
dudmuck | 18:9530d682fd9a | 4218 | { MODEM_LORA, "csn", cmd_lora_sync_sweep, "[12]","(TXTEST) sweep ppg symbol"}, |
dudmuck | 18:9530d682fd9a | 4219 | { MODEM_LORA, "ss", cmd_lora_sync_lo_nibble, "","(TXTEST) ppg low nibble"}, |
dudmuck | 18:9530d682fd9a | 4220 | { MODEM_LORA, "cpl", lora_cycle_payload_length, "[%d stop]","(TXTEST) sweep payload length"}, |
dudmuck | 18:9530d682fd9a | 4221 | { MODEM_LORA, "ro", cmd_lora_data_ramp, "[%d bytes]","(TXTEST) sweep payload data"}, |
dudmuck | 18:9530d682fd9a | 4222 | { MODEM_LORA, "ccr", cmd_lora_cycle_codingrates, "","(TXTEST) cycle coding rates"}, |
dudmuck | 18:9530d682fd9a | 4223 | { MODEM_LORA, "fps", cmd_lora_fixed_payload_symbol, "[symbol_num n_bits]","(TXTEST) sweep symbol, n_bits=bits per symbol set (sf8=24, sf9=28, etc)"}, |
dudmuck | 18:9530d682fd9a | 4224 | { MODEM_LORA, "fpo", cmd_fixed_payload_offset, "<nbytes>","(TXTEST) padding offset for fp tests"}, |
dudmuck | 18:9530d682fd9a | 4225 | { MODEM_LORA, "fp", cmd_lora_fixed_payload, "[bytes]","(TXTEST) fixed payload"}, |
dudmuck | 18:9530d682fd9a | 4226 | { MODEM_LORA, "tab", cmd_lora_toggle_all_bits, "[byte length]","(TXTEST) toggle all bits"}, |
dudmuck | 18:9530d682fd9a | 4227 | { MODEM_LORA, "tcrc", cmd_lora_toggle_crcOn, "","(TXTEST) toggle crcOn"}, |
dudmuck | 18:9530d682fd9a | 4228 | { MODEM_LORA, "thm", cmd_lora_toggle_header_mode, "","(TXTEST) toggle explicit/implicit"}, |
dudmuck | 18:9530d682fd9a | 4229 | #endif /* LORA_TX_TEST */ |
dudmuck | 18:9530d682fd9a | 4230 | |
dudmuck | 21:b84a77dfb43c | 4231 | { MODEM_BOTH, "ttr", cmd_tx_ticker_rate, "<%f seconds>","(TXTEST) get/set tx_ticker rate"}, |
dudmuck | 18:9530d682fd9a | 4232 | { MODEM_LORA, "cadper", cmd_cadper, "","Eiger PER RX using CAD" }, |
dudmuck | 18:9530d682fd9a | 4233 | { MODEM_LORA, "cad", cmd_cad, "<%d num tries>","(RX) run channel activity detection" }, |
dudmuck | 18:9530d682fd9a | 4234 | { MODEM_LORA, "iqinv", cmd_lora_rx_invert, "","(RX) toggle RX IQ invert" }, |
dudmuck | 18:9530d682fd9a | 4235 | { MODEM_LORA, "cin", cmd_lora_tx_invert, "","(TX) toggle TX IQ invert" }, |
dudmuck | 18:9530d682fd9a | 4236 | { MODEM_LORA, "lhp", cmd_hop_period, "<%d>","(RX) get/set hop period"}, |
dudmuck | 18:9530d682fd9a | 4237 | { MODEM_LORA, "sync", cmd_lora_ppg, "<%x>","get/set sync (post-preamble gap)"}, |
dudmuck | 18:9530d682fd9a | 4238 | { MODEM_LORA, "cr", cmd_codingRate, "<1-4>","get/set codingRate"}, |
dudmuck | 18:9530d682fd9a | 4239 | { MODEM_LORA, "lhm", cmd_lora_header_mode, "","toggle explicit/implicit"}, |
dudmuck | 18:9530d682fd9a | 4240 | { MODEM_LORA, "vh", cmd_lora_poll_validHeader, "","toggle polling of validHeader"}, |
dudmuck | 18:9530d682fd9a | 4241 | { MODEM_LORA, "sf", cmd_lora_sf, "<%d>","get/set spreadingFactor"}, |
dudmuck | 18:9530d682fd9a | 4242 | { MODEM_LORA, "ldr", cmd_LowDataRateOptimize, "","toggle LowDataRateOptimize"}, |
dudmuck | 18:9530d682fd9a | 4243 | { MODEM_LORA, "txc", cmd_lora_continuous_tx, "","(TX) toggle TxContinuousMode"}, |
dudmuck | 18:9530d682fd9a | 4244 | { MODEM_BOTH, "tx", cmd_tx, "<%d>","transmit packet. optional payload length"}, |
dudmuck | 18:9530d682fd9a | 4245 | { MODEM_BOTH, "bw", cmd_bandwidth, "<kHz>","get/set bandwith"}, |
dudmuck | 18:9530d682fd9a | 4246 | { MODEM_LORA, "rxt", cmd_rx_timeout, "<%d>","(RX) get/set SymbTimeout"}, |
dudmuck | 18:9530d682fd9a | 4247 | { MODEM_LORA, "rxs", cmd_rx_single, "","start RX_SINGLE"}, |
dudmuck | 18:9530d682fd9a | 4248 | { MODEM_BOTH, "rx", cmd_rx, "","start RX"}, |
dudmuck | 18:9530d682fd9a | 4249 | |
dudmuck | 18:9530d682fd9a | 4250 | { MODEM_BOTH, "h", cmd_hw_reset, "","hardware reset"}, |
dudmuck | 18:9530d682fd9a | 4251 | { MODEM_BOTH, "i", cmd_init, "","initialize radio driver"}, |
dudmuck | 18:9530d682fd9a | 4252 | { MODEM_BOTH, "R", cmd_read_all_regs, "","read all radio registers"}, |
dudmuck | 18:9530d682fd9a | 4253 | { MODEM_BOTH, "r", cmd_radio_reg_read, "[%x]","read single radio register"}, |
dudmuck | 18:9530d682fd9a | 4254 | { MODEM_BOTH, "w", cmd_radio_reg_write, "[%x %x]","write single radio register"}, |
dudmuck | 18:9530d682fd9a | 4255 | |
dudmuck | 18:9530d682fd9a | 4256 | { MODEM_BOTH, "L", cmd_toggle_modem, "","toggle between LoRa / FSK"}, |
dudmuck | 18:9530d682fd9a | 4257 | { MODEM_FSK, "E", cmd_empty_fifo, "","empty out FIFO"}, |
dudmuck | 18:9530d682fd9a | 4258 | { MODEM_FSK, "c", cmd_fsk_test_case, "<%d>","get/set test cases"}, |
dudmuck | 18:9530d682fd9a | 4259 | { MODEM_BOTH, "d", cmd_set_dio, "<%d pin num>","increment dio mapping"}, |
dudmuck | 18:9530d682fd9a | 4260 | { MODEM_BOTH, ".", cmd_print_status, "","print status"}, |
dudmuck | 18:9530d682fd9a | 4261 | { MODEM_BOTH, "?", cmd_help, "","this list of commands"}, |
dudmuck | 19:be8a8b0e7320 | 4262 | { MODEM_BOTH, NULL, NULL, NULL, NULL } |
dudmuck | 18:9530d682fd9a | 4263 | }; |
dudmuck | 18:9530d682fd9a | 4264 | |
dudmuck | 18:9530d682fd9a | 4265 | void cmd_help(uint8_t args_at) |
dudmuck | 18:9530d682fd9a | 4266 | { |
dudmuck | 18:9530d682fd9a | 4267 | int i; |
dudmuck | 18:9530d682fd9a | 4268 | |
dudmuck | 18:9530d682fd9a | 4269 | for (i = 0; menu_items[i].cmd != NULL ; i++) { |
dudmuck | 18:9530d682fd9a | 4270 | if (menu_items[i].modem == MODEM_BOTH) |
dudmuck | 18:9530d682fd9a | 4271 | printf("%s%s\t%s\r\n", menu_items[i].cmd, menu_items[i].arg_descr, menu_items[i].description); |
dudmuck | 18:9530d682fd9a | 4272 | } |
dudmuck | 18:9530d682fd9a | 4273 | |
dudmuck | 18:9530d682fd9a | 4274 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 4275 | for (i = 0; menu_items[i].cmd != NULL ; i++) { |
dudmuck | 18:9530d682fd9a | 4276 | if (menu_items[i].modem == MODEM_LORA) |
dudmuck | 18:9530d682fd9a | 4277 | printf("%s%s\t(LoRa) %s\r\n", menu_items[i].cmd, menu_items[i].arg_descr, menu_items[i].description); |
dudmuck | 18:9530d682fd9a | 4278 | } |
dudmuck | 18:9530d682fd9a | 4279 | } else { |
dudmuck | 18:9530d682fd9a | 4280 | for (i = 0; menu_items[i].cmd != NULL ; i++) { |
dudmuck | 18:9530d682fd9a | 4281 | if (menu_items[i].modem == MODEM_FSK) |
dudmuck | 18:9530d682fd9a | 4282 | printf("%s%s\t(FSK) %s\r\n", menu_items[i].cmd, menu_items[i].arg_descr, menu_items[i].description); |
dudmuck | 18:9530d682fd9a | 4283 | } |
dudmuck | 18:9530d682fd9a | 4284 | } |
dudmuck | 10:d9bb2ce57f05 | 4285 | } |
dudmuck | 10:d9bb2ce57f05 | 4286 | |
dudmuck | 0:be215de91a68 | 4287 | void |
dudmuck | 0:be215de91a68 | 4288 | console() |
dudmuck | 0:be215de91a68 | 4289 | { |
dudmuck | 18:9530d682fd9a | 4290 | int i; |
dudmuck | 18:9530d682fd9a | 4291 | uint8_t user_cmd_len; |
dudmuck | 5:360069ec9953 | 4292 | |
dudmuck | 18:9530d682fd9a | 4293 | if (poll_irq_en) |
dudmuck | 18:9530d682fd9a | 4294 | poll_service_radio(); |
dudmuck | 18:9530d682fd9a | 4295 | else |
dudmuck | 18:9530d682fd9a | 4296 | service_radio(); |
dudmuck | 0:be215de91a68 | 4297 | |
dudmuck | 5:360069ec9953 | 4298 | if (pcbuf_len < 0) { |
dudmuck | 0:be215de91a68 | 4299 | printf("abort\r\n"); |
dudmuck | 21:b84a77dfb43c | 4300 | rx_payloadReady_int_en = false; |
dudmuck | 18:9530d682fd9a | 4301 | cadper_enable = false; |
dudmuck | 8:227605e4a760 | 4302 | per_en = false; |
dudmuck | 5:360069ec9953 | 4303 | pcbuf_len = 0; |
dudmuck | 15:c69b942685ea | 4304 | if ((radio.RegOpMode.bits.Mode != RF_OPMODE_SLEEP) && (radio.RegOpMode.bits.Mode != RF_OPMODE_STANDBY)) { |
dudmuck | 15:c69b942685ea | 4305 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 15:c69b942685ea | 4306 | } |
dudmuck | 18:9530d682fd9a | 4307 | on_txdone_state = ON_TXDONE_STATE_NONE; |
dudmuck | 18:9530d682fd9a | 4308 | tx_ticker.detach(); |
dudmuck | 0:be215de91a68 | 4309 | return; |
dudmuck | 0:be215de91a68 | 4310 | } |
dudmuck | 5:360069ec9953 | 4311 | if (pcbuf_len == 0) |
dudmuck | 5:360069ec9953 | 4312 | return; |
dudmuck | 18:9530d682fd9a | 4313 | |
dudmuck | 0:be215de91a68 | 4314 | printf("\r\n"); |
dudmuck | 18:9530d682fd9a | 4315 | |
dudmuck | 18:9530d682fd9a | 4316 | /* get end of user-entered command */ |
dudmuck | 18:9530d682fd9a | 4317 | user_cmd_len = 1; // first character can be any character |
dudmuck | 18:9530d682fd9a | 4318 | for (i = 1; i <= pcbuf_len; i++) { |
dudmuck | 18:9530d682fd9a | 4319 | if (pcbuf[i] < 'A' || (pcbuf[i] > 'Z' && pcbuf[i] < 'a') || pcbuf[i] > 'z') { |
dudmuck | 18:9530d682fd9a | 4320 | user_cmd_len = i; |
dudmuck | 18:9530d682fd9a | 4321 | break; |
dudmuck | 7:c3c54f222ced | 4322 | } |
dudmuck | 0:be215de91a68 | 4323 | } |
dudmuck | 18:9530d682fd9a | 4324 | |
dudmuck | 18:9530d682fd9a | 4325 | for (i = 0; menu_items[i].cmd != NULL ; i++) { |
dudmuck | 18:9530d682fd9a | 4326 | int mi_len = strlen(menu_items[i].cmd); |
dudmuck | 18:9530d682fd9a | 4327 | if (radio.RegOpMode.bits.LongRangeMode) { |
dudmuck | 18:9530d682fd9a | 4328 | if (menu_items[i].modem == MODEM_FSK) |
dudmuck | 18:9530d682fd9a | 4329 | continue; // FSK commands not used in LoRa |
dudmuck | 18:9530d682fd9a | 4330 | } else { |
dudmuck | 18:9530d682fd9a | 4331 | if (menu_items[i].modem == MODEM_LORA) |
dudmuck | 18:9530d682fd9a | 4332 | continue; // LoRa commands not used in FSK |
dudmuck | 18:9530d682fd9a | 4333 | } |
dudmuck | 18:9530d682fd9a | 4334 | |
dudmuck | 18:9530d682fd9a | 4335 | if (menu_items[i].handler && user_cmd_len == mi_len && (strncmp(pcbuf, menu_items[i].cmd, mi_len) == 0)) { |
dudmuck | 18:9530d682fd9a | 4336 | while (pcbuf[mi_len] == ' ') // skip past spaces |
dudmuck | 18:9530d682fd9a | 4337 | mi_len++; |
dudmuck | 18:9530d682fd9a | 4338 | menu_items[i].handler(mi_len); |
dudmuck | 18:9530d682fd9a | 4339 | break; |
dudmuck | 18:9530d682fd9a | 4340 | } |
dudmuck | 18:9530d682fd9a | 4341 | } |
dudmuck | 18:9530d682fd9a | 4342 | |
dudmuck | 5:360069ec9953 | 4343 | pcbuf_len = 0; |
dudmuck | 0:be215de91a68 | 4344 | printf("> "); |
dudmuck | 18:9530d682fd9a | 4345 | fflush(stdout); |
dudmuck | 0:be215de91a68 | 4346 | } |
dudmuck | 0:be215de91a68 | 4347 | |
dudmuck | 5:360069ec9953 | 4348 | void rx_callback() |
dudmuck | 5:360069ec9953 | 4349 | { |
dudmuck | 5:360069ec9953 | 4350 | static uint8_t pcbuf_idx = 0; |
dudmuck | 5:360069ec9953 | 4351 | static uint8_t prev_len = 0;; |
dudmuck | 5:360069ec9953 | 4352 | char c = pc.getc(); |
dudmuck | 18:9530d682fd9a | 4353 | /*if (kermit.uart_rx_enabled) { |
dudmuck | 18:9530d682fd9a | 4354 | kermit.rx_callback(c); |
dudmuck | 18:9530d682fd9a | 4355 | } else*/ { |
dudmuck | 18:9530d682fd9a | 4356 | if (c == 8) { |
dudmuck | 18:9530d682fd9a | 4357 | if (pcbuf_idx > 0) { |
dudmuck | 18:9530d682fd9a | 4358 | pc.putc(8); |
dudmuck | 18:9530d682fd9a | 4359 | pc.putc(' '); |
dudmuck | 18:9530d682fd9a | 4360 | pc.putc(8); |
dudmuck | 18:9530d682fd9a | 4361 | pcbuf_idx--; |
dudmuck | 18:9530d682fd9a | 4362 | } |
dudmuck | 18:9530d682fd9a | 4363 | } else if (c == 3) { // ctrl-C |
dudmuck | 18:9530d682fd9a | 4364 | pcbuf_len = -1; |
dudmuck | 18:9530d682fd9a | 4365 | } else if (c == '\r') { |
dudmuck | 18:9530d682fd9a | 4366 | if (pcbuf_idx == 0) { |
dudmuck | 18:9530d682fd9a | 4367 | pcbuf_len = prev_len; |
dudmuck | 18:9530d682fd9a | 4368 | } else { |
dudmuck | 18:9530d682fd9a | 4369 | pcbuf[pcbuf_idx] = 0; // null terminate |
dudmuck | 18:9530d682fd9a | 4370 | prev_len = pcbuf_idx; |
dudmuck | 18:9530d682fd9a | 4371 | pcbuf_idx = 0; |
dudmuck | 18:9530d682fd9a | 4372 | pcbuf_len = prev_len; |
dudmuck | 18:9530d682fd9a | 4373 | } |
dudmuck | 18:9530d682fd9a | 4374 | }/* else if (c == SOH) { |
dudmuck | 18:9530d682fd9a | 4375 | kermit.uart_rx_enable(); |
dudmuck | 18:9530d682fd9a | 4376 | }*/ else if (pcbuf_idx < sizeof(pcbuf)) { |
dudmuck | 18:9530d682fd9a | 4377 | pcbuf[pcbuf_idx++] = c; |
dudmuck | 18:9530d682fd9a | 4378 | pc.putc(c); |
dudmuck | 5:360069ec9953 | 4379 | } |
dudmuck | 5:360069ec9953 | 4380 | } |
dudmuck | 5:360069ec9953 | 4381 | } |
dudmuck | 5:360069ec9953 | 4382 | |
dudmuck | 0:be215de91a68 | 4383 | int main() |
dudmuck | 5:360069ec9953 | 4384 | { |
dudmuck | 5:360069ec9953 | 4385 | #if defined(TARGET_NUCLEO_L152RE) && defined(USE_DEBUGGER) |
dudmuck | 5:360069ec9953 | 4386 | DBGMCU_Config(DBGMCU_SLEEP, ENABLE); |
dudmuck | 5:360069ec9953 | 4387 | DBGMCU_Config(DBGMCU_STOP, ENABLE); |
dudmuck | 5:360069ec9953 | 4388 | DBGMCU_Config(DBGMCU_STANDBY, ENABLE); |
dudmuck | 5:360069ec9953 | 4389 | #endif |
dudmuck | 0:be215de91a68 | 4390 | |
dudmuck | 0:be215de91a68 | 4391 | pc.baud(57600); |
dudmuck | 6:fe16f96ee335 | 4392 | printf("\r\nmain()\r\n"); |
dudmuck | 6:fe16f96ee335 | 4393 | |
dudmuck | 5:360069ec9953 | 4394 | pc.attach(rx_callback); |
dudmuck | 0:be215de91a68 | 4395 | |
dudmuck | 21:b84a77dfb43c | 4396 | make_crc_table(); |
dudmuck | 21:b84a77dfb43c | 4397 | |
dudmuck | 15:c69b942685ea | 4398 | #ifndef TARGET_MTS_MDOT_F411RE |
dudmuck | 15:c69b942685ea | 4399 | rfsw.input(); |
dudmuck | 15:c69b942685ea | 4400 | if (rfsw.read()) { |
dudmuck | 15:c69b942685ea | 4401 | shield_type = SHIELD_TYPE_LAS; |
dudmuck | 15:c69b942685ea | 4402 | printf("LAS\r\n"); |
dudmuck | 15:c69b942685ea | 4403 | } else { |
dudmuck | 15:c69b942685ea | 4404 | shield_type = SHIELD_TYPE_MAS; |
dudmuck | 15:c69b942685ea | 4405 | printf("MAS\r\n"); |
dudmuck | 15:c69b942685ea | 4406 | } |
dudmuck | 15:c69b942685ea | 4407 | |
dudmuck | 15:c69b942685ea | 4408 | rfsw.output(); |
dudmuck | 15:c69b942685ea | 4409 | #endif /* !TARGET_MTS_MDOT_F411RE */ |
dudmuck | 6:fe16f96ee335 | 4410 | radio.rf_switch.attach(rfsw_callback); |
dudmuck | 10:d9bb2ce57f05 | 4411 | |
dudmuck | 13:c73caaee93a5 | 4412 | #ifdef FSK_PER |
dudmuck | 13:c73caaee93a5 | 4413 | fsk.enable(false); |
dudmuck | 13:c73caaee93a5 | 4414 | fsk.RegSyncConfig.octet = radio.read_reg(REG_FSK_SYNCCONFIG); |
dudmuck | 13:c73caaee93a5 | 4415 | fsk.RegSyncConfig.bits.SyncSize = 2; |
dudmuck | 13:c73caaee93a5 | 4416 | radio.write_reg(REG_FSK_SYNCCONFIG, fsk.RegSyncConfig.octet); |
dudmuck | 13:c73caaee93a5 | 4417 | radio.write_reg(REG_FSK_SYNCVALUE3, 0x90); |
dudmuck | 13:c73caaee93a5 | 4418 | radio.write_reg(REG_FSK_SYNCVALUE2, 0x4e); |
dudmuck | 13:c73caaee93a5 | 4419 | radio.write_reg(REG_FSK_SYNCVALUE1, 0x63); |
dudmuck | 13:c73caaee93a5 | 4420 | |
dudmuck | 13:c73caaee93a5 | 4421 | fsk.RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 16:b9d36c60f2d3 | 4422 | fsk.RegPreambleDetect.bits.PreambleDetectorSize = 1; |
dudmuck | 16:b9d36c60f2d3 | 4423 | fsk.RegPreambleDetect.bits.PreambleDetectorTol = 10; |
dudmuck | 16:b9d36c60f2d3 | 4424 | radio.write_reg(REG_FSK_PREAMBLEDETECT, fsk.RegPreambleDetect.octet); |
dudmuck | 13:c73caaee93a5 | 4425 | |
dudmuck | 13:c73caaee93a5 | 4426 | fsk.RegRxConfig.octet = radio.read_reg(REG_FSK_RXCONFIG); |
dudmuck | 13:c73caaee93a5 | 4427 | fsk.RegRxConfig.bits.AfcAutoOn = 1; |
dudmuck | 16:b9d36c60f2d3 | 4428 | fsk.RegRxConfig.bits.AgcAutoOn = 1; |
dudmuck | 16:b9d36c60f2d3 | 4429 | fsk.RegRxConfig.bits.RxTrigger = 7; |
dudmuck | 13:c73caaee93a5 | 4430 | radio.write_reg(REG_FSK_RXCONFIG, fsk.RegRxConfig.octet); |
dudmuck | 13:c73caaee93a5 | 4431 | |
dudmuck | 13:c73caaee93a5 | 4432 | radio.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 13:c73caaee93a5 | 4433 | fsk.set_rx_dcc_bw_hz(41666, 1); // afcbw |
dudmuck | 13:c73caaee93a5 | 4434 | fsk.set_rx_dcc_bw_hz(20833, 0); // rxbw |
dudmuck | 13:c73caaee93a5 | 4435 | |
dudmuck | 13:c73caaee93a5 | 4436 | fsk.set_tx_fdev_hz(10000); |
dudmuck | 13:c73caaee93a5 | 4437 | |
dudmuck | 13:c73caaee93a5 | 4438 | radio.write_u16(REG_FSK_PREAMBLEMSB, 8); |
dudmuck | 13:c73caaee93a5 | 4439 | |
dudmuck | 13:c73caaee93a5 | 4440 | fsk.RegPktConfig2.bits.PayloadLength = 64; |
dudmuck | 13:c73caaee93a5 | 4441 | radio.write_u16(REG_FSK_PACKETCONFIG2, fsk.RegPktConfig2.word); |
dudmuck | 13:c73caaee93a5 | 4442 | |
dudmuck | 13:c73caaee93a5 | 4443 | radio.RegDioMapping2.octet = radio.read_reg(REG_DIOMAPPING2); |
dudmuck | 13:c73caaee93a5 | 4444 | radio.RegDioMapping2.bits.Dio5Mapping = 2; // data output to observation |
dudmuck | 14:c57ea544dc18 | 4445 | radio.RegDioMapping2.bits.Dio4Mapping = 3; // output preamble detect indication |
dudmuck | 14:c57ea544dc18 | 4446 | radio.RegDioMapping2.bits.MapPreambleDetect = 1; |
dudmuck | 13:c73caaee93a5 | 4447 | radio.write_reg(REG_DIOMAPPING2, radio.RegDioMapping2.octet); |
dudmuck | 16:b9d36c60f2d3 | 4448 | |
dudmuck | 16:b9d36c60f2d3 | 4449 | RegPreambleDetect.bits.PreambleDetectorOn = 1; |
dudmuck | 16:b9d36c60f2d3 | 4450 | RegPreambleDetect.bits.PreambleDetectorSize = 1; |
dudmuck | 16:b9d36c60f2d3 | 4451 | RegPreambleDetect.bits.PreambleDetectorTol = 10; |
dudmuck | 16:b9d36c60f2d3 | 4452 | write_reg(REG_FSK_PREAMBLEDETECT, RegPreambleDetect.octet); |
dudmuck | 16:b9d36c60f2d3 | 4453 | |
dudmuck | 13:c73caaee93a5 | 4454 | #endif /* FSK_PER */ |
dudmuck | 10:d9bb2ce57f05 | 4455 | |
dudmuck | 10:d9bb2ce57f05 | 4456 | #ifdef START_EIGER_TX |
dudmuck | 14:c57ea544dc18 | 4457 | uint8_t addr; |
dudmuck | 10:d9bb2ce57f05 | 4458 | radio.set_frf_MHz(915.0); |
dudmuck | 11:81ff5bcafd97 | 4459 | |
dudmuck | 11:81ff5bcafd97 | 4460 | radio.RegOcp.octet = radio.read_reg(REG_OCP); |
dudmuck | 11:81ff5bcafd97 | 4461 | radio.RegOcp.bits.OcpTrim = 20; |
dudmuck | 11:81ff5bcafd97 | 4462 | radio.write_reg(REG_OCP, radio.RegOcp.octet); |
dudmuck | 11:81ff5bcafd97 | 4463 | |
dudmuck | 11:81ff5bcafd97 | 4464 | RegPdsTrim1_t pds_trim; |
dudmuck | 14:c57ea544dc18 | 4465 | if (radio.type == SX1276) |
dudmuck | 14:c57ea544dc18 | 4466 | addr = REG_PDSTRIM1_SX1276; |
dudmuck | 14:c57ea544dc18 | 4467 | else |
dudmuck | 14:c57ea544dc18 | 4468 | addr = REG_PDSTRIM1_SX1272; |
dudmuck | 14:c57ea544dc18 | 4469 | |
dudmuck | 14:c57ea544dc18 | 4470 | pds_trim.octet = radio.read_reg(addr); |
dudmuck | 11:81ff5bcafd97 | 4471 | pds_trim.bits.prog_txdac = 7; |
dudmuck | 14:c57ea544dc18 | 4472 | radio.write_reg(addr, pds_trim.octet); |
dudmuck | 11:81ff5bcafd97 | 4473 | |
dudmuck | 13:c73caaee93a5 | 4474 | #ifndef FSK_PER |
dudmuck | 13:c73caaee93a5 | 4475 | lora.enable(); |
dudmuck | 12:beb0387c1b4c | 4476 | lora.setSf(10); |
dudmuck | 10:d9bb2ce57f05 | 4477 | if (radio.type == SX1276) |
dudmuck | 10:d9bb2ce57f05 | 4478 | lora.setBw(7); // 7 == 125khz |
dudmuck | 13:c73caaee93a5 | 4479 | #endif |
dudmuck | 10:d9bb2ce57f05 | 4480 | |
dudmuck | 10:d9bb2ce57f05 | 4481 | toggle_per_en(); |
dudmuck | 10:d9bb2ce57f05 | 4482 | PacketTxCnt = 0; |
dudmuck | 10:d9bb2ce57f05 | 4483 | per_timeout.attach(&per_cb, per_tx_delay); |
dudmuck | 11:81ff5bcafd97 | 4484 | #endif /* START_EIGER_TX */ |
dudmuck | 10:d9bb2ce57f05 | 4485 | |
dudmuck | 10:d9bb2ce57f05 | 4486 | #ifdef START_EIGER_RX |
dudmuck | 13:c73caaee93a5 | 4487 | |
dudmuck | 10:d9bb2ce57f05 | 4488 | radio.set_frf_MHz(915.0); |
dudmuck | 11:81ff5bcafd97 | 4489 | radio.RegPaConfig.bits.PaSelect = 1; // 0: use RFO for sx1276 shield, 1==PA_BOOST |
dudmuck | 10:d9bb2ce57f05 | 4490 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 10:d9bb2ce57f05 | 4491 | |
dudmuck | 10:d9bb2ce57f05 | 4492 | toggle_per_en(); |
dudmuck | 10:d9bb2ce57f05 | 4493 | PacketNormalCnt = 0; |
dudmuck | 20:b11592c9ba5f | 4494 | PacketRxSequencePrev = 0; |
dudmuck | 10:d9bb2ce57f05 | 4495 | PacketPerKoCnt = 0; |
dudmuck | 13:c73caaee93a5 | 4496 | PacketPerOkCnt = 0; |
dudmuck | 13:c73caaee93a5 | 4497 | |
dudmuck | 13:c73caaee93a5 | 4498 | #ifndef FSK_PER |
dudmuck | 13:c73caaee93a5 | 4499 | lora.enable(); |
dudmuck | 13:c73caaee93a5 | 4500 | lora.setSf(10); |
dudmuck | 13:c73caaee93a5 | 4501 | if (radio.type == SX1276) |
dudmuck | 13:c73caaee93a5 | 4502 | lora.setBw(7); // 7 == 125khz |
dudmuck | 10:d9bb2ce57f05 | 4503 | lora.start_rx(); |
dudmuck | 13:c73caaee93a5 | 4504 | #else |
dudmuck | 13:c73caaee93a5 | 4505 | fsk.start_rx(); |
dudmuck | 14:c57ea544dc18 | 4506 | radio.RegDioMapping1.bits.Dio2Mapping = 3; // dio2 to syncadrs |
dudmuck | 14:c57ea544dc18 | 4507 | radio.write_reg(REG_DIOMAPPING1, radio.RegDioMapping1.octet); |
dudmuck | 15:c69b942685ea | 4508 | |
dudmuck | 15:c69b942685ea | 4509 | if (radio.HF) { |
dudmuck | 15:c69b942685ea | 4510 | fsk.RegRssiConfig.octet = radio.read_reg(REG_FSK_RSSICONFIG); |
dudmuck | 15:c69b942685ea | 4511 | fsk.RegRssiConfig.bits.RssiOffset = FSK_RSSI_OFFSET; |
dudmuck | 15:c69b942685ea | 4512 | fsk.RegRssiConfig.bits.RssiSmoothing = FSK_RSSI_SMOOTHING; |
dudmuck | 15:c69b942685ea | 4513 | radio.write_reg(REG_FSK_RSSICONFIG, fsk.RegRssiConfig.octet); |
dudmuck | 15:c69b942685ea | 4514 | } |
dudmuck | 10:d9bb2ce57f05 | 4515 | #endif |
dudmuck | 13:c73caaee93a5 | 4516 | |
dudmuck | 15:c69b942685ea | 4517 | if (radio.HF) { |
dudmuck | 15:c69b942685ea | 4518 | radio.RegLna.bits.LnaBoostHF = 3; |
dudmuck | 15:c69b942685ea | 4519 | radio.write_reg(REG_LNA, radio.RegLna.octet); |
dudmuck | 15:c69b942685ea | 4520 | } |
dudmuck | 15:c69b942685ea | 4521 | |
dudmuck | 13:c73caaee93a5 | 4522 | #endif /* START_EIGER_RX */ |
dudmuck | 15:c69b942685ea | 4523 | |
dudmuck | 15:c69b942685ea | 4524 | (void)radio.get_frf_MHz(); |
dudmuck | 15:c69b942685ea | 4525 | radio.RegPaConfig.octet = radio.read_reg(REG_PACONFIG); |
dudmuck | 20:b11592c9ba5f | 4526 | #ifdef TARGET_MTS_MDOT_F411RE |
dudmuck | 20:b11592c9ba5f | 4527 | radio.RegPaConfig.bits.PaSelect = 1; // mDot uses PA_BOOST |
dudmuck | 20:b11592c9ba5f | 4528 | #else |
dudmuck | 15:c69b942685ea | 4529 | if (shield_type == SHIELD_TYPE_LAS) { |
dudmuck | 15:c69b942685ea | 4530 | // LAS HF=PA_BOOST LF=RFO |
dudmuck | 15:c69b942685ea | 4531 | if (radio.HF) |
dudmuck | 15:c69b942685ea | 4532 | radio.RegPaConfig.bits.PaSelect = 1; |
dudmuck | 15:c69b942685ea | 4533 | else |
dudmuck | 15:c69b942685ea | 4534 | radio.RegPaConfig.bits.PaSelect = 0; |
dudmuck | 15:c69b942685ea | 4535 | } else if (shield_type == SHIELD_TYPE_MAS) { |
dudmuck | 15:c69b942685ea | 4536 | // MAS HF=RFO LF=RFO |
dudmuck | 15:c69b942685ea | 4537 | radio.RegPaConfig.bits.PaSelect = 0; |
dudmuck | 20:b11592c9ba5f | 4538 | } |
dudmuck | 20:b11592c9ba5f | 4539 | #endif |
dudmuck | 15:c69b942685ea | 4540 | radio.RegPaConfig.bits.OutputPower = 15; |
dudmuck | 15:c69b942685ea | 4541 | radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); |
dudmuck | 6:fe16f96ee335 | 4542 | |
dudmuck | 21:b84a77dfb43c | 4543 | #ifdef START_OOK_TX_TEST |
dudmuck | 21:b84a77dfb43c | 4544 | cmd_ook_tx_test(0); |
dudmuck | 21:b84a77dfb43c | 4545 | #endif /* START_OOK_TX_TEST */ |
dudmuck | 0:be215de91a68 | 4546 | |
dudmuck | 0:be215de91a68 | 4547 | while(1) { |
dudmuck | 0:be215de91a68 | 4548 | switch (app) { |
dudmuck | 0:be215de91a68 | 4549 | case APP_NONE: |
dudmuck | 0:be215de91a68 | 4550 | console(); |
dudmuck | 0:be215de91a68 | 4551 | break; |
dudmuck | 0:be215de91a68 | 4552 | case APP_CHAT: |
dudmuck | 0:be215de91a68 | 4553 | console_chat(); |
dudmuck | 0:be215de91a68 | 4554 | break; |
dudmuck | 0:be215de91a68 | 4555 | } // ...switch (app) |
dudmuck | 5:360069ec9953 | 4556 | |
dudmuck | 5:360069ec9953 | 4557 | #if TARGET_NUCLEO_L152RE |
dudmuck | 5:360069ec9953 | 4558 | //sleep(); |
dudmuck | 5:360069ec9953 | 4559 | #endif |
dudmuck | 0:be215de91a68 | 4560 | } // ...while(1) |
dudmuck | 0:be215de91a68 | 4561 | } |
dudmuck | 0:be215de91a68 | 4562 |