sx127x_fsk.h

00001 #include "sx12xx.h"
00002 
00003 #define REG_FSK_BITRATEMSB                            0x02
00004 #define REG_FSK_BITRATELSB                            0x03
00005 #define REG_FSK_FDEVMSB                              0x04 
00006 #define REG_FSK_FDEVLSB                              0x05
00007 
00008 #define REG_FSK_RXCONFIG                                0x0D
00009 #define REG_FSK_RSSICONFIG                            0x0E
00010 #define REG_FSK_RSSICOLLISION                          0x0F // rssi delta threshold (interferer)
00011 #define REG_FSK_RSSITHRESH                            0x10  // trigger level for rssi interrupt
00012 #define REG_FSK_RSSIVALUE                              0x11
00013 #define REG_FSK_RXBW                                    0x12 
00014 #define REG_FSK_AFCBW                                  0x13
00015 #define REG_FSK_OOKPEAK                              0x14   // bitsync config
00016 #define REG_FSK_OOKFIX                                0x15  // threshold dB
00017 #define REG_FSK_OOKAVG                                0x16  
00018 #define REG_FSK_RES17                                  0x17 // barker test
00019 #define REG_FSK_RES18                                  0x18 // barker test
00020 #define REG_FSK_RES19                                  0x19 // barker test
00021 #define REG_FSK_AFCFEI                                0x1A
00022 #define REG_FSK_AFCMSB                                0x1B
00023 #define REG_FSK_AFCLSB                                0x1C
00024 #define REG_FSK_FEIMSB                                0x1D
00025 #define REG_FSK_FEILSB                                0x1E
00026 #define REG_FSK_PREAMBLEDETECT                        0x1F
00027 #define REG_FSK_RXTIMEOUT1                            0x20  // rssi timeout
00028 #define REG_FSK_RXTIMEOUT2                            0x21  // preamble detect timeout
00029 #define REG_FSK_RXTIMEOUT3                            0x22  // sync detect timeout
00030 #define REG_FSK_RXDELAY                              0x23   // RX restart delay
00031 // Oscillator settings
00032 #define REG_FSK_OSC                                  0x24   // clkout output divider
00033 // Packet handler settings
00034 #define REG_FSK_PREAMBLEMSB                          0x25   // preamble length
00035 #define REG_FSK_PREAMBLELSB                          0x26   // preamble length
00036 #define REG_FSK_SYNCCONFIG                            0x27
00037 #define REG_FSK_SYNCVALUE1                            0x28
00038 #define REG_FSK_SYNCVALUE2                            0x29
00039 #define REG_FSK_SYNCVALUE3                            0x2A
00040 #define REG_FSK_SYNCVALUE4                            0x2B
00041 #define REG_FSK_SYNCVALUE5                            0x2C
00042 #define REG_FSK_SYNCVALUE6                            0x2D
00043 #define REG_FSK_SYNCVALUE7                            0x2E
00044 #define REG_FSK_SYNCVALUE8                            0x2F
00045 #define REG_FSK_PACKETCONFIG1                          0x30
00046 #define REG_FSK_PACKETCONFIG2                          0x31
00047 #define REG_FSK_PAYLOADLENGTH                          0x32
00048 #define REG_FSK_NODEADRS                                0x33
00049 #define REG_FSK_BROADCASTADRS                          0x34
00050 #define REG_FSK_FIFOTHRESH                            0x35
00051 // SM settings
00052 #define REG_FSK_SEQCONFIG1                            0x36
00053 #define REG_FSK_SEQCONFIG2                            0x37
00054 #define REG_FSK_TIMERRESOL                            0x38
00055 #define REG_FSK_TIMER1COEF                            0x39  // period of timer1 interrupt
00056 #define REG_FSK_TIMER2COEF                            0x3A  // period of timer2 interrupt
00057 // Service settings
00058 #define REG_FSK_IMAGECAL                                0x3B
00059 #define REG_FSK_TEMP                                    0x3C
00060 #define REG_FSK_LOWBAT                                0x3D  // EOL "end of life"
00061 // Status
00062 #define REG_FSK_IRQFLAGS1                              0x3E
00063 #define REG_FSK_IRQFLAGS2                              0x3F // packet flags
00064 
00065 /******************************************************************************/
00066 
00067 #define FSK_FIFO_SIZE       64
00068 #define FSK_FIFO_SIZE_HALF  (FSK_FIFO_SIZE>>1)
00069 
00070 typedef union {
00071     struct {    // sx1272 register 0x0d
00072         //uint8_t wait_rssi_irq        : 1; // 0 wait for signal strength before entering RX
00073         //uint8_t wait_irq_0x55        : 1; // 1 wait for preamble before entering RX
00074         //uint8_t agc_on_irq_0x55        : 1;   // 2 1=LNA gain adj done until irq_0x55 asserted
00075         uint8_t RxTrigger              : 3; // 0,1,2: 0=none 1=rssiInt 6=preambleDet 7=both
00076         uint8_t AgcAutoOn              : 1; // 3
00077         uint8_t AfcAutoOn              : 1; // 4
00078         uint8_t RestartRxWithPllLock    : 1;    // 5        restart from FSRX mode
00079         uint8_t RestartRxWithoutPllLock : 1;    // 6
00080         uint8_t RestartRxOnCollision    : 1;    // 7
00081     } bits;
00082     uint8_t octet;
00083 } RegRxConfig_t;
00084 
00085 
00086 typedef union {
00087     struct {    // sx1272 register 0x1a
00088         uint8_t AfcAutoClearOn  : 1;    // 0
00089         uint8_t AfcClear        : 1;    // 1    manual clear
00090         uint8_t unused1      : 1;   // 2
00091         uint8_t fei_range      : 1; // 3    FEI range limited by: 0=rxbw    1=fs/2
00092         uint8_t AgcStart        : 1;    // 4    manual trigger AGC
00093         uint8_t unused        : 3;  // 5,6,7 
00094     } bits;
00095     uint8_t octet;
00096 } RegAfcFei_t;
00097 
00098 
00099 typedef union {
00100     struct {    // sx1272 register 0x0e
00101         uint8_t RssiSmoothing   : 3;    // 0,1,2
00102         uint8_t RssiOffset      : 5;    // 3,4,5,6,7
00103     } bits;
00104     uint8_t octet;
00105 } RegRssiConfig_t;
00106 
00107 typedef union {
00108     struct {    // sx1272 register 0x12
00109         //uint8_t RxBw          : 5;    // 0,1,2,3,4        (0,1,2=exp   3,4=mant)
00110         uint8_t Exponent        : 3;    // 0,1,2
00111         uint8_t Mantissa        : 2;    // 3,4
00112         uint8_t dcc_force      : 1; // 5 force dcc on all rxbw (otherwise put only if > 167KHz)
00113         uint8_t dcc_fast_init   : 1;    // 6 
00114         uint8_t reserved        : 1;    // 7 
00115     } bits;
00116     uint8_t octet;
00117 } RegRxBw_t;
00118 
00119 typedef union {
00120     struct {    // sx1272 register 0x14
00121         uint8_t OokPeakThreshStep   : 3;    // 0,1,2
00122         uint8_t OokThreshType      : 2; // 3,4
00123         uint8_t BitSyncOn          : 1; // 5
00124         uint8_t barker_en          : 1; // 6
00125         uint8_t bsync_opt          : 1; // 7    not used
00126     } bits;
00127     uint8_t octet;
00128 } RegOokPeak_t; // DEMOD1 0x14
00129 
00130 typedef union {
00131     struct {    // sx1272 register 0x16
00132         uint8_t OokAverageThreshFilt : 2; // 0,1
00133         uint8_t OokAverageOffset     : 2; // 2,3
00134         uint8_t reserved             : 1; // 4
00135         uint8_t OokPeakThreshDec     : 3; // 5,6,7
00136     } bits;
00137     uint8_t octet;
00138 } RegOokAvg_t; // at 0x16
00139 
00140 typedef union {
00141     struct {    // sx1272 register 0x1f
00142         uint8_t PreambleDetectorTol  : 5;   // 0,1,2,3,4    allowed chip errors
00143         uint8_t PreambleDetectorSize    : 2;    // 5,6    00b=1bytes... 11b=4bytes
00144         uint8_t PreambleDetectorOn    : 1;  // 7
00145     } bits;
00146     uint8_t octet;
00147 } RegPreambleDetect_t;
00148 
00149 typedef union {
00150     struct {    // sx127x register 0x24
00151         uint8_t ClkOut         : 3;   // 0,1,2
00152         uint8_t rc_cal_trigger : 1;    // 3
00153         uint8_t unused         : 4;  // 4,5,6,7
00154     } bits;
00155     uint8_t octet;
00156 } RegOsc_t;
00157 
00158 typedef union {
00159     struct {    // sx1232 register 0x27
00160         uint8_t SyncSize            : 3;    // 0,1,2
00161         uint8_t FifoFillCondition   : 1;    // 3    rx fifo fill starting 0=start-on-sync
00162         uint8_t SyncOn            : 1;  // 4    enable pattern recognition
00163         uint8_t PreamblePolarity    : 1;    // 5    0=0xaa 1=0x55
00164         uint8_t AutoRestartRxMode   : 2;    // 6,7  00b=do not restart 10b=wait-for-pll
00165     } bits;
00166     uint8_t octet;
00167 } RegSyncConfig_t;
00168 
00169 typedef union {
00170     struct {    // sx1232 register 0x30
00171         uint8_t CrCWhiteningType : 1;   // 0       1=IBM-crc   0=ccitt-crc
00172         uint8_t AddressFiltering : 2;   // 1,2   11b = two-byte nodeadrs at 0x2c->0x2f
00173         uint8_t CrcAutoClearOff  : 1;   // 3
00174         uint8_t CrcOn           : 1;    // 4
00175         uint8_t DcFree         : 2; // 5,6 
00176         uint8_t PacketFormatVariable : 1;   // 7       1=variable length, 0=fixed
00177     } bits;
00178     uint8_t octet;
00179 } RegPktConfig1_t;
00180 
00181 typedef union {
00182     struct {    // sx1272 register 0x31 and 0x32
00183         uint16_t PayloadLength      : 11;   // 0->10
00184         uint16_t BeaconOn           : 1;    // 11 
00185         uint16_t IoHomePowerFrame   : 1;    // 12   CRC LFSR init: 0=0x1d0f, 1=0x0000=powerlink
00186         uint16_t IoHomeOn           : 1;    // 13
00187         uint16_t DataModePacket     : 1;    // 14   1=packet mode, 0=continuous mode
00188         uint16_t unused             : 1;    // 15 
00189     } bits;
00190     uint16_t word;
00191 } RegPktConfig2_t;
00192 
00193 typedef union {
00194     struct {    // sx1272 register 0x35
00195         uint8_t FifoThreshold      : 6; // 0,1,2,3,4,5
00196         uint8_t unused            : 1;  // 6 
00197         uint8_t TxStartCondition    : 1;    // 7        0=fifoThresh 1=fifoNotEmpty
00198     } bits;
00199     uint8_t octet;
00200 } RegFifoThreshold_t;
00201 
00202 typedef union {
00203     struct {    // sx1272 register 0x36
00204         uint8_t FromTransmit        : 1;    // 0
00205         uint8_t FromIdle            : 1;    // 1
00206         uint8_t LowPowerSelection   : 1;    // 2
00207         uint8_t FromStart          : 2; // 3,4
00208         uint8_t IdleMode            : 1;    // 5 
00209         uint8_t SequencerStop      : 1; // 6 
00210         uint8_t SequencerStart    : 1;  // 7
00211     } bits;
00212     uint8_t octet;
00213 } RegSeqConfig1_t;   // @0x36
00214 
00215 typedef union {
00216     struct {    // sx1272 register 0x37
00217         uint8_t FromPacketReceived  : 3;    // 0,1,2
00218         uint8_t FromRxTimeout      : 2; // 3,4
00219         uint8_t FromReceive      : 3;   // 5,6,7
00220     } bits;
00221     uint8_t octet;
00222 } RegSeqConfig2_t;   // @0x37
00223 
00224 typedef union {
00225     struct {    // sx1272 register 0x38
00226         uint8_t timer2_resol   : 2; // 0,1
00227         uint8_t timer1_resol   : 2; // 2,3
00228         uint8_t force_hlm_irq  : 1; // 4 
00229         uint8_t hlm_started : 1;    // 5 
00230         uint8_t unused       : 2;   // 6,7
00231     } bits;
00232     uint8_t octet;
00233 } RegTimerResol_t;   // HL42 @0x38
00234 
00235 typedef union {
00236     struct {    // sx1272 register 0x3b
00237         uint8_t TempMonitorOff  : 1;    // 0
00238         uint8_t TempThreshold   : 2;    // 1,2
00239         uint8_t TempChange      : 1;    // 3    read-only
00240         uint8_t unused          : 1;    // 4 
00241         uint8_t ImageCalRunning : 1;    // 5    read-only
00242         uint8_t ImageCalStart   : 1;    // 6    write-only
00243         uint8_t AutoImageCalOn  : 1;    // 7
00244     } bits;
00245     uint8_t octet;
00246 } RegImageCal_t;   // 
00247 
00248 typedef union {
00249     struct {    // sx1232 register 0x3e
00250         uint8_t SyncAddressMatch    : 1;    // 0 
00251         uint8_t PreambleDetect    : 1;  // 1 
00252         uint8_t Timeout          : 1;   // 2    rx-timeout
00253         uint8_t Rssi                : 1;    // 3 
00254         uint8_t PllLock          : 1;   // 4 
00255         uint8_t TxReady          : 1;   // 5 
00256         uint8_t RxReady          : 1;   // 6 
00257         uint8_t ModeReady          : 1; // 7 
00258     } bits;
00259     uint8_t octet;
00260 } RegIrqFlags1_t;   // STAT0
00261 
00262 typedef union {
00263     struct {    // sx1232 register 0x3f
00264         uint8_t LowBat        : 1;  // 0    "eol"
00265         uint8_t CrcOk          : 1; // 1 
00266         uint8_t PayloadReady    : 1;    // 2 
00267         uint8_t PacketSent    : 1;  // 3 
00268         uint8_t FifoOverrun  : 1;   // 4 
00269         uint8_t FifoLevel      : 1; // 5 
00270         uint8_t FifoEmpty      : 1; // 6 
00271         uint8_t FifoFull        : 1;    // 7 
00272     } bits;
00273     uint8_t octet;
00274 } RegIrqFlags2_t;   // STAT1 @0x3f
00275 
00276 //class SX127x_fsk : public SX127x
00277 class SX127x_fsk {
00278     public:
00279         //SX127x_fsk(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1, PinName fem_ctx, PinName fem_cps);
00280         SX127x_fsk(SX127x& r);
00281         
00282         ~SX127x_fsk();
00283         
00284         /** switches from LoRa mode to FSK mdoe
00285          * before SX127x_fsk can be used, eanble() must be called.  LoRa mode is unavailable while FSK is in use.
00286          * @param fast true=bypass reading FSK registers after mode switch */
00287         void enable(bool fast);
00288         
00289         /** put FSK modem to some functioning default */
00290         void init(void);
00291         
00292         /** fills radio FIFO with payload contents, prior to transmission
00293          * @param len count of bytes to put into FIFO
00294          * @note tx_buf[] should contain desired payload (to send) prior to calling
00295          */
00296         void write_fifo(uint8_t len);        
00297         
00298         void start_tx(uint16_t len);
00299         
00300         void start_rx(void);
00301         uint8_t rx_buf_length;
00302         void config_dio0_for_pktmode_rx(void);
00303         
00304         uint32_t get_rx_bw_hz(uint8_t addr);
00305         
00306         /** bw_hz: single side (ssb) */
00307         void set_rx_dcc_bw_hz(uint32_t bw_hz, char afc);
00308         
00309         uint32_t get_bitrate(void);
00310         void set_bitrate(uint32_t);
00311 
00312         uint32_t get_tx_fdev_hz(void);
00313         void set_tx_fdev_hz(uint32_t);
00314         
00315         uint8_t get_modulation_shaping(void);
00316         void set_modulation_shaping(uint8_t);
00317         
00318         service_action_e service(void); // (SLIH) ISR bottom half 
00319         
00320         RegRxConfig_t        RegRxConfig;         // 0x0d
00321         RegRssiConfig_t      RegRssiConfig;       // 0x0e
00322         uint8_t              RegRssiThresh;       // 0x10
00323         RegRxBw_t            RegRxBw;             // 0x12
00324         RegRxBw_t            RegAfcBw;            // 0x13
00325         RegOokPeak_t         RegOokPeak;          // 0x14
00326         RegAfcFei_t          RegAfcFei;           // 0x1a
00327         int16_t              RegAfcValue;         // 0x1c
00328         RegPreambleDetect_t  RegPreambleDetect;   // 0x1f
00329         RegSyncConfig_t      RegSyncConfig;       // 0x27
00330         RegPktConfig1_t      RegPktConfig1;       // 0x30
00331         RegPktConfig2_t      RegPktConfig2;       // 0x31 -> 0x32
00332         RegFifoThreshold_t   RegFifoThreshold;    // 0x35
00333         RegSeqConfig1_t      RegSeqConfig1;       // 0x36
00334         RegSeqConfig2_t      RegSeqConfig2;       // 0x37
00335         RegTimerResol_t      RegTimerResol;       // 0x38
00336         RegImageCal_t        RegImageCal;         // 0x3b
00337         
00338         bool tx_done_sleep; // false:go to standby after tx done, true:sleep
00339         
00340         SX127x& m_xcvr;
00341         
00342     private:
00343         unsigned int bit_period_us;
00344         uint32_t ComputeRxBw( uint8_t mantisse, uint8_t exponent );
00345         void ComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent );     
00346                    
00347 };
00348