Driver library for SX1272/SX1276 transceivers

Dependents:   LORA_RX LORA_TX WindConcentrator hid_test ... more

/media/uploads/dudmuck/lora.png

Driver library for SX1272 and SX1276 radio transceivers.

This device uses CSS modulation to provide much improved link budget. The RF hardware is same as in FSK devices, just with added LoRa spread-spectrum modem.

This library provides functions to configure radio chip and transmit & receive packets.

Using This Library

Library function service_radio() must be called continuously from main loop, to service interrupts from radio.

/media/uploads/dudmuck/sx1272rf1_connector_300.jpg

Board Specific implementation

FunctionPointer for rf_switch callback allows the program to implement control of RF switch unique to their board. Example options are:

  • SKY13373 for external power amplifier implementation. Requires two DigitalOut pins.
  • SKY13350 using PA_BOOST. requires two DigitalOut pins.
  • PE4259-63: controlled directly by radio chip, no software function needed. However, in the case of SX1276MB1xAS, the RXTX pin on IO2 should be driven by this callback function when R16 is installed (without R15) on this shield board.

Some configurations may need to force the use of RFO or PA_BOOST, or a board could offer both options. The rf_switch function pointer callback should support the implementation choice on the board.

further reading

Committer:
Wayne Roberts
Date:
Fri Aug 10 13:48:48 2018 -0700
Revision:
34:c48ef2fc3ec9
Parent:
33:4b9fd8969428
add missing register

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Wayne Roberts 33:4b9fd8969428 1 #include "sx12xx.h"
dudmuck 2:fdae76e1215e 2
dudmuck 2:fdae76e1215e 3 #define REG_FSK_BITRATEMSB 0x02
dudmuck 2:fdae76e1215e 4 #define REG_FSK_BITRATELSB 0x03
dudmuck 2:fdae76e1215e 5 #define REG_FSK_FDEVMSB 0x04
dudmuck 2:fdae76e1215e 6 #define REG_FSK_FDEVLSB 0x05
dudmuck 2:fdae76e1215e 7
dudmuck 2:fdae76e1215e 8 #define REG_FSK_RXCONFIG 0x0D
dudmuck 2:fdae76e1215e 9 #define REG_FSK_RSSICONFIG 0x0E
dudmuck 2:fdae76e1215e 10 #define REG_FSK_RSSICOLLISION 0x0F // rssi delta threshold (interferer)
dudmuck 2:fdae76e1215e 11 #define REG_FSK_RSSITHRESH 0x10 // trigger level for rssi interrupt
dudmuck 2:fdae76e1215e 12 #define REG_FSK_RSSIVALUE 0x11
dudmuck 2:fdae76e1215e 13 #define REG_FSK_RXBW 0x12
dudmuck 2:fdae76e1215e 14 #define REG_FSK_AFCBW 0x13
dudmuck 2:fdae76e1215e 15 #define REG_FSK_OOKPEAK 0x14 // bitsync config
dudmuck 2:fdae76e1215e 16 #define REG_FSK_OOKFIX 0x15 // threshold dB
dudmuck 2:fdae76e1215e 17 #define REG_FSK_OOKAVG 0x16
dudmuck 2:fdae76e1215e 18 #define REG_FSK_RES17 0x17 // barker test
dudmuck 2:fdae76e1215e 19 #define REG_FSK_RES18 0x18 // barker test
dudmuck 2:fdae76e1215e 20 #define REG_FSK_RES19 0x19 // barker test
dudmuck 2:fdae76e1215e 21 #define REG_FSK_AFCFEI 0x1A
dudmuck 2:fdae76e1215e 22 #define REG_FSK_AFCMSB 0x1B
dudmuck 2:fdae76e1215e 23 #define REG_FSK_AFCLSB 0x1C
dudmuck 2:fdae76e1215e 24 #define REG_FSK_FEIMSB 0x1D
dudmuck 2:fdae76e1215e 25 #define REG_FSK_FEILSB 0x1E
dudmuck 2:fdae76e1215e 26 #define REG_FSK_PREAMBLEDETECT 0x1F
dudmuck 2:fdae76e1215e 27 #define REG_FSK_RXTIMEOUT1 0x20 // rssi timeout
dudmuck 2:fdae76e1215e 28 #define REG_FSK_RXTIMEOUT2 0x21 // preamble detect timeout
dudmuck 2:fdae76e1215e 29 #define REG_FSK_RXTIMEOUT3 0x22 // sync detect timeout
dudmuck 2:fdae76e1215e 30 #define REG_FSK_RXDELAY 0x23 // RX restart delay
dudmuck 2:fdae76e1215e 31 // Oscillator settings
dudmuck 2:fdae76e1215e 32 #define REG_FSK_OSC 0x24 // clkout output divider
dudmuck 2:fdae76e1215e 33 // Packet handler settings
dudmuck 2:fdae76e1215e 34 #define REG_FSK_PREAMBLEMSB 0x25 // preamble length
dudmuck 2:fdae76e1215e 35 #define REG_FSK_PREAMBLELSB 0x26 // preamble length
dudmuck 2:fdae76e1215e 36 #define REG_FSK_SYNCCONFIG 0x27
dudmuck 2:fdae76e1215e 37 #define REG_FSK_SYNCVALUE1 0x28
dudmuck 2:fdae76e1215e 38 #define REG_FSK_SYNCVALUE2 0x29
dudmuck 2:fdae76e1215e 39 #define REG_FSK_SYNCVALUE3 0x2A
dudmuck 2:fdae76e1215e 40 #define REG_FSK_SYNCVALUE4 0x2B
dudmuck 2:fdae76e1215e 41 #define REG_FSK_SYNCVALUE5 0x2C
dudmuck 2:fdae76e1215e 42 #define REG_FSK_SYNCVALUE6 0x2D
dudmuck 2:fdae76e1215e 43 #define REG_FSK_SYNCVALUE7 0x2E
dudmuck 2:fdae76e1215e 44 #define REG_FSK_SYNCVALUE8 0x2F
dudmuck 2:fdae76e1215e 45 #define REG_FSK_PACKETCONFIG1 0x30
dudmuck 2:fdae76e1215e 46 #define REG_FSK_PACKETCONFIG2 0x31
dudmuck 2:fdae76e1215e 47 #define REG_FSK_PAYLOADLENGTH 0x32
dudmuck 2:fdae76e1215e 48 #define REG_FSK_NODEADRS 0x33
dudmuck 2:fdae76e1215e 49 #define REG_FSK_BROADCASTADRS 0x34
dudmuck 2:fdae76e1215e 50 #define REG_FSK_FIFOTHRESH 0x35
dudmuck 2:fdae76e1215e 51 // SM settings
dudmuck 2:fdae76e1215e 52 #define REG_FSK_SEQCONFIG1 0x36
dudmuck 2:fdae76e1215e 53 #define REG_FSK_SEQCONFIG2 0x37
dudmuck 2:fdae76e1215e 54 #define REG_FSK_TIMERRESOL 0x38
dudmuck 2:fdae76e1215e 55 #define REG_FSK_TIMER1COEF 0x39 // period of timer1 interrupt
dudmuck 2:fdae76e1215e 56 #define REG_FSK_TIMER2COEF 0x3A // period of timer2 interrupt
dudmuck 2:fdae76e1215e 57 // Service settings
dudmuck 2:fdae76e1215e 58 #define REG_FSK_IMAGECAL 0x3B
dudmuck 2:fdae76e1215e 59 #define REG_FSK_TEMP 0x3C
dudmuck 2:fdae76e1215e 60 #define REG_FSK_LOWBAT 0x3D // EOL "end of life"
dudmuck 2:fdae76e1215e 61 // Status
dudmuck 2:fdae76e1215e 62 #define REG_FSK_IRQFLAGS1 0x3E
dudmuck 2:fdae76e1215e 63 #define REG_FSK_IRQFLAGS2 0x3F // packet flags
dudmuck 2:fdae76e1215e 64
dudmuck 2:fdae76e1215e 65 /******************************************************************************/
dudmuck 2:fdae76e1215e 66
dudmuck 2:fdae76e1215e 67 #define FSK_FIFO_SIZE 64
dudmuck 2:fdae76e1215e 68 #define FSK_FIFO_SIZE_HALF (FSK_FIFO_SIZE>>1)
dudmuck 2:fdae76e1215e 69
dudmuck 2:fdae76e1215e 70 typedef union {
dudmuck 2:fdae76e1215e 71 struct { // sx1272 register 0x0d
dudmuck 2:fdae76e1215e 72 //uint8_t wait_rssi_irq : 1; // 0 wait for signal strength before entering RX
dudmuck 2:fdae76e1215e 73 //uint8_t wait_irq_0x55 : 1; // 1 wait for preamble before entering RX
dudmuck 2:fdae76e1215e 74 //uint8_t agc_on_irq_0x55 : 1; // 2 1=LNA gain adj done until irq_0x55 asserted
dudmuck 2:fdae76e1215e 75 uint8_t RxTrigger : 3; // 0,1,2: 0=none 1=rssiInt 6=preambleDet 7=both
dudmuck 2:fdae76e1215e 76 uint8_t AgcAutoOn : 1; // 3
dudmuck 2:fdae76e1215e 77 uint8_t AfcAutoOn : 1; // 4
dudmuck 2:fdae76e1215e 78 uint8_t RestartRxWithPllLock : 1; // 5 restart from FSRX mode
dudmuck 2:fdae76e1215e 79 uint8_t RestartRxWithoutPllLock : 1; // 6
dudmuck 2:fdae76e1215e 80 uint8_t RestartRxOnCollision : 1; // 7
dudmuck 2:fdae76e1215e 81 } bits;
dudmuck 2:fdae76e1215e 82 uint8_t octet;
dudmuck 3:3bf2515b1eed 83 } RegRxConfig_t;
dudmuck 2:fdae76e1215e 84
dudmuck 2:fdae76e1215e 85
dudmuck 2:fdae76e1215e 86 typedef union {
dudmuck 2:fdae76e1215e 87 struct { // sx1272 register 0x1a
dudmuck 2:fdae76e1215e 88 uint8_t AfcAutoClearOn : 1; // 0
dudmuck 2:fdae76e1215e 89 uint8_t AfcClear : 1; // 1 manual clear
dudmuck 2:fdae76e1215e 90 uint8_t unused1 : 1; // 2
dudmuck 2:fdae76e1215e 91 uint8_t fei_range : 1; // 3 FEI range limited by: 0=rxbw 1=fs/2
dudmuck 2:fdae76e1215e 92 uint8_t AgcStart : 1; // 4 manual trigger AGC
dudmuck 2:fdae76e1215e 93 uint8_t unused : 3; // 5,6,7
dudmuck 2:fdae76e1215e 94 } bits;
dudmuck 2:fdae76e1215e 95 uint8_t octet;
dudmuck 3:3bf2515b1eed 96 } RegAfcFei_t;
dudmuck 2:fdae76e1215e 97
dudmuck 2:fdae76e1215e 98
dudmuck 2:fdae76e1215e 99 typedef union {
dudmuck 2:fdae76e1215e 100 struct { // sx1272 register 0x0e
dudmuck 2:fdae76e1215e 101 uint8_t RssiSmoothing : 3; // 0,1,2
dudmuck 2:fdae76e1215e 102 uint8_t RssiOffset : 5; // 3,4,5,6,7
dudmuck 2:fdae76e1215e 103 } bits;
dudmuck 2:fdae76e1215e 104 uint8_t octet;
dudmuck 3:3bf2515b1eed 105 } RegRssiConfig_t;
dudmuck 2:fdae76e1215e 106
dudmuck 2:fdae76e1215e 107 typedef union {
dudmuck 2:fdae76e1215e 108 struct { // sx1272 register 0x12
dudmuck 2:fdae76e1215e 109 //uint8_t RxBw : 5; // 0,1,2,3,4 (0,1,2=exp 3,4=mant)
dudmuck 2:fdae76e1215e 110 uint8_t Exponent : 3; // 0,1,2
dudmuck 2:fdae76e1215e 111 uint8_t Mantissa : 2; // 3,4
dudmuck 2:fdae76e1215e 112 uint8_t dcc_force : 1; // 5 force dcc on all rxbw (otherwise put only if > 167KHz)
dudmuck 2:fdae76e1215e 113 uint8_t dcc_fast_init : 1; // 6
dudmuck 2:fdae76e1215e 114 uint8_t reserved : 1; // 7
dudmuck 2:fdae76e1215e 115 } bits;
dudmuck 2:fdae76e1215e 116 uint8_t octet;
dudmuck 3:3bf2515b1eed 117 } RegRxBw_t;
dudmuck 2:fdae76e1215e 118
dudmuck 2:fdae76e1215e 119 typedef union {
dudmuck 2:fdae76e1215e 120 struct { // sx1272 register 0x14
dudmuck 2:fdae76e1215e 121 uint8_t OokPeakThreshStep : 3; // 0,1,2
dudmuck 2:fdae76e1215e 122 uint8_t OokThreshType : 2; // 3,4
dudmuck 2:fdae76e1215e 123 uint8_t BitSyncOn : 1; // 5
dudmuck 2:fdae76e1215e 124 uint8_t barker_en : 1; // 6
dudmuck 2:fdae76e1215e 125 uint8_t bsync_opt : 1; // 7 not used
dudmuck 2:fdae76e1215e 126 } bits;
dudmuck 2:fdae76e1215e 127 uint8_t octet;
dudmuck 3:3bf2515b1eed 128 } RegOokPeak_t; // DEMOD1 0x14
dudmuck 2:fdae76e1215e 129
dudmuck 2:fdae76e1215e 130 typedef union {
Wayne Roberts 34:c48ef2fc3ec9 131 struct { // sx1272 register 0x16
Wayne Roberts 34:c48ef2fc3ec9 132 uint8_t OokAverageThreshFilt : 2; // 0,1
Wayne Roberts 34:c48ef2fc3ec9 133 uint8_t OokAverageOffset : 2; // 2,3
Wayne Roberts 34:c48ef2fc3ec9 134 uint8_t reserved : 1; // 4
Wayne Roberts 34:c48ef2fc3ec9 135 uint8_t OokPeakThreshDec : 3; // 5,6,7
Wayne Roberts 34:c48ef2fc3ec9 136 } bits;
Wayne Roberts 34:c48ef2fc3ec9 137 uint8_t octet;
Wayne Roberts 34:c48ef2fc3ec9 138 } RegOokAvg_t; // at 0x16
Wayne Roberts 34:c48ef2fc3ec9 139
Wayne Roberts 34:c48ef2fc3ec9 140 typedef union {
dudmuck 2:fdae76e1215e 141 struct { // sx1272 register 0x1f
dudmuck 2:fdae76e1215e 142 uint8_t PreambleDetectorTol : 5; // 0,1,2,3,4 allowed chip errors
dudmuck 2:fdae76e1215e 143 uint8_t PreambleDetectorSize : 2; // 5,6 00b=1bytes... 11b=4bytes
dudmuck 2:fdae76e1215e 144 uint8_t PreambleDetectorOn : 1; // 7
dudmuck 2:fdae76e1215e 145 } bits;
dudmuck 2:fdae76e1215e 146 uint8_t octet;
dudmuck 3:3bf2515b1eed 147 } RegPreambleDetect_t;
dudmuck 2:fdae76e1215e 148
dudmuck 2:fdae76e1215e 149 typedef union {
dudmuck 27:da6341d9d5b1 150 struct { // sx127x register 0x24
dudmuck 27:da6341d9d5b1 151 uint8_t ClkOut : 3; // 0,1,2
dudmuck 27:da6341d9d5b1 152 uint8_t rc_cal_trigger : 1; // 3
dudmuck 27:da6341d9d5b1 153 uint8_t unused : 4; // 4,5,6,7
dudmuck 27:da6341d9d5b1 154 } bits;
dudmuck 27:da6341d9d5b1 155 uint8_t octet;
dudmuck 27:da6341d9d5b1 156 } RegOsc_t;
dudmuck 27:da6341d9d5b1 157
dudmuck 27:da6341d9d5b1 158 typedef union {
dudmuck 2:fdae76e1215e 159 struct { // sx1232 register 0x27
dudmuck 2:fdae76e1215e 160 uint8_t SyncSize : 3; // 0,1,2
dudmuck 2:fdae76e1215e 161 uint8_t FifoFillCondition : 1; // 3 rx fifo fill starting 0=start-on-sync
dudmuck 2:fdae76e1215e 162 uint8_t SyncOn : 1; // 4 enable pattern recognition
dudmuck 2:fdae76e1215e 163 uint8_t PreamblePolarity : 1; // 5 0=0xaa 1=0x55
dudmuck 2:fdae76e1215e 164 uint8_t AutoRestartRxMode : 2; // 6,7 00b=do not restart 10b=wait-for-pll
dudmuck 2:fdae76e1215e 165 } bits;
dudmuck 2:fdae76e1215e 166 uint8_t octet;
dudmuck 3:3bf2515b1eed 167 } RegSyncConfig_t;
dudmuck 2:fdae76e1215e 168
dudmuck 2:fdae76e1215e 169 typedef union {
dudmuck 2:fdae76e1215e 170 struct { // sx1232 register 0x30
dudmuck 2:fdae76e1215e 171 uint8_t CrCWhiteningType : 1; // 0 1=IBM-crc 0=ccitt-crc
dudmuck 2:fdae76e1215e 172 uint8_t AddressFiltering : 2; // 1,2 11b = two-byte nodeadrs at 0x2c->0x2f
dudmuck 2:fdae76e1215e 173 uint8_t CrcAutoClearOff : 1; // 3
dudmuck 2:fdae76e1215e 174 uint8_t CrcOn : 1; // 4
dudmuck 2:fdae76e1215e 175 uint8_t DcFree : 2; // 5,6
dudmuck 2:fdae76e1215e 176 uint8_t PacketFormatVariable : 1; // 7 1=variable length, 0=fixed
dudmuck 2:fdae76e1215e 177 } bits;
dudmuck 2:fdae76e1215e 178 uint8_t octet;
dudmuck 3:3bf2515b1eed 179 } RegPktConfig1_t;
dudmuck 2:fdae76e1215e 180
dudmuck 2:fdae76e1215e 181 typedef union {
dudmuck 2:fdae76e1215e 182 struct { // sx1272 register 0x31 and 0x32
dudmuck 2:fdae76e1215e 183 uint16_t PayloadLength : 11; // 0->10
dudmuck 2:fdae76e1215e 184 uint16_t BeaconOn : 1; // 11
dudmuck 2:fdae76e1215e 185 uint16_t IoHomePowerFrame : 1; // 12 CRC LFSR init: 0=0x1d0f, 1=0x0000=powerlink
dudmuck 2:fdae76e1215e 186 uint16_t IoHomeOn : 1; // 13
dudmuck 2:fdae76e1215e 187 uint16_t DataModePacket : 1; // 14 1=packet mode, 0=continuous mode
dudmuck 2:fdae76e1215e 188 uint16_t unused : 1; // 15
dudmuck 2:fdae76e1215e 189 } bits;
dudmuck 2:fdae76e1215e 190 uint16_t word;
dudmuck 3:3bf2515b1eed 191 } RegPktConfig2_t;
dudmuck 2:fdae76e1215e 192
dudmuck 2:fdae76e1215e 193 typedef union {
dudmuck 2:fdae76e1215e 194 struct { // sx1272 register 0x35
dudmuck 2:fdae76e1215e 195 uint8_t FifoThreshold : 6; // 0,1,2,3,4,5
dudmuck 2:fdae76e1215e 196 uint8_t unused : 1; // 6
dudmuck 2:fdae76e1215e 197 uint8_t TxStartCondition : 1; // 7 0=fifoThresh 1=fifoNotEmpty
dudmuck 2:fdae76e1215e 198 } bits;
dudmuck 2:fdae76e1215e 199 uint8_t octet;
dudmuck 3:3bf2515b1eed 200 } RegFifoThreshold_t;
dudmuck 2:fdae76e1215e 201
dudmuck 2:fdae76e1215e 202 typedef union {
dudmuck 2:fdae76e1215e 203 struct { // sx1272 register 0x36
dudmuck 2:fdae76e1215e 204 uint8_t FromTransmit : 1; // 0
dudmuck 2:fdae76e1215e 205 uint8_t FromIdle : 1; // 1
dudmuck 2:fdae76e1215e 206 uint8_t LowPowerSelection : 1; // 2
dudmuck 2:fdae76e1215e 207 uint8_t FromStart : 2; // 3,4
dudmuck 2:fdae76e1215e 208 uint8_t IdleMode : 1; // 5
dudmuck 2:fdae76e1215e 209 uint8_t SequencerStop : 1; // 6
dudmuck 2:fdae76e1215e 210 uint8_t SequencerStart : 1; // 7
dudmuck 2:fdae76e1215e 211 } bits;
dudmuck 2:fdae76e1215e 212 uint8_t octet;
dudmuck 3:3bf2515b1eed 213 } RegSeqConfig1_t; // @0x36
dudmuck 2:fdae76e1215e 214
dudmuck 2:fdae76e1215e 215 typedef union {
dudmuck 2:fdae76e1215e 216 struct { // sx1272 register 0x37
dudmuck 2:fdae76e1215e 217 uint8_t FromPacketReceived : 3; // 0,1,2
dudmuck 2:fdae76e1215e 218 uint8_t FromRxTimeout : 2; // 3,4
dudmuck 2:fdae76e1215e 219 uint8_t FromReceive : 3; // 5,6,7
dudmuck 2:fdae76e1215e 220 } bits;
dudmuck 2:fdae76e1215e 221 uint8_t octet;
dudmuck 2:fdae76e1215e 222 } RegSeqConfig2_t; // @0x37
dudmuck 2:fdae76e1215e 223
dudmuck 2:fdae76e1215e 224 typedef union {
dudmuck 2:fdae76e1215e 225 struct { // sx1272 register 0x38
dudmuck 2:fdae76e1215e 226 uint8_t timer2_resol : 2; // 0,1
dudmuck 2:fdae76e1215e 227 uint8_t timer1_resol : 2; // 2,3
dudmuck 2:fdae76e1215e 228 uint8_t force_hlm_irq : 1; // 4
dudmuck 2:fdae76e1215e 229 uint8_t hlm_started : 1; // 5
dudmuck 2:fdae76e1215e 230 uint8_t unused : 2; // 6,7
dudmuck 2:fdae76e1215e 231 } bits;
dudmuck 2:fdae76e1215e 232 uint8_t octet;
dudmuck 3:3bf2515b1eed 233 } RegTimerResol_t; // HL42 @0x38
dudmuck 2:fdae76e1215e 234
dudmuck 2:fdae76e1215e 235 typedef union {
dudmuck 2:fdae76e1215e 236 struct { // sx1272 register 0x3b
dudmuck 2:fdae76e1215e 237 uint8_t TempMonitorOff : 1; // 0
dudmuck 2:fdae76e1215e 238 uint8_t TempThreshold : 2; // 1,2
dudmuck 2:fdae76e1215e 239 uint8_t TempChange : 1; // 3 read-only
dudmuck 2:fdae76e1215e 240 uint8_t unused : 1; // 4
dudmuck 2:fdae76e1215e 241 uint8_t ImageCalRunning : 1; // 5 read-only
dudmuck 2:fdae76e1215e 242 uint8_t ImageCalStart : 1; // 6 write-only
dudmuck 2:fdae76e1215e 243 uint8_t AutoImageCalOn : 1; // 7
dudmuck 2:fdae76e1215e 244 } bits;
dudmuck 2:fdae76e1215e 245 uint8_t octet;
dudmuck 3:3bf2515b1eed 246 } RegImageCal_t; //
dudmuck 2:fdae76e1215e 247
dudmuck 2:fdae76e1215e 248 typedef union {
dudmuck 2:fdae76e1215e 249 struct { // sx1232 register 0x3e
dudmuck 2:fdae76e1215e 250 uint8_t SyncAddressMatch : 1; // 0
dudmuck 2:fdae76e1215e 251 uint8_t PreambleDetect : 1; // 1
dudmuck 2:fdae76e1215e 252 uint8_t Timeout : 1; // 2 rx-timeout
dudmuck 2:fdae76e1215e 253 uint8_t Rssi : 1; // 3
dudmuck 2:fdae76e1215e 254 uint8_t PllLock : 1; // 4
dudmuck 2:fdae76e1215e 255 uint8_t TxReady : 1; // 5
dudmuck 2:fdae76e1215e 256 uint8_t RxReady : 1; // 6
dudmuck 2:fdae76e1215e 257 uint8_t ModeReady : 1; // 7
dudmuck 2:fdae76e1215e 258 } bits;
dudmuck 2:fdae76e1215e 259 uint8_t octet;
dudmuck 3:3bf2515b1eed 260 } RegIrqFlags1_t; // STAT0
dudmuck 2:fdae76e1215e 261
dudmuck 2:fdae76e1215e 262 typedef union {
dudmuck 2:fdae76e1215e 263 struct { // sx1232 register 0x3f
dudmuck 2:fdae76e1215e 264 uint8_t LowBat : 1; // 0 "eol"
dudmuck 2:fdae76e1215e 265 uint8_t CrcOk : 1; // 1
dudmuck 2:fdae76e1215e 266 uint8_t PayloadReady : 1; // 2
dudmuck 2:fdae76e1215e 267 uint8_t PacketSent : 1; // 3
dudmuck 2:fdae76e1215e 268 uint8_t FifoOverrun : 1; // 4
dudmuck 2:fdae76e1215e 269 uint8_t FifoLevel : 1; // 5
dudmuck 2:fdae76e1215e 270 uint8_t FifoEmpty : 1; // 6
dudmuck 2:fdae76e1215e 271 uint8_t FifoFull : 1; // 7
dudmuck 2:fdae76e1215e 272 } bits;
dudmuck 2:fdae76e1215e 273 uint8_t octet;
dudmuck 3:3bf2515b1eed 274 } RegIrqFlags2_t; // STAT1 @0x3f
dudmuck 2:fdae76e1215e 275
dudmuck 2:fdae76e1215e 276 //class SX127x_fsk : public SX127x
dudmuck 2:fdae76e1215e 277 class SX127x_fsk {
dudmuck 2:fdae76e1215e 278 public:
dudmuck 2:fdae76e1215e 279 //SX127x_fsk(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1, PinName fem_ctx, PinName fem_cps);
dudmuck 3:3bf2515b1eed 280 SX127x_fsk(SX127x& r);
dudmuck 2:fdae76e1215e 281
dudmuck 2:fdae76e1215e 282 ~SX127x_fsk();
dudmuck 2:fdae76e1215e 283
dudmuck 3:3bf2515b1eed 284 /** switches from LoRa mode to FSK mdoe
dudmuck 12:bda42457c34a 285 * before SX127x_fsk can be used, eanble() must be called. LoRa mode is unavailable while FSK is in use.
dudmuck 12:bda42457c34a 286 * @param fast true=bypass reading FSK registers after mode switch */
dudmuck 12:bda42457c34a 287 void enable(bool fast);
dudmuck 2:fdae76e1215e 288
dudmuck 4:d987ac2836bf 289 /** put FSK modem to some functioning default */
dudmuck 4:d987ac2836bf 290 void init(void);
dudmuck 4:d987ac2836bf 291
dudmuck 2:fdae76e1215e 292 /** fills radio FIFO with payload contents, prior to transmission
dudmuck 2:fdae76e1215e 293 * @param len count of bytes to put into FIFO
dudmuck 2:fdae76e1215e 294 * @note tx_buf[] should contain desired payload (to send) prior to calling
dudmuck 2:fdae76e1215e 295 */
dudmuck 2:fdae76e1215e 296 void write_fifo(uint8_t len);
dudmuck 2:fdae76e1215e 297
dudmuck 2:fdae76e1215e 298 void start_tx(uint16_t len);
dudmuck 2:fdae76e1215e 299
dudmuck 2:fdae76e1215e 300 void start_rx(void);
dudmuck 3:3bf2515b1eed 301 uint8_t rx_buf_length;
dudmuck 3:3bf2515b1eed 302 void config_dio0_for_pktmode_rx(void);
dudmuck 2:fdae76e1215e 303
dudmuck 2:fdae76e1215e 304 uint32_t get_rx_bw_hz(uint8_t addr);
dudmuck 2:fdae76e1215e 305
dudmuck 2:fdae76e1215e 306 /** bw_hz: single side (ssb) */
dudmuck 2:fdae76e1215e 307 void set_rx_dcc_bw_hz(uint32_t bw_hz, char afc);
dudmuck 2:fdae76e1215e 308
dudmuck 4:d987ac2836bf 309 uint32_t get_bitrate(void);
dudmuck 4:d987ac2836bf 310 void set_bitrate(uint32_t);
dudmuck 4:d987ac2836bf 311
dudmuck 4:d987ac2836bf 312 uint32_t get_tx_fdev_hz(void);
dudmuck 4:d987ac2836bf 313 void set_tx_fdev_hz(uint32_t);
dudmuck 4:d987ac2836bf 314
dudmuck 27:da6341d9d5b1 315 uint8_t get_modulation_shaping(void);
dudmuck 27:da6341d9d5b1 316 void set_modulation_shaping(uint8_t);
dudmuck 27:da6341d9d5b1 317
dudmuck 2:fdae76e1215e 318 service_action_e service(void); // (SLIH) ISR bottom half
dudmuck 2:fdae76e1215e 319
dudmuck 3:3bf2515b1eed 320 RegRxConfig_t RegRxConfig; // 0x0d
dudmuck 3:3bf2515b1eed 321 RegRssiConfig_t RegRssiConfig; // 0x0e
dudmuck 3:3bf2515b1eed 322 uint8_t RegRssiThresh; // 0x10
dudmuck 3:3bf2515b1eed 323 RegRxBw_t RegRxBw; // 0x12
dudmuck 3:3bf2515b1eed 324 RegRxBw_t RegAfcBw; // 0x13
dudmuck 3:3bf2515b1eed 325 RegOokPeak_t RegOokPeak; // 0x14
dudmuck 3:3bf2515b1eed 326 RegAfcFei_t RegAfcFei; // 0x1a
dudmuck 3:3bf2515b1eed 327 int16_t RegAfcValue; // 0x1c
dudmuck 3:3bf2515b1eed 328 RegPreambleDetect_t RegPreambleDetect; // 0x1f
dudmuck 3:3bf2515b1eed 329 RegSyncConfig_t RegSyncConfig; // 0x27
dudmuck 3:3bf2515b1eed 330 RegPktConfig1_t RegPktConfig1; // 0x30
dudmuck 3:3bf2515b1eed 331 RegPktConfig2_t RegPktConfig2; // 0x31 -> 0x32
dudmuck 3:3bf2515b1eed 332 RegFifoThreshold_t RegFifoThreshold; // 0x35
dudmuck 3:3bf2515b1eed 333 RegSeqConfig1_t RegSeqConfig1; // 0x36
dudmuck 3:3bf2515b1eed 334 RegSeqConfig2_t RegSeqConfig2; // 0x37
dudmuck 3:3bf2515b1eed 335 RegTimerResol_t RegTimerResol; // 0x38
dudmuck 3:3bf2515b1eed 336 RegImageCal_t RegImageCal; // 0x3b
dudmuck 3:3bf2515b1eed 337
dudmuck 26:4876e515ff4c 338 bool tx_done_sleep; // false:go to standby after tx done, true:sleep
dudmuck 26:4876e515ff4c 339
dudmuck 9:ae1a71ccd730 340 SX127x& m_xcvr;
dudmuck 2:fdae76e1215e 341
dudmuck 2:fdae76e1215e 342 private:
dudmuck 26:4876e515ff4c 343 unsigned int bit_period_us;
dudmuck 2:fdae76e1215e 344 uint32_t ComputeRxBw( uint8_t mantisse, uint8_t exponent );
dudmuck 9:ae1a71ccd730 345 void ComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent );
dudmuck 3:3bf2515b1eed 346
Wayne Roberts 32:c138a5861ac6 347 };
Wayne Roberts 32:c138a5861ac6 348