wayne roberts / SX127x

Driver library for SX1272/SX1276 transceivers

Dependents:   LORA_RX LORA_TX WindConcentrator hid_test ... more

/media/uploads/dudmuck/lora.png

Driver library for SX1272 and SX1276 radio transceivers.

This device uses CSS modulation to provide much improved link budget. The RF hardware is same as in FSK devices, just with added LoRa spread-spectrum modem.

This library provides functions to configure radio chip and transmit & receive packets.

Using This Library

Library function service_radio() must be called continuously from main loop, to service interrupts from radio.

/media/uploads/dudmuck/sx1272rf1_connector_300.jpg

Board Specific implementation

FunctionPointer for rf_switch callback allows the program to implement control of RF switch unique to their board. Example options are:

  • SKY13373 for external power amplifier implementation. Requires two DigitalOut pins.
  • SKY13350 using PA_BOOST. requires two DigitalOut pins.
  • PE4259-63: controlled directly by radio chip, no software function needed. However, in the case of SX1276MB1xAS, the RXTX pin on IO2 should be driven by this callback function when R16 is installed (without R15) on this shield board.

Some configurations may need to force the use of RFO or PA_BOOST, or a board could offer both options. The rf_switch function pointer callback should support the implementation choice on the board.

further reading

sx127x_lora.h@27:da6341d9d5b1, 2016-07-28 (annotated)

Committer:
dudmuck
Date:
Thu Jul 28 00:57:22 2016 +0000
Revision:
27:da6341d9d5b1
Parent:
26:4876e515ff4c
Child:
33:4b9fd8969428
hw_reset working under pullup condition.  PLL registers defined.    PaRamp register defined. FSK modulation shaping supported.  FSK continuous TX mode supporting DIO0 high level.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 2:fdae76e1215e 1 #include "sx127x.h"
dudmuck 2:fdae76e1215e 2
dudmuck 2:fdae76e1215e 3 // LoRa registers
dudmuck 2:fdae76e1215e 4 #define REG_LR_FIFOADDRPTR 0x0d
dudmuck 2:fdae76e1215e 5 #define REG_LR_FIFOTXBASEADDR 0x0e
dudmuck 2:fdae76e1215e 6 #define REG_LR_FIFORXBASEADDR 0x0f
dudmuck 2:fdae76e1215e 7 #define REG_LR_FIFORXCURRENTADDR /*REG_LR_RXDATAADDR*/ 0x10
dudmuck 2:fdae76e1215e 8 #define REG_LR_IRQFLAGSMASK 0x11
dudmuck 2:fdae76e1215e 9 #define REG_LR_IRQFLAGS 0x12
dudmuck 2:fdae76e1215e 10 #define REG_LR_RXNBBYTES 0x13
dudmuck 2:fdae76e1215e 11 #define REG_LR_RXHEADERCNTVALUE_MSB 0x14
dudmuck 2:fdae76e1215e 12 #define REG_LR_RXHEADERCNTVALUE_LSB 0x15
dudmuck 2:fdae76e1215e 13 #define REG_LR_RXPACKETCNTVALUE_MSB 0x16
dudmuck 2:fdae76e1215e 14 #define REG_LR_RXPACKETCNTVALUE_LSB 0x17
dudmuck 2:fdae76e1215e 15 #define REG_LR_MODEMSTAT 0x18
dudmuck 2:fdae76e1215e 16 #define REG_LR_PKTSNRVALUE 0x19
dudmuck 2:fdae76e1215e 17 #define REG_LR_PKTRSSIVALUE 0x1a
dudmuck 2:fdae76e1215e 18 #define REG_LR_RSSIVALUE 0x1b
dudmuck 2:fdae76e1215e 19 #define REG_LR_HOPCHANNEL 0x1c
dudmuck 2:fdae76e1215e 20 #define REG_LR_MODEMCONFIG 0x1d
dudmuck 2:fdae76e1215e 21 #define REG_LR_MODEMCONFIG2 0x1e
dudmuck 2:fdae76e1215e 22 #define REG_LR_SYMBTIMEOUTLSB 0x1f
dudmuck 2:fdae76e1215e 23 #define REG_LR_PREAMBLEMSB 0x20
dudmuck 2:fdae76e1215e 24 #define REG_LR_PREAMBLELSB 0x21
dudmuck 2:fdae76e1215e 25 #define REG_LR_PAYLOADLENGTH 0x22 // and RX length for implicit
dudmuck 2:fdae76e1215e 26 #define REG_LR_RX_MAX_PAYLOADLENGTH 0x23 // length limit for explicit mode
dudmuck 2:fdae76e1215e 27 #define REG_LR_HOPPERIOD 0x24
dudmuck 2:fdae76e1215e 28 #define REG_LR_RXBYTEADDR /*REG_LR_RXDATAADDR*/ 0x25
dudmuck 2:fdae76e1215e 29 #define REG_LR_MODEMCONFIG3 0x26 // sx1272 REG_LR_PPM_CORRECTION_MSB
dudmuck 2:fdae76e1215e 30 #define REG_LR_PPM_CORRECTION_LSB 0x27
dudmuck 2:fdae76e1215e 31 #define REG_LR_TEST28 0x28 // est_freq_error
dudmuck 2:fdae76e1215e 32 #define REG_LR_TEST29 0x29 // est_freq_error
dudmuck 2:fdae76e1215e 33 #define REG_LR_TEST2A 0x2a // est_freq_error
dudmuck 2:fdae76e1215e 34 #define REG_LR_TEST2B 0x2b //
dudmuck 2:fdae76e1215e 35 #define REG_LR_WIDEBAND_RSSI 0x2c
dudmuck 2:fdae76e1215e 36 #define REG_LR_AGCH_TH 0x2d // agc_upper_th
dudmuck 2:fdae76e1215e 37 #define REG_LR_AGCL_TH 0x2e // agc_lower_th
dudmuck 2:fdae76e1215e 38 #define REG_LR_IFFRQH 0x2f // if_freq(12:8)
dudmuck 2:fdae76e1215e 39 #define REG_LR_IFFRQL 0x30 // if_freq(7:0)
dudmuck 2:fdae76e1215e 40 #define REG_LR_TEST31 0x31 // if_freq_auto, ...
dudmuck 2:fdae76e1215e 41 #define REG_LR_TEST32 0x32 //
dudmuck 15:3f3fc6792f97 42 #define REG_LR_TEST33 0x33 // invert IQ
dudmuck 11:4210303ac88d 43 #define REG_LR_CAD_PEAK_TO_NOISE_RATIO 0x34
dudmuck 11:4210303ac88d 44 #define REG_LR_CAD_MIN_PEAK 0x35
dudmuck 18:0ecb6adb7c0b 45 #define REG_LR_SX1276_AUTO_DRIFT 0x36
dudmuck 2:fdae76e1215e 46 #define REG_LR_DETECTION_THRESHOLD 0x37
dudmuck 11:4210303ac88d 47 #define REG_LR_SYNC_BYTE 0x39 // default 0x12 (value of 0x21 will isolate network)
dudmuck 18:0ecb6adb7c0b 48 #define REG_LR_GAIN_DRIFT 0x3a
dudmuck 17:59279bc8cdab 49 #define REG_LR_DRIFT_INVERT 0x3b
dudmuck 2:fdae76e1215e 50
dudmuck 2:fdae76e1215e 51 typedef union {
dudmuck 2:fdae76e1215e 52 struct { // sx127x register 0x12
dudmuck 2:fdae76e1215e 53 uint8_t CadDetected : 1; // 0
dudmuck 2:fdae76e1215e 54 uint8_t FhssChangeChannel : 1; // 1
dudmuck 2:fdae76e1215e 55 uint8_t CadDone : 1; // 2
dudmuck 2:fdae76e1215e 56 uint8_t TxDone : 1; // 3
dudmuck 2:fdae76e1215e 57 uint8_t ValidHeader : 1; // 4
dudmuck 2:fdae76e1215e 58 uint8_t PayloadCrcError : 1; // 5
dudmuck 2:fdae76e1215e 59 uint8_t RxDone : 1; // 6
dudmuck 2:fdae76e1215e 60 uint8_t RxTimeout : 1; // 7
dudmuck 2:fdae76e1215e 61 } bits;
dudmuck 2:fdae76e1215e 62 uint8_t octet;
dudmuck 2:fdae76e1215e 63 } RegIrqFlags_t;
dudmuck 2:fdae76e1215e 64
dudmuck 2:fdae76e1215e 65 typedef union {
dudmuck 2:fdae76e1215e 66 struct { // sx127x register 0x18
dudmuck 2:fdae76e1215e 67 uint8_t detect : 1; // 0
dudmuck 2:fdae76e1215e 68 uint8_t sync : 1; // 1
dudmuck 2:fdae76e1215e 69 uint8_t rx_ongoing : 1; // 2
dudmuck 2:fdae76e1215e 70 uint8_t header_valid : 1; // 3
dudmuck 2:fdae76e1215e 71 uint8_t clear : 1; // 4
dudmuck 2:fdae76e1215e 72 uint8_t RxCodingRate : 3; // 5,6,7
dudmuck 2:fdae76e1215e 73 } bits;
dudmuck 2:fdae76e1215e 74 uint8_t octet;
dudmuck 2:fdae76e1215e 75 } RegModemStatus_t;
dudmuck 2:fdae76e1215e 76
dudmuck 2:fdae76e1215e 77 typedef union {
dudmuck 2:fdae76e1215e 78 struct { // sx127x register 0x1c
dudmuck 2:fdae76e1215e 79 uint8_t FhssPresentChannel : 6; // 0,1,2,3,4,5
dudmuck 2:fdae76e1215e 80 uint8_t RxPayloadCrcOn : 1; // 6
dudmuck 2:fdae76e1215e 81 uint8_t PllTimeout : 1; // 7
dudmuck 2:fdae76e1215e 82 } bits;
dudmuck 2:fdae76e1215e 83 uint8_t octet;
dudmuck 2:fdae76e1215e 84 } RegHopChannel_t;
dudmuck 2:fdae76e1215e 85
dudmuck 2:fdae76e1215e 86 typedef union {
dudmuck 2:fdae76e1215e 87 struct { // sx1276 register 0x1d
dudmuck 2:fdae76e1215e 88 uint8_t ImplicitHeaderModeOn : 1; // 0
dudmuck 2:fdae76e1215e 89 uint8_t CodingRate : 3; // 1,2,3
dudmuck 2:fdae76e1215e 90 uint8_t Bw : 4; // 4,5,6,7
dudmuck 2:fdae76e1215e 91 } sx1276bits;
dudmuck 2:fdae76e1215e 92 struct { // sx1272 register 0x1d
dudmuck 2:fdae76e1215e 93 uint8_t LowDataRateOptimize : 1; // 0 ppm_offset: number of cyclic shifts possible to encode to symbol
dudmuck 2:fdae76e1215e 94 uint8_t RxPayloadCrcOn : 1; // 1
dudmuck 2:fdae76e1215e 95 uint8_t ImplicitHeaderModeOn : 1; // 2
dudmuck 2:fdae76e1215e 96 uint8_t CodingRate : 3; // 3,4,5
dudmuck 2:fdae76e1215e 97 uint8_t Bw : 2; // 6,7
dudmuck 2:fdae76e1215e 98 } sx1272bits;
dudmuck 2:fdae76e1215e 99 uint8_t octet;
dudmuck 2:fdae76e1215e 100 } RegModemConfig_t;
dudmuck 2:fdae76e1215e 101
dudmuck 2:fdae76e1215e 102 typedef union {
dudmuck 2:fdae76e1215e 103 struct { // sx1276 register 0x1e
dudmuck 2:fdae76e1215e 104 uint8_t SymbTimeoutMsb : 2; // 0,1
dudmuck 2:fdae76e1215e 105 uint8_t RxPayloadCrcOn : 1; // 2
dudmuck 2:fdae76e1215e 106 uint8_t TxContinuousMode : 1; // 3
dudmuck 2:fdae76e1215e 107 uint8_t SpreadingFactor : 4; // 4,5,6,7
dudmuck 2:fdae76e1215e 108 } sx1276bits;
dudmuck 2:fdae76e1215e 109 struct { // sx1272 register 0x1e
dudmuck 2:fdae76e1215e 110 uint8_t SymbTimeoutMsb : 2; // 0,1
dudmuck 2:fdae76e1215e 111 uint8_t AgcAutoOn : 1; // 2
dudmuck 2:fdae76e1215e 112 uint8_t TxContinuousMode : 1; // 3
dudmuck 2:fdae76e1215e 113 uint8_t SpreadingFactor : 4; // 4,5,6,7
dudmuck 2:fdae76e1215e 114 } sx1272bits;
dudmuck 2:fdae76e1215e 115 uint8_t octet;
dudmuck 2:fdae76e1215e 116 } RegModemConfig2_t;
dudmuck 2:fdae76e1215e 117
dudmuck 2:fdae76e1215e 118 typedef union {
dudmuck 2:fdae76e1215e 119 struct { // sx127x register 0x26
dudmuck 2:fdae76e1215e 120 uint8_t reserved : 2; // 0,1
dudmuck 2:fdae76e1215e 121 uint8_t AgcAutoOn : 1; // 2
dudmuck 10:7382c260c4b1 122 uint8_t LowDataRateOptimize : 1; // 3 ppm_offset, use when symbol duration exceeds 16ms
dudmuck 2:fdae76e1215e 123 uint8_t unused : 4; // 4,5,6,7
dudmuck 2:fdae76e1215e 124 } sx1276bits;
dudmuck 2:fdae76e1215e 125 uint8_t octet;
dudmuck 2:fdae76e1215e 126 uint8_t sx1272_ppm_correction_msb;
dudmuck 2:fdae76e1215e 127 } RegModemConfig3_t;
dudmuck 2:fdae76e1215e 128
dudmuck 2:fdae76e1215e 129
dudmuck 2:fdae76e1215e 130 typedef union {
dudmuck 2:fdae76e1215e 131 struct { // sx127x register 0x31
dudmuck 2:fdae76e1215e 132 uint8_t detect_trig_same_peaks_nb : 3; // 0,1,2
dudmuck 2:fdae76e1215e 133 uint8_t disable_pll_timeout : 1; // 3
dudmuck 2:fdae76e1215e 134 uint8_t tracking_intergral : 2; // 4,5
dudmuck 2:fdae76e1215e 135 uint8_t frame_sync_gain : 1; // 6
dudmuck 2:fdae76e1215e 136 uint8_t if_freq_auto : 1; // 7
dudmuck 2:fdae76e1215e 137 } bits;
dudmuck 2:fdae76e1215e 138 uint8_t octet;
dudmuck 2:fdae76e1215e 139 } RegTest31_t;
dudmuck 2:fdae76e1215e 140
dudmuck 15:3f3fc6792f97 141 typedef union {
dudmuck 15:3f3fc6792f97 142 struct { // sx127x register 0x33
dudmuck 17:59279bc8cdab 143 uint8_t chirp_invert_tx : 1; // 0 invert TX spreading sequence (default=1)
dudmuck 17:59279bc8cdab 144 uint8_t chirp_invert_rx : 1; // 1 invert chip direction in RX mode (default=1)
dudmuck 15:3f3fc6792f97 145 uint8_t sync_detect_th : 1; // 2 require 6dB despread SNR during preamble
dudmuck 15:3f3fc6792f97 146 uint8_t invert_coef_phase : 1; // 3
dudmuck 15:3f3fc6792f97 147 uint8_t invert_coef_amp : 1; // 4
dudmuck 15:3f3fc6792f97 148 uint8_t quad_correction_en : 1; // 5 enable IQ compensation
dudmuck 17:59279bc8cdab 149 uint8_t invert_i_q : 1; // 6 RX invert (default=0)
dudmuck 15:3f3fc6792f97 150 uint8_t start_rambist : 1; // 7
dudmuck 15:3f3fc6792f97 151 } bits;
dudmuck 15:3f3fc6792f97 152 uint8_t octet;
dudmuck 15:3f3fc6792f97 153 } RegTest33_t;
dudmuck 15:3f3fc6792f97 154
dudmuck 17:59279bc8cdab 155 typedef union {
dudmuck 18:0ecb6adb7c0b 156 struct { // sx1276 register 0x36
dudmuck 26:4876e515ff4c 157 uint8_t freq_to_time_drift_auto : 1; // 0 manual control of 0x3a register (1=auto)
dudmuck 26:4876e515ff4c 158 uint8_t sd_max_freq_deviation_auto : 1; // 1 manual control of 0x3b[3:1] (1=auto)
dudmuck 18:0ecb6adb7c0b 159 uint8_t reserved : 6; //
dudmuck 18:0ecb6adb7c0b 160 } bits;
dudmuck 18:0ecb6adb7c0b 161 uint8_t octet;
dudmuck 18:0ecb6adb7c0b 162 } RegAutoDrift_t;
dudmuck 18:0ecb6adb7c0b 163
dudmuck 18:0ecb6adb7c0b 164 typedef union {
dudmuck 18:0ecb6adb7c0b 165 struct { // sx127x register 0x3a
dudmuck 18:0ecb6adb7c0b 166 uint8_t freq_to_time_drift : 6; // 0,1,2,3,4,5 manual control of 0x3a register
dudmuck 18:0ecb6adb7c0b 167 uint8_t preamble_timing_gain : 1; // 6,7
dudmuck 18:0ecb6adb7c0b 168 } bits;
dudmuck 18:0ecb6adb7c0b 169 uint8_t octet;
dudmuck 18:0ecb6adb7c0b 170 } RegGainDrift_t;
dudmuck 18:0ecb6adb7c0b 171
dudmuck 18:0ecb6adb7c0b 172 typedef union {
dudmuck 17:59279bc8cdab 173 struct { // sx127x register 0x3b
dudmuck 17:59279bc8cdab 174 uint8_t coarse_sync : 1; // 0 must be set to 1
dudmuck 17:59279bc8cdab 175 uint8_t fine_sync : 1; // 1 must be clr to 0
dudmuck 17:59279bc8cdab 176 uint8_t invert_timing_error_per_symbol : 1; // 2 set to !invert_i_q
dudmuck 17:59279bc8cdab 177 uint8_t invert_freq_error : 1; // 3
dudmuck 17:59279bc8cdab 178 uint8_t invert_delta_sampling : 1; // 4 must be set to 1
dudmuck 17:59279bc8cdab 179 uint8_t reserved : 1; // 5 must be clr to 0
dudmuck 17:59279bc8cdab 180 uint8_t invert_fast_timing : 1; // 6
dudmuck 17:59279bc8cdab 181 uint8_t invert_carry_in : 1; // 7
dudmuck 17:59279bc8cdab 182 } bits;
dudmuck 17:59279bc8cdab 183 uint8_t octet;
dudmuck 17:59279bc8cdab 184 } RegDriftInvert_t;
dudmuck 17:59279bc8cdab 185
dudmuck 17:59279bc8cdab 186
dudmuck 2:fdae76e1215e 187 //class SX127x_lora : public SX127x
dudmuck 2:fdae76e1215e 188 class SX127x_lora {
dudmuck 2:fdae76e1215e 189 public:
dudmuck 2:fdae76e1215e 190 //SX127x_lora(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1, PinName fem_ctx, PinName fem_cps);
dudmuck 3:3bf2515b1eed 191 SX127x_lora(SX127x& r);
dudmuck 2:fdae76e1215e 192
dudmuck 2:fdae76e1215e 193 ~SX127x_lora();
dudmuck 2:fdae76e1215e 194
dudmuck 2:fdae76e1215e 195 /** changes from FSK mode to LoRa mdoe */
dudmuck 2:fdae76e1215e 196 void enable(void);
dudmuck 2:fdae76e1215e 197
dudmuck 2:fdae76e1215e 198 /** fills radio FIFO with payload contents, prior to transmission
dudmuck 2:fdae76e1215e 199 * @param len count of bytes to put into FIFO
dudmuck 2:fdae76e1215e 200 * @note tx_buf[] should contain desired payload (to send) prior to calling
dudmuck 2:fdae76e1215e 201 */
dudmuck 2:fdae76e1215e 202 void write_fifo(uint8_t len);
dudmuck 2:fdae76e1215e 203
dudmuck 2:fdae76e1215e 204 /** transmit a packet
dudmuck 2:fdae76e1215e 205 * @param len size of packet
dudmuck 2:fdae76e1215e 206 * @note Limited to (lora fifo size 256)
dudmuck 2:fdae76e1215e 207 */
dudmuck 2:fdae76e1215e 208 void start_tx(uint8_t len);
dudmuck 2:fdae76e1215e 209
dudmuck 19:1ee6ef1ab73f 210 /** start continuous receive mode
dudmuck 27:da6341d9d5b1 211 * @param mode RF_OPMODE_RECEIVER or RF_OPMODE_RECEIVER_SINGLE
dudmuck 2:fdae76e1215e 212 * @note the variable service_action needs to be monitored to indicate read_fifo() needs to be called to pull packet from FIFO.
dudmuck 2:fdae76e1215e 213 */
dudmuck 27:da6341d9d5b1 214 void start_rx(chip_mode_e mode);
dudmuck 2:fdae76e1215e 215
dudmuck 2:fdae76e1215e 216 /** Called by main program when indicated by service_action variable, to pull recevied packet from radio FIFO.
dudmuck 2:fdae76e1215e 217 * @returns count of bytes received
dudmuck 2:fdae76e1215e 218 * @note received packet in rx_buf[]
dudmuck 2:fdae76e1215e 219 */
dudmuck 2:fdae76e1215e 220 void read_fifo(uint8_t len);
dudmuck 2:fdae76e1215e 221
dudmuck 2:fdae76e1215e 222 /** CodingRate: how much FEC to encoding onto packet */
dudmuck 2:fdae76e1215e 223 uint8_t getCodingRate(bool from_rx); // false:transmitted, true:last recevied packet
dudmuck 2:fdae76e1215e 224 void setCodingRate(uint8_t cr);
dudmuck 2:fdae76e1215e 225
dudmuck 2:fdae76e1215e 226 /** HeaderMode: explicit mode sents CodingRate and payload length, implicit mode requires assumption by receiver */
dudmuck 2:fdae76e1215e 227 bool getHeaderMode(void);
dudmuck 2:fdae76e1215e 228 void setHeaderMode(bool hm);
dudmuck 2:fdae76e1215e 229
dudmuck 2:fdae76e1215e 230 /** bandwidth: SX1272 has three bandwidths. SX1276 adds more narrower bandwidths. */
dudmuck 2:fdae76e1215e 231 uint8_t getBw(void);
dudmuck 2:fdae76e1215e 232 void setBw(uint8_t bw);
dudmuck 2:fdae76e1215e 233
dudmuck 16:3de8e1c465eb 234 /** Set bandwidth in KHz *
dudmuck 16:3de8e1c465eb 235 * @param khz lora bandwidth in KHz
dudmuck 16:3de8e1c465eb 236 */
dudmuck 16:3de8e1c465eb 237 void setBw_KHz(int khz);
dudmuck 16:3de8e1c465eb 238
dudmuck 2:fdae76e1215e 239 /** spreading factor: trade-off between data rate and processing gain (link budget) */
dudmuck 2:fdae76e1215e 240 uint8_t getSf(void);
dudmuck 2:fdae76e1215e 241 void setSf(uint8_t sf);
dudmuck 2:fdae76e1215e 242
dudmuck 2:fdae76e1215e 243 /** enable CRC in transmitted packet */
dudmuck 2:fdae76e1215e 244 bool getRxPayloadCrcOn(void);
dudmuck 2:fdae76e1215e 245 void setRxPayloadCrcOn(bool);
dudmuck 2:fdae76e1215e 246
dudmuck 2:fdae76e1215e 247 bool getAgcAutoOn(void);
dudmuck 2:fdae76e1215e 248 void setAgcAutoOn(bool);
dudmuck 2:fdae76e1215e 249
dudmuck 23:1df3dddcb43e 250 int get_pkt_rssi(void);
dudmuck 23:1df3dddcb43e 251 int get_current_rssi(void);
dudmuck 2:fdae76e1215e 252
dudmuck 10:7382c260c4b1 253 /** retrieve symbol duration from bandwidth and spreading factor
dudmuck 10:7382c260c4b1 254 * @returns symbol duration in milliseconds
dudmuck 10:7382c260c4b1 255 */
dudmuck 10:7382c260c4b1 256 float get_symbol_period(void);
dudmuck 10:7382c260c4b1 257
dudmuck 2:fdae76e1215e 258 service_action_e service(void); // (SLIH) ISR bottom half
dudmuck 2:fdae76e1215e 259
dudmuck 2:fdae76e1215e 260 bool poll_vh;
dudmuck 2:fdae76e1215e 261
dudmuck 14:f39b9bf5290f 262 void set_nb_trig_peaks(int);
dudmuck 14:f39b9bf5290f 263
dudmuck 15:3f3fc6792f97 264 /** get receiver difference in RF frequency
dudmuck 15:3f3fc6792f97 265 * @returns hertz
dudmuck 15:3f3fc6792f97 266 * @note if receiver is lower in frequency than transmitter, a negative Hz will be returned
dudmuck 15:3f3fc6792f97 267 */
dudmuck 15:3f3fc6792f97 268 int get_freq_error_Hz(void);
dudmuck 15:3f3fc6792f97 269
dudmuck 17:59279bc8cdab 270
dudmuck 17:59279bc8cdab 271 /** invert transmitted spectrum */
dudmuck 17:59279bc8cdab 272 void invert_tx(bool);
dudmuck 17:59279bc8cdab 273
dudmuck 17:59279bc8cdab 274 /** invert spectrum on receiver */
dudmuck 17:59279bc8cdab 275 void invert_rx(bool);
dudmuck 17:59279bc8cdab 276
dudmuck 2:fdae76e1215e 277 RegIrqFlags_t RegIrqFlags; // 0x12
dudmuck 2:fdae76e1215e 278 uint8_t RegRxNbBytes; // 0x13
dudmuck 2:fdae76e1215e 279 RegModemStatus_t RegModemStatus; // 0x18
dudmuck 2:fdae76e1215e 280 int8_t RegPktSnrValue; // 0x19 signed, s/n can be negative
dudmuck 2:fdae76e1215e 281 uint8_t RegPktRssiValue; // 0x1a
dudmuck 2:fdae76e1215e 282 RegHopChannel_t RegHopChannel; // 0x1c
dudmuck 2:fdae76e1215e 283 RegModemConfig_t RegModemConfig; // 0x1d
dudmuck 2:fdae76e1215e 284 RegModemConfig2_t RegModemConfig2; // 0x1e
dudmuck 2:fdae76e1215e 285 uint16_t RegPreamble; // 0x20->0x21
dudmuck 2:fdae76e1215e 286 uint8_t RegPayloadLength; // 0x22
dudmuck 2:fdae76e1215e 287 uint8_t RegRxMaxPayloadLength; // 0x23
dudmuck 2:fdae76e1215e 288 uint8_t RegHopPeriod; // 0x24
dudmuck 2:fdae76e1215e 289 RegModemConfig3_t RegModemConfig3; // 0x26
dudmuck 2:fdae76e1215e 290 RegTest31_t RegTest31; // 0x31
dudmuck 17:59279bc8cdab 291 RegTest33_t RegTest33; // 0x33
dudmuck 19:1ee6ef1ab73f 292 RegAutoDrift_t RegAutoDrift; // 0x36 sx1276 only
dudmuck 19:1ee6ef1ab73f 293 RegGainDrift_t RegGainDrift; // 0x3a
dudmuck 17:59279bc8cdab 294 RegDriftInvert_t RegDriftInvert; // 0x3b
dudmuck 2:fdae76e1215e 295
dudmuck 19:1ee6ef1ab73f 296
dudmuck 9:ae1a71ccd730 297 SX127x& m_xcvr;
dudmuck 12:bda42457c34a 298
dudmuck 2:fdae76e1215e 299 private:
dudmuck 14:f39b9bf5290f 300
dudmuck 2:fdae76e1215e 301 };