wayne roberts / SX127x

Driver library for SX1272/SX1276 transceivers

Dependents:   LORA_RX LORA_TX WindConcentrator hid_test ... more

/media/uploads/dudmuck/lora.png

Driver library for SX1272 and SX1276 radio transceivers.

This device uses CSS modulation to provide much improved link budget. The RF hardware is same as in FSK devices, just with added LoRa spread-spectrum modem.

This library provides functions to configure radio chip and transmit & receive packets.

Using This Library

Library function service_radio() must be called continuously from main loop, to service interrupts from radio.

/media/uploads/dudmuck/sx1272rf1_connector_300.jpg

Board Specific implementation

FunctionPointer for rf_switch callback allows the program to implement control of RF switch unique to their board. Example options are:

  • SKY13373 for external power amplifier implementation. Requires two DigitalOut pins.
  • SKY13350 using PA_BOOST. requires two DigitalOut pins.
  • PE4259-63: controlled directly by radio chip, no software function needed. However, in the case of SX1276MB1xAS, the RXTX pin on IO2 should be driven by this callback function when R16 is installed (without R15) on this shield board.

Some configurations may need to force the use of RFO or PA_BOOST, or a board could offer both options. The rf_switch function pointer callback should support the implementation choice on the board.

further reading

sx127x_fsk.cpp@8:c9592cbc9f86, 2015-02-18 (annotated)

Committer:
dudmuck
Date:
Wed Feb 18 16:53:36 2015 +0000
Revision:
8:c9592cbc9f86
Parent:
4:d987ac2836bf
Child:
12:bda42457c34a
fixed error in setSf() for SX1276

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 2:fdae76e1215e 1 #include "sx127x_fsk.h"
dudmuck 2:fdae76e1215e 2
dudmuck 2:fdae76e1215e 3 /* SX127x driver
dudmuck 2:fdae76e1215e 4 * Copyright (c) 2013 Semtech
dudmuck 2:fdae76e1215e 5 *
dudmuck 2:fdae76e1215e 6 * Licensed under the Apache License, Version 2.0 (the "License");
dudmuck 2:fdae76e1215e 7 * you may not use this file except in compliance with the License.
dudmuck 2:fdae76e1215e 8 * You may obtain a copy of the License at
dudmuck 2:fdae76e1215e 9 *
dudmuck 2:fdae76e1215e 10 * http://www.apache.org/licenses/LICENSE-2.0
dudmuck 2:fdae76e1215e 11 *
dudmuck 2:fdae76e1215e 12 * Unless required by applicable law or agreed to in writing, software
dudmuck 2:fdae76e1215e 13 * distributed under the License is distributed on an "AS IS" BASIS,
dudmuck 2:fdae76e1215e 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dudmuck 2:fdae76e1215e 15 * See the License for the specific language governing permissions and
dudmuck 2:fdae76e1215e 16 * limitations under the License.
dudmuck 2:fdae76e1215e 17 */
dudmuck 3:3bf2515b1eed 18
dudmuck 3:3bf2515b1eed 19 SX127x_fsk::SX127x_fsk(SX127x& r) : m_xcvr(r)
dudmuck 2:fdae76e1215e 20 {
dudmuck 2:fdae76e1215e 21 }
dudmuck 2:fdae76e1215e 22
dudmuck 2:fdae76e1215e 23 SX127x_fsk::~SX127x_fsk()
dudmuck 2:fdae76e1215e 24 {
dudmuck 2:fdae76e1215e 25 }
dudmuck 2:fdae76e1215e 26
dudmuck 2:fdae76e1215e 27 void SX127x_fsk::write_fifo(uint8_t len)
dudmuck 2:fdae76e1215e 28 {
dudmuck 2:fdae76e1215e 29 int i;
dudmuck 2:fdae76e1215e 30
dudmuck 2:fdae76e1215e 31 m_xcvr.m_cs = 0;
dudmuck 2:fdae76e1215e 32 m_xcvr.m_spi.write(REG_FIFO | 0x80); // bit7 is high for writing to radio
dudmuck 2:fdae76e1215e 33
dudmuck 3:3bf2515b1eed 34 if (!m_xcvr.RegOpMode.bits.LongRangeMode && RegPktConfig1.bits.PacketFormatVariable) {
dudmuck 2:fdae76e1215e 35 m_xcvr.m_spi.write(len);
dudmuck 3:3bf2515b1eed 36 }
dudmuck 2:fdae76e1215e 37
dudmuck 2:fdae76e1215e 38 for (i = 0; i < len; i++) {
dudmuck 2:fdae76e1215e 39 m_xcvr.m_spi.write(m_xcvr.tx_buf[i]);
dudmuck 2:fdae76e1215e 40 }
dudmuck 2:fdae76e1215e 41 m_xcvr.m_cs = 1;
dudmuck 2:fdae76e1215e 42 }
dudmuck 2:fdae76e1215e 43
dudmuck 2:fdae76e1215e 44 void SX127x_fsk::enable()
dudmuck 2:fdae76e1215e 45 {
dudmuck 2:fdae76e1215e 46 m_xcvr.set_opmode(RF_OPMODE_SLEEP);
dudmuck 2:fdae76e1215e 47
dudmuck 2:fdae76e1215e 48 m_xcvr.RegOpMode.bits.LongRangeMode = 0;
dudmuck 2:fdae76e1215e 49 m_xcvr.write_reg(REG_OPMODE, m_xcvr.RegOpMode.octet);
dudmuck 2:fdae76e1215e 50 wait(0.01);
dudmuck 2:fdae76e1215e 51
dudmuck 2:fdae76e1215e 52 RegPktConfig1.octet = m_xcvr.read_reg(REG_FSK_PACKETCONFIG1);
dudmuck 2:fdae76e1215e 53 RegPktConfig2.word = m_xcvr.read_u16(REG_FSK_PACKETCONFIG2);
dudmuck 3:3bf2515b1eed 54 RegRxConfig.octet = m_xcvr.read_u16(REG_FSK_RXCONFIG);
dudmuck 3:3bf2515b1eed 55 RegPreambleDetect.octet = m_xcvr.read_reg(REG_FSK_PREAMBLEDETECT);
dudmuck 3:3bf2515b1eed 56 RegSyncConfig.octet = m_xcvr.read_reg(REG_FSK_SYNCCONFIG);
dudmuck 3:3bf2515b1eed 57 RegFifoThreshold.octet = m_xcvr.read_reg(REG_FSK_FIFOTHRESH);
dudmuck 3:3bf2515b1eed 58 RegAfcFei.octet = m_xcvr.read_reg(REG_FSK_AFCFEI);
dudmuck 3:3bf2515b1eed 59
dudmuck 3:3bf2515b1eed 60 if (!RegFifoThreshold.bits.TxStartCondition) {
dudmuck 3:3bf2515b1eed 61 RegFifoThreshold.bits.TxStartCondition = 1; // start TX on fifoEmpty==0
dudmuck 3:3bf2515b1eed 62 m_xcvr.write_reg(REG_FSK_FIFOTHRESH, RegFifoThreshold.octet);
dudmuck 3:3bf2515b1eed 63 }
dudmuck 3:3bf2515b1eed 64
dudmuck 3:3bf2515b1eed 65 if (RegSyncConfig.bits.AutoRestartRxMode != 1) {
dudmuck 3:3bf2515b1eed 66 RegSyncConfig.bits.AutoRestartRxMode = 1;
dudmuck 3:3bf2515b1eed 67 m_xcvr.write_reg(REG_FSK_SYNCCONFIG, RegSyncConfig.octet);
dudmuck 3:3bf2515b1eed 68 }
dudmuck 3:3bf2515b1eed 69
dudmuck 3:3bf2515b1eed 70 if (RegPreambleDetect.bits.PreambleDetectorTol != 10) {
dudmuck 3:3bf2515b1eed 71 RegPreambleDetect.bits.PreambleDetectorTol = 10;
dudmuck 3:3bf2515b1eed 72 m_xcvr.write_reg(REG_FSK_PREAMBLEDETECT, RegPreambleDetect.octet);
dudmuck 3:3bf2515b1eed 73 }
dudmuck 2:fdae76e1215e 74
dudmuck 2:fdae76e1215e 75 m_xcvr.set_opmode(RF_OPMODE_STANDBY);
dudmuck 2:fdae76e1215e 76 }
dudmuck 2:fdae76e1215e 77
dudmuck 4:d987ac2836bf 78 void SX127x_fsk::init()
dudmuck 4:d987ac2836bf 79 {
dudmuck 4:d987ac2836bf 80 m_xcvr.set_opmode(RF_OPMODE_STANDBY);
dudmuck 4:d987ac2836bf 81
dudmuck 4:d987ac2836bf 82 RegRxConfig.bits.RxTrigger = 6; // have RX restart (trigger) on preamble detection
dudmuck 4:d987ac2836bf 83 RegRxConfig.bits.AfcAutoOn = 1; // have AFC performed on RX restart (RX trigger)
dudmuck 4:d987ac2836bf 84 m_xcvr.write_reg(REG_FSK_RXCONFIG, RegRxConfig.octet);
dudmuck 4:d987ac2836bf 85
dudmuck 4:d987ac2836bf 86 RegPreambleDetect.bits.PreambleDetectorOn = 1; // enable preamble detector
dudmuck 4:d987ac2836bf 87 m_xcvr.write_reg(REG_FSK_PREAMBLEDETECT, RegPreambleDetect.octet);
dudmuck 4:d987ac2836bf 88
dudmuck 4:d987ac2836bf 89 m_xcvr.write_reg(REG_FSK_SYNCVALUE1, 0x55);
dudmuck 4:d987ac2836bf 90 m_xcvr.write_reg(REG_FSK_SYNCVALUE2, 0x6f);
dudmuck 4:d987ac2836bf 91 m_xcvr.write_reg(REG_FSK_SYNCVALUE3, 0x4e);
dudmuck 4:d987ac2836bf 92 RegSyncConfig.bits.SyncSize = 2;
dudmuck 4:d987ac2836bf 93 m_xcvr.write_reg(REG_FSK_SYNCCONFIG, RegSyncConfig.octet);
dudmuck 4:d987ac2836bf 94
dudmuck 4:d987ac2836bf 95 // in case these were changed from default:
dudmuck 4:d987ac2836bf 96 set_bitrate(4800);
dudmuck 4:d987ac2836bf 97 set_tx_fdev_hz(5050);
dudmuck 4:d987ac2836bf 98 set_rx_dcc_bw_hz(10500, 0); // rxbw
dudmuck 4:d987ac2836bf 99 set_rx_dcc_bw_hz(50000, 1); // afcbw
dudmuck 4:d987ac2836bf 100 }
dudmuck 4:d987ac2836bf 101
dudmuck 4:d987ac2836bf 102 uint32_t SX127x_fsk::get_bitrate()
dudmuck 4:d987ac2836bf 103 {
dudmuck 4:d987ac2836bf 104 uint16_t br = m_xcvr.read_u16(REG_FSK_BITRATEMSB);
dudmuck 4:d987ac2836bf 105
dudmuck 4:d987ac2836bf 106 if (br == 0)
dudmuck 4:d987ac2836bf 107 return 0;
dudmuck 4:d987ac2836bf 108 else
dudmuck 4:d987ac2836bf 109 return XTAL_FREQ / br;
dudmuck 4:d987ac2836bf 110 }
dudmuck 4:d987ac2836bf 111
dudmuck 4:d987ac2836bf 112 void SX127x_fsk::set_bitrate(uint32_t bps)
dudmuck 4:d987ac2836bf 113 {
dudmuck 4:d987ac2836bf 114 uint16_t tmpBitrate = XTAL_FREQ / bps;
dudmuck 4:d987ac2836bf 115 //printf("tmpBitrate:%d = %d / %d\r\n", tmpBitrate, XTAL_FREQ, bps);
dudmuck 4:d987ac2836bf 116 m_xcvr.write_u16(REG_FSK_BITRATEMSB, tmpBitrate);
dudmuck 4:d987ac2836bf 117 }
dudmuck 4:d987ac2836bf 118
dudmuck 4:d987ac2836bf 119 void SX127x_fsk::set_tx_fdev_hz(uint32_t hz)
dudmuck 4:d987ac2836bf 120 {
dudmuck 4:d987ac2836bf 121 float tmpFdev = hz / FREQ_STEP_HZ;
dudmuck 4:d987ac2836bf 122 uint16_t v;
dudmuck 4:d987ac2836bf 123 //printf("tmpFdev:%f = %d / %f\r\n", tmpFdev, hz, FREQ_STEP_HZ);
dudmuck 4:d987ac2836bf 124 v = (uint16_t)tmpFdev;
dudmuck 4:d987ac2836bf 125 m_xcvr.write_u16(REG_FSK_FDEVMSB, v);
dudmuck 4:d987ac2836bf 126 }
dudmuck 4:d987ac2836bf 127
dudmuck 4:d987ac2836bf 128 uint32_t SX127x_fsk::get_tx_fdev_hz(void)
dudmuck 4:d987ac2836bf 129 {
dudmuck 4:d987ac2836bf 130 uint16_t fdev = m_xcvr.read_u16(REG_FSK_FDEVMSB);
dudmuck 4:d987ac2836bf 131 return fdev * FREQ_STEP_HZ;
dudmuck 4:d987ac2836bf 132 }
dudmuck 4:d987ac2836bf 133
dudmuck 2:fdae76e1215e 134 uint32_t SX127x_fsk::ComputeRxBw( uint8_t mantisse, uint8_t exponent )
dudmuck 2:fdae76e1215e 135 {
dudmuck 2:fdae76e1215e 136 // rxBw
dudmuck 2:fdae76e1215e 137 if (m_xcvr.RegOpMode.bits.ModulationType == 0)
dudmuck 2:fdae76e1215e 138 return XTAL_FREQ / (mantisse * (1 << (exponent+2)));
dudmuck 2:fdae76e1215e 139 else
dudmuck 2:fdae76e1215e 140 return XTAL_FREQ / (mantisse * (1 << (exponent+3)));
dudmuck 2:fdae76e1215e 141 }
dudmuck 2:fdae76e1215e 142
dudmuck 2:fdae76e1215e 143
dudmuck 2:fdae76e1215e 144 void SX127x_fsk::ComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent )
dudmuck 2:fdae76e1215e 145 {
dudmuck 2:fdae76e1215e 146 uint8_t tmpExp, tmpMant;
dudmuck 2:fdae76e1215e 147 double tmpRxBw;
dudmuck 2:fdae76e1215e 148 double rxBwMin = 10e6;
dudmuck 2:fdae76e1215e 149
dudmuck 2:fdae76e1215e 150 for( tmpExp = 0; tmpExp < 8; tmpExp++ ) {
dudmuck 2:fdae76e1215e 151 for( tmpMant = 16; tmpMant <= 24; tmpMant += 4 ) {
dudmuck 2:fdae76e1215e 152 tmpRxBw = ComputeRxBw(tmpMant, tmpExp);
dudmuck 2:fdae76e1215e 153 if( fabs( tmpRxBw - rxBwValue ) < rxBwMin ) {
dudmuck 2:fdae76e1215e 154 rxBwMin = fabs( tmpRxBw - rxBwValue );
dudmuck 2:fdae76e1215e 155 *mantisse = tmpMant;
dudmuck 2:fdae76e1215e 156 *exponent = tmpExp;
dudmuck 2:fdae76e1215e 157 }
dudmuck 2:fdae76e1215e 158 }
dudmuck 2:fdae76e1215e 159 }
dudmuck 2:fdae76e1215e 160 }
dudmuck 2:fdae76e1215e 161
dudmuck 2:fdae76e1215e 162
dudmuck 2:fdae76e1215e 163 uint32_t SX127x_fsk::get_rx_bw_hz(uint8_t addr)
dudmuck 2:fdae76e1215e 164 {
dudmuck 3:3bf2515b1eed 165 RegRxBw_t reg_bw;
dudmuck 2:fdae76e1215e 166 uint8_t mantissa;
dudmuck 2:fdae76e1215e 167
dudmuck 2:fdae76e1215e 168 if (m_xcvr.RegOpMode.bits.LongRangeMode)
dudmuck 2:fdae76e1215e 169 return 0;
dudmuck 2:fdae76e1215e 170
dudmuck 2:fdae76e1215e 171 reg_bw.octet = m_xcvr.read_reg(addr);
dudmuck 2:fdae76e1215e 172 switch (reg_bw.bits.Mantissa) {
dudmuck 2:fdae76e1215e 173 case 0: mantissa = 16; break;
dudmuck 2:fdae76e1215e 174 case 1: mantissa = 20; break;
dudmuck 2:fdae76e1215e 175 case 2: mantissa = 24; break;
dudmuck 2:fdae76e1215e 176 default: mantissa = 0; break;
dudmuck 2:fdae76e1215e 177 }
dudmuck 2:fdae76e1215e 178
dudmuck 2:fdae76e1215e 179 if (addr == REG_FSK_RXBW)
dudmuck 2:fdae76e1215e 180 RegRxBw.octet = reg_bw.octet;
dudmuck 2:fdae76e1215e 181 else if (addr == REG_FSK_AFCBW)
dudmuck 2:fdae76e1215e 182 RegAfcBw.octet = reg_bw.octet;
dudmuck 2:fdae76e1215e 183
dudmuck 2:fdae76e1215e 184 return ComputeRxBw(mantissa, reg_bw.bits.Exponent);
dudmuck 2:fdae76e1215e 185 }
dudmuck 2:fdae76e1215e 186
dudmuck 2:fdae76e1215e 187
dudmuck 2:fdae76e1215e 188 void SX127x_fsk::set_rx_dcc_bw_hz(uint32_t bw_hz, char afc)
dudmuck 2:fdae76e1215e 189 {
dudmuck 2:fdae76e1215e 190 uint8_t mantisse = 0;
dudmuck 2:fdae76e1215e 191 uint8_t exponent = 0;
dudmuck 2:fdae76e1215e 192
dudmuck 2:fdae76e1215e 193 if (m_xcvr.RegOpMode.bits.LongRangeMode)
dudmuck 2:fdae76e1215e 194 return;
dudmuck 2:fdae76e1215e 195
dudmuck 2:fdae76e1215e 196 ComputeRxBwMantExp( bw_hz, &mantisse, &exponent );
dudmuck 2:fdae76e1215e 197 //printf("bw_hz:%d, mantisse:%d, exponent:%d\n", bw_hz, mantisse, exponent );
dudmuck 2:fdae76e1215e 198 switch( mantisse ) {
dudmuck 2:fdae76e1215e 199 case 16:
dudmuck 2:fdae76e1215e 200 RegRxBw.bits.Mantissa = 0;
dudmuck 2:fdae76e1215e 201 break;
dudmuck 2:fdae76e1215e 202 case 20:
dudmuck 2:fdae76e1215e 203 RegRxBw.bits.Mantissa = 1;
dudmuck 2:fdae76e1215e 204 break;
dudmuck 2:fdae76e1215e 205 case 24:
dudmuck 2:fdae76e1215e 206 RegRxBw.bits.Mantissa = 2;
dudmuck 2:fdae76e1215e 207 break;
dudmuck 2:fdae76e1215e 208 default:
dudmuck 2:fdae76e1215e 209 // Something went terribely wrong
dudmuck 2:fdae76e1215e 210 printf("maintisse:%d\n", mantisse);
dudmuck 2:fdae76e1215e 211 break;
dudmuck 2:fdae76e1215e 212 }
dudmuck 2:fdae76e1215e 213 RegRxBw.bits.Exponent = exponent;
dudmuck 2:fdae76e1215e 214
dudmuck 2:fdae76e1215e 215 if (afc)
dudmuck 2:fdae76e1215e 216 m_xcvr.write_reg(REG_FSK_AFCBW, RegRxBw.octet);
dudmuck 2:fdae76e1215e 217 else
dudmuck 2:fdae76e1215e 218 m_xcvr.write_reg(REG_FSK_RXBW, RegRxBw.octet);
dudmuck 2:fdae76e1215e 219 }
dudmuck 2:fdae76e1215e 220
dudmuck 2:fdae76e1215e 221
dudmuck 2:fdae76e1215e 222 void SX127x_fsk::start_tx(uint16_t arg_len)
dudmuck 2:fdae76e1215e 223 {
dudmuck 2:fdae76e1215e 224 uint16_t pkt_buf_len;
dudmuck 3:3bf2515b1eed 225 RegIrqFlags2_t RegIrqFlags2;
dudmuck 2:fdae76e1215e 226 int maxlen = FSK_FIFO_SIZE-1;
dudmuck 2:fdae76e1215e 227
dudmuck 2:fdae76e1215e 228 if (m_xcvr.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) {
dudmuck 2:fdae76e1215e 229 m_xcvr.set_opmode(RF_OPMODE_STANDBY);
dudmuck 2:fdae76e1215e 230 }
dudmuck 2:fdae76e1215e 231
dudmuck 2:fdae76e1215e 232 if (m_xcvr.RegDioMapping1.bits.Dio0Mapping != 0) {
dudmuck 2:fdae76e1215e 233 m_xcvr.RegDioMapping1.bits.Dio0Mapping = 0;
dudmuck 2:fdae76e1215e 234 m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet);
dudmuck 2:fdae76e1215e 235 }
dudmuck 2:fdae76e1215e 236
dudmuck 2:fdae76e1215e 237 if (RegPktConfig1.bits.PacketFormatVariable) {
dudmuck 2:fdae76e1215e 238 pkt_buf_len = arg_len;
dudmuck 2:fdae76e1215e 239 } else {
dudmuck 2:fdae76e1215e 240 pkt_buf_len = RegPktConfig2.bits.PayloadLength;
dudmuck 2:fdae76e1215e 241 printf("fixed-fmt %d\r\n", pkt_buf_len);
dudmuck 2:fdae76e1215e 242 }
dudmuck 2:fdae76e1215e 243
dudmuck 2:fdae76e1215e 244 RegIrqFlags2.octet = m_xcvr.read_reg(REG_FSK_IRQFLAGS2);
dudmuck 2:fdae76e1215e 245 if (RegIrqFlags2.bits.FifoEmpty) {
dudmuck 2:fdae76e1215e 246 if (RegPktConfig1.bits.PacketFormatVariable) {
dudmuck 2:fdae76e1215e 247 --maxlen; // space for length byte
dudmuck 2:fdae76e1215e 248 if (pkt_buf_len > maxlen) {
dudmuck 2:fdae76e1215e 249 /*setup_FifoLevel(FALLING_EDGE);
dudmuck 2:fdae76e1215e 250 radio_write_fifo_(pkt_buf, maxlen, pkt_buf_len);
dudmuck 2:fdae76e1215e 251 remaining_ = pkt_buf_len - maxlen;
dudmuck 2:fdae76e1215e 252 printf("var-oversized %d R=%d\r\n", pkt_buf_len, remaining_);*/
dudmuck 2:fdae76e1215e 253 printf("var-oversized %d\r\n", pkt_buf_len);
dudmuck 2:fdae76e1215e 254 } else {
dudmuck 8:c9592cbc9f86 255 //setup_FifoLevel(NO_EDGE); // disable
dudmuck 2:fdae76e1215e 256 write_fifo(pkt_buf_len);
dudmuck 2:fdae76e1215e 257 //remaining_ = 0; // all was sent
dudmuck 2:fdae76e1215e 258 }
dudmuck 2:fdae76e1215e 259 } else { // fixed-length pkt format...
dudmuck 2:fdae76e1215e 260 pkt_buf_len = RegPktConfig2.bits.PayloadLength;
dudmuck 2:fdae76e1215e 261 if (RegPktConfig2.bits.PayloadLength > maxlen) {
dudmuck 2:fdae76e1215e 262 /*setup_FifoLevel(FALLING_EDGE);
dudmuck 2:fdae76e1215e 263 radio_write_fifo_(pkt_buf, maxlen, -1);
dudmuck 2:fdae76e1215e 264 remaining_ = SX1272FSK->RegPktConfig2.bits.PayloadLength - maxlen;*/
dudmuck 2:fdae76e1215e 265 printf("todo: fsk large packet\r\n");
dudmuck 2:fdae76e1215e 266 } else {
dudmuck 2:fdae76e1215e 267 //setup_FifoLevel(NO_EDGE); // disable
dudmuck 2:fdae76e1215e 268 printf("fixed-write-fifo %d\r\n", RegPktConfig2.bits.PayloadLength);
dudmuck 2:fdae76e1215e 269 write_fifo(RegPktConfig2.bits.PayloadLength);
dudmuck 2:fdae76e1215e 270 }
dudmuck 2:fdae76e1215e 271 }
dudmuck 2:fdae76e1215e 272 } else
dudmuck 2:fdae76e1215e 273 printf("fifo not empty %02x\r\n", RegIrqFlags2.octet);
dudmuck 2:fdae76e1215e 274
dudmuck 2:fdae76e1215e 275 m_xcvr.set_opmode(RF_OPMODE_TRANSMITTER);
dudmuck 2:fdae76e1215e 276
dudmuck 2:fdae76e1215e 277 }
dudmuck 2:fdae76e1215e 278
dudmuck 3:3bf2515b1eed 279 void SX127x_fsk::config_dio0_for_pktmode_rx()
dudmuck 3:3bf2515b1eed 280 {
dudmuck 3:3bf2515b1eed 281 if (RegPktConfig1.bits.CrcOn) {
dudmuck 3:3bf2515b1eed 282 if (m_xcvr.RegDioMapping1.bits.Dio0Mapping != 1) {
dudmuck 3:3bf2515b1eed 283 m_xcvr.RegDioMapping1.bits.Dio0Mapping = 1; // to CrcOk
dudmuck 3:3bf2515b1eed 284 m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet);
dudmuck 3:3bf2515b1eed 285 }
dudmuck 3:3bf2515b1eed 286 } else { // Crc Off, use PayloadReady
dudmuck 3:3bf2515b1eed 287 if (m_xcvr.RegDioMapping1.bits.Dio0Mapping != 0) {
dudmuck 3:3bf2515b1eed 288 m_xcvr.RegDioMapping1.bits.Dio0Mapping = 0; // to PayloadReady
dudmuck 3:3bf2515b1eed 289 m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet);
dudmuck 3:3bf2515b1eed 290 }
dudmuck 3:3bf2515b1eed 291 }
dudmuck 3:3bf2515b1eed 292 }
dudmuck 2:fdae76e1215e 293
dudmuck 2:fdae76e1215e 294 void SX127x_fsk::start_rx()
dudmuck 2:fdae76e1215e 295 {
dudmuck 2:fdae76e1215e 296 if (m_xcvr.RegOpMode.bits.LongRangeMode)
dudmuck 2:fdae76e1215e 297 return;
dudmuck 2:fdae76e1215e 298
dudmuck 2:fdae76e1215e 299 if (m_xcvr.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) {
dudmuck 2:fdae76e1215e 300 // was already receiving, restart it
dudmuck 2:fdae76e1215e 301 m_xcvr.set_opmode(RF_OPMODE_STANDBY);
dudmuck 2:fdae76e1215e 302 wait(0.01);
dudmuck 2:fdae76e1215e 303 }
dudmuck 3:3bf2515b1eed 304
dudmuck 3:3bf2515b1eed 305 config_dio0_for_pktmode_rx();
dudmuck 3:3bf2515b1eed 306
dudmuck 2:fdae76e1215e 307 m_xcvr.set_opmode(RF_OPMODE_RECEIVER);
dudmuck 2:fdae76e1215e 308 }
dudmuck 2:fdae76e1215e 309
dudmuck 2:fdae76e1215e 310 service_action_e SX127x_fsk::service()
dudmuck 2:fdae76e1215e 311 {
dudmuck 2:fdae76e1215e 312 int i;
dudmuck 2:fdae76e1215e 313
dudmuck 2:fdae76e1215e 314 if (m_xcvr.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) {
dudmuck 2:fdae76e1215e 315 if (m_xcvr.dio0) {
dudmuck 2:fdae76e1215e 316 m_xcvr.set_opmode(RF_OPMODE_STANDBY);
dudmuck 2:fdae76e1215e 317 return SERVICE_TX_DONE;
dudmuck 2:fdae76e1215e 318 }
dudmuck 3:3bf2515b1eed 319 } else if (m_xcvr.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER && m_xcvr.dio0) {
dudmuck 3:3bf2515b1eed 320 if (RegRxConfig.bits.AfcAutoOn)
dudmuck 3:3bf2515b1eed 321 RegAfcValue = m_xcvr.read_s16(REG_FSK_AFCMSB);
dudmuck 3:3bf2515b1eed 322
dudmuck 2:fdae76e1215e 323 if (RegPktConfig1.bits.PacketFormatVariable) {
dudmuck 3:3bf2515b1eed 324 rx_buf_length = m_xcvr.read_reg(REG_FIFO);
dudmuck 2:fdae76e1215e 325 } else {
dudmuck 3:3bf2515b1eed 326 rx_buf_length = RegPktConfig2.bits.PayloadLength;
dudmuck 2:fdae76e1215e 327 }
dudmuck 2:fdae76e1215e 328
dudmuck 2:fdae76e1215e 329 m_xcvr.m_cs = 0;
dudmuck 2:fdae76e1215e 330 m_xcvr.m_spi.write(REG_FIFO); // bit7 is low for reading from radio
dudmuck 3:3bf2515b1eed 331 for (i = 0; i < rx_buf_length; i++) {
dudmuck 2:fdae76e1215e 332 m_xcvr.rx_buf[i] = m_xcvr.m_spi.write(0);
dudmuck 2:fdae76e1215e 333 }
dudmuck 2:fdae76e1215e 334 m_xcvr.m_cs = 1;
dudmuck 2:fdae76e1215e 335 return SERVICE_READ_FIFO;
dudmuck 2:fdae76e1215e 336 }
dudmuck 2:fdae76e1215e 337
dudmuck 2:fdae76e1215e 338 return SERVICE_NONE;
dudmuck 2:fdae76e1215e 339 }