DMA_UART_example - Example of UART-DMA transfers taken form the npx …

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Matt Lloyd / Mbed 2 deprecated DMA_UART_example

Example of UART-DMA transfers taken form the npx cmsis driver libary

lpc17xx_gpdma.h@0:7480abd3b63b, 2010-09-30 (annotated)

Committer:: dpslwk
Date:: Thu Sep 30 20:13:24 2010 +0000
Revision:: 0:7480abd3b63b

Who changed what in which revision?

User	Revision	Line number	New contents of line
dpslwk	0:7480abd3b63b	1	/*********************************************************************//
dpslwk	0:7480abd3b63b	2	* @file lpc17xx_gpdma.h
dpslwk	0:7480abd3b63b	3	* @brief Contains all macro definitions and function prototypes
dpslwk	0:7480abd3b63b	4	* support for GPDMA firmware library on LPC17xx
dpslwk	0:7480abd3b63b	5	* @version 2.0
dpslwk	0:7480abd3b63b	6	* @date 21. May. 2010
dpslwk	0:7480abd3b63b	7	* @author NXP MCU SW Application Team
dpslwk	0:7480abd3b63b	8	**************************************************************************
dpslwk	0:7480abd3b63b	9	* Software that is described herein is for illustrative purposes only
dpslwk	0:7480abd3b63b	10	* which provides customers with programming information regarding the
dpslwk	0:7480abd3b63b	11	* products. This software is supplied "AS IS" without any warranties.
dpslwk	0:7480abd3b63b	12	* NXP Semiconductors assumes no responsibility or liability for the
dpslwk	0:7480abd3b63b	13	* use of the software, conveys no license or title under any patent,
dpslwk	0:7480abd3b63b	14	* copyright, or mask work right to the product. NXP Semiconductors
dpslwk	0:7480abd3b63b	15	* reserves the right to make changes in the software without
dpslwk	0:7480abd3b63b	16	* notification. NXP Semiconductors also make no representation or
dpslwk	0:7480abd3b63b	17	* warranty that such application will be suitable for the specified
dpslwk	0:7480abd3b63b	18	* use without further testing or modification.
dpslwk	0:7480abd3b63b	19	**************************************************************************/
dpslwk	0:7480abd3b63b	20
dpslwk	0:7480abd3b63b	21	/* Peripheral group ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	22	/** @defgroup GPDMA GPDMA
dpslwk	0:7480abd3b63b	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
dpslwk	0:7480abd3b63b	24	* @{
dpslwk	0:7480abd3b63b	25	*/
dpslwk	0:7480abd3b63b	26
dpslwk	0:7480abd3b63b	27	#ifndef LPC17XX_GPDMA_H_
dpslwk	0:7480abd3b63b	28	#define LPC17XX_GPDMA_H_
dpslwk	0:7480abd3b63b	29
dpslwk	0:7480abd3b63b	30	/* Includes ------------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	31	#include "LPC17xx.h"
dpslwk	0:7480abd3b63b	32	#include "lpc_types.h"
dpslwk	0:7480abd3b63b	33
dpslwk	0:7480abd3b63b	34
dpslwk	0:7480abd3b63b	35	#ifdef __cplusplus
dpslwk	0:7480abd3b63b	36	extern "C"
dpslwk	0:7480abd3b63b	37	{
dpslwk	0:7480abd3b63b	38	#endif
dpslwk	0:7480abd3b63b	39
dpslwk	0:7480abd3b63b	40	/* Public Macros -------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	41	/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
dpslwk	0:7480abd3b63b	42	* @{
dpslwk	0:7480abd3b63b	43	*/
dpslwk	0:7480abd3b63b	44
dpslwk	0:7480abd3b63b	45	/** DMA Connection number definitions */
dpslwk	0:7480abd3b63b	46	#define GPDMA_CONN_SSP0_Tx ((0UL)) /*< SSP0 Tx /
dpslwk	0:7480abd3b63b	47	#define GPDMA_CONN_SSP0_Rx ((1UL)) /*< SSP0 Rx /
dpslwk	0:7480abd3b63b	48	#define GPDMA_CONN_SSP1_Tx ((2UL)) /*< SSP1 Tx /
dpslwk	0:7480abd3b63b	49	#define GPDMA_CONN_SSP1_Rx ((3UL)) /*< SSP1 Rx /
dpslwk	0:7480abd3b63b	50	#define GPDMA_CONN_ADC ((4UL)) /*< ADC /
dpslwk	0:7480abd3b63b	51	#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /*< I2S channel 0 /
dpslwk	0:7480abd3b63b	52	#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /*< I2S channel 1 /
dpslwk	0:7480abd3b63b	53	#define GPDMA_CONN_DAC ((7UL)) /*< DAC /
dpslwk	0:7480abd3b63b	54	#define GPDMA_CONN_UART0_Tx ((8UL)) /*< UART0 Tx /
dpslwk	0:7480abd3b63b	55	#define GPDMA_CONN_UART0_Rx ((9UL)) /*< UART0 Rx /
dpslwk	0:7480abd3b63b	56	#define GPDMA_CONN_UART1_Tx ((10UL)) /*< UART1 Tx /
dpslwk	0:7480abd3b63b	57	#define GPDMA_CONN_UART1_Rx ((11UL)) /*< UART1 Rx /
dpslwk	0:7480abd3b63b	58	#define GPDMA_CONN_UART2_Tx ((12UL)) /*< UART2 Tx /
dpslwk	0:7480abd3b63b	59	#define GPDMA_CONN_UART2_Rx ((13UL)) /*< UART2 Rx /
dpslwk	0:7480abd3b63b	60	#define GPDMA_CONN_UART3_Tx ((14UL)) /*< UART3 Tx /
dpslwk	0:7480abd3b63b	61	#define GPDMA_CONN_UART3_Rx ((15UL)) /*< UART3 Rx /
dpslwk	0:7480abd3b63b	62	#define GPDMA_CONN_MAT0_0 ((16UL)) /*< MAT0.0 /
dpslwk	0:7480abd3b63b	63	#define GPDMA_CONN_MAT0_1 ((17UL)) /*< MAT0.1 /
dpslwk	0:7480abd3b63b	64	#define GPDMA_CONN_MAT1_0 ((18UL)) /*< MAT1.0 /
dpslwk	0:7480abd3b63b	65	#define GPDMA_CONN_MAT1_1 ((19UL)) /*< MAT1.1 /
dpslwk	0:7480abd3b63b	66	#define GPDMA_CONN_MAT2_0 ((20UL)) /*< MAT2.0 /
dpslwk	0:7480abd3b63b	67	#define GPDMA_CONN_MAT2_1 ((21UL)) /*< MAT2.1 /
dpslwk	0:7480abd3b63b	68	#define GPDMA_CONN_MAT3_0 ((22UL)) /*< MAT3.0 /
dpslwk	0:7480abd3b63b	69	#define GPDMA_CONN_MAT3_1 ((23UL)) /*< MAT3.1 /
dpslwk	0:7480abd3b63b	70
dpslwk	0:7480abd3b63b	71	/** GPDMA Transfer type definitions */
dpslwk	0:7480abd3b63b	72	#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /*< Memory to memory - DMA control /
dpslwk	0:7480abd3b63b	73	#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /*< Memory to peripheral - DMA control /
dpslwk	0:7480abd3b63b	74	#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /*< Peripheral to memory - DMA control /
dpslwk	0:7480abd3b63b	75	#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /*< Source peripheral to destination peripheral - DMA control /
dpslwk	0:7480abd3b63b	76
dpslwk	0:7480abd3b63b	77	/** Burst size in Source and Destination definitions */
dpslwk	0:7480abd3b63b	78	#define GPDMA_BSIZE_1 ((0UL)) /*< Burst size = 1 /
dpslwk	0:7480abd3b63b	79	#define GPDMA_BSIZE_4 ((1UL)) /*< Burst size = 4 /
dpslwk	0:7480abd3b63b	80	#define GPDMA_BSIZE_8 ((2UL)) /*< Burst size = 8 /
dpslwk	0:7480abd3b63b	81	#define GPDMA_BSIZE_16 ((3UL)) /*< Burst size = 16 /
dpslwk	0:7480abd3b63b	82	#define GPDMA_BSIZE_32 ((4UL)) /*< Burst size = 32 /
dpslwk	0:7480abd3b63b	83	#define GPDMA_BSIZE_64 ((5UL)) /*< Burst size = 64 /
dpslwk	0:7480abd3b63b	84	#define GPDMA_BSIZE_128 ((6UL)) /*< Burst size = 128 /
dpslwk	0:7480abd3b63b	85	#define GPDMA_BSIZE_256 ((7UL)) /*< Burst size = 256 /
dpslwk	0:7480abd3b63b	86
dpslwk	0:7480abd3b63b	87	/** Width in Source transfer width and Destination transfer width definitions */
dpslwk	0:7480abd3b63b	88	#define GPDMA_WIDTH_BYTE ((0UL)) /*< Width = 1 byte /
dpslwk	0:7480abd3b63b	89	#define GPDMA_WIDTH_HALFWORD ((1UL)) /*< Width = 2 bytes /
dpslwk	0:7480abd3b63b	90	#define GPDMA_WIDTH_WORD ((2UL)) /*< Width = 4 bytes /
dpslwk	0:7480abd3b63b	91
dpslwk	0:7480abd3b63b	92	/** DMA Request Select Mode definitions */
dpslwk	0:7480abd3b63b	93	#define GPDMA_REQSEL_UART ((0UL)) /*< UART TX/RX is selected /
dpslwk	0:7480abd3b63b	94	#define GPDMA_REQSEL_TIMER ((1UL)) /*< Timer match is selected /
dpslwk	0:7480abd3b63b	95
dpslwk	0:7480abd3b63b	96	/**
dpslwk	0:7480abd3b63b	97	* @}
dpslwk	0:7480abd3b63b	98	*/
dpslwk	0:7480abd3b63b	99
dpslwk	0:7480abd3b63b	100
dpslwk	0:7480abd3b63b	101	/* Private Macros ------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	102	/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
dpslwk	0:7480abd3b63b	103	* @{
dpslwk	0:7480abd3b63b	104	*/
dpslwk	0:7480abd3b63b	105
dpslwk	0:7480abd3b63b	106	/* --------------------- BIT DEFINITIONS -------------------------------------- */
dpslwk	0:7480abd3b63b	107	/*******************************************************************//
dpslwk	0:7480abd3b63b	108	* Macro defines for DMA Interrupt Status register
dpslwk	0:7480abd3b63b	109	**********************************************************************/
dpslwk	0:7480abd3b63b	110	#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	111	#define GPDMA_DMACIntStat_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	112
dpslwk	0:7480abd3b63b	113	/*******************************************************************//
dpslwk	0:7480abd3b63b	114	* Macro defines for DMA Interrupt Terminal Count Request Status register
dpslwk	0:7480abd3b63b	115	**********************************************************************/
dpslwk	0:7480abd3b63b	116	#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	117	#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	118
dpslwk	0:7480abd3b63b	119	/*******************************************************************//
dpslwk	0:7480abd3b63b	120	* Macro defines for DMA Interrupt Terminal Count Request Clear register
dpslwk	0:7480abd3b63b	121	**********************************************************************/
dpslwk	0:7480abd3b63b	122	#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	123	#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	124
dpslwk	0:7480abd3b63b	125	/*******************************************************************//
dpslwk	0:7480abd3b63b	126	* Macro defines for DMA Interrupt Error Status register
dpslwk	0:7480abd3b63b	127	**********************************************************************/
dpslwk	0:7480abd3b63b	128	#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	129	#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	130
dpslwk	0:7480abd3b63b	131	/*******************************************************************//
dpslwk	0:7480abd3b63b	132	* Macro defines for DMA Interrupt Error Clear register
dpslwk	0:7480abd3b63b	133	**********************************************************************/
dpslwk	0:7480abd3b63b	134	#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	135	#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	136
dpslwk	0:7480abd3b63b	137	/*******************************************************************//
dpslwk	0:7480abd3b63b	138	* Macro defines for DMA Raw Interrupt Terminal Count Status register
dpslwk	0:7480abd3b63b	139	**********************************************************************/
dpslwk	0:7480abd3b63b	140	#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	141	#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	142
dpslwk	0:7480abd3b63b	143	/*******************************************************************//
dpslwk	0:7480abd3b63b	144	* Macro defines for DMA Raw Error Interrupt Status register
dpslwk	0:7480abd3b63b	145	**********************************************************************/
dpslwk	0:7480abd3b63b	146	#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	147	#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	148
dpslwk	0:7480abd3b63b	149	/*******************************************************************//
dpslwk	0:7480abd3b63b	150	* Macro defines for DMA Enabled Channel register
dpslwk	0:7480abd3b63b	151	**********************************************************************/
dpslwk	0:7480abd3b63b	152	#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
dpslwk	0:7480abd3b63b	153	#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	154
dpslwk	0:7480abd3b63b	155	/*******************************************************************//
dpslwk	0:7480abd3b63b	156	* Macro defines for DMA Software Burst Request register
dpslwk	0:7480abd3b63b	157	**********************************************************************/
dpslwk	0:7480abd3b63b	158	#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
dpslwk	0:7480abd3b63b	159	#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
dpslwk	0:7480abd3b63b	160
dpslwk	0:7480abd3b63b	161	/*******************************************************************//
dpslwk	0:7480abd3b63b	162	* Macro defines for DMA Software Single Request register
dpslwk	0:7480abd3b63b	163	**********************************************************************/
dpslwk	0:7480abd3b63b	164	#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
dpslwk	0:7480abd3b63b	165	#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
dpslwk	0:7480abd3b63b	166
dpslwk	0:7480abd3b63b	167	/*******************************************************************//
dpslwk	0:7480abd3b63b	168	* Macro defines for DMA Software Last Burst Request register
dpslwk	0:7480abd3b63b	169	**********************************************************************/
dpslwk	0:7480abd3b63b	170	#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
dpslwk	0:7480abd3b63b	171	#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
dpslwk	0:7480abd3b63b	172
dpslwk	0:7480abd3b63b	173	/*******************************************************************//
dpslwk	0:7480abd3b63b	174	* Macro defines for DMA Software Last Single Request register
dpslwk	0:7480abd3b63b	175	**********************************************************************/
dpslwk	0:7480abd3b63b	176	#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
dpslwk	0:7480abd3b63b	177	#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
dpslwk	0:7480abd3b63b	178
dpslwk	0:7480abd3b63b	179	/*******************************************************************//
dpslwk	0:7480abd3b63b	180	* Macro defines for DMA Configuration register
dpslwk	0:7480abd3b63b	181	**********************************************************************/
dpslwk	0:7480abd3b63b	182	#define GPDMA_DMACConfig_E ((0x01)) /*< DMA Controller enable/
dpslwk	0:7480abd3b63b	183	#define GPDMA_DMACConfig_M ((0x02)) /*< AHB Master endianness configuration/
dpslwk	0:7480abd3b63b	184	#define GPDMA_DMACConfig_BITMASK ((0x03))
dpslwk	0:7480abd3b63b	185
dpslwk	0:7480abd3b63b	186	/*******************************************************************//
dpslwk	0:7480abd3b63b	187	* Macro defines for DMA Synchronization register
dpslwk	0:7480abd3b63b	188	**********************************************************************/
dpslwk	0:7480abd3b63b	189	#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
dpslwk	0:7480abd3b63b	190	#define GPDMA_DMACSync_BITMASK ((0xFFFF))
dpslwk	0:7480abd3b63b	191
dpslwk	0:7480abd3b63b	192	/*******************************************************************//
dpslwk	0:7480abd3b63b	193	* Macro defines for DMA Request Select register
dpslwk	0:7480abd3b63b	194	**********************************************************************/
dpslwk	0:7480abd3b63b	195	#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
dpslwk	0:7480abd3b63b	196	#define GPDMA_DMAReqSel_BITMASK ((0xFF))
dpslwk	0:7480abd3b63b	197
dpslwk	0:7480abd3b63b	198	/*******************************************************************//
dpslwk	0:7480abd3b63b	199	* Macro defines for DMA Channel Linked List Item registers
dpslwk	0:7480abd3b63b	200	**********************************************************************/
dpslwk	0:7480abd3b63b	201	/** DMA Channel Linked List Item registers bit mask*/
dpslwk	0:7480abd3b63b	202	#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
dpslwk	0:7480abd3b63b	203
dpslwk	0:7480abd3b63b	204	/*******************************************************************//
dpslwk	0:7480abd3b63b	205	* Macro defines for DMA channel control registers
dpslwk	0:7480abd3b63b	206	**********************************************************************/
dpslwk	0:7480abd3b63b	207	#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /*< Transfer size/
dpslwk	0:7480abd3b63b	208	#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /*< Source burst size/
dpslwk	0:7480abd3b63b	209	#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /*< Destination burst size/
dpslwk	0:7480abd3b63b	210	#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /*< Source transfer width/
dpslwk	0:7480abd3b63b	211	#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /*< Destination transfer width/
dpslwk	0:7480abd3b63b	212	#define GPDMA_DMACCxControl_SI ((1UL<<26)) /*< Source increment/
dpslwk	0:7480abd3b63b	213	#define GPDMA_DMACCxControl_DI ((1UL<<27)) /*< Destination increment/
dpslwk	0:7480abd3b63b	214	#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /*< Indicates that the access is in user mode or privileged mode/
dpslwk	0:7480abd3b63b	215	#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /*< Indicates that the access is bufferable or not bufferable/
dpslwk	0:7480abd3b63b	216	#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /*< Indicates that the access is cacheable or not cacheable/
dpslwk	0:7480abd3b63b	217	#define GPDMA_DMACCxControl_I ((1UL<<31)) /*< Terminal count interrupt enable bit /
dpslwk	0:7480abd3b63b	218	/** DMA channel control registers bit mask */
dpslwk	0:7480abd3b63b	219	#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
dpslwk	0:7480abd3b63b	220
dpslwk	0:7480abd3b63b	221	/*******************************************************************//
dpslwk	0:7480abd3b63b	222	* Macro defines for DMA Channel Configuration registers
dpslwk	0:7480abd3b63b	223	**********************************************************************/
dpslwk	0:7480abd3b63b	224	#define GPDMA_DMACCxConfig_E ((1UL<<0)) /*< DMA control enable/
dpslwk	0:7480abd3b63b	225	#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /*< Source peripheral/
dpslwk	0:7480abd3b63b	226	#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /*< Destination peripheral/
dpslwk	0:7480abd3b63b	227	#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /*< This value indicates the type of transfer/
dpslwk	0:7480abd3b63b	228	#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /*< Interrupt error mask/
dpslwk	0:7480abd3b63b	229	#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /*< Terminal count interrupt mask/
dpslwk	0:7480abd3b63b	230	#define GPDMA_DMACCxConfig_L ((1UL<<16)) /*< Lock/
dpslwk	0:7480abd3b63b	231	#define GPDMA_DMACCxConfig_A ((1UL<<17)) /*< Active/
dpslwk	0:7480abd3b63b	232	#define GPDMA_DMACCxConfig_H ((1UL<<18)) /*< Halt/
dpslwk	0:7480abd3b63b	233	/** DMA Channel Configuration registers bit mask */
dpslwk	0:7480abd3b63b	234	#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
dpslwk	0:7480abd3b63b	235
dpslwk	0:7480abd3b63b	236	/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
dpslwk	0:7480abd3b63b	237	/* Macros check GPDMA channel */
dpslwk	0:7480abd3b63b	238	#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
dpslwk	0:7480abd3b63b	239
dpslwk	0:7480abd3b63b	240	/* Macros check GPDMA connection type */
dpslwk	0:7480abd3b63b	241	#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) \|\| (n==GPDMA_CONN_SSP0_Rx) \
dpslwk	0:7480abd3b63b	242	\|\| (n==GPDMA_CONN_SSP1_Tx) \|\| (n==GPDMA_CONN_SSP1_Rx) \
dpslwk	0:7480abd3b63b	243	\|\| (n==GPDMA_CONN_ADC) \|\| (n==GPDMA_CONN_I2S_Channel_0) \
dpslwk	0:7480abd3b63b	244	\|\| (n==GPDMA_CONN_I2S_Channel_1) \|\| (n==GPDMA_CONN_DAC) \
dpslwk	0:7480abd3b63b	245	\|\| (n==GPDMA_CONN_UART0_Tx) \|\| (n==GPDMA_CONN_UART0_Rx) \
dpslwk	0:7480abd3b63b	246	\|\| (n==GPDMA_CONN_UART1_Tx) \|\| (n==GPDMA_CONN_UART1_Rx) \
dpslwk	0:7480abd3b63b	247	\|\| (n==GPDMA_CONN_UART2_Tx) \|\| (n==GPDMA_CONN_UART2_Rx) \
dpslwk	0:7480abd3b63b	248	\|\| (n==GPDMA_CONN_UART3_Tx) \|\| (n==GPDMA_CONN_UART3_Rx) \
dpslwk	0:7480abd3b63b	249	\|\| (n==GPDMA_CONN_MAT0_0) \|\| (n==GPDMA_CONN_MAT0_1) \
dpslwk	0:7480abd3b63b	250	\|\| (n==GPDMA_CONN_MAT1_0) \|\| (n==GPDMA_CONN_MAT1_1) \
dpslwk	0:7480abd3b63b	251	\|\| (n==GPDMA_CONN_MAT2_0) \|\| (n==GPDMA_CONN_MAT2_1) \
dpslwk	0:7480abd3b63b	252	\|\| (n==GPDMA_CONN_MAT3_0) \|\| (n==GPDMA_CONN_MAT3_1))
dpslwk	0:7480abd3b63b	253
dpslwk	0:7480abd3b63b	254	/* Macros check GPDMA burst size type */
dpslwk	0:7480abd3b63b	255	#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) \|\| (n==GPDMA_BSIZE_4) \
dpslwk	0:7480abd3b63b	256	\|\| (n==GPDMA_BSIZE_8) \|\| (n==GPDMA_BSIZE_16) \
dpslwk	0:7480abd3b63b	257	\|\| (n==GPDMA_BSIZE_32) \|\| (n==GPDMA_BSIZE_64) \
dpslwk	0:7480abd3b63b	258	\|\| (n==GPDMA_BSIZE_128) \|\| (n==GPDMA_BSIZE_256))
dpslwk	0:7480abd3b63b	259
dpslwk	0:7480abd3b63b	260	/* Macros check GPDMA width type */
dpslwk	0:7480abd3b63b	261	#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) \|\| (n==GPDMA_WIDTH_HALFWORD) \
dpslwk	0:7480abd3b63b	262	\|\| (n==GPDMA_WIDTH_WORD))
dpslwk	0:7480abd3b63b	263
dpslwk	0:7480abd3b63b	264	/* Macros check GPDMA status type */
dpslwk	0:7480abd3b63b	265	#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) \|\| (n==GPDMA_STAT_INTTC) \
dpslwk	0:7480abd3b63b	266	\|\| (n==GPDMA_STAT_INTERR) \|\| (n==GPDMA_STAT_RAWINTTC) \
dpslwk	0:7480abd3b63b	267	\|\| (n==GPDMA_STAT_RAWINTERR) \|\| (n==GPDMA_STAT_ENABLED_CH))
dpslwk	0:7480abd3b63b	268
dpslwk	0:7480abd3b63b	269	/* Macros check GPDMA transfer type */
dpslwk	0:7480abd3b63b	270	#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)\|\|(n==GPDMA_TRANSFERTYPE_M2P) \
dpslwk	0:7480abd3b63b	271	\|\|(n==GPDMA_TRANSFERTYPE_P2M)\|\|(n==GPDMA_TRANSFERTYPE_P2P))
dpslwk	0:7480abd3b63b	272
dpslwk	0:7480abd3b63b	273	/* Macros check GPDMA state clear type */
dpslwk	0:7480abd3b63b	274	#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) \|\| (n==GPDMA_STATCLR_INTERR))
dpslwk	0:7480abd3b63b	275
dpslwk	0:7480abd3b63b	276	/* Macros check GPDMA request select type */
dpslwk	0:7480abd3b63b	277	#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) \|\| (n==GPDMA_REQSEL_TIMER))
dpslwk	0:7480abd3b63b	278	/**
dpslwk	0:7480abd3b63b	279	* @}
dpslwk	0:7480abd3b63b	280	*/
dpslwk	0:7480abd3b63b	281
dpslwk	0:7480abd3b63b	282
dpslwk	0:7480abd3b63b	283	/* Public Types --------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	284	/** @defgroup GPDMA_Public_Types GPDMA Public Types
dpslwk	0:7480abd3b63b	285	* @{
dpslwk	0:7480abd3b63b	286	*/
dpslwk	0:7480abd3b63b	287
dpslwk	0:7480abd3b63b	288	/**
dpslwk	0:7480abd3b63b	289	* @brief GPDMA Status enumeration
dpslwk	0:7480abd3b63b	290	*/
dpslwk	0:7480abd3b63b	291	typedef enum {
dpslwk	0:7480abd3b63b	292	GPDMA_STAT_INT, /*< GPDMA Interrupt Status /
dpslwk	0:7480abd3b63b	293	GPDMA_STAT_INTTC, /*< GPDMA Interrupt Terminal Count Request Status /
dpslwk	0:7480abd3b63b	294	GPDMA_STAT_INTERR, /*< GPDMA Interrupt Error Status /
dpslwk	0:7480abd3b63b	295	GPDMA_STAT_RAWINTTC, /*< GPDMA Raw Interrupt Terminal Count Status /
dpslwk	0:7480abd3b63b	296	GPDMA_STAT_RAWINTERR, /*< GPDMA Raw Error Interrupt Status /
dpslwk	0:7480abd3b63b	297	GPDMA_STAT_ENABLED_CH /*< GPDMA Enabled Channel Status /
dpslwk	0:7480abd3b63b	298	} GPDMA_Status_Type;
dpslwk	0:7480abd3b63b	299
dpslwk	0:7480abd3b63b	300	/**
dpslwk	0:7480abd3b63b	301	* @brief GPDMA Interrupt clear status enumeration
dpslwk	0:7480abd3b63b	302	*/
dpslwk	0:7480abd3b63b	303	typedef enum{
dpslwk	0:7480abd3b63b	304	GPDMA_STATCLR_INTTC, /*< GPDMA Interrupt Terminal Count Request Clear /
dpslwk	0:7480abd3b63b	305	GPDMA_STATCLR_INTERR /*< GPDMA Interrupt Error Clear /
dpslwk	0:7480abd3b63b	306	}GPDMA_StateClear_Type;
dpslwk	0:7480abd3b63b	307
dpslwk	0:7480abd3b63b	308	/**
dpslwk	0:7480abd3b63b	309	* @brief GPDMA Channel configuration structure type definition
dpslwk	0:7480abd3b63b	310	*/
dpslwk	0:7480abd3b63b	311	typedef struct {
dpslwk	0:7480abd3b63b	312	uint32_t ChannelNum; /**< DMA channel number, should be in
dpslwk	0:7480abd3b63b	313	range from 0 to 7.
dpslwk	0:7480abd3b63b	314	Note: DMA channel 0 has the highest priority
dpslwk	0:7480abd3b63b	315	and DMA channel 7 the lowest priority.
dpslwk	0:7480abd3b63b	316	*/
dpslwk	0:7480abd3b63b	317	uint32_t TransferSize; /*< Length/Size of transfer /
dpslwk	0:7480abd3b63b	318	uint32_t TransferWidth; /*< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only /
dpslwk	0:7480abd3b63b	319	uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
dpslwk	0:7480abd3b63b	320	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
dpslwk	0:7480abd3b63b	321	uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
dpslwk	0:7480abd3b63b	322	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
dpslwk	0:7480abd3b63b	323	uint32_t TransferType; /**< Transfer Type, should be one of the following:
dpslwk	0:7480abd3b63b	324	- GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
dpslwk	0:7480abd3b63b	325	- GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
dpslwk	0:7480abd3b63b	326	- GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
dpslwk	0:7480abd3b63b	327	- GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
dpslwk	0:7480abd3b63b	328	*/
dpslwk	0:7480abd3b63b	329	uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
dpslwk	0:7480abd3b63b	330	GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
dpslwk	0:7480abd3b63b	331	following:
dpslwk	0:7480abd3b63b	332	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
dpslwk	0:7480abd3b63b	333	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
dpslwk	0:7480abd3b63b	334	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
dpslwk	0:7480abd3b63b	335	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
dpslwk	0:7480abd3b63b	336	- GPDMA_CONN_ADC: ADC
dpslwk	0:7480abd3b63b	337	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
dpslwk	0:7480abd3b63b	338	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
dpslwk	0:7480abd3b63b	339	- GPDMA_CONN_DAC: DAC
dpslwk	0:7480abd3b63b	340	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
dpslwk	0:7480abd3b63b	341	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
dpslwk	0:7480abd3b63b	342	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
dpslwk	0:7480abd3b63b	343	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
dpslwk	0:7480abd3b63b	344	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
dpslwk	0:7480abd3b63b	345	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
dpslwk	0:7480abd3b63b	346	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
dpslwk	0:7480abd3b63b	347	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
dpslwk	0:7480abd3b63b	348	*/
dpslwk	0:7480abd3b63b	349	uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
dpslwk	0:7480abd3b63b	350	GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
dpslwk	0:7480abd3b63b	351	following:
dpslwk	0:7480abd3b63b	352	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
dpslwk	0:7480abd3b63b	353	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
dpslwk	0:7480abd3b63b	354	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
dpslwk	0:7480abd3b63b	355	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
dpslwk	0:7480abd3b63b	356	- GPDMA_CONN_ADC: ADC
dpslwk	0:7480abd3b63b	357	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
dpslwk	0:7480abd3b63b	358	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
dpslwk	0:7480abd3b63b	359	- GPDMA_CONN_DAC: DAC
dpslwk	0:7480abd3b63b	360	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
dpslwk	0:7480abd3b63b	361	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
dpslwk	0:7480abd3b63b	362	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
dpslwk	0:7480abd3b63b	363	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
dpslwk	0:7480abd3b63b	364	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
dpslwk	0:7480abd3b63b	365	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
dpslwk	0:7480abd3b63b	366	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
dpslwk	0:7480abd3b63b	367	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
dpslwk	0:7480abd3b63b	368	*/
dpslwk	0:7480abd3b63b	369	uint32_t DMALLI; /**< Linker List Item structure data address
dpslwk	0:7480abd3b63b	370	if there's no Linker List, set as '0'
dpslwk	0:7480abd3b63b	371	*/
dpslwk	0:7480abd3b63b	372	} GPDMA_Channel_CFG_Type;
dpslwk	0:7480abd3b63b	373
dpslwk	0:7480abd3b63b	374	/**
dpslwk	0:7480abd3b63b	375	* @brief GPDMA Linker List Item structure type definition
dpslwk	0:7480abd3b63b	376	*/
dpslwk	0:7480abd3b63b	377	typedef struct {
dpslwk	0:7480abd3b63b	378	uint32_t SrcAddr; /*< Source Address /
dpslwk	0:7480abd3b63b	379	uint32_t DstAddr; /*< Destination address /
dpslwk	0:7480abd3b63b	380	uint32_t NextLLI; /*< Next LLI address, otherwise set to '0' /
dpslwk	0:7480abd3b63b	381	uint32_t Control; /*< GPDMA Control of this LLI /
dpslwk	0:7480abd3b63b	382	} GPDMA_LLI_Type;
dpslwk	0:7480abd3b63b	383
dpslwk	0:7480abd3b63b	384
dpslwk	0:7480abd3b63b	385	/**
dpslwk	0:7480abd3b63b	386	* @}
dpslwk	0:7480abd3b63b	387	*/
dpslwk	0:7480abd3b63b	388
dpslwk	0:7480abd3b63b	389	/* Public Functions ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	390	/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
dpslwk	0:7480abd3b63b	391	* @{
dpslwk	0:7480abd3b63b	392	*/
dpslwk	0:7480abd3b63b	393
dpslwk	0:7480abd3b63b	394	void GPDMA_Init(void);
dpslwk	0:7480abd3b63b	395	//Status GPDMA_Setup(GPDMA_Channel_CFG_Type GPDMAChannelConfig, fnGPDMACbs_Type pfnGPDMACbs);
dpslwk	0:7480abd3b63b	396	Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
dpslwk	0:7480abd3b63b	397	IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
dpslwk	0:7480abd3b63b	398	void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
dpslwk	0:7480abd3b63b	399	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
dpslwk	0:7480abd3b63b	400	//void GPDMA_IntHandler(void);
dpslwk	0:7480abd3b63b	401
dpslwk	0:7480abd3b63b	402	/**
dpslwk	0:7480abd3b63b	403	* @}
dpslwk	0:7480abd3b63b	404	*/
dpslwk	0:7480abd3b63b	405
dpslwk	0:7480abd3b63b	406
dpslwk	0:7480abd3b63b	407	#ifdef __cplusplus
dpslwk	0:7480abd3b63b	408	}
dpslwk	0:7480abd3b63b	409	#endif
dpslwk	0:7480abd3b63b	410
dpslwk	0:7480abd3b63b	411	#endif /* LPC17XX_GPDMA_H_ */
dpslwk	0:7480abd3b63b	412
dpslwk	0:7480abd3b63b	413	/**
dpslwk	0:7480abd3b63b	414	* @}
dpslwk	0:7480abd3b63b	415	*/
dpslwk	0:7480abd3b63b	416
dpslwk	0:7480abd3b63b	417	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Sep 2010
Imports:	234
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	6

lpc17xx_gpdma.h@0:7480abd3b63b, 2010-09-30 (annotated)

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