DMA_UART_example - Example of UART-DMA transfers taken form the npx …

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Matt Lloyd / Mbed 2 deprecated DMA_UART_example

Example of UART-DMA transfers taken form the npx cmsis driver libary

lpc17xx_gpdma.c@0:7480abd3b63b, 2010-09-30 (annotated)

Committer:: dpslwk
Date:: Thu Sep 30 20:13:24 2010 +0000
Revision:: 0:7480abd3b63b

Who changed what in which revision?

User	Revision	Line number	New contents of line
dpslwk	0:7480abd3b63b	1	/*********************************************************************//
dpslwk	0:7480abd3b63b	2	* @file lpc17xx_gpdma.c
dpslwk	0:7480abd3b63b	3	* @brief Contains all functions support for GPDMA firmware library on LPC17xx
dpslwk	0:7480abd3b63b	4	* @version 2.0
dpslwk	0:7480abd3b63b	5	* @date 21. May. 2010
dpslwk	0:7480abd3b63b	6	* @author NXP MCU SW Application Team
dpslwk	0:7480abd3b63b	7	**************************************************************************
dpslwk	0:7480abd3b63b	8	* Software that is described herein is for illustrative purposes only
dpslwk	0:7480abd3b63b	9	* which provides customers with programming information regarding the
dpslwk	0:7480abd3b63b	10	* products. This software is supplied "AS IS" without any warranties.
dpslwk	0:7480abd3b63b	11	* NXP Semiconductors assumes no responsibility or liability for the
dpslwk	0:7480abd3b63b	12	* use of the software, conveys no license or title under any patent,
dpslwk	0:7480abd3b63b	13	* copyright, or mask work right to the product. NXP Semiconductors
dpslwk	0:7480abd3b63b	14	* reserves the right to make changes in the software without
dpslwk	0:7480abd3b63b	15	* notification. NXP Semiconductors also make no representation or
dpslwk	0:7480abd3b63b	16	* warranty that such application will be suitable for the specified
dpslwk	0:7480abd3b63b	17	* use without further testing or modification.
dpslwk	0:7480abd3b63b	18	**********************************************************************/
dpslwk	0:7480abd3b63b	19
dpslwk	0:7480abd3b63b	20	/* Peripheral group ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	21	/** @addtogroup GPDMA
dpslwk	0:7480abd3b63b	22	* @{
dpslwk	0:7480abd3b63b	23	*/
dpslwk	0:7480abd3b63b	24
dpslwk	0:7480abd3b63b	25	/* Includes ------------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	26	#include "lpc17xx_gpdma.h"
dpslwk	0:7480abd3b63b	27	#include "lpc17xx_clkpwr.h"
dpslwk	0:7480abd3b63b	28
dpslwk	0:7480abd3b63b	29	/* If this source file built with example, the LPC17xx FW library configuration
dpslwk	0:7480abd3b63b	30	* file in each example directory ("lpc17xx_libcfg.h") must be included,
dpslwk	0:7480abd3b63b	31	* otherwise the default FW library configuration file must be included instead
dpslwk	0:7480abd3b63b	32	*/
dpslwk	0:7480abd3b63b	33	#ifdef __BUILD_WITH_EXAMPLE__
dpslwk	0:7480abd3b63b	34	#include "lpc17xx_libcfg.h"
dpslwk	0:7480abd3b63b	35	#else
dpslwk	0:7480abd3b63b	36	#include "lpc17xx_libcfg_default.h"
dpslwk	0:7480abd3b63b	37	#endif /* __BUILD_WITH_EXAMPLE__ */
dpslwk	0:7480abd3b63b	38
dpslwk	0:7480abd3b63b	39	#ifdef _GPDMA
dpslwk	0:7480abd3b63b	40
dpslwk	0:7480abd3b63b	41
dpslwk	0:7480abd3b63b	42	/* Private Variables ---------------------------------------------------------- */
dpslwk	0:7480abd3b63b	43	/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
dpslwk	0:7480abd3b63b	44	* @{
dpslwk	0:7480abd3b63b	45	*/
dpslwk	0:7480abd3b63b	46
dpslwk	0:7480abd3b63b	47	/**
dpslwk	0:7480abd3b63b	48	* @brief Lookup Table of Connection Type matched with
dpslwk	0:7480abd3b63b	49	* Peripheral Data (FIFO) register base address
dpslwk	0:7480abd3b63b	50	*/
dpslwk	0:7480abd3b63b	51	#ifdef __IAR_SYSTEMS_ICC__
dpslwk	0:7480abd3b63b	52	volatile const void *GPDMA_LUTPerAddr[] = {
dpslwk	0:7480abd3b63b	53	(&LPC_SSP0->DR), // SSP0 Tx
dpslwk	0:7480abd3b63b	54	(&LPC_SSP0->DR), // SSP0 Rx
dpslwk	0:7480abd3b63b	55	(&LPC_SSP1->DR), // SSP1 Tx
dpslwk	0:7480abd3b63b	56	(&LPC_SSP1->DR), // SSP1 Rx
dpslwk	0:7480abd3b63b	57	(&LPC_ADC->ADGDR), // ADC
dpslwk	0:7480abd3b63b	58	(&LPC_I2S->I2STXFIFO), // I2S Tx
dpslwk	0:7480abd3b63b	59	(&LPC_I2S->I2SRXFIFO), // I2S Rx
dpslwk	0:7480abd3b63b	60	(&LPC_DAC->DACR), // DAC
dpslwk	0:7480abd3b63b	61	(&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
dpslwk	0:7480abd3b63b	62	(&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
dpslwk	0:7480abd3b63b	63	(&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
dpslwk	0:7480abd3b63b	64	(&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
dpslwk	0:7480abd3b63b	65	(&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
dpslwk	0:7480abd3b63b	66	(&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
dpslwk	0:7480abd3b63b	67	(&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
dpslwk	0:7480abd3b63b	68	(&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
dpslwk	0:7480abd3b63b	69	(&LPC_TIM0->MR0), // MAT0.0
dpslwk	0:7480abd3b63b	70	(&LPC_TIM0->MR1), // MAT0.1
dpslwk	0:7480abd3b63b	71	(&LPC_TIM1->MR0), // MAT1.0
dpslwk	0:7480abd3b63b	72	(&LPC_TIM1->MR1), // MAT1.1
dpslwk	0:7480abd3b63b	73	(&LPC_TIM2->MR0), // MAT2.0
dpslwk	0:7480abd3b63b	74	(&LPC_TIM2->MR1), // MAT2.1
dpslwk	0:7480abd3b63b	75	(&LPC_TIM3->MR0), // MAT3.0
dpslwk	0:7480abd3b63b	76	(&LPC_TIM3->MR1), // MAT3.1
dpslwk	0:7480abd3b63b	77	};
dpslwk	0:7480abd3b63b	78	#else
dpslwk	0:7480abd3b63b	79	const uint32_t GPDMA_LUTPerAddr[] = {
dpslwk	0:7480abd3b63b	80	((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
dpslwk	0:7480abd3b63b	81	((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
dpslwk	0:7480abd3b63b	82	((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
dpslwk	0:7480abd3b63b	83	((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
dpslwk	0:7480abd3b63b	84	((uint32_t)&LPC_ADC->ADGDR), // ADC
dpslwk	0:7480abd3b63b	85	((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
dpslwk	0:7480abd3b63b	86	((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
dpslwk	0:7480abd3b63b	87	((uint32_t)&LPC_DAC->DACR), // DAC
dpslwk	0:7480abd3b63b	88	((uint32_t)&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
dpslwk	0:7480abd3b63b	89	((uint32_t)&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
dpslwk	0:7480abd3b63b	90	((uint32_t)&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
dpslwk	0:7480abd3b63b	91	((uint32_t)&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
dpslwk	0:7480abd3b63b	92	((uint32_t)&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
dpslwk	0:7480abd3b63b	93	((uint32_t)&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
dpslwk	0:7480abd3b63b	94	((uint32_t)&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
dpslwk	0:7480abd3b63b	95	((uint32_t)&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
dpslwk	0:7480abd3b63b	96	((uint32_t)&LPC_TIM0->MR0), // MAT0.0
dpslwk	0:7480abd3b63b	97	((uint32_t)&LPC_TIM0->MR1), // MAT0.1
dpslwk	0:7480abd3b63b	98	((uint32_t)&LPC_TIM1->MR0), // MAT1.0
dpslwk	0:7480abd3b63b	99	((uint32_t)&LPC_TIM1->MR1), // MAT1.1
dpslwk	0:7480abd3b63b	100	((uint32_t)&LPC_TIM2->MR0), // MAT2.0
dpslwk	0:7480abd3b63b	101	((uint32_t)&LPC_TIM2->MR1), // MAT2.1
dpslwk	0:7480abd3b63b	102	((uint32_t)&LPC_TIM3->MR0), // MAT3.0
dpslwk	0:7480abd3b63b	103	((uint32_t)&LPC_TIM3->MR1), // MAT3.1
dpslwk	0:7480abd3b63b	104	};
dpslwk	0:7480abd3b63b	105	#endif
dpslwk	0:7480abd3b63b	106	/**
dpslwk	0:7480abd3b63b	107	* @brief Lookup Table of GPDMA Channel Number matched with
dpslwk	0:7480abd3b63b	108	* GPDMA channel pointer
dpslwk	0:7480abd3b63b	109	*/
dpslwk	0:7480abd3b63b	110	const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
dpslwk	0:7480abd3b63b	111	LPC_GPDMACH0, // GPDMA Channel 0
dpslwk	0:7480abd3b63b	112	LPC_GPDMACH1, // GPDMA Channel 1
dpslwk	0:7480abd3b63b	113	LPC_GPDMACH2, // GPDMA Channel 2
dpslwk	0:7480abd3b63b	114	LPC_GPDMACH3, // GPDMA Channel 3
dpslwk	0:7480abd3b63b	115	LPC_GPDMACH4, // GPDMA Channel 4
dpslwk	0:7480abd3b63b	116	LPC_GPDMACH5, // GPDMA Channel 5
dpslwk	0:7480abd3b63b	117	LPC_GPDMACH6, // GPDMA Channel 6
dpslwk	0:7480abd3b63b	118	LPC_GPDMACH7, // GPDMA Channel 7
dpslwk	0:7480abd3b63b	119	};
dpslwk	0:7480abd3b63b	120	/**
dpslwk	0:7480abd3b63b	121	* @brief Optimized Peripheral Source and Destination burst size
dpslwk	0:7480abd3b63b	122	*/
dpslwk	0:7480abd3b63b	123	const uint8_t GPDMA_LUTPerBurst[] = {
dpslwk	0:7480abd3b63b	124	GPDMA_BSIZE_4, // SSP0 Tx
dpslwk	0:7480abd3b63b	125	GPDMA_BSIZE_4, // SSP0 Rx
dpslwk	0:7480abd3b63b	126	GPDMA_BSIZE_4, // SSP1 Tx
dpslwk	0:7480abd3b63b	127	GPDMA_BSIZE_4, // SSP1 Rx
dpslwk	0:7480abd3b63b	128	GPDMA_BSIZE_4, // ADC
dpslwk	0:7480abd3b63b	129	GPDMA_BSIZE_32, // I2S channel 0
dpslwk	0:7480abd3b63b	130	GPDMA_BSIZE_32, // I2S channel 1
dpslwk	0:7480abd3b63b	131	GPDMA_BSIZE_1, // DAC
dpslwk	0:7480abd3b63b	132	GPDMA_BSIZE_1, // UART0 Tx
dpslwk	0:7480abd3b63b	133	GPDMA_BSIZE_1, // UART0 Rx
dpslwk	0:7480abd3b63b	134	GPDMA_BSIZE_1, // UART1 Tx
dpslwk	0:7480abd3b63b	135	GPDMA_BSIZE_1, // UART1 Rx
dpslwk	0:7480abd3b63b	136	GPDMA_BSIZE_1, // UART2 Tx
dpslwk	0:7480abd3b63b	137	GPDMA_BSIZE_1, // UART2 Rx
dpslwk	0:7480abd3b63b	138	GPDMA_BSIZE_1, // UART3 Tx
dpslwk	0:7480abd3b63b	139	GPDMA_BSIZE_1, // UART3 Rx
dpslwk	0:7480abd3b63b	140	GPDMA_BSIZE_1, // MAT0.0
dpslwk	0:7480abd3b63b	141	GPDMA_BSIZE_1, // MAT0.1
dpslwk	0:7480abd3b63b	142	GPDMA_BSIZE_1, // MAT1.0
dpslwk	0:7480abd3b63b	143	GPDMA_BSIZE_1, // MAT1.1
dpslwk	0:7480abd3b63b	144	GPDMA_BSIZE_1, // MAT2.0
dpslwk	0:7480abd3b63b	145	GPDMA_BSIZE_1, // MAT2.1
dpslwk	0:7480abd3b63b	146	GPDMA_BSIZE_1, // MAT3.0
dpslwk	0:7480abd3b63b	147	GPDMA_BSIZE_1, // MAT3.1
dpslwk	0:7480abd3b63b	148	};
dpslwk	0:7480abd3b63b	149	/**
dpslwk	0:7480abd3b63b	150	* @brief Optimized Peripheral Source and Destination transfer width
dpslwk	0:7480abd3b63b	151	*/
dpslwk	0:7480abd3b63b	152	const uint8_t GPDMA_LUTPerWid[] = {
dpslwk	0:7480abd3b63b	153	GPDMA_WIDTH_BYTE, // SSP0 Tx
dpslwk	0:7480abd3b63b	154	GPDMA_WIDTH_BYTE, // SSP0 Rx
dpslwk	0:7480abd3b63b	155	GPDMA_WIDTH_BYTE, // SSP1 Tx
dpslwk	0:7480abd3b63b	156	GPDMA_WIDTH_BYTE, // SSP1 Rx
dpslwk	0:7480abd3b63b	157	GPDMA_WIDTH_WORD, // ADC
dpslwk	0:7480abd3b63b	158	GPDMA_WIDTH_WORD, // I2S channel 0
dpslwk	0:7480abd3b63b	159	GPDMA_WIDTH_WORD, // I2S channel 1
dpslwk	0:7480abd3b63b	160	GPDMA_WIDTH_BYTE, // DAC
dpslwk	0:7480abd3b63b	161	GPDMA_WIDTH_BYTE, // UART0 Tx
dpslwk	0:7480abd3b63b	162	GPDMA_WIDTH_BYTE, // UART0 Rx
dpslwk	0:7480abd3b63b	163	GPDMA_WIDTH_BYTE, // UART1 Tx
dpslwk	0:7480abd3b63b	164	GPDMA_WIDTH_BYTE, // UART1 Rx
dpslwk	0:7480abd3b63b	165	GPDMA_WIDTH_BYTE, // UART2 Tx
dpslwk	0:7480abd3b63b	166	GPDMA_WIDTH_BYTE, // UART2 Rx
dpslwk	0:7480abd3b63b	167	GPDMA_WIDTH_BYTE, // UART3 Tx
dpslwk	0:7480abd3b63b	168	GPDMA_WIDTH_BYTE, // UART3 Rx
dpslwk	0:7480abd3b63b	169	GPDMA_WIDTH_WORD, // MAT0.0
dpslwk	0:7480abd3b63b	170	GPDMA_WIDTH_WORD, // MAT0.1
dpslwk	0:7480abd3b63b	171	GPDMA_WIDTH_WORD, // MAT1.0
dpslwk	0:7480abd3b63b	172	GPDMA_WIDTH_WORD, // MAT1.1
dpslwk	0:7480abd3b63b	173	GPDMA_WIDTH_WORD, // MAT2.0
dpslwk	0:7480abd3b63b	174	GPDMA_WIDTH_WORD, // MAT2.1
dpslwk	0:7480abd3b63b	175	GPDMA_WIDTH_WORD, // MAT3.0
dpslwk	0:7480abd3b63b	176	GPDMA_WIDTH_WORD, // MAT3.1
dpslwk	0:7480abd3b63b	177	};
dpslwk	0:7480abd3b63b	178
dpslwk	0:7480abd3b63b	179	/**
dpslwk	0:7480abd3b63b	180	* @}
dpslwk	0:7480abd3b63b	181	*/
dpslwk	0:7480abd3b63b	182
dpslwk	0:7480abd3b63b	183	/* Public Functions ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	184	/** @addtogroup GPDMA_Public_Functions
dpslwk	0:7480abd3b63b	185	* @{
dpslwk	0:7480abd3b63b	186	*/
dpslwk	0:7480abd3b63b	187
dpslwk	0:7480abd3b63b	188	/******************************************************************//
dpslwk	0:7480abd3b63b	189	* @brief Initialize GPDMA controller
dpslwk	0:7480abd3b63b	190	* @param None
dpslwk	0:7480abd3b63b	191	* @return None
dpslwk	0:7480abd3b63b	192	*********************************************************************/
dpslwk	0:7480abd3b63b	193	void GPDMA_Init(void)
dpslwk	0:7480abd3b63b	194	{
dpslwk	0:7480abd3b63b	195	/* Enable GPDMA clock */
dpslwk	0:7480abd3b63b	196	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
dpslwk	0:7480abd3b63b	197
dpslwk	0:7480abd3b63b	198	// Reset all channel configuration register
dpslwk	0:7480abd3b63b	199	LPC_GPDMACH0->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	200	LPC_GPDMACH1->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	201	LPC_GPDMACH2->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	202	LPC_GPDMACH3->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	203	LPC_GPDMACH4->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	204	LPC_GPDMACH5->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	205	LPC_GPDMACH6->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	206	LPC_GPDMACH7->DMACCConfig = 0;
dpslwk	0:7480abd3b63b	207
dpslwk	0:7480abd3b63b	208	/* Clear all DMA interrupt and error flag */
dpslwk	0:7480abd3b63b	209	LPC_GPDMA->DMACIntTCClear = 0xFF;
dpslwk	0:7480abd3b63b	210	LPC_GPDMA->DMACIntErrClr = 0xFF;
dpslwk	0:7480abd3b63b	211	}
dpslwk	0:7480abd3b63b	212
dpslwk	0:7480abd3b63b	213	/******************************************************************//
dpslwk	0:7480abd3b63b	214	* @brief Setup GPDMA channel peripheral according to the specified
dpslwk	0:7480abd3b63b	215	* parameters in the GPDMAChannelConfig.
dpslwk	0:7480abd3b63b	216	* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
dpslwk	0:7480abd3b63b	217	* structure that contains the configuration
dpslwk	0:7480abd3b63b	218	* information for the specified GPDMA channel peripheral.
dpslwk	0:7480abd3b63b	219	* @return ERROR if selected channel is enabled before
dpslwk	0:7480abd3b63b	220	* or SUCCESS if channel is configured successfully
dpslwk	0:7480abd3b63b	221	*********************************************************************/
dpslwk	0:7480abd3b63b	222	Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
dpslwk	0:7480abd3b63b	223	{
dpslwk	0:7480abd3b63b	224	LPC_GPDMACH_TypeDef *pDMAch;
dpslwk	0:7480abd3b63b	225	uint32_t tmp1, tmp2;
dpslwk	0:7480abd3b63b	226
dpslwk	0:7480abd3b63b	227	if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
dpslwk	0:7480abd3b63b	228	// This channel is enabled, return ERROR, need to release this channel first
dpslwk	0:7480abd3b63b	229	return ERROR;
dpslwk	0:7480abd3b63b	230	}
dpslwk	0:7480abd3b63b	231
dpslwk	0:7480abd3b63b	232	// Get Channel pointer
dpslwk	0:7480abd3b63b	233	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
dpslwk	0:7480abd3b63b	234
dpslwk	0:7480abd3b63b	235	// Reset the Interrupt status
dpslwk	0:7480abd3b63b	236	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
dpslwk	0:7480abd3b63b	237	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
dpslwk	0:7480abd3b63b	238
dpslwk	0:7480abd3b63b	239	// Clear DMA configure
dpslwk	0:7480abd3b63b	240	pDMAch->DMACCControl = 0x00;
dpslwk	0:7480abd3b63b	241	pDMAch->DMACCConfig = 0x00;
dpslwk	0:7480abd3b63b	242
dpslwk	0:7480abd3b63b	243	/* Assign Linker List Item value */
dpslwk	0:7480abd3b63b	244	pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
dpslwk	0:7480abd3b63b	245
dpslwk	0:7480abd3b63b	246	/* Set value to Channel Control Registers */
dpslwk	0:7480abd3b63b	247	switch (GPDMAChannelConfig->TransferType)
dpslwk	0:7480abd3b63b	248	{
dpslwk	0:7480abd3b63b	249	// Memory to memory
dpslwk	0:7480abd3b63b	250	case GPDMA_TRANSFERTYPE_M2M:
dpslwk	0:7480abd3b63b	251	// Assign physical source and destination address
dpslwk	0:7480abd3b63b	252	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
dpslwk	0:7480abd3b63b	253	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
dpslwk	0:7480abd3b63b	254	pDMAch->DMACCControl
dpslwk	0:7480abd3b63b	255	= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
dpslwk	0:7480abd3b63b	256	\| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
dpslwk	0:7480abd3b63b	257	\| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
dpslwk	0:7480abd3b63b	258	\| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
dpslwk	0:7480abd3b63b	259	\| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
dpslwk	0:7480abd3b63b	260	\| GPDMA_DMACCxControl_SI \
dpslwk	0:7480abd3b63b	261	\| GPDMA_DMACCxControl_DI \
dpslwk	0:7480abd3b63b	262	\| GPDMA_DMACCxControl_I;
dpslwk	0:7480abd3b63b	263	break;
dpslwk	0:7480abd3b63b	264	// Memory to peripheral
dpslwk	0:7480abd3b63b	265	case GPDMA_TRANSFERTYPE_M2P:
dpslwk	0:7480abd3b63b	266	// Assign physical source
dpslwk	0:7480abd3b63b	267	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
dpslwk	0:7480abd3b63b	268	// Assign peripheral destination address
dpslwk	0:7480abd3b63b	269	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
dpslwk	0:7480abd3b63b	270	pDMAch->DMACCControl
dpslwk	0:7480abd3b63b	271	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
dpslwk	0:7480abd3b63b	272	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	273	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	274	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	275	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	276	\| GPDMA_DMACCxControl_SI \
dpslwk	0:7480abd3b63b	277	\| GPDMA_DMACCxControl_I;
dpslwk	0:7480abd3b63b	278	break;
dpslwk	0:7480abd3b63b	279	// Peripheral to memory
dpslwk	0:7480abd3b63b	280	case GPDMA_TRANSFERTYPE_P2M:
dpslwk	0:7480abd3b63b	281	// Assign peripheral source address
dpslwk	0:7480abd3b63b	282	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
dpslwk	0:7480abd3b63b	283	// Assign memory destination address
dpslwk	0:7480abd3b63b	284	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
dpslwk	0:7480abd3b63b	285	pDMAch->DMACCControl
dpslwk	0:7480abd3b63b	286	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
dpslwk	0:7480abd3b63b	287	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	288	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	289	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	290	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	291	\| GPDMA_DMACCxControl_DI \
dpslwk	0:7480abd3b63b	292	\| GPDMA_DMACCxControl_I;
dpslwk	0:7480abd3b63b	293	break;
dpslwk	0:7480abd3b63b	294	// Peripheral to peripheral
dpslwk	0:7480abd3b63b	295	case GPDMA_TRANSFERTYPE_P2P:
dpslwk	0:7480abd3b63b	296	// Assign peripheral source address
dpslwk	0:7480abd3b63b	297	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
dpslwk	0:7480abd3b63b	298	// Assign peripheral destination address
dpslwk	0:7480abd3b63b	299	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
dpslwk	0:7480abd3b63b	300	pDMAch->DMACCControl
dpslwk	0:7480abd3b63b	301	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
dpslwk	0:7480abd3b63b	302	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	303	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	304	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
dpslwk	0:7480abd3b63b	305	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
dpslwk	0:7480abd3b63b	306	\| GPDMA_DMACCxControl_I;
dpslwk	0:7480abd3b63b	307	break;
dpslwk	0:7480abd3b63b	308	// Do not support any more transfer type, return ERROR
dpslwk	0:7480abd3b63b	309	default:
dpslwk	0:7480abd3b63b	310	return ERROR;
dpslwk	0:7480abd3b63b	311	}
dpslwk	0:7480abd3b63b	312
dpslwk	0:7480abd3b63b	313	/* Re-Configure DMA Request Select for source peripheral */
dpslwk	0:7480abd3b63b	314	if (GPDMAChannelConfig->SrcConn > 15)
dpslwk	0:7480abd3b63b	315	{
dpslwk	0:7480abd3b63b	316	LPC_SC->RESERVED9 \|= (1<<(GPDMAChannelConfig->SrcConn - 16));
dpslwk	0:7480abd3b63b	317	} else {
dpslwk	0:7480abd3b63b	318	LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
dpslwk	0:7480abd3b63b	319	}
dpslwk	0:7480abd3b63b	320
dpslwk	0:7480abd3b63b	321	/* Re-Configure DMA Request Select for Destination peripheral */
dpslwk	0:7480abd3b63b	322	if (GPDMAChannelConfig->DstConn > 15)
dpslwk	0:7480abd3b63b	323	{
dpslwk	0:7480abd3b63b	324	LPC_SC->RESERVED9 \|= (1<<(GPDMAChannelConfig->DstConn - 16));
dpslwk	0:7480abd3b63b	325	} else {
dpslwk	0:7480abd3b63b	326	LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
dpslwk	0:7480abd3b63b	327	}
dpslwk	0:7480abd3b63b	328
dpslwk	0:7480abd3b63b	329	/* Enable DMA channels, little endian */
dpslwk	0:7480abd3b63b	330	LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
dpslwk	0:7480abd3b63b	331	while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
dpslwk	0:7480abd3b63b	332
dpslwk	0:7480abd3b63b	333	// Calculate absolute value for Connection number
dpslwk	0:7480abd3b63b	334	tmp1 = GPDMAChannelConfig->SrcConn;
dpslwk	0:7480abd3b63b	335	tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
dpslwk	0:7480abd3b63b	336	tmp2 = GPDMAChannelConfig->DstConn;
dpslwk	0:7480abd3b63b	337	tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
dpslwk	0:7480abd3b63b	338
dpslwk	0:7480abd3b63b	339	// Configure DMA Channel, enable Error Counter and Terminate counter
dpslwk	0:7480abd3b63b	340	pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE \| GPDMA_DMACCxConfig_ITC /\| GPDMA_DMACCxConfig_E/ \
dpslwk	0:7480abd3b63b	341	\| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
dpslwk	0:7480abd3b63b	342	\| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
dpslwk	0:7480abd3b63b	343	\| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
dpslwk	0:7480abd3b63b	344
dpslwk	0:7480abd3b63b	345	return SUCCESS;
dpslwk	0:7480abd3b63b	346	}
dpslwk	0:7480abd3b63b	347
dpslwk	0:7480abd3b63b	348
dpslwk	0:7480abd3b63b	349	/*******************************************************************//
dpslwk	0:7480abd3b63b	350	* @brief Enable/Disable DMA channel
dpslwk	0:7480abd3b63b	351	* @param[in] channelNum GPDMA channel, should be in range from 0 to 7
dpslwk	0:7480abd3b63b	352	* @param[in] NewState New State of this command, should be:
dpslwk	0:7480abd3b63b	353	* - ENABLE.
dpslwk	0:7480abd3b63b	354	* - DISABLE.
dpslwk	0:7480abd3b63b	355	* @return None
dpslwk	0:7480abd3b63b	356	**********************************************************************/
dpslwk	0:7480abd3b63b	357	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
dpslwk	0:7480abd3b63b	358	{
dpslwk	0:7480abd3b63b	359	LPC_GPDMACH_TypeDef *pDMAch;
dpslwk	0:7480abd3b63b	360
dpslwk	0:7480abd3b63b	361	// Get Channel pointer
dpslwk	0:7480abd3b63b	362	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
dpslwk	0:7480abd3b63b	363
dpslwk	0:7480abd3b63b	364	if (NewState == ENABLE) {
dpslwk	0:7480abd3b63b	365	pDMAch->DMACCConfig \|= GPDMA_DMACCxConfig_E;
dpslwk	0:7480abd3b63b	366	} else {
dpslwk	0:7480abd3b63b	367	pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
dpslwk	0:7480abd3b63b	368	}
dpslwk	0:7480abd3b63b	369	}
dpslwk	0:7480abd3b63b	370	/*******************************************************************//
dpslwk	0:7480abd3b63b	371	* @brief Check if corresponding channel does have an active interrupt
dpslwk	0:7480abd3b63b	372	* request or not
dpslwk	0:7480abd3b63b	373	* @param[in] type type of status, should be:
dpslwk	0:7480abd3b63b	374	* - GPDMA_STAT_INT: GPDMA Interrupt Status
dpslwk	0:7480abd3b63b	375	* - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
dpslwk	0:7480abd3b63b	376	* - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
dpslwk	0:7480abd3b63b	377	* - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
dpslwk	0:7480abd3b63b	378	* - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
dpslwk	0:7480abd3b63b	379	* - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
dpslwk	0:7480abd3b63b	380	* @param[in] channel GPDMA channel, should be in range from 0 to 7
dpslwk	0:7480abd3b63b	381	* @return IntStatus status of DMA channel interrupt after masking
dpslwk	0:7480abd3b63b	382	* Should be:
dpslwk	0:7480abd3b63b	383	* - SET: the corresponding channel has no active interrupt request
dpslwk	0:7480abd3b63b	384	* - RESET: the corresponding channel does have an active interrupt request
dpslwk	0:7480abd3b63b	385	**********************************************************************/
dpslwk	0:7480abd3b63b	386	IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
dpslwk	0:7480abd3b63b	387	{
dpslwk	0:7480abd3b63b	388	CHECK_PARAM(PARAM_GPDMA_STAT(type));
dpslwk	0:7480abd3b63b	389	CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
dpslwk	0:7480abd3b63b	390
dpslwk	0:7480abd3b63b	391	switch (type)
dpslwk	0:7480abd3b63b	392	{
dpslwk	0:7480abd3b63b	393	case GPDMA_STAT_INT: //check status of DMA channel interrupts
dpslwk	0:7480abd3b63b	394	if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
dpslwk	0:7480abd3b63b	395	return SET;
dpslwk	0:7480abd3b63b	396	return RESET;
dpslwk	0:7480abd3b63b	397	case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
dpslwk	0:7480abd3b63b	398	if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
dpslwk	0:7480abd3b63b	399	return SET;
dpslwk	0:7480abd3b63b	400	return RESET;
dpslwk	0:7480abd3b63b	401	case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
dpslwk	0:7480abd3b63b	402	if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
dpslwk	0:7480abd3b63b	403	return SET;
dpslwk	0:7480abd3b63b	404	return RESET;
dpslwk	0:7480abd3b63b	405	case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
dpslwk	0:7480abd3b63b	406	if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
dpslwk	0:7480abd3b63b	407	return SET;
dpslwk	0:7480abd3b63b	408	return RESET;
dpslwk	0:7480abd3b63b	409	case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
dpslwk	0:7480abd3b63b	410	if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
dpslwk	0:7480abd3b63b	411	return SET;
dpslwk	0:7480abd3b63b	412	return RESET;
dpslwk	0:7480abd3b63b	413	default: //check enable status for DMA channels
dpslwk	0:7480abd3b63b	414	if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
dpslwk	0:7480abd3b63b	415	return SET;
dpslwk	0:7480abd3b63b	416	return RESET;
dpslwk	0:7480abd3b63b	417	}
dpslwk	0:7480abd3b63b	418	}
dpslwk	0:7480abd3b63b	419
dpslwk	0:7480abd3b63b	420	/*******************************************************************//
dpslwk	0:7480abd3b63b	421	* @brief Clear one or more interrupt requests on DMA channels
dpslwk	0:7480abd3b63b	422	* @param[in] type type of interrupt request, should be:
dpslwk	0:7480abd3b63b	423	* - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
dpslwk	0:7480abd3b63b	424	* - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
dpslwk	0:7480abd3b63b	425	* @param[in] channel GPDMA channel, should be in range from 0 to 7
dpslwk	0:7480abd3b63b	426	* @return None
dpslwk	0:7480abd3b63b	427	**********************************************************************/
dpslwk	0:7480abd3b63b	428	void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
dpslwk	0:7480abd3b63b	429	{
dpslwk	0:7480abd3b63b	430	CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
dpslwk	0:7480abd3b63b	431	CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
dpslwk	0:7480abd3b63b	432
dpslwk	0:7480abd3b63b	433	if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
dpslwk	0:7480abd3b63b	434	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
dpslwk	0:7480abd3b63b	435	else // clear the error interrupt request
dpslwk	0:7480abd3b63b	436	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
dpslwk	0:7480abd3b63b	437	}
dpslwk	0:7480abd3b63b	438
dpslwk	0:7480abd3b63b	439	/**
dpslwk	0:7480abd3b63b	440	* @}
dpslwk	0:7480abd3b63b	441	*/
dpslwk	0:7480abd3b63b	442
dpslwk	0:7480abd3b63b	443	#endif /* _GPDMA */
dpslwk	0:7480abd3b63b	444
dpslwk	0:7480abd3b63b	445	/**
dpslwk	0:7480abd3b63b	446	* @}
dpslwk	0:7480abd3b63b	447	*/
dpslwk	0:7480abd3b63b	448
dpslwk	0:7480abd3b63b	449	/* --------------------------------- End Of File ------------------------------ */
dpslwk	0:7480abd3b63b	450

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Sep 2010
Imports:	234
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	6

lpc17xx_gpdma.c@0:7480abd3b63b, 2010-09-30 (annotated)

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