DMA_UART_example - Example of UART-DMA transfers taken form the npx …

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Matt Lloyd / Mbed 2 deprecated DMA_UART_example

Example of UART-DMA transfers taken form the npx cmsis driver libary

lpc17xx_clkpwr.c@0:7480abd3b63b, 2010-09-30 (annotated)

Committer:: dpslwk
Date:: Thu Sep 30 20:13:24 2010 +0000
Revision:: 0:7480abd3b63b

Who changed what in which revision?

User	Revision	Line number	New contents of line
dpslwk	0:7480abd3b63b	1	/*********************************************************************//
dpslwk	0:7480abd3b63b	2	* @file lpc17xx_clkpwr.c
dpslwk	0:7480abd3b63b	3	* @brief Contains all functions support for Clock and Power Control
dpslwk	0:7480abd3b63b	4	* firmware library on LPC17xx
dpslwk	0:7480abd3b63b	5	* @version 3.0
dpslwk	0:7480abd3b63b	6	* @date 18. June. 2010
dpslwk	0:7480abd3b63b	7	* @author NXP MCU SW Application Team
dpslwk	0:7480abd3b63b	8	**************************************************************************
dpslwk	0:7480abd3b63b	9	* Software that is described herein is for illustrative purposes only
dpslwk	0:7480abd3b63b	10	* which provides customers with programming information regarding the
dpslwk	0:7480abd3b63b	11	* products. This software is supplied "AS IS" without any warranties.
dpslwk	0:7480abd3b63b	12	* NXP Semiconductors assumes no responsibility or liability for the
dpslwk	0:7480abd3b63b	13	* use of the software, conveys no license or title under any patent,
dpslwk	0:7480abd3b63b	14	* copyright, or mask work right to the product. NXP Semiconductors
dpslwk	0:7480abd3b63b	15	* reserves the right to make changes in the software without
dpslwk	0:7480abd3b63b	16	* notification. NXP Semiconductors also make no representation or
dpslwk	0:7480abd3b63b	17	* warranty that such application will be suitable for the specified
dpslwk	0:7480abd3b63b	18	* use without further testing or modification.
dpslwk	0:7480abd3b63b	19	**********************************************************************/
dpslwk	0:7480abd3b63b	20
dpslwk	0:7480abd3b63b	21	/* Peripheral group ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	22	/** @addtogroup CLKPWR
dpslwk	0:7480abd3b63b	23	* @{
dpslwk	0:7480abd3b63b	24	*/
dpslwk	0:7480abd3b63b	25
dpslwk	0:7480abd3b63b	26	/* Includes ------------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	27	#include "lpc17xx_clkpwr.h"
dpslwk	0:7480abd3b63b	28
dpslwk	0:7480abd3b63b	29
dpslwk	0:7480abd3b63b	30	/* Public Functions ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	31	/** @addtogroup CLKPWR_Public_Functions
dpslwk	0:7480abd3b63b	32	* @{
dpslwk	0:7480abd3b63b	33	*/
dpslwk	0:7480abd3b63b	34
dpslwk	0:7480abd3b63b	35	/*******************************************************************//
dpslwk	0:7480abd3b63b	36	* @brief Set value of each Peripheral Clock Selection
dpslwk	0:7480abd3b63b	37	* @param[in] ClkType Peripheral Clock Selection of each type,
dpslwk	0:7480abd3b63b	38	* should be one of the following:
dpslwk	0:7480abd3b63b	39	* - CLKPWR_PCLKSEL_WDT : WDT
dpslwk	0:7480abd3b63b	40	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
dpslwk	0:7480abd3b63b	41	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
dpslwk	0:7480abd3b63b	42	- CLKPWR_PCLKSEL_UART0 : UART 0
dpslwk	0:7480abd3b63b	43	- CLKPWR_PCLKSEL_UART1 : UART 1
dpslwk	0:7480abd3b63b	44	- CLKPWR_PCLKSEL_PWM1 : PWM 1
dpslwk	0:7480abd3b63b	45	- CLKPWR_PCLKSEL_I2C0 : I2C 0
dpslwk	0:7480abd3b63b	46	- CLKPWR_PCLKSEL_SPI : SPI
dpslwk	0:7480abd3b63b	47	- CLKPWR_PCLKSEL_SSP1 : SSP 1
dpslwk	0:7480abd3b63b	48	- CLKPWR_PCLKSEL_DAC : DAC
dpslwk	0:7480abd3b63b	49	- CLKPWR_PCLKSEL_ADC : ADC
dpslwk	0:7480abd3b63b	50	- CLKPWR_PCLKSEL_CAN1 : CAN 1
dpslwk	0:7480abd3b63b	51	- CLKPWR_PCLKSEL_CAN2 : CAN 2
dpslwk	0:7480abd3b63b	52	- CLKPWR_PCLKSEL_ACF : ACF
dpslwk	0:7480abd3b63b	53	- CLKPWR_PCLKSEL_QEI : QEI
dpslwk	0:7480abd3b63b	54	- CLKPWR_PCLKSEL_PCB : PCB
dpslwk	0:7480abd3b63b	55	- CLKPWR_PCLKSEL_I2C1 : I2C 1
dpslwk	0:7480abd3b63b	56	- CLKPWR_PCLKSEL_SSP0 : SSP 0
dpslwk	0:7480abd3b63b	57	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
dpslwk	0:7480abd3b63b	58	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
dpslwk	0:7480abd3b63b	59	- CLKPWR_PCLKSEL_UART2 : UART 2
dpslwk	0:7480abd3b63b	60	- CLKPWR_PCLKSEL_UART3 : UART 3
dpslwk	0:7480abd3b63b	61	- CLKPWR_PCLKSEL_I2C2 : I2C 2
dpslwk	0:7480abd3b63b	62	- CLKPWR_PCLKSEL_I2S : I2S
dpslwk	0:7480abd3b63b	63	- CLKPWR_PCLKSEL_RIT : RIT
dpslwk	0:7480abd3b63b	64	- CLKPWR_PCLKSEL_SYSCON : SYSCON
dpslwk	0:7480abd3b63b	65	- CLKPWR_PCLKSEL_MC : MC
dpslwk	0:7480abd3b63b	66
dpslwk	0:7480abd3b63b	67	* @param[in] DivVal Value of divider, should be:
dpslwk	0:7480abd3b63b	68	* - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
dpslwk	0:7480abd3b63b	69	* - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
dpslwk	0:7480abd3b63b	70	* - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
dpslwk	0:7480abd3b63b	71	*
dpslwk	0:7480abd3b63b	72	* @return none
dpslwk	0:7480abd3b63b	73	**********************************************************************/
dpslwk	0:7480abd3b63b	74	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
dpslwk	0:7480abd3b63b	75	{
dpslwk	0:7480abd3b63b	76	uint32_t bitpos;
dpslwk	0:7480abd3b63b	77
dpslwk	0:7480abd3b63b	78	bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
dpslwk	0:7480abd3b63b	79
dpslwk	0:7480abd3b63b	80	/* PCLKSEL0 selected */
dpslwk	0:7480abd3b63b	81	if (ClkType < 32)
dpslwk	0:7480abd3b63b	82	{
dpslwk	0:7480abd3b63b	83	/* Clear two bit at bit position */
dpslwk	0:7480abd3b63b	84	LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
dpslwk	0:7480abd3b63b	85
dpslwk	0:7480abd3b63b	86	/* Set two selected bit */
dpslwk	0:7480abd3b63b	87	LPC_SC->PCLKSEL0 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
dpslwk	0:7480abd3b63b	88	}
dpslwk	0:7480abd3b63b	89	/* PCLKSEL1 selected */
dpslwk	0:7480abd3b63b	90	else
dpslwk	0:7480abd3b63b	91	{
dpslwk	0:7480abd3b63b	92	/* Clear two bit at bit position */
dpslwk	0:7480abd3b63b	93	LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
dpslwk	0:7480abd3b63b	94
dpslwk	0:7480abd3b63b	95	/* Set two selected bit */
dpslwk	0:7480abd3b63b	96	LPC_SC->PCLKSEL1 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
dpslwk	0:7480abd3b63b	97	}
dpslwk	0:7480abd3b63b	98	}
dpslwk	0:7480abd3b63b	99
dpslwk	0:7480abd3b63b	100
dpslwk	0:7480abd3b63b	101	/*******************************************************************//
dpslwk	0:7480abd3b63b	102	* @brief Get current value of each Peripheral Clock Selection
dpslwk	0:7480abd3b63b	103	* @param[in] ClkType Peripheral Clock Selection of each type,
dpslwk	0:7480abd3b63b	104	* should be one of the following:
dpslwk	0:7480abd3b63b	105	* - CLKPWR_PCLKSEL_WDT : WDT
dpslwk	0:7480abd3b63b	106	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
dpslwk	0:7480abd3b63b	107	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
dpslwk	0:7480abd3b63b	108	- CLKPWR_PCLKSEL_UART0 : UART 0
dpslwk	0:7480abd3b63b	109	- CLKPWR_PCLKSEL_UART1 : UART 1
dpslwk	0:7480abd3b63b	110	- CLKPWR_PCLKSEL_PWM1 : PWM 1
dpslwk	0:7480abd3b63b	111	- CLKPWR_PCLKSEL_I2C0 : I2C 0
dpslwk	0:7480abd3b63b	112	- CLKPWR_PCLKSEL_SPI : SPI
dpslwk	0:7480abd3b63b	113	- CLKPWR_PCLKSEL_SSP1 : SSP 1
dpslwk	0:7480abd3b63b	114	- CLKPWR_PCLKSEL_DAC : DAC
dpslwk	0:7480abd3b63b	115	- CLKPWR_PCLKSEL_ADC : ADC
dpslwk	0:7480abd3b63b	116	- CLKPWR_PCLKSEL_CAN1 : CAN 1
dpslwk	0:7480abd3b63b	117	- CLKPWR_PCLKSEL_CAN2 : CAN 2
dpslwk	0:7480abd3b63b	118	- CLKPWR_PCLKSEL_ACF : ACF
dpslwk	0:7480abd3b63b	119	- CLKPWR_PCLKSEL_QEI : QEI
dpslwk	0:7480abd3b63b	120	- CLKPWR_PCLKSEL_PCB : PCB
dpslwk	0:7480abd3b63b	121	- CLKPWR_PCLKSEL_I2C1 : I2C 1
dpslwk	0:7480abd3b63b	122	- CLKPWR_PCLKSEL_SSP0 : SSP 0
dpslwk	0:7480abd3b63b	123	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
dpslwk	0:7480abd3b63b	124	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
dpslwk	0:7480abd3b63b	125	- CLKPWR_PCLKSEL_UART2 : UART 2
dpslwk	0:7480abd3b63b	126	- CLKPWR_PCLKSEL_UART3 : UART 3
dpslwk	0:7480abd3b63b	127	- CLKPWR_PCLKSEL_I2C2 : I2C 2
dpslwk	0:7480abd3b63b	128	- CLKPWR_PCLKSEL_I2S : I2S
dpslwk	0:7480abd3b63b	129	- CLKPWR_PCLKSEL_RIT : RIT
dpslwk	0:7480abd3b63b	130	- CLKPWR_PCLKSEL_SYSCON : SYSCON
dpslwk	0:7480abd3b63b	131	- CLKPWR_PCLKSEL_MC : MC
dpslwk	0:7480abd3b63b	132
dpslwk	0:7480abd3b63b	133	* @return Value of Selected Peripheral Clock Selection
dpslwk	0:7480abd3b63b	134	**********************************************************************/
dpslwk	0:7480abd3b63b	135	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
dpslwk	0:7480abd3b63b	136	{
dpslwk	0:7480abd3b63b	137	uint32_t bitpos, retval;
dpslwk	0:7480abd3b63b	138
dpslwk	0:7480abd3b63b	139	if (ClkType < 32)
dpslwk	0:7480abd3b63b	140	{
dpslwk	0:7480abd3b63b	141	bitpos = ClkType;
dpslwk	0:7480abd3b63b	142	retval = LPC_SC->PCLKSEL0;
dpslwk	0:7480abd3b63b	143	}
dpslwk	0:7480abd3b63b	144	else
dpslwk	0:7480abd3b63b	145	{
dpslwk	0:7480abd3b63b	146	bitpos = ClkType - 32;
dpslwk	0:7480abd3b63b	147	retval = LPC_SC->PCLKSEL1;
dpslwk	0:7480abd3b63b	148	}
dpslwk	0:7480abd3b63b	149
dpslwk	0:7480abd3b63b	150	retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
dpslwk	0:7480abd3b63b	151	return retval;
dpslwk	0:7480abd3b63b	152	}
dpslwk	0:7480abd3b63b	153
dpslwk	0:7480abd3b63b	154
dpslwk	0:7480abd3b63b	155
dpslwk	0:7480abd3b63b	156	/*******************************************************************//
dpslwk	0:7480abd3b63b	157	* @brief Get current value of each Peripheral Clock
dpslwk	0:7480abd3b63b	158	* @param[in] ClkType Peripheral Clock Selection of each type,
dpslwk	0:7480abd3b63b	159	* should be one of the following:
dpslwk	0:7480abd3b63b	160	* - CLKPWR_PCLKSEL_WDT : WDT
dpslwk	0:7480abd3b63b	161	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
dpslwk	0:7480abd3b63b	162	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
dpslwk	0:7480abd3b63b	163	- CLKPWR_PCLKSEL_UART0 : UART 0
dpslwk	0:7480abd3b63b	164	- CLKPWR_PCLKSEL_UART1 : UART 1
dpslwk	0:7480abd3b63b	165	- CLKPWR_PCLKSEL_PWM1 : PWM 1
dpslwk	0:7480abd3b63b	166	- CLKPWR_PCLKSEL_I2C0 : I2C 0
dpslwk	0:7480abd3b63b	167	- CLKPWR_PCLKSEL_SPI : SPI
dpslwk	0:7480abd3b63b	168	- CLKPWR_PCLKSEL_SSP1 : SSP 1
dpslwk	0:7480abd3b63b	169	- CLKPWR_PCLKSEL_DAC : DAC
dpslwk	0:7480abd3b63b	170	- CLKPWR_PCLKSEL_ADC : ADC
dpslwk	0:7480abd3b63b	171	- CLKPWR_PCLKSEL_CAN1 : CAN 1
dpslwk	0:7480abd3b63b	172	- CLKPWR_PCLKSEL_CAN2 : CAN 2
dpslwk	0:7480abd3b63b	173	- CLKPWR_PCLKSEL_ACF : ACF
dpslwk	0:7480abd3b63b	174	- CLKPWR_PCLKSEL_QEI : QEI
dpslwk	0:7480abd3b63b	175	- CLKPWR_PCLKSEL_PCB : PCB
dpslwk	0:7480abd3b63b	176	- CLKPWR_PCLKSEL_I2C1 : I2C 1
dpslwk	0:7480abd3b63b	177	- CLKPWR_PCLKSEL_SSP0 : SSP 0
dpslwk	0:7480abd3b63b	178	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
dpslwk	0:7480abd3b63b	179	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
dpslwk	0:7480abd3b63b	180	- CLKPWR_PCLKSEL_UART2 : UART 2
dpslwk	0:7480abd3b63b	181	- CLKPWR_PCLKSEL_UART3 : UART 3
dpslwk	0:7480abd3b63b	182	- CLKPWR_PCLKSEL_I2C2 : I2C 2
dpslwk	0:7480abd3b63b	183	- CLKPWR_PCLKSEL_I2S : I2S
dpslwk	0:7480abd3b63b	184	- CLKPWR_PCLKSEL_RIT : RIT
dpslwk	0:7480abd3b63b	185	- CLKPWR_PCLKSEL_SYSCON : SYSCON
dpslwk	0:7480abd3b63b	186	- CLKPWR_PCLKSEL_MC : MC
dpslwk	0:7480abd3b63b	187
dpslwk	0:7480abd3b63b	188	* @return Value of Selected Peripheral Clock
dpslwk	0:7480abd3b63b	189	**********************************************************************/
dpslwk	0:7480abd3b63b	190	uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
dpslwk	0:7480abd3b63b	191	{
dpslwk	0:7480abd3b63b	192	uint32_t retval, div;
dpslwk	0:7480abd3b63b	193
dpslwk	0:7480abd3b63b	194	retval = SystemCoreClock;
dpslwk	0:7480abd3b63b	195	div = CLKPWR_GetPCLKSEL(ClkType);
dpslwk	0:7480abd3b63b	196
dpslwk	0:7480abd3b63b	197	switch (div)
dpslwk	0:7480abd3b63b	198	{
dpslwk	0:7480abd3b63b	199	case 0:
dpslwk	0:7480abd3b63b	200	div = 4;
dpslwk	0:7480abd3b63b	201	break;
dpslwk	0:7480abd3b63b	202
dpslwk	0:7480abd3b63b	203	case 1:
dpslwk	0:7480abd3b63b	204	div = 1;
dpslwk	0:7480abd3b63b	205	break;
dpslwk	0:7480abd3b63b	206
dpslwk	0:7480abd3b63b	207	case 2:
dpslwk	0:7480abd3b63b	208	div = 2;
dpslwk	0:7480abd3b63b	209	break;
dpslwk	0:7480abd3b63b	210
dpslwk	0:7480abd3b63b	211	case 3:
dpslwk	0:7480abd3b63b	212	div = 8;
dpslwk	0:7480abd3b63b	213	break;
dpslwk	0:7480abd3b63b	214	}
dpslwk	0:7480abd3b63b	215	retval /= div;
dpslwk	0:7480abd3b63b	216
dpslwk	0:7480abd3b63b	217	return retval;
dpslwk	0:7480abd3b63b	218	}
dpslwk	0:7480abd3b63b	219
dpslwk	0:7480abd3b63b	220
dpslwk	0:7480abd3b63b	221
dpslwk	0:7480abd3b63b	222	/*******************************************************************//
dpslwk	0:7480abd3b63b	223	* @brief Configure power supply for each peripheral according to NewState
dpslwk	0:7480abd3b63b	224	* @param[in] PPType Type of peripheral used to enable power,
dpslwk	0:7480abd3b63b	225	* should be one of the following:
dpslwk	0:7480abd3b63b	226	* - CLKPWR_PCONP_PCTIM0 : Timer 0
dpslwk	0:7480abd3b63b	227	- CLKPWR_PCONP_PCTIM1 : Timer 1
dpslwk	0:7480abd3b63b	228	- CLKPWR_PCONP_PCUART0 : UART 0
dpslwk	0:7480abd3b63b	229	- CLKPWR_PCONP_PCUART1 : UART 1
dpslwk	0:7480abd3b63b	230	- CLKPWR_PCONP_PCPWM1 : PWM 1
dpslwk	0:7480abd3b63b	231	- CLKPWR_PCONP_PCI2C0 : I2C 0
dpslwk	0:7480abd3b63b	232	- CLKPWR_PCONP_PCSPI : SPI
dpslwk	0:7480abd3b63b	233	- CLKPWR_PCONP_PCRTC : RTC
dpslwk	0:7480abd3b63b	234	- CLKPWR_PCONP_PCSSP1 : SSP 1
dpslwk	0:7480abd3b63b	235	- CLKPWR_PCONP_PCAD : ADC
dpslwk	0:7480abd3b63b	236	- CLKPWR_PCONP_PCAN1 : CAN 1
dpslwk	0:7480abd3b63b	237	- CLKPWR_PCONP_PCAN2 : CAN 2
dpslwk	0:7480abd3b63b	238	- CLKPWR_PCONP_PCGPIO : GPIO
dpslwk	0:7480abd3b63b	239	- CLKPWR_PCONP_PCRIT : RIT
dpslwk	0:7480abd3b63b	240	- CLKPWR_PCONP_PCMC : MC
dpslwk	0:7480abd3b63b	241	- CLKPWR_PCONP_PCQEI : QEI
dpslwk	0:7480abd3b63b	242	- CLKPWR_PCONP_PCI2C1 : I2C 1
dpslwk	0:7480abd3b63b	243	- CLKPWR_PCONP_PCSSP0 : SSP 0
dpslwk	0:7480abd3b63b	244	- CLKPWR_PCONP_PCTIM2 : Timer 2
dpslwk	0:7480abd3b63b	245	- CLKPWR_PCONP_PCTIM3 : Timer 3
dpslwk	0:7480abd3b63b	246	- CLKPWR_PCONP_PCUART2 : UART 2
dpslwk	0:7480abd3b63b	247	- CLKPWR_PCONP_PCUART3 : UART 3
dpslwk	0:7480abd3b63b	248	- CLKPWR_PCONP_PCI2C2 : I2C 2
dpslwk	0:7480abd3b63b	249	- CLKPWR_PCONP_PCI2S : I2S
dpslwk	0:7480abd3b63b	250	- CLKPWR_PCONP_PCGPDMA : GPDMA
dpslwk	0:7480abd3b63b	251	- CLKPWR_PCONP_PCENET : Ethernet
dpslwk	0:7480abd3b63b	252	- CLKPWR_PCONP_PCUSB : USB
dpslwk	0:7480abd3b63b	253	*
dpslwk	0:7480abd3b63b	254	* @param[in] NewState New state of Peripheral Power, should be:
dpslwk	0:7480abd3b63b	255	* - ENABLE : Enable power for this peripheral
dpslwk	0:7480abd3b63b	256	* - DISABLE : Disable power for this peripheral
dpslwk	0:7480abd3b63b	257	*
dpslwk	0:7480abd3b63b	258	* @return none
dpslwk	0:7480abd3b63b	259	**********************************************************************/
dpslwk	0:7480abd3b63b	260	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
dpslwk	0:7480abd3b63b	261	{
dpslwk	0:7480abd3b63b	262	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	263	{
dpslwk	0:7480abd3b63b	264	LPC_SC->PCONP \|= PPType & CLKPWR_PCONP_BITMASK;
dpslwk	0:7480abd3b63b	265	}
dpslwk	0:7480abd3b63b	266	else if (NewState == DISABLE)
dpslwk	0:7480abd3b63b	267	{
dpslwk	0:7480abd3b63b	268	LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
dpslwk	0:7480abd3b63b	269	}
dpslwk	0:7480abd3b63b	270	}
dpslwk	0:7480abd3b63b	271
dpslwk	0:7480abd3b63b	272
dpslwk	0:7480abd3b63b	273	/*******************************************************************//
dpslwk	0:7480abd3b63b	274	* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
dpslwk	0:7480abd3b63b	275	* @param[in] None
dpslwk	0:7480abd3b63b	276	* @return None
dpslwk	0:7480abd3b63b	277	**********************************************************************/
dpslwk	0:7480abd3b63b	278	void CLKPWR_Sleep(void)
dpslwk	0:7480abd3b63b	279	{
dpslwk	0:7480abd3b63b	280	LPC_SC->PCON = 0x00;
dpslwk	0:7480abd3b63b	281	/* Sleep Mode*/
dpslwk	0:7480abd3b63b	282	__WFI();
dpslwk	0:7480abd3b63b	283	}
dpslwk	0:7480abd3b63b	284
dpslwk	0:7480abd3b63b	285
dpslwk	0:7480abd3b63b	286	/*******************************************************************//
dpslwk	0:7480abd3b63b	287	* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
dpslwk	0:7480abd3b63b	288	* @param[in] None
dpslwk	0:7480abd3b63b	289	* @return None
dpslwk	0:7480abd3b63b	290	**********************************************************************/
dpslwk	0:7480abd3b63b	291	void CLKPWR_DeepSleep(void)
dpslwk	0:7480abd3b63b	292	{
dpslwk	0:7480abd3b63b	293	/* Deep-Sleep Mode, set SLEEPDEEP bit */
dpslwk	0:7480abd3b63b	294	SCB->SCR = 0x4;
dpslwk	0:7480abd3b63b	295	LPC_SC->PCON = 0x8;
dpslwk	0:7480abd3b63b	296	/* Deep Sleep Mode*/
dpslwk	0:7480abd3b63b	297	__WFI();
dpslwk	0:7480abd3b63b	298	}
dpslwk	0:7480abd3b63b	299
dpslwk	0:7480abd3b63b	300
dpslwk	0:7480abd3b63b	301	/*******************************************************************//
dpslwk	0:7480abd3b63b	302	* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
dpslwk	0:7480abd3b63b	303	* @param[in] None
dpslwk	0:7480abd3b63b	304	* @return None
dpslwk	0:7480abd3b63b	305	**********************************************************************/
dpslwk	0:7480abd3b63b	306	void CLKPWR_PowerDown(void)
dpslwk	0:7480abd3b63b	307	{
dpslwk	0:7480abd3b63b	308	/* Deep-Sleep Mode, set SLEEPDEEP bit */
dpslwk	0:7480abd3b63b	309	SCB->SCR = 0x4;
dpslwk	0:7480abd3b63b	310	LPC_SC->PCON = 0x09;
dpslwk	0:7480abd3b63b	311	/* Power Down Mode*/
dpslwk	0:7480abd3b63b	312	__WFI();
dpslwk	0:7480abd3b63b	313	}
dpslwk	0:7480abd3b63b	314
dpslwk	0:7480abd3b63b	315
dpslwk	0:7480abd3b63b	316	/*******************************************************************//
dpslwk	0:7480abd3b63b	317	* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
dpslwk	0:7480abd3b63b	318	* @param[in] None
dpslwk	0:7480abd3b63b	319	* @return None
dpslwk	0:7480abd3b63b	320	**********************************************************************/
dpslwk	0:7480abd3b63b	321	void CLKPWR_DeepPowerDown(void)
dpslwk	0:7480abd3b63b	322	{
dpslwk	0:7480abd3b63b	323	/* Deep-Sleep Mode, set SLEEPDEEP bit */
dpslwk	0:7480abd3b63b	324	SCB->SCR = 0x4;
dpslwk	0:7480abd3b63b	325	LPC_SC->PCON = 0x03;
dpslwk	0:7480abd3b63b	326	/* Deep Power Down Mode*/
dpslwk	0:7480abd3b63b	327	__WFI();
dpslwk	0:7480abd3b63b	328	}
dpslwk	0:7480abd3b63b	329
dpslwk	0:7480abd3b63b	330	/**
dpslwk	0:7480abd3b63b	331	* @}
dpslwk	0:7480abd3b63b	332	*/
dpslwk	0:7480abd3b63b	333
dpslwk	0:7480abd3b63b	334	/**
dpslwk	0:7480abd3b63b	335	* @}
dpslwk	0:7480abd3b63b	336	*/
dpslwk	0:7480abd3b63b	337
dpslwk	0:7480abd3b63b	338	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Sep 2010
Imports:	234
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	6

lpc17xx_clkpwr.c@0:7480abd3b63b, 2010-09-30 (annotated)

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