Example self-announcing webserver which controls a servo through a smallHTML userinterface.

Dependencies:   mbed

Committer:
dirkx
Date:
Sat Aug 14 15:56:01 2010 +0000
Revision:
0:a259777c45a3

        

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dirkx 0:a259777c45a3 1
dirkx 0:a259777c45a3 2 /*
dirkx 0:a259777c45a3 3 Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
dirkx 0:a259777c45a3 4
dirkx 0:a259777c45a3 5 Permission is hereby granted, free of charge, to any person obtaining a copy
dirkx 0:a259777c45a3 6 of this software and associated documentation files (the "Software"), to deal
dirkx 0:a259777c45a3 7 in the Software without restriction, including without limitation the rights
dirkx 0:a259777c45a3 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
dirkx 0:a259777c45a3 9 copies of the Software, and to permit persons to whom the Software is
dirkx 0:a259777c45a3 10 furnished to do so, subject to the following conditions:
dirkx 0:a259777c45a3 11
dirkx 0:a259777c45a3 12 The above copyright notice and this permission notice shall be included in
dirkx 0:a259777c45a3 13 all copies or substantial portions of the Software.
dirkx 0:a259777c45a3 14
dirkx 0:a259777c45a3 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
dirkx 0:a259777c45a3 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
dirkx 0:a259777c45a3 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
dirkx 0:a259777c45a3 18 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
dirkx 0:a259777c45a3 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
dirkx 0:a259777c45a3 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
dirkx 0:a259777c45a3 21 THE SOFTWARE.
dirkx 0:a259777c45a3 22 */
dirkx 0:a259777c45a3 23
dirkx 0:a259777c45a3 24 /*
dirkx 0:a259777c45a3 25 **************************************************************************************************************
dirkx 0:a259777c45a3 26 * NXP USB Host Stack
dirkx 0:a259777c45a3 27 *
dirkx 0:a259777c45a3 28 * (c) Copyright 2008, NXP SemiConductors
dirkx 0:a259777c45a3 29 * (c) Copyright 2008, OnChip Technologies LLC
dirkx 0:a259777c45a3 30 * All Rights Reserved
dirkx 0:a259777c45a3 31 *
dirkx 0:a259777c45a3 32 * www.nxp.com
dirkx 0:a259777c45a3 33 * www.onchiptech.com
dirkx 0:a259777c45a3 34 *
dirkx 0:a259777c45a3 35 * File : usbhost_lpc17xx.h
dirkx 0:a259777c45a3 36 * Programmer(s) : Ravikanth.P
dirkx 0:a259777c45a3 37 * Version :
dirkx 0:a259777c45a3 38 *
dirkx 0:a259777c45a3 39 **************************************************************************************************************
dirkx 0:a259777c45a3 40 */
dirkx 0:a259777c45a3 41
dirkx 0:a259777c45a3 42 #ifndef USBHOST_LPC17xx_H
dirkx 0:a259777c45a3 43 #define USBHOST_LPC17xx_H
dirkx 0:a259777c45a3 44
dirkx 0:a259777c45a3 45 /*
dirkx 0:a259777c45a3 46 **************************************************************************************************************
dirkx 0:a259777c45a3 47 * INCLUDE HEADER FILES
dirkx 0:a259777c45a3 48 **************************************************************************************************************
dirkx 0:a259777c45a3 49 */
dirkx 0:a259777c45a3 50
dirkx 0:a259777c45a3 51 #include "usbhost_inc.h"
dirkx 0:a259777c45a3 52
dirkx 0:a259777c45a3 53 /*
dirkx 0:a259777c45a3 54 **************************************************************************************************************
dirkx 0:a259777c45a3 55 * PRINT CONFIGURATION
dirkx 0:a259777c45a3 56 **************************************************************************************************************
dirkx 0:a259777c45a3 57 */
dirkx 0:a259777c45a3 58
dirkx 0:a259777c45a3 59 #define PRINT_ENABLE 1
dirkx 0:a259777c45a3 60
dirkx 0:a259777c45a3 61 #if PRINT_ENABLE
dirkx 0:a259777c45a3 62 #define PRINT_Log(...) printf(__VA_ARGS__)
dirkx 0:a259777c45a3 63 #define PRINT_Err(rc) printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
dirkx 0:a259777c45a3 64
dirkx 0:a259777c45a3 65 #else
dirkx 0:a259777c45a3 66 #define PRINT_Log(...) do {} while(0)
dirkx 0:a259777c45a3 67 #define PRINT_Err(rc) do {} while(0)
dirkx 0:a259777c45a3 68
dirkx 0:a259777c45a3 69 #endif
dirkx 0:a259777c45a3 70
dirkx 0:a259777c45a3 71 /*
dirkx 0:a259777c45a3 72 **************************************************************************************************************
dirkx 0:a259777c45a3 73 * GENERAL DEFINITIONS
dirkx 0:a259777c45a3 74 **************************************************************************************************************
dirkx 0:a259777c45a3 75 */
dirkx 0:a259777c45a3 76
dirkx 0:a259777c45a3 77 #define DESC_LENGTH(x) x[0]
dirkx 0:a259777c45a3 78 #define DESC_TYPE(x) x[1]
dirkx 0:a259777c45a3 79
dirkx 0:a259777c45a3 80
dirkx 0:a259777c45a3 81 #define HOST_GET_DESCRIPTOR(descType, descIndex, data, length) \
dirkx 0:a259777c45a3 82 Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR, \
dirkx 0:a259777c45a3 83 (descType << 8)|(descIndex), 0, length, data)
dirkx 0:a259777c45a3 84
dirkx 0:a259777c45a3 85 #define HOST_SET_ADDRESS(new_addr) \
dirkx 0:a259777c45a3 86 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS, \
dirkx 0:a259777c45a3 87 new_addr, 0, 0, NULL)
dirkx 0:a259777c45a3 88
dirkx 0:a259777c45a3 89 #define USBH_SET_CONFIGURATION(configNum) \
dirkx 0:a259777c45a3 90 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
dirkx 0:a259777c45a3 91 configNum, 0, 0, NULL)
dirkx 0:a259777c45a3 92
dirkx 0:a259777c45a3 93 #define USBH_SET_INTERFACE(ifNum, altNum) \
dirkx 0:a259777c45a3 94 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE, \
dirkx 0:a259777c45a3 95 altNum, ifNum, 0, NULL)
dirkx 0:a259777c45a3 96
dirkx 0:a259777c45a3 97 /*
dirkx 0:a259777c45a3 98 **************************************************************************************************************
dirkx 0:a259777c45a3 99 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
dirkx 0:a259777c45a3 100 **************************************************************************************************************
dirkx 0:a259777c45a3 101 */
dirkx 0:a259777c45a3 102
dirkx 0:a259777c45a3 103 /* ------------------ HcControl Register --------------------- */
dirkx 0:a259777c45a3 104 #define OR_CONTROL_CLE 0x00000010
dirkx 0:a259777c45a3 105 #define OR_CONTROL_BLE 0x00000020
dirkx 0:a259777c45a3 106 #define OR_CONTROL_HCFS 0x000000C0
dirkx 0:a259777c45a3 107 #define OR_CONTROL_HC_OPER 0x00000080
dirkx 0:a259777c45a3 108 /* ----------------- HcCommandStatus Register ----------------- */
dirkx 0:a259777c45a3 109 #define OR_CMD_STATUS_HCR 0x00000001
dirkx 0:a259777c45a3 110 #define OR_CMD_STATUS_CLF 0x00000002
dirkx 0:a259777c45a3 111 #define OR_CMD_STATUS_BLF 0x00000004
dirkx 0:a259777c45a3 112 /* --------------- HcInterruptStatus Register ----------------- */
dirkx 0:a259777c45a3 113 #define OR_INTR_STATUS_WDH 0x00000002
dirkx 0:a259777c45a3 114 #define OR_INTR_STATUS_RHSC 0x00000040
dirkx 0:a259777c45a3 115 /* --------------- HcInterruptEnable Register ----------------- */
dirkx 0:a259777c45a3 116 #define OR_INTR_ENABLE_WDH 0x00000002
dirkx 0:a259777c45a3 117 #define OR_INTR_ENABLE_RHSC 0x00000040
dirkx 0:a259777c45a3 118 #define OR_INTR_ENABLE_MIE 0x80000000
dirkx 0:a259777c45a3 119 /* ---------------- HcRhDescriptorA Register ------------------ */
dirkx 0:a259777c45a3 120 #define OR_RH_STATUS_LPSC 0x00010000
dirkx 0:a259777c45a3 121 #define OR_RH_STATUS_DRWE 0x00008000
dirkx 0:a259777c45a3 122 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
dirkx 0:a259777c45a3 123 #define OR_RH_PORT_CCS 0x00000001
dirkx 0:a259777c45a3 124 #define OR_RH_PORT_PRS 0x00000010
dirkx 0:a259777c45a3 125 #define OR_RH_PORT_CSC 0x00010000
dirkx 0:a259777c45a3 126 #define OR_RH_PORT_PRSC 0x00100000
dirkx 0:a259777c45a3 127
dirkx 0:a259777c45a3 128
dirkx 0:a259777c45a3 129 /*
dirkx 0:a259777c45a3 130 **************************************************************************************************************
dirkx 0:a259777c45a3 131 * FRAME INTERVAL
dirkx 0:a259777c45a3 132 **************************************************************************************************************
dirkx 0:a259777c45a3 133 */
dirkx 0:a259777c45a3 134
dirkx 0:a259777c45a3 135 #define FI 0x2EDF /* 12000 bits per frame (-1) */
dirkx 0:a259777c45a3 136 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
dirkx 0:a259777c45a3 137
dirkx 0:a259777c45a3 138 /*
dirkx 0:a259777c45a3 139 **************************************************************************************************************
dirkx 0:a259777c45a3 140 * ENDPOINT DESCRIPTOR CONTROL FIELDS
dirkx 0:a259777c45a3 141 **************************************************************************************************************
dirkx 0:a259777c45a3 142 */
dirkx 0:a259777c45a3 143
dirkx 0:a259777c45a3 144 #define ED_SKIP (USB_INT32U) (0x00001000) /* Skip this ep in queue */
dirkx 0:a259777c45a3 145
dirkx 0:a259777c45a3 146 /*
dirkx 0:a259777c45a3 147 **************************************************************************************************************
dirkx 0:a259777c45a3 148 * TRANSFER DESCRIPTOR CONTROL FIELDS
dirkx 0:a259777c45a3 149 **************************************************************************************************************
dirkx 0:a259777c45a3 150 */
dirkx 0:a259777c45a3 151
dirkx 0:a259777c45a3 152 #define TD_ROUNDING (USB_INT32U) (0x00040000) /* Buffer Rounding */
dirkx 0:a259777c45a3 153 #define TD_SETUP (USB_INT32U)(0) /* Direction of Setup Packet */
dirkx 0:a259777c45a3 154 #define TD_IN (USB_INT32U)(0x00100000) /* Direction In */
dirkx 0:a259777c45a3 155 #define TD_OUT (USB_INT32U)(0x00080000) /* Direction Out */
dirkx 0:a259777c45a3 156 #define TD_DELAY_INT(x) (USB_INT32U)((x) << 21) /* Delay Interrupt */
dirkx 0:a259777c45a3 157 #define TD_TOGGLE_0 (USB_INT32U)(0x02000000) /* Toggle 0 */
dirkx 0:a259777c45a3 158 #define TD_TOGGLE_1 (USB_INT32U)(0x03000000) /* Toggle 1 */
dirkx 0:a259777c45a3 159 #define TD_CC (USB_INT32U)(0xF0000000) /* Completion Code */
dirkx 0:a259777c45a3 160
dirkx 0:a259777c45a3 161 /*
dirkx 0:a259777c45a3 162 **************************************************************************************************************
dirkx 0:a259777c45a3 163 * USB STANDARD REQUEST DEFINITIONS
dirkx 0:a259777c45a3 164 **************************************************************************************************************
dirkx 0:a259777c45a3 165 */
dirkx 0:a259777c45a3 166
dirkx 0:a259777c45a3 167 #define USB_DESCRIPTOR_TYPE_DEVICE 1
dirkx 0:a259777c45a3 168 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
dirkx 0:a259777c45a3 169 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
dirkx 0:a259777c45a3 170 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
dirkx 0:a259777c45a3 171 /* ----------- Control RequestType Fields ----------- */
dirkx 0:a259777c45a3 172 #define USB_DEVICE_TO_HOST 0x80
dirkx 0:a259777c45a3 173 #define USB_HOST_TO_DEVICE 0x00
dirkx 0:a259777c45a3 174 #define USB_REQUEST_TYPE_CLASS 0x20
dirkx 0:a259777c45a3 175 #define USB_RECIPIENT_DEVICE 0x00
dirkx 0:a259777c45a3 176 #define USB_RECIPIENT_INTERFACE 0x01
dirkx 0:a259777c45a3 177 /* -------------- USB Standard Requests -------------- */
dirkx 0:a259777c45a3 178 #define SET_ADDRESS 5
dirkx 0:a259777c45a3 179 #define GET_DESCRIPTOR 6
dirkx 0:a259777c45a3 180 #define SET_CONFIGURATION 9
dirkx 0:a259777c45a3 181 #define SET_INTERFACE 11
dirkx 0:a259777c45a3 182
dirkx 0:a259777c45a3 183 /*
dirkx 0:a259777c45a3 184 **************************************************************************************************************
dirkx 0:a259777c45a3 185 * TYPE DEFINITIONS
dirkx 0:a259777c45a3 186 **************************************************************************************************************
dirkx 0:a259777c45a3 187 */
dirkx 0:a259777c45a3 188
dirkx 0:a259777c45a3 189 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
dirkx 0:a259777c45a3 190 volatile USB_INT32U Control; /* Endpoint descriptor control */
dirkx 0:a259777c45a3 191 volatile USB_INT32U TailTd; /* Physical address of tail in Transfer descriptor list */
dirkx 0:a259777c45a3 192 volatile USB_INT32U HeadTd; /* Physcial address of head in Transfer descriptor list */
dirkx 0:a259777c45a3 193 volatile USB_INT32U Next; /* Physical address of next Endpoint descriptor */
dirkx 0:a259777c45a3 194 } HCED;
dirkx 0:a259777c45a3 195
dirkx 0:a259777c45a3 196 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
dirkx 0:a259777c45a3 197 volatile USB_INT32U Control; /* Transfer descriptor control */
dirkx 0:a259777c45a3 198 volatile USB_INT32U CurrBufPtr; /* Physical address of current buffer pointer */
dirkx 0:a259777c45a3 199 volatile USB_INT32U Next; /* Physical pointer to next Transfer Descriptor */
dirkx 0:a259777c45a3 200 volatile USB_INT32U BufEnd; /* Physical address of end of buffer */
dirkx 0:a259777c45a3 201 } HCTD;
dirkx 0:a259777c45a3 202
dirkx 0:a259777c45a3 203 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
dirkx 0:a259777c45a3 204 volatile USB_INT32U IntTable[32]; /* Interrupt Table */
dirkx 0:a259777c45a3 205 volatile USB_INT32U FrameNumber; /* Frame Number */
dirkx 0:a259777c45a3 206 volatile USB_INT32U DoneHead; /* Done Head */
dirkx 0:a259777c45a3 207 volatile USB_INT08U Reserved[116]; /* Reserved for future use */
dirkx 0:a259777c45a3 208 volatile USB_INT08U Unknown[4]; /* Unused */
dirkx 0:a259777c45a3 209 } HCCA;
dirkx 0:a259777c45a3 210
dirkx 0:a259777c45a3 211 /*
dirkx 0:a259777c45a3 212 **************************************************************************************************************
dirkx 0:a259777c45a3 213 * EXTERN DECLARATIONS
dirkx 0:a259777c45a3 214 **************************************************************************************************************
dirkx 0:a259777c45a3 215 */
dirkx 0:a259777c45a3 216 #if 0
dirkx 0:a259777c45a3 217 extern volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
dirkx 0:a259777c45a3 218 extern volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
dirkx 0:a259777c45a3 219 extern volatile HCED *EDBulkHead;
dirkx 0:a259777c45a3 220 extern volatile HCTD *TDHead; /* Head transfer descriptor structure */
dirkx 0:a259777c45a3 221 extern volatile HCTD *TDTail; /* Tail transfer descriptor structure */
dirkx 0:a259777c45a3 222 #endif
dirkx 0:a259777c45a3 223 extern volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
dirkx 0:a259777c45a3 224
dirkx 0:a259777c45a3 225 /*
dirkx 0:a259777c45a3 226 **************************************************************************************************************
dirkx 0:a259777c45a3 227 * FUNCTION PROTOTYPES
dirkx 0:a259777c45a3 228 **************************************************************************************************************
dirkx 0:a259777c45a3 229 */
dirkx 0:a259777c45a3 230
dirkx 0:a259777c45a3 231 void Host_Init (void);
dirkx 0:a259777c45a3 232
dirkx 0:a259777c45a3 233 extern "C" void USB_IRQHandler(void) __irq;
dirkx 0:a259777c45a3 234
dirkx 0:a259777c45a3 235 USB_INT32S Host_EnumDev (void);
dirkx 0:a259777c45a3 236
dirkx 0:a259777c45a3 237 USB_INT32S Host_TDresult(volatile HCED *ed,
dirkx 0:a259777c45a3 238 volatile USB_INT32U token);
dirkx 0:a259777c45a3 239
dirkx 0:a259777c45a3 240 USB_INT32S Host_ProcessTD(volatile HCED *ed,
dirkx 0:a259777c45a3 241 volatile USB_INT32U token,
dirkx 0:a259777c45a3 242 volatile USB_INT08U *buffer,
dirkx 0:a259777c45a3 243 USB_INT32U buffer_len,
dirkx 0:a259777c45a3 244 bool block = true);
dirkx 0:a259777c45a3 245
dirkx 0:a259777c45a3 246
dirkx 0:a259777c45a3 247 void Host_DelayUS ( USB_INT32U delay);
dirkx 0:a259777c45a3 248 void Host_DelayMS ( USB_INT32U delay);
dirkx 0:a259777c45a3 249
dirkx 0:a259777c45a3 250
dirkx 0:a259777c45a3 251 void Host_TDInit (volatile HCTD *td);
dirkx 0:a259777c45a3 252 void Host_EDInit (volatile HCED *ed);
dirkx 0:a259777c45a3 253 void Host_HCCAInit (volatile HCCA *hcca);
dirkx 0:a259777c45a3 254
dirkx 0:a259777c45a3 255 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
dirkx 0:a259777c45a3 256 USB_INT08U b_request,
dirkx 0:a259777c45a3 257 USB_INT16U w_value,
dirkx 0:a259777c45a3 258 USB_INT16U w_index,
dirkx 0:a259777c45a3 259 USB_INT16U w_length,
dirkx 0:a259777c45a3 260 volatile USB_INT08U *buffer);
dirkx 0:a259777c45a3 261
dirkx 0:a259777c45a3 262 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
dirkx 0:a259777c45a3 263 USB_INT08U b_request,
dirkx 0:a259777c45a3 264 USB_INT16U w_value,
dirkx 0:a259777c45a3 265 USB_INT16U w_index,
dirkx 0:a259777c45a3 266 USB_INT16U w_length,
dirkx 0:a259777c45a3 267 volatile USB_INT08U *buffer);
dirkx 0:a259777c45a3 268
dirkx 0:a259777c45a3 269 void Host_FillSetup( USB_INT08U bm_request_type,
dirkx 0:a259777c45a3 270 USB_INT08U b_request,
dirkx 0:a259777c45a3 271 USB_INT16U w_value,
dirkx 0:a259777c45a3 272 USB_INT16U w_index,
dirkx 0:a259777c45a3 273 USB_INT16U w_length);
dirkx 0:a259777c45a3 274
dirkx 0:a259777c45a3 275
dirkx 0:a259777c45a3 276 void Host_WDHWait (void);
dirkx 0:a259777c45a3 277
dirkx 0:a259777c45a3 278
dirkx 0:a259777c45a3 279 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem);
dirkx 0:a259777c45a3 280 void WriteLE32U (volatile USB_INT08U *pmem,
dirkx 0:a259777c45a3 281 USB_INT32U val);
dirkx 0:a259777c45a3 282 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem);
dirkx 0:a259777c45a3 283 void WriteLE16U (volatile USB_INT08U *pmem,
dirkx 0:a259777c45a3 284 USB_INT16U val);
dirkx 0:a259777c45a3 285 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem);
dirkx 0:a259777c45a3 286 void WriteBE32U (volatile USB_INT08U *pmem,
dirkx 0:a259777c45a3 287 USB_INT32U val);
dirkx 0:a259777c45a3 288 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem);
dirkx 0:a259777c45a3 289 void WriteBE16U (volatile USB_INT08U *pmem,
dirkx 0:a259777c45a3 290 USB_INT16U val);
dirkx 0:a259777c45a3 291
dirkx 0:a259777c45a3 292 #endif