Sadaei Osakabe / Mbed 2 deprecated OV7670_with_AL422B_Color_Size_test

OV7670_with_AL422B Color & Size Test Program

Dependencies:   mbed

ov7670reg.h@4:2c412c97678c, 2013-02-18 (annotated)

Committer:
diasea
Date:
Mon Feb 18 07:53:46 2013 +0000
Revision:
4:2c412c97678c
Parent:
0:6be5fa68dddc 
fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
diasea 0:6be5fa68dddc 1 // size register
diasea 0:6be5fa68dddc 2 #define REG_COM7 0x12 /* Control 7 */
diasea 0:6be5fa68dddc 3 #define REG_HSTART 0x17 /* Horiz start high bits */
diasea 0:6be5fa68dddc 4 #define REG_HSTOP 0x18 /* Horiz stop high bits */
diasea 0:6be5fa68dddc 5 #define REG_HREF 0x32 /* HREF pieces */
diasea 0:6be5fa68dddc 6 #define REG_VSTART 0x19 /* Vert start high bits */
diasea 0:6be5fa68dddc 7 #define REG_VSTOP 0x1a /* Vert stop high bits */
diasea 0:6be5fa68dddc 8 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
diasea 0:6be5fa68dddc 9 #define REG_COM3 0x0c /* Control 3 */
diasea 0:6be5fa68dddc 10 #define REG_COM14 0x3e /* Control 14 */
diasea 0:6be5fa68dddc 11 #define REG_SCALING_XSC 0x70
diasea 0:6be5fa68dddc 12 #define REG_SCALING_YSC 0x71
diasea 0:6be5fa68dddc 13 #define REG_SCALING_DCWCTR 0x72
diasea 0:6be5fa68dddc 14 #define REG_SCALING_PCLK_DIV 0x73
diasea 0:6be5fa68dddc 15 #define REG_SCALING_PCLK_DELAY 0xa2
diasea 0:6be5fa68dddc 16
diasea 0:6be5fa68dddc 17 // VGA setting
diasea 0:6be5fa68dddc 18 #define COM7_VGA 0x00
diasea 0:6be5fa68dddc 19 #define HSTART_VGA 0x13
diasea 0:6be5fa68dddc 20 #define HSTOP_VGA 0x01
diasea 4:2c412c97678c 21 #define HREF_VGA 0x36 //0xb6 0x36
diasea 0:6be5fa68dddc 22 #define VSTART_VGA 0x02
diasea 0:6be5fa68dddc 23 #define VSTOP_VGA 0x7a
diasea 0:6be5fa68dddc 24 #define VREF_VGA 0x0a
diasea 0:6be5fa68dddc 25 #define COM3_VGA 0x00
diasea 0:6be5fa68dddc 26 #define COM14_VGA 0x00
diasea 0:6be5fa68dddc 27 #define SCALING_XSC_VGA 0x3a
diasea 0:6be5fa68dddc 28 #define SCALING_YSC_VGA 0x35
diasea 0:6be5fa68dddc 29 #define SCALING_DCWCTR_VGA 0x11
diasea 0:6be5fa68dddc 30 #define SCALING_PCLK_DIV_VGA 0xf0
diasea 0:6be5fa68dddc 31 #define SCALING_PCLK_DELAY_VGA 0x02
diasea 0:6be5fa68dddc 32
diasea 0:6be5fa68dddc 33 // QVGA setting
diasea 0:6be5fa68dddc 34 #define COM7_QVGA 0x00
diasea 0:6be5fa68dddc 35 #define HSTART_QVGA 0x16
diasea 0:6be5fa68dddc 36 #define HSTOP_QVGA 0x04
diasea 0:6be5fa68dddc 37 #define HREF_QVGA 0x00
diasea 0:6be5fa68dddc 38 #define VSTART_QVGA 0x02
diasea 0:6be5fa68dddc 39 #define VSTOP_QVGA 0x7a
diasea 0:6be5fa68dddc 40 #define VREF_QVGA 0x0a
diasea 0:6be5fa68dddc 41 #define COM3_QVGA 0x04
diasea 0:6be5fa68dddc 42 #define COM14_QVGA 0x19
diasea 0:6be5fa68dddc 43 #define SCALING_XSC_QVGA 0x3a
diasea 0:6be5fa68dddc 44 #define SCALING_YSC_QVGA 0x35
diasea 0:6be5fa68dddc 45 #define SCALING_DCWCTR_QVGA 0x11
diasea 0:6be5fa68dddc 46 #define SCALING_PCLK_DIV_QVGA 0xf1
diasea 0:6be5fa68dddc 47 #define SCALING_PCLK_DELAY_QVGA 0x02
diasea 0:6be5fa68dddc 48
diasea 0:6be5fa68dddc 49 // QQVGA setting
diasea 0:6be5fa68dddc 50 #define COM7_QQVGA 0x00
diasea 0:6be5fa68dddc 51 #define HSTART_QQVGA 0x16
diasea 0:6be5fa68dddc 52 #define HSTOP_QQVGA 0x04
diasea 0:6be5fa68dddc 53 #define HREF_QQVGA 0xa4 //0x24? 0xa4?
diasea 0:6be5fa68dddc 54 #define VSTART_QQVGA 0x02
diasea 0:6be5fa68dddc 55 #define VSTOP_QQVGA 0x7a
diasea 0:6be5fa68dddc 56 #define VREF_QQVGA 0x0a
diasea 0:6be5fa68dddc 57 #define COM3_QQVGA 0x04
diasea 0:6be5fa68dddc 58 #define COM14_QQVGA 0x1a
diasea 0:6be5fa68dddc 59 #define SCALING_XSC_QQVGA 0x3a
diasea 0:6be5fa68dddc 60 #define SCALING_YSC_QQVGA 0x35
diasea 0:6be5fa68dddc 61 #define SCALING_DCWCTR_QQVGA 0x22
diasea 0:6be5fa68dddc 62 #define SCALING_PCLK_DIV_QQVGA 0xf2
diasea 0:6be5fa68dddc 63 #define SCALING_PCLK_DELAY_QQVGA 0x02
diasea 0:6be5fa68dddc 64
diasea 0:6be5fa68dddc 65 // CIF setting no tested linux src 2.6.29-rc5 ov7670_soc.c
diasea 0:6be5fa68dddc 66 #define COM7_CIF 0x00
diasea 0:6be5fa68dddc 67 #define HSTART_CIF 0x15
diasea 0:6be5fa68dddc 68 #define HSTOP_CIF 0x0b
diasea 0:6be5fa68dddc 69 #define HREF_CIF 0xb6
diasea 0:6be5fa68dddc 70 #define VSTART_CIF 0x03
diasea 0:6be5fa68dddc 71 #define VSTOP_CIF 0x7b
diasea 0:6be5fa68dddc 72 #define VREF_CIF 0x02
diasea 0:6be5fa68dddc 73 #define COM3_CIF 0x08
diasea 0:6be5fa68dddc 74 #define COM14_CIF 0x11
diasea 0:6be5fa68dddc 75 #define SCALING_XSC_CIF 0x3a
diasea 0:6be5fa68dddc 76 #define SCALING_YSC_CIF 0x35
diasea 0:6be5fa68dddc 77 #define SCALING_DCWCTR_CIF 0x11
diasea 0:6be5fa68dddc 78 #define SCALING_PCLK_DIV_CIF 0xf1
diasea 0:6be5fa68dddc 79 #define SCALING_PCLK_DELAY_CIF 0x02
diasea 0:6be5fa68dddc 80
diasea 0:6be5fa68dddc 81 // QCIF setting no tested no tested linux src 2.6.29-rc5 ov7670_soc.c
diasea 0:6be5fa68dddc 82 #define COM7_QCIF 0x00
diasea 0:6be5fa68dddc 83 #define HSTART_QCIF 0x39
diasea 0:6be5fa68dddc 84 #define HSTOP_QCIF 0x03
diasea 0:6be5fa68dddc 85 #define HREF_QCIF 0x80
diasea 0:6be5fa68dddc 86 #define VSTART_QCIF 0x03
diasea 0:6be5fa68dddc 87 #define VSTOP_QCIF 0x7b
diasea 0:6be5fa68dddc 88 #define VREF_QCIF 0x02
diasea 0:6be5fa68dddc 89 #define COM3_QCIF 0x0c
diasea 0:6be5fa68dddc 90 #define COM14_QCIF 0x11
diasea 0:6be5fa68dddc 91 #define SCALING_XSC_QCIF 0x3a
diasea 0:6be5fa68dddc 92 #define SCALING_YSC_QCIF 0x35
diasea 0:6be5fa68dddc 93 #define SCALING_DCWCTR_QCIF 0x11
diasea 0:6be5fa68dddc 94 #define SCALING_PCLK_DIV_QCIF 0xf1
diasea 0:6be5fa68dddc 95 #define SCALING_PCLK_DELAY_QCIF 0x52
diasea 0:6be5fa68dddc 96
diasea 0:6be5fa68dddc 97 // YUV
diasea 0:6be5fa68dddc 98 #define REG_COM13 0x3d /* Control 13 */
diasea 0:6be5fa68dddc 99 #define REG_TSLB 0x3a /* lots of stuff */
diasea 0:6be5fa68dddc 100
diasea 0:6be5fa68dddc 101 #define COM7_YUV 0x00 /* YUV */
diasea 0:6be5fa68dddc 102 #define COM13_UV 0x00 /* U before V - w/TSLB */
diasea 0:6be5fa68dddc 103 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
diasea 0:6be5fa68dddc 104 #define TSLB_VLAST 0x00 /* YUYV - see com13 */
diasea 0:6be5fa68dddc 105 #define TSLB_ULAST 0x00 /* YVYU - see com13 */
diasea 0:6be5fa68dddc 106 #define TSLB_YLAST 0x08 /* UYVY or VYUY - see com13 */
diasea 0:6be5fa68dddc 107
diasea 0:6be5fa68dddc 108 // RGB
diasea 0:6be5fa68dddc 109 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
diasea 0:6be5fa68dddc 110
diasea 0:6be5fa68dddc 111 // RGB444
diasea 0:6be5fa68dddc 112 #define REG_RGB444 0x8c /* RGB 444 control */
diasea 0:6be5fa68dddc 113 #define REG_COM15 0x40 /* Control 15 */
diasea 0:6be5fa68dddc 114
diasea 0:6be5fa68dddc 115 #define RGB444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
diasea 0:6be5fa68dddc 116 #define RGB444_XBGR 0x00
diasea 0:6be5fa68dddc 117 #define RGB444_BGRX 0x01 /* Empty nibble at end */
diasea 0:6be5fa68dddc 118 #define COM15_RGB444 0x10 /* RGB444 output */
diasea 0:6be5fa68dddc 119
diasea 0:6be5fa68dddc 120 // RGB555
diasea 0:6be5fa68dddc 121 #define RGB444_DISABLE 0x00 /* Turn off RGB444, overrides 5x5 */
diasea 0:6be5fa68dddc 122 #define COM15_RGB555 0x30 /* RGB555 output */
diasea 0:6be5fa68dddc 123
diasea 0:6be5fa68dddc 124 // RGB565
diasea 0:6be5fa68dddc 125 #define COM15_RGB565 0x10 /* RGB565 output */
diasea 0:6be5fa68dddc 126
diasea 0:6be5fa68dddc 127 // Bayer RGB
diasea 0:6be5fa68dddc 128 #define COM7_BAYER 0x01 /* Bayer format */
diasea 0:6be5fa68dddc 129 #define COM7_PBAYER 0x05 /* "Processed bayer" */
diasea 0:6be5fa68dddc 130
diasea 0:6be5fa68dddc 131
diasea 0:6be5fa68dddc 132 // data format
diasea 0:6be5fa68dddc 133 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
diasea 0:6be5fa68dddc 134 #define COM15_R01FE 0x80 /* 01 to FE */
diasea 0:6be5fa68dddc 135 #define COM15_R00FF 0xc0 /* 00 to FF */
diasea 0:6be5fa68dddc 136
diasea 0:6be5fa68dddc 137 // Night mode, flicker, banding /
diasea 0:6be5fa68dddc 138 #define REG_COM11 0x3b /* Control 11 */
diasea 0:6be5fa68dddc 139 #define COM11_NIGHT 0x80 /* NIght mode enable */
diasea 0:6be5fa68dddc 140 #define COM11_NIGHT_MIN_RATE_1_1 0x00 /* Normal mode same */
diasea 0:6be5fa68dddc 141 #define COM11_NIGHT_MIN_RATE_1_2 0x20 /* Normal mode 1/2 */
diasea 0:6be5fa68dddc 142 #define COM11_NIGHT_MIN_RATE_1_4 0x40 /* Normal mode 1/4 */
diasea 0:6be5fa68dddc 143 #define COM11_NIGHT_MIN_RATE_1_8 0x60 /* Normal mode 1/5 */
diasea 0:6be5fa68dddc 144 #define COM11_HZAUTO_ON 0x10 /* Auto detect 50/60 Hz on */
diasea 0:6be5fa68dddc 145 #define COM11_HZAUTO_OFF 0x00 /* Auto detect 50/60 Hz off */
diasea 0:6be5fa68dddc 146 #define COM11_60HZ 0x00 /* Manual 60Hz select */
diasea 0:6be5fa68dddc 147 #define COM11_50HZ 0x08 /* Manual 50Hz select */
diasea 0:6be5fa68dddc 148 #define COM11_EXP 0x02
diasea 0:6be5fa68dddc 149
diasea 0:6be5fa68dddc 150 #define REG_MTX1 0x4f
diasea 0:6be5fa68dddc 151 #define REG_MTX2 0x50
diasea 0:6be5fa68dddc 152 #define REG_MTX3 0x51
diasea 0:6be5fa68dddc 153 #define REG_MTX4 0x52
diasea 0:6be5fa68dddc 154 #define REG_MTX5 0x53
diasea 0:6be5fa68dddc 155 #define REG_MTX6 0x54
diasea 0:6be5fa68dddc 156 #define REG_BRIGHT 0x55 /* Brightness */
diasea 0:6be5fa68dddc 157 #define REG_CONTRAS 0x56 /* Contrast control */
diasea 0:6be5fa68dddc 158 #define REG_CONTRAS_CENTER 0x57
diasea 0:6be5fa68dddc 159 #define REG_MTXS 0x58
diasea 0:6be5fa68dddc 160 #define REG_MANU 0x67
diasea 0:6be5fa68dddc 161 #define REG_MANV 0x68
diasea 0:6be5fa68dddc 162 #define REG_GFIX 0x69 /* Fix gain control */
diasea 0:6be5fa68dddc 163 #define REG_GGAIN 0x6a
diasea 0:6be5fa68dddc 164 #define REG_DBLV 0x6b
diasea 0:6be5fa68dddc 165
diasea 0:6be5fa68dddc 166 #define REG_COM9 0x14 // Control 9 - gain ceiling
diasea 0:6be5fa68dddc 167 #define COM9_AGC_2X 0x00
diasea 0:6be5fa68dddc 168 #define COM9_AGC_4X 0x10
diasea 0:6be5fa68dddc 169 #define COM9_AGC_8X 0x20
diasea 0:6be5fa68dddc 170 #define COM9_AGC_16X 0x30
diasea 0:6be5fa68dddc 171 #define COM9_AGC_32X 0x40
diasea 0:6be5fa68dddc 172 #define COM9_AGC_64X 0x50
diasea 0:6be5fa68dddc 173 #define COM9_AGC_128X 0x60
diasea 0:6be5fa68dddc 174 #define COM9_AGC_MASK 0x70
diasea 0:6be5fa68dddc 175 #define COM9_FREEZE 0x01
diasea 0:6be5fa68dddc 176 #define COM13_GAMMA 0x80 /* Gamma enable */
diasea 0:6be5fa68dddc 177 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
diasea 0:6be5fa68dddc 178 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
diasea 0:6be5fa68dddc 179 #define REG_BLUE 0x01 /* blue gain */
diasea 0:6be5fa68dddc 180 #define REG_RED 0x02 /* red gain */
diasea 0:6be5fa68dddc 181 #define REG_COM1 0x04 /* Control 1 */
diasea 0:6be5fa68dddc 182 #define COM1_CCIR656 0x40 /* CCIR656 enable */
diasea 0:6be5fa68dddc 183 #define REG_BAVE 0x05 /* U/B Average level */
diasea 0:6be5fa68dddc 184 #define REG_GbAVE 0x06 /* Y/Gb Average level */
diasea 0:6be5fa68dddc 185 #define REG_AECHH 0x07 /* AEC MS 5 bits */
diasea 0:6be5fa68dddc 186 #define REG_RAVE 0x08 /* V/R Average level */
diasea 0:6be5fa68dddc 187 #define REG_COM2 0x09 /* Control 2 */
diasea 0:6be5fa68dddc 188 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
diasea 0:6be5fa68dddc 189 #define REG_PID 0x0a /* Product ID MSB */
diasea 0:6be5fa68dddc 190 #define REG_VER 0x0b /* Product ID LSB */
diasea 0:6be5fa68dddc 191 #define COM3_SWAP 0x40 /* Byte swap */
diasea 0:6be5fa68dddc 192 #define COM3_SCALEEN 0x08 /* Enable scaling */
diasea 0:6be5fa68dddc 193 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
diasea 0:6be5fa68dddc 194 #define REG_COM4 0x0d /* Control 4 */
diasea 0:6be5fa68dddc 195 #define REG_COM5 0x0e /* All "reserved" */
diasea 0:6be5fa68dddc 196 #define REG_COM6 0x0f /* Control 6 */
diasea 0:6be5fa68dddc 197 #define REG_AECH 0x10 /* More bits of AEC value */
diasea 0:6be5fa68dddc 198 #define REG_CLKRC 0x11 /* Clocl control */
diasea 0:6be5fa68dddc 199 #define CLK_EXT 0x40 /* Use external clock directly */
diasea 0:6be5fa68dddc 200 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
diasea 0:6be5fa68dddc 201 #define COM7_RESET 0x80 /* Register reset */
diasea 0:6be5fa68dddc 202 #define COM7_FMT_MASK 0x38
diasea 0:6be5fa68dddc 203 #define COM7_FMT_VGA 0x00
diasea 0:6be5fa68dddc 204 #define COM7_FMT_CIF 0x20 /* CIF format */
diasea 0:6be5fa68dddc 205 #define COM7_FMT_QVGA 0x10 /* QVGA format */
diasea 0:6be5fa68dddc 206 #define COM7_FMT_QCIF 0x08 /* QCIF format */
diasea 0:6be5fa68dddc 207 #define REG_COM8 0x13 /* Control 8 */
diasea 0:6be5fa68dddc 208 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
diasea 0:6be5fa68dddc 209 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
diasea 0:6be5fa68dddc 210 #define COM8_BFILT 0x20 /* Band filter enable */
diasea 0:6be5fa68dddc 211 #define COM8_AGC 0x04 /* Auto gain enable */
diasea 0:6be5fa68dddc 212 #define COM8_AWB 0x02 /* White balance enable */
diasea 0:6be5fa68dddc 213 #define COM8_AEC 0x01 /* Auto exposure enable */
diasea 0:6be5fa68dddc 214 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
diasea 0:6be5fa68dddc 215 #define REG_COM10 0x15 /* Control 10 */
diasea 0:6be5fa68dddc 216 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
diasea 0:6be5fa68dddc 217 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
diasea 0:6be5fa68dddc 218 #define COM10_HREF_REV 0x08 /* Reverse HREF */
diasea 0:6be5fa68dddc 219 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
diasea 0:6be5fa68dddc 220 #define COM10_VS_NEG 0x02 /* VSYNC negative */
diasea 0:6be5fa68dddc 221 #define COM10_HS_NEG 0x01 /* HSYNC negative */
diasea 0:6be5fa68dddc 222 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
diasea 0:6be5fa68dddc 223 #define REG_MIDH 0x1c /* Manuf. ID high */
diasea 0:6be5fa68dddc 224 #define REG_MIDL 0x1d /* Manuf. ID low */
diasea 0:6be5fa68dddc 225 #define REG_MVFP 0x1e /* Mirror / vflip */
diasea 0:6be5fa68dddc 226 #define MVFP_MIRROR 0x20 /* Mirror image */
diasea 0:6be5fa68dddc 227 #define MVFP_FLIP 0x10 /* Vertical flip */
diasea 0:6be5fa68dddc 228 #define REG_AEW 0x24 /* AGC upper limit */
diasea 0:6be5fa68dddc 229 #define REG_AEB 0x25 /* AGC lower limit */
diasea 0:6be5fa68dddc 230 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
diasea 0:6be5fa68dddc 231 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
diasea 0:6be5fa68dddc 232 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
diasea 0:6be5fa68dddc 233 #define REG_COM12 0x3c /* Control 12 */
diasea 0:6be5fa68dddc 234 #define COM12_HREF 0x80 /* HREF always */
diasea 0:6be5fa68dddc 235 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
diasea 0:6be5fa68dddc 236 #define REG_EDGE 0x3f /* Edge enhancement factor */
diasea 0:6be5fa68dddc 237 #define REG_COM16 0x41 /* Control 16 */
diasea 0:6be5fa68dddc 238 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
diasea 0:6be5fa68dddc 239 #define REG_COM17 0x42 /* Control 17 */
diasea 0:6be5fa68dddc 240 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
diasea 0:6be5fa68dddc 241 #define COM17_CBAR 0x08 /* DSP Color bar */
diasea 0:6be5fa68dddc 242 #define REG_CMATRIX_BASE 0x4f
diasea 0:6be5fa68dddc 243 #define CMATRIX_LEN 6
diasea 0:6be5fa68dddc 244 #define REG_REG76 0x76 /* OV's name */
diasea 0:6be5fa68dddc 245 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
diasea 0:6be5fa68dddc 246 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
diasea 0:6be5fa68dddc 247 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
diasea 0:6be5fa68dddc 248 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
diasea 0:6be5fa68dddc 249 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
diasea 0:6be5fa68dddc 250 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
diasea 0:6be5fa68dddc 251 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
diasea 0:6be5fa68dddc 252 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
diasea 0:6be5fa68dddc 253 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
diasea 0:6be5fa68dddc 254 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
diasea 0:6be5fa68dddc 255 #define REG_BD60MAX 0xab /* 60hz banding step limit */