Sadaei Osakabe / Mbed 2 deprecated OV7670_with_AL422B_Color_Size_test

OV7670_with_AL422B Color & Size Test Program

Dependencies:   mbed

ov7670.h@4:2c412c97678c, 2013-02-18 (annotated)

Committer:
diasea
Date:
Mon Feb 18 07:53:46 2013 +0000
Revision:
4:2c412c97678c
Parent:
1:2483905139b6 
fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
diasea 0:6be5fa68dddc 1 #include "mbed.h"
diasea 0:6be5fa68dddc 2 #include "ov7670reg.h"
diasea 0:6be5fa68dddc 3
diasea 0:6be5fa68dddc 4 #define OV7670_WRITE (0x42)
diasea 0:6be5fa68dddc 5 #define OV7670_READ (0x43)
diasea 0:6be5fa68dddc 6 #define OV7670_WRITEWAIT (20)
diasea 0:6be5fa68dddc 7 #define OV7670_NOACK (0)
diasea 0:6be5fa68dddc 8 #define OV7670_REGMAX (201)
diasea 0:6be5fa68dddc 9 #define OV7670_I2CFREQ (50000)
diasea 0:6be5fa68dddc 10
diasea 0:6be5fa68dddc 11 //
diasea 0:6be5fa68dddc 12 // OV7670 + FIFO AL422B camera board test
diasea 0:6be5fa68dddc 13 //
diasea 1:2483905139b6 14 class OV7670
diasea 0:6be5fa68dddc 15 {
diasea 0:6be5fa68dddc 16 public:
diasea 4:2c412c97678c 17 I2C camera;
diasea 0:6be5fa68dddc 18 InterruptIn vsync,href;
diasea 4:2c412c97678c 19 DigitalOut wen;
diasea 4:2c412c97678c 20 BusIn data;
diasea 4:2c412c97678c 21 DigitalOut rrst,oe,rclk;
diasea 4:2c412c97678c 22 volatile int LineCounter;
diasea 4:2c412c97678c 23 volatile int LastLines;
diasea 4:2c412c97678c 24 volatile bool CaptureReq;
diasea 4:2c412c97678c 25 volatile bool Busy;
diasea 4:2c412c97678c 26 volatile bool Done;
diasea 0:6be5fa68dddc 27
diasea 0:6be5fa68dddc 28 OV7670(
diasea 0:6be5fa68dddc 29 PinName sda,// Camera I2C port
diasea 0:6be5fa68dddc 30 PinName scl,// Camera I2C port
diasea 0:6be5fa68dddc 31 PinName vs, // VSYNC
diasea 0:6be5fa68dddc 32 PinName hr, // HREF
diasea 0:6be5fa68dddc 33 PinName we, // WEN
diasea 0:6be5fa68dddc 34 PinName d7, // D7
diasea 0:6be5fa68dddc 35 PinName d6, // D6
diasea 0:6be5fa68dddc 36 PinName d5, // D5
diasea 0:6be5fa68dddc 37 PinName d4, // D4
diasea 0:6be5fa68dddc 38 PinName d3, // D3
diasea 0:6be5fa68dddc 39 PinName d2, // D2
diasea 0:6be5fa68dddc 40 PinName d1, // D1
diasea 0:6be5fa68dddc 41 PinName d0, // D0
diasea 0:6be5fa68dddc 42 PinName rt, // /RRST
diasea 0:6be5fa68dddc 43 PinName o, // /OE
diasea 0:6be5fa68dddc 44 PinName rc // RCLK
diasea 0:6be5fa68dddc 45 ) : camera(sda,scl),vsync(vs),href(hr),wen(we),data(d0,d1,d2,d3,d4,d5,d6,d7),rrst(rt),oe(o),rclk(rc)
diasea 0:6be5fa68dddc 46 {
diasea 4:2c412c97678c 47 camera.stop();
diasea 4:2c412c97678c 48 camera.frequency(OV7670_I2CFREQ);
diasea 4:2c412c97678c 49 vsync.fall(this,&OV7670::VsyncHandler);
diasea 4:2c412c97678c 50 href.rise(this,&OV7670::HrefHandler);
diasea 4:2c412c97678c 51 CaptureReq = false;
diasea 4:2c412c97678c 52 Busy = false;
diasea 4:2c412c97678c 53 Done = false;
diasea 4:2c412c97678c 54 LineCounter = 0;
diasea 4:2c412c97678c 55 rrst = 1;
diasea 4:2c412c97678c 56 oe = 1;
diasea 4:2c412c97678c 57 rclk = 1;
diasea 4:2c412c97678c 58 wen = 0;
diasea 0:6be5fa68dddc 59 }
diasea 0:6be5fa68dddc 60
diasea 0:6be5fa68dddc 61 // capture request
diasea 0:6be5fa68dddc 62 void CaptureNext(void)
diasea 0:6be5fa68dddc 63 {
diasea 4:2c412c97678c 64 CaptureReq = true;
diasea 4:2c412c97678c 65 Busy = true;
diasea 0:6be5fa68dddc 66 }
diasea 0:6be5fa68dddc 67
diasea 0:6be5fa68dddc 68 // capture done? (with clear)
diasea 0:6be5fa68dddc 69 bool CaptureDone(void)
diasea 0:6be5fa68dddc 70 {
diasea 4:2c412c97678c 71 bool result;
diasea 0:6be5fa68dddc 72 if (Busy) {
diasea 4:2c412c97678c 73 result = false;
diasea 0:6be5fa68dddc 74 } else {
diasea 4:2c412c97678c 75 result = Done;
diasea 4:2c412c97678c 76 Done = false;
diasea 0:6be5fa68dddc 77 }
diasea 4:2c412c97678c 78 return result;
diasea 0:6be5fa68dddc 79 }
diasea 0:6be5fa68dddc 80
diasea 0:6be5fa68dddc 81 // write to camera
diasea 0:6be5fa68dddc 82 void WriteReg(int addr,int data)
diasea 0:6be5fa68dddc 83 {
diasea 0:6be5fa68dddc 84 // WRITE 0x42,ADDR,DATA
diasea 4:2c412c97678c 85 camera.start();
diasea 4:2c412c97678c 86 camera.write(OV7670_WRITE);
diasea 0:6be5fa68dddc 87 wait_us(OV7670_WRITEWAIT);
diasea 4:2c412c97678c 88 camera.write(addr);
diasea 0:6be5fa68dddc 89 wait_us(OV7670_WRITEWAIT);
diasea 4:2c412c97678c 90 camera.write(data);
diasea 4:2c412c97678c 91 camera.stop();
diasea 0:6be5fa68dddc 92 }
diasea 0:6be5fa68dddc 93
diasea 0:6be5fa68dddc 94 // read from camera
diasea 0:6be5fa68dddc 95 int ReadReg(int addr)
diasea 0:6be5fa68dddc 96 {
diasea 4:2c412c97678c 97 int data;
diasea 0:6be5fa68dddc 98
diasea 0:6be5fa68dddc 99 // WRITE 0x42,ADDR
diasea 4:2c412c97678c 100 camera.start();
diasea 4:2c412c97678c 101 camera.write(OV7670_WRITE);
diasea 0:6be5fa68dddc 102 wait_us(OV7670_WRITEWAIT);
diasea 4:2c412c97678c 103 camera.write(addr);
diasea 4:2c412c97678c 104 camera.stop();
diasea 0:6be5fa68dddc 105 wait_us(OV7670_WRITEWAIT);
diasea 0:6be5fa68dddc 106
diasea 0:6be5fa68dddc 107 // WRITE 0x43,READ
diasea 4:2c412c97678c 108 camera.start();
diasea 4:2c412c97678c 109 camera.write(OV7670_READ);
diasea 0:6be5fa68dddc 110 wait_us(OV7670_WRITEWAIT);
diasea 4:2c412c97678c 111 data = camera.read(OV7670_NOACK);
diasea 4:2c412c97678c 112 camera.stop();
diasea 0:6be5fa68dddc 113
diasea 4:2c412c97678c 114 return data;
diasea 0:6be5fa68dddc 115 }
diasea 0:6be5fa68dddc 116
diasea 0:6be5fa68dddc 117 // print register
diasea 0:6be5fa68dddc 118 void PrintRegister(void) {
diasea 0:6be5fa68dddc 119 printf("AD : +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F");
diasea 0:6be5fa68dddc 120 for (int i=0;i<OV7670_REGMAX;i++) {
diasea 0:6be5fa68dddc 121 int data;
diasea 0:6be5fa68dddc 122 data = ReadReg(i); // READ REG
diasea 0:6be5fa68dddc 123 if ((i & 0x0F) == 0) {
diasea 0:6be5fa68dddc 124 printf("\r\n%02X : ",i);
diasea 0:6be5fa68dddc 125 }
diasea 0:6be5fa68dddc 126 printf("%02X ",data);
diasea 0:6be5fa68dddc 127 }
diasea 0:6be5fa68dddc 128 printf("\r\n");
diasea 0:6be5fa68dddc 129 }
diasea 0:6be5fa68dddc 130
diasea 0:6be5fa68dddc 131 void Reset(void) {
diasea 4:2c412c97678c 132 WriteReg(REG_COM7,COM7_RESET); // RESET CAMERA
diasea 4:2c412c97678c 133 wait_ms(200);
diasea 0:6be5fa68dddc 134 }
diasea 0:6be5fa68dddc 135
diasea 0:6be5fa68dddc 136 void InitForFIFOWriteReset(void) {
diasea 4:2c412c97678c 137 WriteReg(REG_COM10, COM10_VS_NEG);
diasea 0:6be5fa68dddc 138 }
diasea 0:6be5fa68dddc 139
diasea 0:6be5fa68dddc 140 void InitSetColorbar(void) {
diasea 0:6be5fa68dddc 141 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 142 // color bar
diasea 0:6be5fa68dddc 143 WriteReg(REG_COM17, reg_com7|COM17_CBAR);
diasea 0:6be5fa68dddc 144 }
diasea 0:6be5fa68dddc 145
diasea 0:6be5fa68dddc 146 void InitDefaultReg(void) {
diasea 0:6be5fa68dddc 147 // Gamma curve values
diasea 0:6be5fa68dddc 148 WriteReg(0x7a, 0x20);
diasea 0:6be5fa68dddc 149 WriteReg(0x7b, 0x10);
diasea 0:6be5fa68dddc 150 WriteReg(0x7c, 0x1e);
diasea 0:6be5fa68dddc 151 WriteReg(0x7d, 0x35);
diasea 0:6be5fa68dddc 152 WriteReg(0x7e, 0x5a);
diasea 0:6be5fa68dddc 153 WriteReg(0x7f, 0x69);
diasea 0:6be5fa68dddc 154 WriteReg(0x80, 0x76);
diasea 0:6be5fa68dddc 155 WriteReg(0x81, 0x80);
diasea 0:6be5fa68dddc 156 WriteReg(0x82, 0x88);
diasea 0:6be5fa68dddc 157 WriteReg(0x83, 0x8f);
diasea 0:6be5fa68dddc 158 WriteReg(0x84, 0x96);
diasea 0:6be5fa68dddc 159 WriteReg(0x85, 0xa3);
diasea 0:6be5fa68dddc 160 WriteReg(0x86, 0xaf);
diasea 0:6be5fa68dddc 161 WriteReg(0x87, 0xc4);
diasea 0:6be5fa68dddc 162 WriteReg(0x88, 0xd7);
diasea 0:6be5fa68dddc 163 WriteReg(0x89, 0xe8);
diasea 0:6be5fa68dddc 164
diasea 0:6be5fa68dddc 165 // AGC and AEC parameters. Note we start by disabling those features,
diasea 0:6be5fa68dddc 166 //then turn them only after tweaking the values.
diasea 0:6be5fa68dddc 167 WriteReg(REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT);
diasea 0:6be5fa68dddc 168 WriteReg(REG_GAIN, 0);
diasea 0:6be5fa68dddc 169 WriteReg(REG_AECH, 0);
diasea 0:6be5fa68dddc 170 WriteReg(REG_COM4, 0x40);
diasea 0:6be5fa68dddc 171 // magic reserved bit
diasea 0:6be5fa68dddc 172 WriteReg(REG_COM9, 0x18);
diasea 0:6be5fa68dddc 173 // 4x gain + magic rsvd bit
diasea 0:6be5fa68dddc 174 WriteReg(REG_BD50MAX, 0x05);
diasea 0:6be5fa68dddc 175 WriteReg(REG_BD60MAX, 0x07);
diasea 0:6be5fa68dddc 176 WriteReg(REG_AEW, 0x95);
diasea 0:6be5fa68dddc 177 WriteReg(REG_AEB, 0x33);
diasea 0:6be5fa68dddc 178 WriteReg(REG_VPT, 0xe3);
diasea 0:6be5fa68dddc 179 WriteReg(REG_HAECC1, 0x78);
diasea 0:6be5fa68dddc 180 WriteReg(REG_HAECC2, 0x68);
diasea 0:6be5fa68dddc 181 WriteReg(0xa1, 0x03);
diasea 0:6be5fa68dddc 182 // magic
diasea 0:6be5fa68dddc 183 WriteReg(REG_HAECC3, 0xd8);
diasea 0:6be5fa68dddc 184 WriteReg(REG_HAECC4, 0xd8);
diasea 0:6be5fa68dddc 185 WriteReg(REG_HAECC5, 0xf0);
diasea 0:6be5fa68dddc 186 WriteReg(REG_HAECC6, 0x90);
diasea 0:6be5fa68dddc 187 WriteReg(REG_HAECC7, 0x94);
diasea 0:6be5fa68dddc 188 WriteReg(REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC);
diasea 0:6be5fa68dddc 189
diasea 0:6be5fa68dddc 190 // Almost all of these are magic "reserved" values.
diasea 0:6be5fa68dddc 191 WriteReg(REG_COM5, 0x61);
diasea 0:6be5fa68dddc 192 WriteReg(REG_COM6, 0x4b);
diasea 0:6be5fa68dddc 193 WriteReg(0x16, 0x02);
diasea 0:6be5fa68dddc 194 WriteReg(REG_MVFP, 0x07);
diasea 0:6be5fa68dddc 195 WriteReg(0x21, 0x02);
diasea 0:6be5fa68dddc 196 WriteReg(0x22, 0x91);
diasea 0:6be5fa68dddc 197 WriteReg(0x29, 0x07);
diasea 0:6be5fa68dddc 198 WriteReg(0x33, 0x0b);
diasea 0:6be5fa68dddc 199 WriteReg(0x35, 0x0b);
diasea 0:6be5fa68dddc 200 WriteReg(0x37, 0x1d);
diasea 0:6be5fa68dddc 201 WriteReg(0x38, 0x71);
diasea 0:6be5fa68dddc 202 WriteReg(0x39, 0x2a);
diasea 0:6be5fa68dddc 203 WriteReg(REG_COM12, 0x78);
diasea 0:6be5fa68dddc 204 WriteReg(0x4d, 0x40);
diasea 0:6be5fa68dddc 205 WriteReg(0x4e, 0x20);
diasea 0:6be5fa68dddc 206 WriteReg(REG_GFIX, 0);
diasea 0:6be5fa68dddc 207 WriteReg(0x6b, 0x0a);
diasea 0:6be5fa68dddc 208 WriteReg(0x74, 0x10);
diasea 0:6be5fa68dddc 209 WriteReg(0x8d, 0x4f);
diasea 0:6be5fa68dddc 210 WriteReg(0x8e, 0);
diasea 0:6be5fa68dddc 211 WriteReg(0x8f, 0);
diasea 0:6be5fa68dddc 212 WriteReg(0x90, 0);
diasea 0:6be5fa68dddc 213 WriteReg(0x91, 0);
diasea 0:6be5fa68dddc 214 WriteReg(0x96, 0);
diasea 0:6be5fa68dddc 215 WriteReg(0x9a, 0);
diasea 0:6be5fa68dddc 216 WriteReg(0xb0, 0x84);
diasea 0:6be5fa68dddc 217 WriteReg(0xb1, 0x0c);
diasea 0:6be5fa68dddc 218 WriteReg(0xb2, 0x0e);
diasea 0:6be5fa68dddc 219 WriteReg(0xb3, 0x82);
diasea 0:6be5fa68dddc 220 WriteReg(0xb8, 0x0a);
diasea 0:6be5fa68dddc 221
diasea 0:6be5fa68dddc 222 // More reserved magic, some of which tweaks white balance
diasea 0:6be5fa68dddc 223 WriteReg(0x43, 0x0a);
diasea 0:6be5fa68dddc 224 WriteReg(0x44, 0xf0);
diasea 0:6be5fa68dddc 225 WriteReg(0x45, 0x34);
diasea 0:6be5fa68dddc 226 WriteReg(0x46, 0x58);
diasea 0:6be5fa68dddc 227 WriteReg(0x47, 0x28);
diasea 0:6be5fa68dddc 228 WriteReg(0x48, 0x3a);
diasea 0:6be5fa68dddc 229 WriteReg(0x59, 0x88);
diasea 0:6be5fa68dddc 230 WriteReg(0x5a, 0x88);
diasea 0:6be5fa68dddc 231 WriteReg(0x5b, 0x44);
diasea 0:6be5fa68dddc 232 WriteReg(0x5c, 0x67);
diasea 0:6be5fa68dddc 233 WriteReg(0x5d, 0x49);
diasea 0:6be5fa68dddc 234 WriteReg(0x5e, 0x0e);
diasea 0:6be5fa68dddc 235 WriteReg(0x6c, 0x0a);
diasea 0:6be5fa68dddc 236 WriteReg(0x6d, 0x55);
diasea 0:6be5fa68dddc 237 WriteReg(0x6e, 0x11);
diasea 0:6be5fa68dddc 238 WriteReg(0x6f, 0x9f);
diasea 0:6be5fa68dddc 239 // "9e for advance AWB"
diasea 0:6be5fa68dddc 240 WriteReg(0x6a, 0x40);
diasea 0:6be5fa68dddc 241 WriteReg(REG_BLUE, 0x40);
diasea 0:6be5fa68dddc 242 WriteReg(REG_RED, 0x60);
diasea 0:6be5fa68dddc 243 WriteReg(REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB);
diasea 0:6be5fa68dddc 244
diasea 0:6be5fa68dddc 245 // Matrix coefficients
diasea 0:6be5fa68dddc 246 WriteReg(0x4f, 0x80);
diasea 0:6be5fa68dddc 247 WriteReg(0x50, 0x80);
diasea 0:6be5fa68dddc 248 WriteReg(0x51, 0);
diasea 0:6be5fa68dddc 249 WriteReg(0x52, 0x22);
diasea 0:6be5fa68dddc 250 WriteReg(0x53, 0x5e);
diasea 0:6be5fa68dddc 251 WriteReg(0x54, 0x80);
diasea 0:6be5fa68dddc 252 WriteReg(0x58, 0x9e);
diasea 0:6be5fa68dddc 253
diasea 0:6be5fa68dddc 254 WriteReg(REG_COM16, COM16_AWBGAIN);
diasea 0:6be5fa68dddc 255 WriteReg(REG_EDGE, 0);
diasea 0:6be5fa68dddc 256 WriteReg(0x75, 0x05);
diasea 0:6be5fa68dddc 257 WriteReg(0x76, 0xe1);
diasea 0:6be5fa68dddc 258 WriteReg(0x4c, 0);
diasea 0:6be5fa68dddc 259 WriteReg(0x77, 0x01);
diasea 0:6be5fa68dddc 260 WriteReg(0x4b, 0x09);
diasea 0:6be5fa68dddc 261 WriteReg(0xc9, 0x60);
diasea 0:6be5fa68dddc 262 WriteReg(REG_COM16, 0x38);
diasea 0:6be5fa68dddc 263 WriteReg(0x56, 0x40);
diasea 0:6be5fa68dddc 264
diasea 0:6be5fa68dddc 265 WriteReg(0x34, 0x11);
diasea 0:6be5fa68dddc 266 WriteReg(REG_COM11, COM11_EXP|COM11_HZAUTO_ON);
diasea 0:6be5fa68dddc 267 WriteReg(0xa4, 0x88);
diasea 0:6be5fa68dddc 268 WriteReg(0x96, 0);
diasea 0:6be5fa68dddc 269 WriteReg(0x97, 0x30);
diasea 0:6be5fa68dddc 270 WriteReg(0x98, 0x20);
diasea 0:6be5fa68dddc 271 WriteReg(0x99, 0x30);
diasea 0:6be5fa68dddc 272 WriteReg(0x9a, 0x84);
diasea 0:6be5fa68dddc 273 WriteReg(0x9b, 0x29);
diasea 0:6be5fa68dddc 274 WriteReg(0x9c, 0x03);
diasea 0:6be5fa68dddc 275 WriteReg(0x9d, 0x4c);
diasea 0:6be5fa68dddc 276 WriteReg(0x9e, 0x3f);
diasea 0:6be5fa68dddc 277 WriteReg(0x78, 0x04);
diasea 0:6be5fa68dddc 278
diasea 0:6be5fa68dddc 279 // Extra-weird stuff. Some sort of multiplexor register
diasea 0:6be5fa68dddc 280 WriteReg(0x79, 0x01);
diasea 0:6be5fa68dddc 281 WriteReg(0xc8, 0xf0);
diasea 0:6be5fa68dddc 282 WriteReg(0x79, 0x0f);
diasea 0:6be5fa68dddc 283 WriteReg(0xc8, 0x00);
diasea 0:6be5fa68dddc 284 WriteReg(0x79, 0x10);
diasea 0:6be5fa68dddc 285 WriteReg(0xc8, 0x7e);
diasea 0:6be5fa68dddc 286 WriteReg(0x79, 0x0a);
diasea 0:6be5fa68dddc 287 WriteReg(0xc8, 0x80);
diasea 0:6be5fa68dddc 288 WriteReg(0x79, 0x0b);
diasea 0:6be5fa68dddc 289 WriteReg(0xc8, 0x01);
diasea 0:6be5fa68dddc 290 WriteReg(0x79, 0x0c);
diasea 0:6be5fa68dddc 291 WriteReg(0xc8, 0x0f);
diasea 0:6be5fa68dddc 292 WriteReg(0x79, 0x0d);
diasea 0:6be5fa68dddc 293 WriteReg(0xc8, 0x20);
diasea 0:6be5fa68dddc 294 WriteReg(0x79, 0x09);
diasea 0:6be5fa68dddc 295 WriteReg(0xc8, 0x80);
diasea 0:6be5fa68dddc 296 WriteReg(0x79, 0x02);
diasea 0:6be5fa68dddc 297 WriteReg(0xc8, 0xc0);
diasea 0:6be5fa68dddc 298 WriteReg(0x79, 0x03);
diasea 0:6be5fa68dddc 299 WriteReg(0xc8, 0x40);
diasea 0:6be5fa68dddc 300 WriteReg(0x79, 0x05);
diasea 0:6be5fa68dddc 301 WriteReg(0xc8, 0x30);
diasea 0:6be5fa68dddc 302 WriteReg(0x79, 0x26);
diasea 0:6be5fa68dddc 303 }
diasea 0:6be5fa68dddc 304
diasea 0:6be5fa68dddc 305 void InitRGB444(void){
diasea 0:6be5fa68dddc 306 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 307
diasea 0:6be5fa68dddc 308 WriteReg(REG_COM7, reg_com7|COM7_RGB);
diasea 0:6be5fa68dddc 309 WriteReg(REG_RGB444, RGB444_ENABLE|RGB444_XBGR);
diasea 0:6be5fa68dddc 310 WriteReg(REG_COM15, COM15_R01FE|COM15_RGB444);
diasea 0:6be5fa68dddc 311
diasea 0:6be5fa68dddc 312 WriteReg(REG_COM1, 0x40); // Magic reserved bit
diasea 0:6be5fa68dddc 313 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
diasea 0:6be5fa68dddc 314 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
diasea 0:6be5fa68dddc 315 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
diasea 0:6be5fa68dddc 316 WriteReg(0x51, 0x00); // vb
diasea 0:6be5fa68dddc 317 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
diasea 0:6be5fa68dddc 318 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
diasea 0:6be5fa68dddc 319 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
diasea 0:6be5fa68dddc 320 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2); // Magic rsvd bit
diasea 0:6be5fa68dddc 321
diasea 0:6be5fa68dddc 322 WriteReg(REG_TSLB, 0x04);
diasea 0:6be5fa68dddc 323 }
diasea 0:6be5fa68dddc 324
diasea 0:6be5fa68dddc 325 void InitRGB555(void){
diasea 0:6be5fa68dddc 326 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 327
diasea 0:6be5fa68dddc 328 WriteReg(REG_COM7, reg_com7|COM7_RGB);
diasea 0:6be5fa68dddc 329 WriteReg(REG_RGB444, RGB444_DISABLE);
diasea 0:6be5fa68dddc 330 WriteReg(REG_COM15, COM15_RGB555|COM15_R00FF);
diasea 0:6be5fa68dddc 331
diasea 0:6be5fa68dddc 332 WriteReg(REG_TSLB, 0x04);
diasea 0:6be5fa68dddc 333
diasea 0:6be5fa68dddc 334 WriteReg(REG_COM1, 0x00);
diasea 0:6be5fa68dddc 335 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
diasea 0:6be5fa68dddc 336 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
diasea 0:6be5fa68dddc 337 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
diasea 0:6be5fa68dddc 338 WriteReg(0x51, 0x00); // vb
diasea 0:6be5fa68dddc 339 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
diasea 0:6be5fa68dddc 340 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
diasea 0:6be5fa68dddc 341 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
diasea 0:6be5fa68dddc 342 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT);
diasea 0:6be5fa68dddc 343 }
diasea 0:6be5fa68dddc 344
diasea 0:6be5fa68dddc 345 void InitRGB565(void){
diasea 0:6be5fa68dddc 346 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 347
diasea 0:6be5fa68dddc 348 WriteReg(REG_COM7, reg_com7|COM7_RGB);
diasea 0:6be5fa68dddc 349 WriteReg(REG_RGB444, RGB444_DISABLE);
diasea 0:6be5fa68dddc 350 WriteReg(REG_COM15, COM15_R00FF|COM15_RGB565);
diasea 0:6be5fa68dddc 351
diasea 0:6be5fa68dddc 352 WriteReg(REG_TSLB, 0x04);
diasea 0:6be5fa68dddc 353
diasea 0:6be5fa68dddc 354 WriteReg(REG_COM1, 0x00);
diasea 0:6be5fa68dddc 355 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
diasea 0:6be5fa68dddc 356 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
diasea 0:6be5fa68dddc 357 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
diasea 0:6be5fa68dddc 358 WriteReg(0x51, 0x00); // vb
diasea 0:6be5fa68dddc 359 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
diasea 0:6be5fa68dddc 360 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
diasea 0:6be5fa68dddc 361 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
diasea 0:6be5fa68dddc 362 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT);
diasea 0:6be5fa68dddc 363 }
diasea 0:6be5fa68dddc 364
diasea 0:6be5fa68dddc 365 void InitYUV(void){
diasea 0:6be5fa68dddc 366 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 367
diasea 0:6be5fa68dddc 368 WriteReg(REG_COM7, reg_com7|COM7_YUV);
diasea 0:6be5fa68dddc 369 WriteReg(REG_RGB444, RGB444_DISABLE);
diasea 0:6be5fa68dddc 370 WriteReg(REG_COM15, COM15_R00FF);
diasea 0:6be5fa68dddc 371
diasea 0:6be5fa68dddc 372 WriteReg(REG_TSLB, 0x04);
diasea 0:6be5fa68dddc 373 // WriteReg(REG_TSLB, 0x14);
diasea 0:6be5fa68dddc 374 // WriteReg(REG_MANU, 0x00);
diasea 0:6be5fa68dddc 375 // WriteReg(REG_MANV, 0x00);
diasea 0:6be5fa68dddc 376
diasea 0:6be5fa68dddc 377 WriteReg(REG_COM1, 0x00);
diasea 0:6be5fa68dddc 378 WriteReg(REG_COM9, 0x18); // 4x gain ceiling; 0x8 is reserved bit
diasea 0:6be5fa68dddc 379 WriteReg(0x4f, 0x80); // "matrix coefficient 1"
diasea 0:6be5fa68dddc 380 WriteReg(0x50, 0x80); // "matrix coefficient 2"
diasea 0:6be5fa68dddc 381 WriteReg(0x51, 0x00); // vb
diasea 0:6be5fa68dddc 382 WriteReg(0x52, 0x22); // "matrix coefficient 4"
diasea 0:6be5fa68dddc 383 WriteReg(0x53, 0x5e); // "matrix coefficient 5"
diasea 0:6be5fa68dddc 384 WriteReg(0x54, 0x80); // "matrix coefficient 6"
diasea 0:6be5fa68dddc 385 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT|COM13_UVSWAP);
diasea 0:6be5fa68dddc 386 }
diasea 0:6be5fa68dddc 387
diasea 0:6be5fa68dddc 388 void InitBayerRGB(void){
diasea 0:6be5fa68dddc 389 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 390
diasea 4:2c412c97678c 391 // odd line BGBG... even line GRGR...
diasea 4:2c412c97678c 392 WriteReg(REG_COM7, reg_com7|COM7_BAYER);
diasea 4:2c412c97678c 393 // odd line GBGB... even line RGRG...
diasea 4:2c412c97678c 394 //WriteReg(REG_COM7, reg_com7|COM7_PBAYER);
diasea 4:2c412c97678c 395
diasea 0:6be5fa68dddc 396 WriteReg(REG_RGB444, RGB444_DISABLE);
diasea 0:6be5fa68dddc 397 WriteReg(REG_COM15, COM15_R00FF);
diasea 0:6be5fa68dddc 398
diasea 0:6be5fa68dddc 399 WriteReg(REG_COM13, 0x08); /* No gamma, magic rsvd bit */
diasea 0:6be5fa68dddc 400 WriteReg(REG_COM16, 0x3d); /* Edge enhancement, denoise */
diasea 0:6be5fa68dddc 401 WriteReg(REG_REG76, 0xe1); /* Pix correction, magic rsvd */
diasea 0:6be5fa68dddc 402
diasea 0:6be5fa68dddc 403 WriteReg(REG_TSLB, 0x04);
diasea 0:6be5fa68dddc 404 }
diasea 0:6be5fa68dddc 405
diasea 0:6be5fa68dddc 406 void InitVGA(void) {
diasea 0:6be5fa68dddc 407 // VGA
diasea 0:6be5fa68dddc 408 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 409
diasea 0:6be5fa68dddc 410 WriteReg(REG_COM7,reg_com7|COM7_VGA);
diasea 4:2c412c97678c 411
diasea 0:6be5fa68dddc 412 WriteReg(REG_HSTART,HSTART_VGA);
diasea 0:6be5fa68dddc 413 WriteReg(REG_HSTOP,HSTOP_VGA);
diasea 0:6be5fa68dddc 414 WriteReg(REG_HREF,HREF_VGA);
diasea 0:6be5fa68dddc 415 WriteReg(REG_VSTART,VSTART_VGA);
diasea 0:6be5fa68dddc 416 WriteReg(REG_VSTOP,VSTOP_VGA);
diasea 0:6be5fa68dddc 417 WriteReg(REG_VREF,VREF_VGA);
diasea 0:6be5fa68dddc 418 WriteReg(REG_COM3, COM3_VGA);
diasea 0:6be5fa68dddc 419 WriteReg(REG_COM14, COM14_VGA);
diasea 0:6be5fa68dddc 420 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
diasea 0:6be5fa68dddc 421 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
diasea 0:6be5fa68dddc 422 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
diasea 0:6be5fa68dddc 423 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
diasea 0:6be5fa68dddc 424 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
diasea 0:6be5fa68dddc 425 }
diasea 0:6be5fa68dddc 426
diasea 0:6be5fa68dddc 427 void InitFIFO_2bytes_color_nealy_limit_size(void) {
diasea 0:6be5fa68dddc 428 // nealy FIFO limit 544x360
diasea 0:6be5fa68dddc 429 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 430
diasea 0:6be5fa68dddc 431 WriteReg(REG_COM7,reg_com7|COM7_VGA);
diasea 4:2c412c97678c 432
diasea 0:6be5fa68dddc 433 WriteReg(REG_HSTART,HSTART_VGA);
diasea 0:6be5fa68dddc 434 WriteReg(REG_HSTOP,HSTOP_VGA);
diasea 0:6be5fa68dddc 435 WriteReg(REG_HREF,HREF_VGA);
diasea 0:6be5fa68dddc 436 WriteReg(REG_VSTART,VSTART_VGA);
diasea 0:6be5fa68dddc 437 WriteReg(REG_VSTOP,VSTOP_VGA);
diasea 0:6be5fa68dddc 438 WriteReg(REG_VREF,VREF_VGA);
diasea 0:6be5fa68dddc 439 WriteReg(REG_COM3, COM3_VGA);
diasea 0:6be5fa68dddc 440 WriteReg(REG_COM14, COM14_VGA);
diasea 0:6be5fa68dddc 441 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
diasea 0:6be5fa68dddc 442 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
diasea 0:6be5fa68dddc 443 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
diasea 0:6be5fa68dddc 444 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
diasea 0:6be5fa68dddc 445 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
diasea 0:6be5fa68dddc 446
diasea 0:6be5fa68dddc 447 WriteReg(REG_HSTART, 0x17);
diasea 0:6be5fa68dddc 448 WriteReg(REG_HSTOP, 0x5b);
diasea 0:6be5fa68dddc 449 WriteReg(REG_VSTART, 0x12);
diasea 0:6be5fa68dddc 450 WriteReg(REG_VSTOP, 0x6c);
diasea 0:6be5fa68dddc 451 }
diasea 0:6be5fa68dddc 452
diasea 0:6be5fa68dddc 453 void InitVGA_3_4(void) {
diasea 0:6be5fa68dddc 454 // VGA 3/4 -> 480x360
diasea 0:6be5fa68dddc 455 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 456
diasea 0:6be5fa68dddc 457 WriteReg(REG_COM7,reg_com7|COM7_VGA);
diasea 4:2c412c97678c 458
diasea 0:6be5fa68dddc 459 WriteReg(REG_HSTART,HSTART_VGA);
diasea 0:6be5fa68dddc 460 WriteReg(REG_HSTOP,HSTOP_VGA);
diasea 0:6be5fa68dddc 461 WriteReg(REG_HREF,HREF_VGA);
diasea 0:6be5fa68dddc 462 WriteReg(REG_VSTART,VSTART_VGA);
diasea 0:6be5fa68dddc 463 WriteReg(REG_VSTOP,VSTOP_VGA);
diasea 0:6be5fa68dddc 464 WriteReg(REG_VREF,VREF_VGA);
diasea 0:6be5fa68dddc 465 WriteReg(REG_COM3, COM3_VGA);
diasea 0:6be5fa68dddc 466 WriteReg(REG_COM14, COM14_VGA);
diasea 0:6be5fa68dddc 467 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
diasea 0:6be5fa68dddc 468 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
diasea 0:6be5fa68dddc 469 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
diasea 0:6be5fa68dddc 470 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
diasea 0:6be5fa68dddc 471 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
diasea 0:6be5fa68dddc 472
diasea 0:6be5fa68dddc 473 WriteReg(REG_HSTART, 0x1b);
diasea 0:6be5fa68dddc 474 WriteReg(REG_HSTOP, 0x57);
diasea 0:6be5fa68dddc 475 WriteReg(REG_VSTART, 0x12);
diasea 0:6be5fa68dddc 476 WriteReg(REG_VSTOP, 0x6c);
diasea 0:6be5fa68dddc 477 }
diasea 0:6be5fa68dddc 478
diasea 0:6be5fa68dddc 479 void InitQVGA(void) {
diasea 0:6be5fa68dddc 480 // QQVGA
diasea 0:6be5fa68dddc 481 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 482
diasea 0:6be5fa68dddc 483 WriteReg(REG_COM7,reg_com7|COM7_QVGA);
diasea 0:6be5fa68dddc 484
diasea 0:6be5fa68dddc 485 WriteReg(REG_HSTART,HSTART_QVGA);
diasea 0:6be5fa68dddc 486 WriteReg(REG_HSTOP,HSTOP_QVGA);
diasea 0:6be5fa68dddc 487 WriteReg(REG_HREF,HREF_QVGA);
diasea 0:6be5fa68dddc 488 WriteReg(REG_VSTART,VSTART_QVGA);
diasea 0:6be5fa68dddc 489 WriteReg(REG_VSTOP,VSTOP_QVGA);
diasea 0:6be5fa68dddc 490 WriteReg(REG_VREF,VREF_QVGA);
diasea 0:6be5fa68dddc 491 WriteReg(REG_COM3, COM3_QVGA);
diasea 0:6be5fa68dddc 492 WriteReg(REG_COM14, COM14_QVGA);
diasea 0:6be5fa68dddc 493 WriteReg(REG_SCALING_XSC, SCALING_XSC_QVGA);
diasea 0:6be5fa68dddc 494 WriteReg(REG_SCALING_YSC, SCALING_YSC_QVGA);
diasea 0:6be5fa68dddc 495 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_QVGA);
diasea 0:6be5fa68dddc 496 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_QVGA);
diasea 0:6be5fa68dddc 497 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_QVGA);
diasea 0:6be5fa68dddc 498 }
diasea 0:6be5fa68dddc 499
diasea 0:6be5fa68dddc 500 void InitQQVGA(void) {
diasea 0:6be5fa68dddc 501 // QQVGA
diasea 0:6be5fa68dddc 502 int reg_com7 = ReadReg(REG_COM7);
diasea 0:6be5fa68dddc 503
diasea 0:6be5fa68dddc 504 WriteReg(REG_COM7,reg_com7|COM7_QQVGA);
diasea 0:6be5fa68dddc 505
diasea 0:6be5fa68dddc 506 WriteReg(REG_HSTART,HSTART_QQVGA);
diasea 0:6be5fa68dddc 507 WriteReg(REG_HSTOP,HSTOP_QQVGA);
diasea 0:6be5fa68dddc 508 WriteReg(REG_HREF,HREF_QQVGA);
diasea 0:6be5fa68dddc 509 WriteReg(REG_VSTART,VSTART_QQVGA);
diasea 0:6be5fa68dddc 510 WriteReg(REG_VSTOP,VSTOP_QQVGA);
diasea 0:6be5fa68dddc 511 WriteReg(REG_VREF,VREF_QQVGA);
diasea 0:6be5fa68dddc 512 WriteReg(REG_COM3, COM3_QQVGA);
diasea 0:6be5fa68dddc 513 WriteReg(REG_COM14, COM14_QQVGA);
diasea 0:6be5fa68dddc 514 WriteReg(REG_SCALING_XSC, SCALING_XSC_QQVGA);
diasea 0:6be5fa68dddc 515 WriteReg(REG_SCALING_YSC, SCALING_YSC_QQVGA);
diasea 0:6be5fa68dddc 516 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_QQVGA);
diasea 0:6be5fa68dddc 517 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_QQVGA);
diasea 0:6be5fa68dddc 518 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_QQVGA);
diasea 0:6be5fa68dddc 519 }
diasea 0:6be5fa68dddc 520
diasea 0:6be5fa68dddc 521 // vsync handler
diasea 0:6be5fa68dddc 522 void VsyncHandler(void)
diasea 0:6be5fa68dddc 523 {
diasea 0:6be5fa68dddc 524 // Capture Enable
diasea 0:6be5fa68dddc 525 if (CaptureReq) {
diasea 4:2c412c97678c 526 wen = 1;
diasea 4:2c412c97678c 527 Done = false;
diasea 4:2c412c97678c 528 CaptureReq = false;
diasea 0:6be5fa68dddc 529 } else {
diasea 4:2c412c97678c 530 wen = 0;
diasea 0:6be5fa68dddc 531 if (Busy) {
diasea 4:2c412c97678c 532 Busy = false;
diasea 4:2c412c97678c 533 Done = true;
diasea 0:6be5fa68dddc 534 }
diasea 0:6be5fa68dddc 535 }
diasea 0:6be5fa68dddc 536
diasea 0:6be5fa68dddc 537 // Hline Counter
diasea 4:2c412c97678c 538 LastLines = LineCounter;
diasea 4:2c412c97678c 539 LineCounter = 0;
diasea 0:6be5fa68dddc 540 }
diasea 0:6be5fa68dddc 541
diasea 0:6be5fa68dddc 542 // href handler
diasea 0:6be5fa68dddc 543 void HrefHandler(void)
diasea 0:6be5fa68dddc 544 {
diasea 4:2c412c97678c 545 LineCounter++;
diasea 0:6be5fa68dddc 546 }
diasea 0:6be5fa68dddc 547
diasea 0:6be5fa68dddc 548 // Data Read
diasea 0:6be5fa68dddc 549 int ReadOneByte(void)
diasea 0:6be5fa68dddc 550 {
diasea 4:2c412c97678c 551 int result;
diasea 4:2c412c97678c 552 rclk = 1;
diasea 4:2c412c97678c 553 // wait_us(1);
diasea 4:2c412c97678c 554 result = data;
diasea 4:2c412c97678c 555 rclk = 0;
diasea 4:2c412c97678c 556 return result;
diasea 0:6be5fa68dddc 557 }
diasea 0:6be5fa68dddc 558
diasea 0:6be5fa68dddc 559 // Data Start
diasea 0:6be5fa68dddc 560 void ReadStart(void)
diasea 0:6be5fa68dddc 561 {
diasea 4:2c412c97678c 562 rrst = 0;
diasea 4:2c412c97678c 563 oe = 0;
diasea 4:2c412c97678c 564 wait_us(1);
diasea 4:2c412c97678c 565 rclk = 0;
diasea 4:2c412c97678c 566 wait_us(1);
diasea 4:2c412c97678c 567 rclk = 1;
diasea 4:2c412c97678c 568 wait_us(1);
diasea 4:2c412c97678c 569 rrst = 1;
diasea 0:6be5fa68dddc 570 }
diasea 0:6be5fa68dddc 571
diasea 0:6be5fa68dddc 572 // Data Stop
diasea 0:6be5fa68dddc 573 void ReadStop(void)
diasea 0:6be5fa68dddc 574 {
diasea 4:2c412c97678c 575 oe = 1;
diasea 4:2c412c97678c 576 ReadOneByte();
diasea 4:2c412c97678c 577 rclk = 1;
diasea 0:6be5fa68dddc 578 }
diasea 0:6be5fa68dddc 579 };