Damian Gabino / picoGW_mcu

MCU driver/HAL for the Picocell Gateway concentrator board. The firmware implements either a USB CDC protocol or a UART protocol to bridge commands coming from host to the SX1308 SPI interface.

src/mbed-dev/hal/spi_api.h@0:c76361bd82e8, 2018-04-11 (annotated)

Committer:
dgabino
Date:
Wed Apr 11 14:42:47 2018 +0000
Revision:
0:c76361bd82e8
Initial commit

Who changed what in which revision?

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dgabino 0:c76361bd82e8 1 /* mbed Microcontroller Library
dgabino 0:c76361bd82e8 2 * Copyright (c) 2006-2013 ARM Limited
dgabino 0:c76361bd82e8 3 *
dgabino 0:c76361bd82e8 4 * Licensed under the Apache License, Version 2.0 (the "License");
dgabino 0:c76361bd82e8 5 * you may not use this file except in compliance with the License.
dgabino 0:c76361bd82e8 6 * You may obtain a copy of the License at
dgabino 0:c76361bd82e8 7 *
dgabino 0:c76361bd82e8 8 * http://www.apache.org/licenses/LICENSE-2.0
dgabino 0:c76361bd82e8 9 *
dgabino 0:c76361bd82e8 10 * Unless required by applicable law or agreed to in writing, software
dgabino 0:c76361bd82e8 11 * distributed under the License is distributed on an "AS IS" BASIS,
dgabino 0:c76361bd82e8 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dgabino 0:c76361bd82e8 13 * See the License for the specific language governing permissions and
dgabino 0:c76361bd82e8 14 * limitations under the License.
dgabino 0:c76361bd82e8 15 */
dgabino 0:c76361bd82e8 16 #ifndef MBED_SPI_API_H
dgabino 0:c76361bd82e8 17 #define MBED_SPI_API_H
dgabino 0:c76361bd82e8 18
dgabino 0:c76361bd82e8 19 #include "device.h"
dgabino 0:c76361bd82e8 20 #include "dma_api.h"
dgabino 0:c76361bd82e8 21 #include "buffer.h"
dgabino 0:c76361bd82e8 22
dgabino 0:c76361bd82e8 23 #if DEVICE_SPI
dgabino 0:c76361bd82e8 24
dgabino 0:c76361bd82e8 25 #define SPI_EVENT_ERROR (1 << 1)
dgabino 0:c76361bd82e8 26 #define SPI_EVENT_COMPLETE (1 << 2)
dgabino 0:c76361bd82e8 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
dgabino 0:c76361bd82e8 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
dgabino 0:c76361bd82e8 29
dgabino 0:c76361bd82e8 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
dgabino 0:c76361bd82e8 31
dgabino 0:c76361bd82e8 32 #define SPI_FILL_WORD (0xFFFF)
dgabino 0:c76361bd82e8 33
dgabino 0:c76361bd82e8 34 #if DEVICE_SPI_ASYNCH
dgabino 0:c76361bd82e8 35 /** Asynch SPI HAL structure
dgabino 0:c76361bd82e8 36 */
dgabino 0:c76361bd82e8 37 typedef struct {
dgabino 0:c76361bd82e8 38 struct spi_s spi; /**< Target specific SPI structure */
dgabino 0:c76361bd82e8 39 struct buffer_s tx_buff; /**< Tx buffer */
dgabino 0:c76361bd82e8 40 struct buffer_s rx_buff; /**< Rx buffer */
dgabino 0:c76361bd82e8 41 } spi_t;
dgabino 0:c76361bd82e8 42
dgabino 0:c76361bd82e8 43 #else
dgabino 0:c76361bd82e8 44 /** Non-asynch SPI HAL structure
dgabino 0:c76361bd82e8 45 */
dgabino 0:c76361bd82e8 46 typedef struct spi_s spi_t;
dgabino 0:c76361bd82e8 47
dgabino 0:c76361bd82e8 48 #endif
dgabino 0:c76361bd82e8 49
dgabino 0:c76361bd82e8 50 #ifdef __cplusplus
dgabino 0:c76361bd82e8 51 extern "C" {
dgabino 0:c76361bd82e8 52 #endif
dgabino 0:c76361bd82e8 53
dgabino 0:c76361bd82e8 54 /**
dgabino 0:c76361bd82e8 55 * \defgroup hal_GeneralSPI SPI Configuration Functions
dgabino 0:c76361bd82e8 56 * @{
dgabino 0:c76361bd82e8 57 */
dgabino 0:c76361bd82e8 58
dgabino 0:c76361bd82e8 59 /** Initialize the SPI peripheral
dgabino 0:c76361bd82e8 60 *
dgabino 0:c76361bd82e8 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
dgabino 0:c76361bd82e8 62 * @param[out] obj The SPI object to initialize
dgabino 0:c76361bd82e8 63 * @param[in] mosi The pin to use for MOSI
dgabino 0:c76361bd82e8 64 * @param[in] miso The pin to use for MISO
dgabino 0:c76361bd82e8 65 * @param[in] sclk The pin to use for SCLK
dgabino 0:c76361bd82e8 66 * @param[in] ssel The pin to use for SSEL
dgabino 0:c76361bd82e8 67 */
dgabino 0:c76361bd82e8 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
dgabino 0:c76361bd82e8 69
dgabino 0:c76361bd82e8 70 /** Release a SPI object
dgabino 0:c76361bd82e8 71 *
dgabino 0:c76361bd82e8 72 * TODO: spi_free is currently unimplemented
dgabino 0:c76361bd82e8 73 * This will require reference counting at the C++ level to be safe
dgabino 0:c76361bd82e8 74 *
dgabino 0:c76361bd82e8 75 * Return the pins owned by the SPI object to their reset state
dgabino 0:c76361bd82e8 76 * Disable the SPI peripheral
dgabino 0:c76361bd82e8 77 * Disable the SPI clock
dgabino 0:c76361bd82e8 78 * @param[in] obj The SPI object to deinitialize
dgabino 0:c76361bd82e8 79 */
dgabino 0:c76361bd82e8 80 void spi_free(spi_t *obj);
dgabino 0:c76361bd82e8 81
dgabino 0:c76361bd82e8 82 /** Configure the SPI format
dgabino 0:c76361bd82e8 83 *
dgabino 0:c76361bd82e8 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
dgabino 0:c76361bd82e8 85 * The default bit order is MSB.
dgabino 0:c76361bd82e8 86 * @param[in,out] obj The SPI object to configure
dgabino 0:c76361bd82e8 87 * @param[in] bits The number of bits per frame
dgabino 0:c76361bd82e8 88 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
dgabino 0:c76361bd82e8 89 * @param[in] slave Zero for master mode or non-zero for slave mode
dgabino 0:c76361bd82e8 90 */
dgabino 0:c76361bd82e8 91 void spi_format(spi_t *obj, int bits, int mode, int slave);
dgabino 0:c76361bd82e8 92
dgabino 0:c76361bd82e8 93 /** Set the SPI baud rate
dgabino 0:c76361bd82e8 94 *
dgabino 0:c76361bd82e8 95 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
dgabino 0:c76361bd82e8 96 * Configures the SPI peripheral's baud rate
dgabino 0:c76361bd82e8 97 * @param[in,out] obj The SPI object to configure
dgabino 0:c76361bd82e8 98 * @param[in] hz The baud rate in Hz
dgabino 0:c76361bd82e8 99 */
dgabino 0:c76361bd82e8 100 void spi_frequency(spi_t *obj, int hz);
dgabino 0:c76361bd82e8 101
dgabino 0:c76361bd82e8 102 /**@}*/
dgabino 0:c76361bd82e8 103 /**
dgabino 0:c76361bd82e8 104 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
dgabino 0:c76361bd82e8 105 * @{
dgabino 0:c76361bd82e8 106 */
dgabino 0:c76361bd82e8 107
dgabino 0:c76361bd82e8 108 /** Write a byte out in master mode and receive a value
dgabino 0:c76361bd82e8 109 *
dgabino 0:c76361bd82e8 110 * @param[in] obj The SPI peripheral to use for sending
dgabino 0:c76361bd82e8 111 * @param[in] value The value to send
dgabino 0:c76361bd82e8 112 * @return Returns the value received during send
dgabino 0:c76361bd82e8 113 */
dgabino 0:c76361bd82e8 114 int spi_master_write(spi_t *obj, int value);
dgabino 0:c76361bd82e8 115
dgabino 0:c76361bd82e8 116 /** Check if a value is available to read
dgabino 0:c76361bd82e8 117 *
dgabino 0:c76361bd82e8 118 * @param[in] obj The SPI peripheral to check
dgabino 0:c76361bd82e8 119 * @return non-zero if a value is available
dgabino 0:c76361bd82e8 120 */
dgabino 0:c76361bd82e8 121 int spi_slave_receive(spi_t *obj);
dgabino 0:c76361bd82e8 122
dgabino 0:c76361bd82e8 123 /** Get a received value out of the SPI receive buffer in slave mode
dgabino 0:c76361bd82e8 124 *
dgabino 0:c76361bd82e8 125 * Blocks until a value is available
dgabino 0:c76361bd82e8 126 * @param[in] obj The SPI peripheral to read
dgabino 0:c76361bd82e8 127 * @return The value received
dgabino 0:c76361bd82e8 128 */
dgabino 0:c76361bd82e8 129 int spi_slave_read(spi_t *obj);
dgabino 0:c76361bd82e8 130
dgabino 0:c76361bd82e8 131 /** Write a value to the SPI peripheral in slave mode
dgabino 0:c76361bd82e8 132 *
dgabino 0:c76361bd82e8 133 * Blocks until the SPI peripheral can be written to
dgabino 0:c76361bd82e8 134 * @param[in] obj The SPI peripheral to write
dgabino 0:c76361bd82e8 135 * @param[in] value The value to write
dgabino 0:c76361bd82e8 136 */
dgabino 0:c76361bd82e8 137 void spi_slave_write(spi_t *obj, int value);
dgabino 0:c76361bd82e8 138
dgabino 0:c76361bd82e8 139 /** Checks if the specified SPI peripheral is in use
dgabino 0:c76361bd82e8 140 *
dgabino 0:c76361bd82e8 141 * @param[in] obj The SPI peripheral to check
dgabino 0:c76361bd82e8 142 * @return non-zero if the peripheral is currently transmitting
dgabino 0:c76361bd82e8 143 */
dgabino 0:c76361bd82e8 144 int spi_busy(spi_t *obj);
dgabino 0:c76361bd82e8 145
dgabino 0:c76361bd82e8 146 /** Get the module number
dgabino 0:c76361bd82e8 147 *
dgabino 0:c76361bd82e8 148 * @param[in] obj The SPI peripheral to check
dgabino 0:c76361bd82e8 149 * @return The module number
dgabino 0:c76361bd82e8 150 */
dgabino 0:c76361bd82e8 151 uint8_t spi_get_module(spi_t *obj);
dgabino 0:c76361bd82e8 152
dgabino 0:c76361bd82e8 153 /**@}*/
dgabino 0:c76361bd82e8 154
dgabino 0:c76361bd82e8 155 #if DEVICE_SPI_ASYNCH
dgabino 0:c76361bd82e8 156 /**
dgabino 0:c76361bd82e8 157 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
dgabino 0:c76361bd82e8 158 * @{
dgabino 0:c76361bd82e8 159 */
dgabino 0:c76361bd82e8 160
dgabino 0:c76361bd82e8 161 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
dgabino 0:c76361bd82e8 162 *
dgabino 0:c76361bd82e8 163 * @param[in] obj The SPI object that holds the transfer information
dgabino 0:c76361bd82e8 164 * @param[in] tx The transmit buffer
dgabino 0:c76361bd82e8 165 * @param[in] tx_length The number of bytes to transmit
dgabino 0:c76361bd82e8 166 * @param[in] rx The receive buffer
dgabino 0:c76361bd82e8 167 * @param[in] rx_length The number of bytes to receive
dgabino 0:c76361bd82e8 168 * @param[in] bit_width The bit width of buffer words
dgabino 0:c76361bd82e8 169 * @param[in] event The logical OR of events to be registered
dgabino 0:c76361bd82e8 170 * @param[in] handler SPI interrupt handler
dgabino 0:c76361bd82e8 171 * @param[in] hint A suggestion for how to use DMA with this transfer
dgabino 0:c76361bd82e8 172 */
dgabino 0:c76361bd82e8 173 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
dgabino 0:c76361bd82e8 174
dgabino 0:c76361bd82e8 175 /** The asynchronous IRQ handler
dgabino 0:c76361bd82e8 176 *
dgabino 0:c76361bd82e8 177 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
dgabino 0:c76361bd82e8 178 * conditions, such as buffer overflows or transfer complete.
dgabino 0:c76361bd82e8 179 * @param[in] obj The SPI object that holds the transfer information
dgabino 0:c76361bd82e8 180 * @return Event flags if a transfer termination condition was met; otherwise 0.
dgabino 0:c76361bd82e8 181 */
dgabino 0:c76361bd82e8 182 uint32_t spi_irq_handler_asynch(spi_t *obj);
dgabino 0:c76361bd82e8 183
dgabino 0:c76361bd82e8 184 /** Attempts to determine if the SPI peripheral is already in use
dgabino 0:c76361bd82e8 185 *
dgabino 0:c76361bd82e8 186 * If a temporary DMA channel has been allocated, peripheral is in use.
dgabino 0:c76361bd82e8 187 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
dgabino 0:c76361bd82e8 188 * channel were allocated.
dgabino 0:c76361bd82e8 189 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
dgabino 0:c76361bd82e8 190 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
dgabino 0:c76361bd82e8 191 * there are any bytes in the FIFOs.
dgabino 0:c76361bd82e8 192 * @param[in] obj The SPI object to check for activity
dgabino 0:c76361bd82e8 193 * @return Non-zero if the SPI port is active or zero if it is not.
dgabino 0:c76361bd82e8 194 */
dgabino 0:c76361bd82e8 195 uint8_t spi_active(spi_t *obj);
dgabino 0:c76361bd82e8 196
dgabino 0:c76361bd82e8 197 /** Abort an SPI transfer
dgabino 0:c76361bd82e8 198 *
dgabino 0:c76361bd82e8 199 * @param obj The SPI peripheral to stop
dgabino 0:c76361bd82e8 200 */
dgabino 0:c76361bd82e8 201 void spi_abort_asynch(spi_t *obj);
dgabino 0:c76361bd82e8 202
dgabino 0:c76361bd82e8 203
dgabino 0:c76361bd82e8 204 #endif
dgabino 0:c76361bd82e8 205
dgabino 0:c76361bd82e8 206 /**@}*/
dgabino 0:c76361bd82e8 207
dgabino 0:c76361bd82e8 208 #ifdef __cplusplus
dgabino 0:c76361bd82e8 209 }
dgabino 0:c76361bd82e8 210 #endif // __cplusplus
dgabino 0:c76361bd82e8 211
dgabino 0:c76361bd82e8 212 #endif // SPI_DEVICE
dgabino 0:c76361bd82e8 213
dgabino 0:c76361bd82e8 214 #endif // MBED_SPI_API_H