Damian Gabino / picoGW_hal

Host driver/HAL to build a LoRa Picocell Gateway which communicates through USB with a concentrator board based on Semtech SX1308 multi-channel modem and SX1257/SX1255 RF transceivers.

libloragw/inc/loragw_com.h@0:102b50f941d0, 2018-04-11 (annotated)

Committer:
dgabino
Date:
Wed Apr 11 14:38:42 2018 +0000
Revision:
0:102b50f941d0
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dgabino 0:102b50f941d0 1 /*
dgabino 0:102b50f941d0 2 / _____) _ | |
dgabino 0:102b50f941d0 3 ( (____ _____ ____ _| |_ _____ ____| |__
dgabino 0:102b50f941d0 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
dgabino 0:102b50f941d0 5 _____) ) ____| | | || |_| ____( (___| | | |
dgabino 0:102b50f941d0 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
dgabino 0:102b50f941d0 7 (C)2017 Semtech-Cycleo
dgabino 0:102b50f941d0 8
dgabino 0:102b50f941d0 9 Description:
dgabino 0:102b50f941d0 10 A communication bridge layer to abstract linux/windows OS or others.
dgabino 0:102b50f941d0 11 The current project support only linux os
dgabino 0:102b50f941d0 12
dgabino 0:102b50f941d0 13 License: Revised BSD License, see LICENSE.TXT file include in the project
dgabino 0:102b50f941d0 14
dgabino 0:102b50f941d0 15 */
dgabino 0:102b50f941d0 16
dgabino 0:102b50f941d0 17 #ifndef _LORAGW_COM_H
dgabino 0:102b50f941d0 18 #define _LORAGW_COM_H
dgabino 0:102b50f941d0 19
dgabino 0:102b50f941d0 20 /* -------------------------------------------------------------------------- */
dgabino 0:102b50f941d0 21 /* --- DEPENDANCIES --------------------------------------------------------- */
dgabino 0:102b50f941d0 22
dgabino 0:102b50f941d0 23 #include <stdint.h> /* C99 types*/
dgabino 0:102b50f941d0 24
dgabino 0:102b50f941d0 25 #include "config.h" /* library configuration options (dynamically generated) */
dgabino 0:102b50f941d0 26
dgabino 0:102b50f941d0 27 /* -------------------------------------------------------------------------- */
dgabino 0:102b50f941d0 28 /* --- PUBLIC CONSTANTS ----------------------------------------------------- */
dgabino 0:102b50f941d0 29
dgabino 0:102b50f941d0 30 #define LGW_COM_SUCCESS 0
dgabino 0:102b50f941d0 31 #define LGW_COM_ERROR -1
dgabino 0:102b50f941d0 32 #define LGW_BURST_CHUNK 1024
dgabino 0:102b50f941d0 33 #define LGW_COM_MUX_MODE0 0x0 /* No FPGA */
dgabino 0:102b50f941d0 34 #define LGW_COM_MUX_TARGET_SX1301 0x0
dgabino 0:102b50f941d0 35
dgabino 0:102b50f941d0 36 #define ATOMICTX 600
dgabino 0:102b50f941d0 37 #define ATOMICRX 900
dgabino 0:102b50f941d0 38
dgabino 0:102b50f941d0 39 #define CMD_HEADER_TX_SIZE 4 /* id + len_msb + len_lsb + address */
dgabino 0:102b50f941d0 40 #define CMD_HEADER_RX_SIZE 4 /* id + len_msb + len_lsb + status */
dgabino 0:102b50f941d0 41
dgabino 0:102b50f941d0 42 #define CMD_DATA_TX_SIZE ATOMICTX
dgabino 0:102b50f941d0 43 #define CMD_DATA_RX_SIZE (1024 + 16 * 44) /* MAX_FIFO + 16 * METADATA_SIZE_ALIGNED */
dgabino 0:102b50f941d0 44
dgabino 0:102b50f941d0 45 #define ACK_OK 1
dgabino 0:102b50f941d0 46 #define ACK_KO 0
dgabino 0:102b50f941d0 47
dgabino 0:102b50f941d0 48 /* -------------------------------------------------------------------------- */
dgabino 0:102b50f941d0 49 /* --- PUBLIC TYPES --------------------------------------------------------- */
dgabino 0:102b50f941d0 50
dgabino 0:102b50f941d0 51 /**
dgabino 0:102b50f941d0 52 @struct lgw_com_cmd_t
dgabino 0:102b50f941d0 53 @brief structure for host to mcu commands
dgabino 0:102b50f941d0 54 */
dgabino 0:102b50f941d0 55 /********************************************************/
dgabino 0:102b50f941d0 56 /* cmd name | description */
dgabino 0:102b50f941d0 57 /*------------------------------------------------------*/
dgabino 0:102b50f941d0 58 /* r |Read register */
dgabino 0:102b50f941d0 59 /* s |Read long burst First packet */
dgabino 0:102b50f941d0 60 /* t |Read long burst Middle packet */
dgabino 0:102b50f941d0 61 /* u |Read long burst End packet */
dgabino 0:102b50f941d0 62 /* p |Read atomic burst packet */
dgabino 0:102b50f941d0 63 /* w |Write register */
dgabino 0:102b50f941d0 64 /* x |Write long burst First packet */
dgabino 0:102b50f941d0 65 /* y |Write long burst Middle packet */
dgabino 0:102b50f941d0 66 /* z |Write long burst End packet */
dgabino 0:102b50f941d0 67 /* a |Write atomic burst packet */
dgabino 0:102b50f941d0 68 /*------------------------------------------------------*/
dgabino 0:102b50f941d0 69 /* b |lgw_receive cmd */
dgabino 0:102b50f941d0 70 /* c |lgw_rxrf_setconf cmd */
dgabino 0:102b50f941d0 71 /* d |int lgw_rxif_setconf_cmd */
dgabino 0:102b50f941d0 72 /* f |int lgw_send cmd */
dgabino 0:102b50f941d0 73 /* h |lgw_txgain_setconf */
dgabino 0:102b50f941d0 74 /* q |lgw_trigger */
dgabino 0:102b50f941d0 75 /* i |lgw_board_setconf */
dgabino 0:102b50f941d0 76 /* j |lgw_calibration_snapshot */
dgabino 0:102b50f941d0 77 /* l |lgw_check_fw_version */
dgabino 0:102b50f941d0 78 /* m |Reset STM32 */
dgabino 0:102b50f941d0 79 /* n |Go to bootloader */
dgabino 0:102b50f941d0 80 /********************************************************/
dgabino 0:102b50f941d0 81
dgabino 0:102b50f941d0 82 typedef struct {
dgabino 0:102b50f941d0 83 char id; /*!> command ID */
dgabino 0:102b50f941d0 84 uint8_t len_msb; /*!> command length MSB */
dgabino 0:102b50f941d0 85 uint8_t len_lsb; /*!> command length LSB */
dgabino 0:102b50f941d0 86 uint8_t address; /*!> register address for register read/write commands */
dgabino 0:102b50f941d0 87 uint8_t cmd_data[CMD_DATA_TX_SIZE]; /*!> raw data to be transfered */
dgabino 0:102b50f941d0 88 } lgw_com_cmd_t;
dgabino 0:102b50f941d0 89
dgabino 0:102b50f941d0 90 /**
dgabino 0:102b50f941d0 91 @struct lgw_com_ans_t
dgabino 0:102b50f941d0 92 @brief structure for mcu to host command answers
dgabino 0:102b50f941d0 93 */
dgabino 0:102b50f941d0 94 typedef struct {
dgabino 0:102b50f941d0 95 char id; /*!> command ID */
dgabino 0:102b50f941d0 96 uint8_t len_msb; /*!> command length MSB */
dgabino 0:102b50f941d0 97 uint8_t len_lsb; /*!> command length LSB */
dgabino 0:102b50f941d0 98 uint8_t status; /*!> command acknoledge */
dgabino 0:102b50f941d0 99 uint8_t ans_data[CMD_DATA_RX_SIZE]; /*!> raw answer data */
dgabino 0:102b50f941d0 100 } lgw_com_ans_t;
dgabino 0:102b50f941d0 101
dgabino 0:102b50f941d0 102 /**
dgabino 0:102b50f941d0 103 @brief Generic file handle for communication bridge
dgabino 0:102b50f941d0 104 */
dgabino 0:102b50f941d0 105 #ifdef _WIN32
dgabino 0:102b50f941d0 106 typedef HANDLE lgw_handle_t;
dgabino 0:102b50f941d0 107 #define LGW_GET_HANDLE(x) ((lgw_handle_t *)x)
dgabino 0:102b50f941d0 108 #elif __linux__
dgabino 0:102b50f941d0 109 typedef int lgw_handle_t;
dgabino 0:102b50f941d0 110 #define LGW_GET_HANDLE(x) (*(lgw_handle_t *)x)
dgabino 0:102b50f941d0 111 #endif
dgabino 0:102b50f941d0 112
dgabino 0:102b50f941d0 113
dgabino 0:102b50f941d0 114 /* -------------------------------------------------------------------------- */
dgabino 0:102b50f941d0 115 /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */
dgabino 0:102b50f941d0 116
dgabino 0:102b50f941d0 117 /**
dgabino 0:102b50f941d0 118 @brief LoRa concentrator USB setup
dgabino 0:102b50f941d0 119 @param com_target_ptr pointer on a generic pointer to USB target
dgabino 0:102b50f941d0 120 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 121 */
dgabino 0:102b50f941d0 122
dgabino 0:102b50f941d0 123 int lgw_com_open(void **com_target_ptr, const char *com_path);
dgabino 0:102b50f941d0 124
dgabino 0:102b50f941d0 125 /**
dgabino 0:102b50f941d0 126 @brief LoRa concentrator USB close
dgabino 0:102b50f941d0 127 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 128 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 129 */
dgabino 0:102b50f941d0 130
dgabino 0:102b50f941d0 131 int lgw_com_close(void *com_target);
dgabino 0:102b50f941d0 132
dgabino 0:102b50f941d0 133 /**
dgabino 0:102b50f941d0 134 @brief LoRa usb bridge to spi sx1308 concentrator single-byte write
dgabino 0:102b50f941d0 135 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 136 @param address 7-bit register address
dgabino 0:102b50f941d0 137 @param data data byte to write
dgabino 0:102b50f941d0 138 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 139 */
dgabino 0:102b50f941d0 140 int lgw_com_w(void *com_target, uint8_t com_mux_mode, uint8_t com_mux_target, uint8_t address, uint8_t data);
dgabino 0:102b50f941d0 141
dgabino 0:102b50f941d0 142 /**
dgabino 0:102b50f941d0 143 @brief LoRa usb bridge to spi sx1308 concentrator single-byte read
dgabino 0:102b50f941d0 144 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 145 @param address 7-bit register address
dgabino 0:102b50f941d0 146 @param data data byte to write
dgabino 0:102b50f941d0 147 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 148 */
dgabino 0:102b50f941d0 149 int lgw_com_r(void *com_target, uint8_t com_mux_mode, uint8_t com_mux_target, uint8_t address, uint8_t *data);
dgabino 0:102b50f941d0 150
dgabino 0:102b50f941d0 151 /**
dgabino 0:102b50f941d0 152 @brief LoRa usb bridge to spi sx1308 concentrator burst (multiple-byte) write
dgabino 0:102b50f941d0 153 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 154 @param address 7-bit register address
dgabino 0:102b50f941d0 155 @param data pointer to byte array that will be sent to the LoRa concentrator
dgabino 0:102b50f941d0 156 @param size size of the transfer, in byte(s)
dgabino 0:102b50f941d0 157 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 158 */
dgabino 0:102b50f941d0 159 int lgw_com_wb(void *com_target, uint8_t com_mux_mode, uint8_t com_mux_target, uint8_t address, uint8_t *data, uint16_t size);
dgabino 0:102b50f941d0 160
dgabino 0:102b50f941d0 161 /**
dgabino 0:102b50f941d0 162 @brief LoRa usb bridge to spi sx1308 concentrator burst (multiple-byte) read
dgabino 0:102b50f941d0 163 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 164 @param address 7-bit register address
dgabino 0:102b50f941d0 165 @param data pointer to byte array that will be written from the LoRa concentrator
dgabino 0:102b50f941d0 166 @param size size of the transfer, in byte(s)
dgabino 0:102b50f941d0 167 @return status of register operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 168 */
dgabino 0:102b50f941d0 169 int lgw_com_rb(void *com_target, uint8_t com_mux_mode, uint8_t com_mux_target, uint8_t address, uint8_t *data, uint16_t size);
dgabino 0:102b50f941d0 170
dgabino 0:102b50f941d0 171 /**
dgabino 0:102b50f941d0 172 @brief Send command to concentrator through MCU, and wait for answer
dgabino 0:102b50f941d0 173 @param com_target generic pointer to USB target
dgabino 0:102b50f941d0 174 @param cmd command to be sent to the concentrator
dgabino 0:102b50f941d0 175 @param ans answer received from the concentrator
dgabino 0:102b50f941d0 176 @return status of operation (LGW_COM_SUCCESS/LGW_COM_ERROR)
dgabino 0:102b50f941d0 177 */
dgabino 0:102b50f941d0 178 int lgw_com_send_command(void *com_target, lgw_com_cmd_t cmd, lgw_com_ans_t *ans);
dgabino 0:102b50f941d0 179
dgabino 0:102b50f941d0 180 #endif
dgabino 0:102b50f941d0 181
dgabino 0:102b50f941d0 182 /* --- EOF ------------------------------------------------------------------ */