Dewant Katare / Mbed 2 deprecated RFID_RC522

RFID-RC522, SPI, FRDMk64F

Dependencies:   mbed

MFRC522.cpp@0:35581ea6b194, 2019-04-17 (annotated)

Committer:
dewantkatare
Date:
Wed Apr 17 20:36:49 2019 +0000
Revision:
0:35581ea6b194
RFID-RC522, K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dewantkatare 0:35581ea6b194 1 /*
dewantkatare 0:35581ea6b194 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
dewantkatare 0:35581ea6b194 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
dewantkatare 0:35581ea6b194 4 * Released into the public domain.
dewantkatare 0:35581ea6b194 5 */
dewantkatare 0:35581ea6b194 6
dewantkatare 0:35581ea6b194 7 #include "MFRC522.h"
dewantkatare 0:35581ea6b194 8
dewantkatare 0:35581ea6b194 9 static const char* const _TypeNamePICC[] =
dewantkatare 0:35581ea6b194 10 {
dewantkatare 0:35581ea6b194 11 "Unknown type",
dewantkatare 0:35581ea6b194 12 "PICC compliant with ISO/IEC 14443-4",
dewantkatare 0:35581ea6b194 13 "PICC compliant with ISO/IEC 18092 (NFC)",
dewantkatare 0:35581ea6b194 14 "MIFARE Mini, 320 bytes",
dewantkatare 0:35581ea6b194 15 "MIFARE 1KB",
dewantkatare 0:35581ea6b194 16 "MIFARE 4KB",
dewantkatare 0:35581ea6b194 17 "MIFARE Ultralight or Ultralight C",
dewantkatare 0:35581ea6b194 18 "MIFARE Plus",
dewantkatare 0:35581ea6b194 19 "MIFARE TNP3XXX",
dewantkatare 0:35581ea6b194 20
dewantkatare 0:35581ea6b194 21 /* not complete UID */
dewantkatare 0:35581ea6b194 22 "SAK indicates UID is not complete"
dewantkatare 0:35581ea6b194 23 };
dewantkatare 0:35581ea6b194 24
dewantkatare 0:35581ea6b194 25 static const char* const _ErrorMessage[] =
dewantkatare 0:35581ea6b194 26 {
dewantkatare 0:35581ea6b194 27 "Unknown error",
dewantkatare 0:35581ea6b194 28 "Success",
dewantkatare 0:35581ea6b194 29 "Error in communication",
dewantkatare 0:35581ea6b194 30 "Collision detected",
dewantkatare 0:35581ea6b194 31 "Timeout in communication",
dewantkatare 0:35581ea6b194 32 "A buffer is not big enough",
dewantkatare 0:35581ea6b194 33 "Internal error in the code, should not happen",
dewantkatare 0:35581ea6b194 34 "Invalid argument",
dewantkatare 0:35581ea6b194 35 "The CRC_A does not match",
dewantkatare 0:35581ea6b194 36 "A MIFARE PICC responded with NAK"
dewantkatare 0:35581ea6b194 37 };
dewantkatare 0:35581ea6b194 38
dewantkatare 0:35581ea6b194 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
dewantkatare 0:35581ea6b194 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
dewantkatare 0:35581ea6b194 41
dewantkatare 0:35581ea6b194 42 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 43 // Functions for setting up the driver
dewantkatare 0:35581ea6b194 44 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 45
dewantkatare 0:35581ea6b194 46 /**
dewantkatare 0:35581ea6b194 47 * Constructor.
dewantkatare 0:35581ea6b194 48 * Prepares the output pins.
dewantkatare 0:35581ea6b194 49 */
dewantkatare 0:35581ea6b194 50 MFRC522::MFRC522(PinName mosi,
dewantkatare 0:35581ea6b194 51 PinName miso,
dewantkatare 0:35581ea6b194 52 PinName sclk,
dewantkatare 0:35581ea6b194 53 PinName cs,
dewantkatare 0:35581ea6b194 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
dewantkatare 0:35581ea6b194 55 {
dewantkatare 0:35581ea6b194 56 /* Configure SPI bus */
dewantkatare 0:35581ea6b194 57 m_SPI.format(8, 0);
dewantkatare 0:35581ea6b194 58 m_SPI.frequency(8000000);
dewantkatare 0:35581ea6b194 59
dewantkatare 0:35581ea6b194 60 /* Release SPI-CS pin */
dewantkatare 0:35581ea6b194 61 m_CS = 1;
dewantkatare 0:35581ea6b194 62
dewantkatare 0:35581ea6b194 63 /* Release RESET pin */
dewantkatare 0:35581ea6b194 64 m_RESET = 1;
dewantkatare 0:35581ea6b194 65 } // End constructor
dewantkatare 0:35581ea6b194 66
dewantkatare 0:35581ea6b194 67
dewantkatare 0:35581ea6b194 68 /**
dewantkatare 0:35581ea6b194 69 * Destructor.
dewantkatare 0:35581ea6b194 70 */
dewantkatare 0:35581ea6b194 71 MFRC522::~MFRC522()
dewantkatare 0:35581ea6b194 72 {
dewantkatare 0:35581ea6b194 73
dewantkatare 0:35581ea6b194 74 }
dewantkatare 0:35581ea6b194 75
dewantkatare 0:35581ea6b194 76
dewantkatare 0:35581ea6b194 77 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 78 // Basic interface functions for communicating with the MFRC522
dewantkatare 0:35581ea6b194 79 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 80
dewantkatare 0:35581ea6b194 81 /**
dewantkatare 0:35581ea6b194 82 * Writes a byte to the specified register in the MFRC522 chip.
dewantkatare 0:35581ea6b194 83 * The interface is described in the datasheet section 8.1.2.
dewantkatare 0:35581ea6b194 84 */
dewantkatare 0:35581ea6b194 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
dewantkatare 0:35581ea6b194 86 {
dewantkatare 0:35581ea6b194 87 m_CS = 0; /* Select SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 88
dewantkatare 0:35581ea6b194 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
dewantkatare 0:35581ea6b194 90 (void) m_SPI.write(reg & 0x7E);
dewantkatare 0:35581ea6b194 91 (void) m_SPI.write(value);
dewantkatare 0:35581ea6b194 92
dewantkatare 0:35581ea6b194 93 m_CS = 1; /* Release SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 94 } // End PCD_WriteRegister()
dewantkatare 0:35581ea6b194 95
dewantkatare 0:35581ea6b194 96 /**
dewantkatare 0:35581ea6b194 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
dewantkatare 0:35581ea6b194 98 * The interface is described in the datasheet section 8.1.2.
dewantkatare 0:35581ea6b194 99 */
dewantkatare 0:35581ea6b194 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
dewantkatare 0:35581ea6b194 101 {
dewantkatare 0:35581ea6b194 102 m_CS = 0; /* Select SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 103
dewantkatare 0:35581ea6b194 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
dewantkatare 0:35581ea6b194 105 (void) m_SPI.write(reg & 0x7E);
dewantkatare 0:35581ea6b194 106 for (uint8_t index = 0; index < count; index++)
dewantkatare 0:35581ea6b194 107 {
dewantkatare 0:35581ea6b194 108 (void) m_SPI.write(values[index]);
dewantkatare 0:35581ea6b194 109 }
dewantkatare 0:35581ea6b194 110
dewantkatare 0:35581ea6b194 111 m_CS = 1; /* Release SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 112 } // End PCD_WriteRegister()
dewantkatare 0:35581ea6b194 113
dewantkatare 0:35581ea6b194 114 /**
dewantkatare 0:35581ea6b194 115 * Reads a byte from the specified register in the MFRC522 chip.
dewantkatare 0:35581ea6b194 116 * The interface is described in the datasheet section 8.1.2.
dewantkatare 0:35581ea6b194 117 */
dewantkatare 0:35581ea6b194 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
dewantkatare 0:35581ea6b194 119 {
dewantkatare 0:35581ea6b194 120 uint8_t value;
dewantkatare 0:35581ea6b194 121 m_CS = 0; /* Select SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 122
dewantkatare 0:35581ea6b194 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
dewantkatare 0:35581ea6b194 124 (void) m_SPI.write(0x80 | reg);
dewantkatare 0:35581ea6b194 125
dewantkatare 0:35581ea6b194 126 // Read the value back. Send 0 to stop reading.
dewantkatare 0:35581ea6b194 127 value = m_SPI.write(0);
dewantkatare 0:35581ea6b194 128
dewantkatare 0:35581ea6b194 129 m_CS = 1; /* Release SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 130
dewantkatare 0:35581ea6b194 131 return value;
dewantkatare 0:35581ea6b194 132 } // End PCD_ReadRegister()
dewantkatare 0:35581ea6b194 133
dewantkatare 0:35581ea6b194 134 /**
dewantkatare 0:35581ea6b194 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
dewantkatare 0:35581ea6b194 136 * The interface is described in the datasheet section 8.1.2.
dewantkatare 0:35581ea6b194 137 */
dewantkatare 0:35581ea6b194 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
dewantkatare 0:35581ea6b194 139 {
dewantkatare 0:35581ea6b194 140 if (count == 0) { return; }
dewantkatare 0:35581ea6b194 141
dewantkatare 0:35581ea6b194 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
dewantkatare 0:35581ea6b194 143 uint8_t index = 0; // Index in values array.
dewantkatare 0:35581ea6b194 144
dewantkatare 0:35581ea6b194 145 m_CS = 0; /* Select SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 146 count--; // One read is performed outside of the loop
dewantkatare 0:35581ea6b194 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
dewantkatare 0:35581ea6b194 148
dewantkatare 0:35581ea6b194 149 while (index < count)
dewantkatare 0:35581ea6b194 150 {
dewantkatare 0:35581ea6b194 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
dewantkatare 0:35581ea6b194 152 {
dewantkatare 0:35581ea6b194 153 // Create bit mask for bit positions rxAlign..7
dewantkatare 0:35581ea6b194 154 uint8_t mask = 0;
dewantkatare 0:35581ea6b194 155 for (uint8_t i = rxAlign; i <= 7; i++)
dewantkatare 0:35581ea6b194 156 {
dewantkatare 0:35581ea6b194 157 mask |= (1 << i);
dewantkatare 0:35581ea6b194 158 }
dewantkatare 0:35581ea6b194 159
dewantkatare 0:35581ea6b194 160 // Read value and tell that we want to read the same address again.
dewantkatare 0:35581ea6b194 161 uint8_t value = m_SPI.write(address);
dewantkatare 0:35581ea6b194 162
dewantkatare 0:35581ea6b194 163 // Apply mask to both current value of values[0] and the new data in value.
dewantkatare 0:35581ea6b194 164 values[0] = (values[index] & ~mask) | (value & mask);
dewantkatare 0:35581ea6b194 165 }
dewantkatare 0:35581ea6b194 166 else
dewantkatare 0:35581ea6b194 167 {
dewantkatare 0:35581ea6b194 168 // Read value and tell that we want to read the same address again.
dewantkatare 0:35581ea6b194 169 values[index] = m_SPI.write(address);
dewantkatare 0:35581ea6b194 170 }
dewantkatare 0:35581ea6b194 171
dewantkatare 0:35581ea6b194 172 index++;
dewantkatare 0:35581ea6b194 173 }
dewantkatare 0:35581ea6b194 174
dewantkatare 0:35581ea6b194 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
dewantkatare 0:35581ea6b194 176
dewantkatare 0:35581ea6b194 177 m_CS = 1; /* Release SPI Chip MFRC522 */
dewantkatare 0:35581ea6b194 178 } // End PCD_ReadRegister()
dewantkatare 0:35581ea6b194 179
dewantkatare 0:35581ea6b194 180 /**
dewantkatare 0:35581ea6b194 181 * Sets the bits given in mask in register reg.
dewantkatare 0:35581ea6b194 182 */
dewantkatare 0:35581ea6b194 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
dewantkatare 0:35581ea6b194 184 {
dewantkatare 0:35581ea6b194 185 uint8_t tmp = PCD_ReadRegister(reg);
dewantkatare 0:35581ea6b194 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
dewantkatare 0:35581ea6b194 187 } // End PCD_SetRegisterBitMask()
dewantkatare 0:35581ea6b194 188
dewantkatare 0:35581ea6b194 189 /**
dewantkatare 0:35581ea6b194 190 * Clears the bits given in mask from register reg.
dewantkatare 0:35581ea6b194 191 */
dewantkatare 0:35581ea6b194 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
dewantkatare 0:35581ea6b194 193 {
dewantkatare 0:35581ea6b194 194 uint8_t tmp = PCD_ReadRegister(reg);
dewantkatare 0:35581ea6b194 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
dewantkatare 0:35581ea6b194 196 } // End PCD_ClearRegisterBitMask()
dewantkatare 0:35581ea6b194 197
dewantkatare 0:35581ea6b194 198
dewantkatare 0:35581ea6b194 199 /**
dewantkatare 0:35581ea6b194 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
dewantkatare 0:35581ea6b194 201 */
dewantkatare 0:35581ea6b194 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
dewantkatare 0:35581ea6b194 203 {
dewantkatare 0:35581ea6b194 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
dewantkatare 0:35581ea6b194 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
dewantkatare 0:35581ea6b194 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
dewantkatare 0:35581ea6b194 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
dewantkatare 0:35581ea6b194 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
dewantkatare 0:35581ea6b194 209
dewantkatare 0:35581ea6b194 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
dewantkatare 0:35581ea6b194 211 uint16_t i = 5000;
dewantkatare 0:35581ea6b194 212 uint8_t n;
dewantkatare 0:35581ea6b194 213 while (1)
dewantkatare 0:35581ea6b194 214 {
dewantkatare 0:35581ea6b194 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
dewantkatare 0:35581ea6b194 216 if (n & 0x04)
dewantkatare 0:35581ea6b194 217 {
dewantkatare 0:35581ea6b194 218 // CRCIRq bit set - calculation done
dewantkatare 0:35581ea6b194 219 break;
dewantkatare 0:35581ea6b194 220 }
dewantkatare 0:35581ea6b194 221
dewantkatare 0:35581ea6b194 222 if (--i == 0)
dewantkatare 0:35581ea6b194 223 {
dewantkatare 0:35581ea6b194 224 // The emergency break. We will eventually terminate on this one after 89ms.
dewantkatare 0:35581ea6b194 225 // Communication with the MFRC522 might be down.
dewantkatare 0:35581ea6b194 226 return STATUS_TIMEOUT;
dewantkatare 0:35581ea6b194 227 }
dewantkatare 0:35581ea6b194 228 }
dewantkatare 0:35581ea6b194 229
dewantkatare 0:35581ea6b194 230 // Stop calculating CRC for new content in the FIFO.
dewantkatare 0:35581ea6b194 231 PCD_WriteRegister(CommandReg, PCD_Idle);
dewantkatare 0:35581ea6b194 232
dewantkatare 0:35581ea6b194 233 // Transfer the result from the registers to the result buffer
dewantkatare 0:35581ea6b194 234 result[0] = PCD_ReadRegister(CRCResultRegL);
dewantkatare 0:35581ea6b194 235 result[1] = PCD_ReadRegister(CRCResultRegH);
dewantkatare 0:35581ea6b194 236 return STATUS_OK;
dewantkatare 0:35581ea6b194 237 } // End PCD_CalculateCRC()
dewantkatare 0:35581ea6b194 238
dewantkatare 0:35581ea6b194 239
dewantkatare 0:35581ea6b194 240 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 241 // Functions for manipulating the MFRC522
dewantkatare 0:35581ea6b194 242 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 243
dewantkatare 0:35581ea6b194 244 /**
dewantkatare 0:35581ea6b194 245 * Initializes the MFRC522 chip.
dewantkatare 0:35581ea6b194 246 */
dewantkatare 0:35581ea6b194 247 void MFRC522::PCD_Init()
dewantkatare 0:35581ea6b194 248 {
dewantkatare 0:35581ea6b194 249 /* Reset MFRC522 */
dewantkatare 0:35581ea6b194 250 m_RESET = 0;
dewantkatare 0:35581ea6b194 251 wait_ms(10);
dewantkatare 0:35581ea6b194 252 m_RESET = 1;
dewantkatare 0:35581ea6b194 253
dewantkatare 0:35581ea6b194 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
dewantkatare 0:35581ea6b194 255 wait_ms(50);
dewantkatare 0:35581ea6b194 256
dewantkatare 0:35581ea6b194 257 // When communicating with a PICC we need a timeout if something goes wrong.
dewantkatare 0:35581ea6b194 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
dewantkatare 0:35581ea6b194 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
dewantkatare 0:35581ea6b194 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
dewantkatare 0:35581ea6b194 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
dewantkatare 0:35581ea6b194 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
dewantkatare 0:35581ea6b194 263 PCD_WriteRegister(TReloadRegL, 0xE8);
dewantkatare 0:35581ea6b194 264
dewantkatare 0:35581ea6b194 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
dewantkatare 0:35581ea6b194 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
dewantkatare 0:35581ea6b194 267
dewantkatare 0:35581ea6b194 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
dewantkatare 0:35581ea6b194 269
dewantkatare 0:35581ea6b194 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
dewantkatare 0:35581ea6b194 271 } // End PCD_Init()
dewantkatare 0:35581ea6b194 272
dewantkatare 0:35581ea6b194 273 /**
dewantkatare 0:35581ea6b194 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
dewantkatare 0:35581ea6b194 275 */
dewantkatare 0:35581ea6b194 276 void MFRC522::PCD_Reset()
dewantkatare 0:35581ea6b194 277 {
dewantkatare 0:35581ea6b194 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
dewantkatare 0:35581ea6b194 279 // The datasheet does not mention how long the SoftRest command takes to complete.
dewantkatare 0:35581ea6b194 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
dewantkatare 0:35581ea6b194 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
dewantkatare 0:35581ea6b194 282 wait_ms(50);
dewantkatare 0:35581ea6b194 283
dewantkatare 0:35581ea6b194 284 // Wait for the PowerDown bit in CommandReg to be cleared
dewantkatare 0:35581ea6b194 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
dewantkatare 0:35581ea6b194 286 {
dewantkatare 0:35581ea6b194 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
dewantkatare 0:35581ea6b194 288 }
dewantkatare 0:35581ea6b194 289 } // End PCD_Reset()
dewantkatare 0:35581ea6b194 290
dewantkatare 0:35581ea6b194 291 /**
dewantkatare 0:35581ea6b194 292 * Turns the antenna on by enabling pins TX1 and TX2.
dewantkatare 0:35581ea6b194 293 * After a reset these pins disabled.
dewantkatare 0:35581ea6b194 294 */
dewantkatare 0:35581ea6b194 295 void MFRC522::PCD_AntennaOn()
dewantkatare 0:35581ea6b194 296 {
dewantkatare 0:35581ea6b194 297 uint8_t value = PCD_ReadRegister(TxControlReg);
dewantkatare 0:35581ea6b194 298 if ((value & 0x03) != 0x03)
dewantkatare 0:35581ea6b194 299 {
dewantkatare 0:35581ea6b194 300 PCD_WriteRegister(TxControlReg, value | 0x03);
dewantkatare 0:35581ea6b194 301 }
dewantkatare 0:35581ea6b194 302 } // End PCD_AntennaOn()
dewantkatare 0:35581ea6b194 303
dewantkatare 0:35581ea6b194 304 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 305 // Functions for communicating with PICCs
dewantkatare 0:35581ea6b194 306 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 307
dewantkatare 0:35581ea6b194 308 /**
dewantkatare 0:35581ea6b194 309 * Executes the Transceive command.
dewantkatare 0:35581ea6b194 310 * CRC validation can only be done if backData and backLen are specified.
dewantkatare 0:35581ea6b194 311 */
dewantkatare 0:35581ea6b194 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
dewantkatare 0:35581ea6b194 313 uint8_t sendLen,
dewantkatare 0:35581ea6b194 314 uint8_t *backData,
dewantkatare 0:35581ea6b194 315 uint8_t *backLen,
dewantkatare 0:35581ea6b194 316 uint8_t *validBits,
dewantkatare 0:35581ea6b194 317 uint8_t rxAlign,
dewantkatare 0:35581ea6b194 318 bool checkCRC)
dewantkatare 0:35581ea6b194 319 {
dewantkatare 0:35581ea6b194 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
dewantkatare 0:35581ea6b194 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
dewantkatare 0:35581ea6b194 322 } // End PCD_TransceiveData()
dewantkatare 0:35581ea6b194 323
dewantkatare 0:35581ea6b194 324 /**
dewantkatare 0:35581ea6b194 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
dewantkatare 0:35581ea6b194 326 * CRC validation can only be done if backData and backLen are specified.
dewantkatare 0:35581ea6b194 327 */
dewantkatare 0:35581ea6b194 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
dewantkatare 0:35581ea6b194 329 uint8_t waitIRq,
dewantkatare 0:35581ea6b194 330 uint8_t *sendData,
dewantkatare 0:35581ea6b194 331 uint8_t sendLen,
dewantkatare 0:35581ea6b194 332 uint8_t *backData,
dewantkatare 0:35581ea6b194 333 uint8_t *backLen,
dewantkatare 0:35581ea6b194 334 uint8_t *validBits,
dewantkatare 0:35581ea6b194 335 uint8_t rxAlign,
dewantkatare 0:35581ea6b194 336 bool checkCRC)
dewantkatare 0:35581ea6b194 337 {
dewantkatare 0:35581ea6b194 338 uint8_t n, _validBits = 0;
dewantkatare 0:35581ea6b194 339 uint32_t i;
dewantkatare 0:35581ea6b194 340
dewantkatare 0:35581ea6b194 341 // Prepare values for BitFramingReg
dewantkatare 0:35581ea6b194 342 uint8_t txLastBits = validBits ? *validBits : 0;
dewantkatare 0:35581ea6b194 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
dewantkatare 0:35581ea6b194 344
dewantkatare 0:35581ea6b194 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
dewantkatare 0:35581ea6b194 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
dewantkatare 0:35581ea6b194 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
dewantkatare 0:35581ea6b194 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
dewantkatare 0:35581ea6b194 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
dewantkatare 0:35581ea6b194 350 PCD_WriteRegister(CommandReg, command); // Execute the command
dewantkatare 0:35581ea6b194 351 if (command == PCD_Transceive)
dewantkatare 0:35581ea6b194 352 {
dewantkatare 0:35581ea6b194 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
dewantkatare 0:35581ea6b194 354 }
dewantkatare 0:35581ea6b194 355
dewantkatare 0:35581ea6b194 356 // Wait for the command to complete.
dewantkatare 0:35581ea6b194 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
dewantkatare 0:35581ea6b194 358 // Each iteration of the do-while-loop takes 17.86us.
dewantkatare 0:35581ea6b194 359 i = 2000;
dewantkatare 0:35581ea6b194 360 while (1)
dewantkatare 0:35581ea6b194 361 {
dewantkatare 0:35581ea6b194 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
dewantkatare 0:35581ea6b194 363 if (n & waitIRq)
dewantkatare 0:35581ea6b194 364 { // One of the interrupts that signal success has been set.
dewantkatare 0:35581ea6b194 365 break;
dewantkatare 0:35581ea6b194 366 }
dewantkatare 0:35581ea6b194 367
dewantkatare 0:35581ea6b194 368 if (n & 0x01)
dewantkatare 0:35581ea6b194 369 { // Timer interrupt - nothing received in 25ms
dewantkatare 0:35581ea6b194 370 return STATUS_TIMEOUT;
dewantkatare 0:35581ea6b194 371 }
dewantkatare 0:35581ea6b194 372
dewantkatare 0:35581ea6b194 373 if (--i == 0)
dewantkatare 0:35581ea6b194 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
dewantkatare 0:35581ea6b194 375 return STATUS_TIMEOUT;
dewantkatare 0:35581ea6b194 376 }
dewantkatare 0:35581ea6b194 377 }
dewantkatare 0:35581ea6b194 378
dewantkatare 0:35581ea6b194 379 // Stop now if any errors except collisions were detected.
dewantkatare 0:35581ea6b194 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
dewantkatare 0:35581ea6b194 381 if (errorRegValue & 0x13)
dewantkatare 0:35581ea6b194 382 { // BufferOvfl ParityErr ProtocolErr
dewantkatare 0:35581ea6b194 383 return STATUS_ERROR;
dewantkatare 0:35581ea6b194 384 }
dewantkatare 0:35581ea6b194 385
dewantkatare 0:35581ea6b194 386 // If the caller wants data back, get it from the MFRC522.
dewantkatare 0:35581ea6b194 387 if (backData && backLen)
dewantkatare 0:35581ea6b194 388 {
dewantkatare 0:35581ea6b194 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
dewantkatare 0:35581ea6b194 390 if (n > *backLen)
dewantkatare 0:35581ea6b194 391 {
dewantkatare 0:35581ea6b194 392 return STATUS_NO_ROOM;
dewantkatare 0:35581ea6b194 393 }
dewantkatare 0:35581ea6b194 394
dewantkatare 0:35581ea6b194 395 *backLen = n; // Number of bytes returned
dewantkatare 0:35581ea6b194 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
dewantkatare 0:35581ea6b194 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
dewantkatare 0:35581ea6b194 398 if (validBits)
dewantkatare 0:35581ea6b194 399 {
dewantkatare 0:35581ea6b194 400 *validBits = _validBits;
dewantkatare 0:35581ea6b194 401 }
dewantkatare 0:35581ea6b194 402 }
dewantkatare 0:35581ea6b194 403
dewantkatare 0:35581ea6b194 404 // Tell about collisions
dewantkatare 0:35581ea6b194 405 if (errorRegValue & 0x08)
dewantkatare 0:35581ea6b194 406 { // CollErr
dewantkatare 0:35581ea6b194 407 return STATUS_COLLISION;
dewantkatare 0:35581ea6b194 408 }
dewantkatare 0:35581ea6b194 409
dewantkatare 0:35581ea6b194 410 // Perform CRC_A validation if requested.
dewantkatare 0:35581ea6b194 411 if (backData && backLen && checkCRC)
dewantkatare 0:35581ea6b194 412 {
dewantkatare 0:35581ea6b194 413 // In this case a MIFARE Classic NAK is not OK.
dewantkatare 0:35581ea6b194 414 if ((*backLen == 1) && (_validBits == 4))
dewantkatare 0:35581ea6b194 415 {
dewantkatare 0:35581ea6b194 416 return STATUS_MIFARE_NACK;
dewantkatare 0:35581ea6b194 417 }
dewantkatare 0:35581ea6b194 418
dewantkatare 0:35581ea6b194 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
dewantkatare 0:35581ea6b194 420 if ((*backLen < 2) || (_validBits != 0))
dewantkatare 0:35581ea6b194 421 {
dewantkatare 0:35581ea6b194 422 return STATUS_CRC_WRONG;
dewantkatare 0:35581ea6b194 423 }
dewantkatare 0:35581ea6b194 424
dewantkatare 0:35581ea6b194 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
dewantkatare 0:35581ea6b194 426 uint8_t controlBuffer[2];
dewantkatare 0:35581ea6b194 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
dewantkatare 0:35581ea6b194 428 if (n != STATUS_OK)
dewantkatare 0:35581ea6b194 429 {
dewantkatare 0:35581ea6b194 430 return n;
dewantkatare 0:35581ea6b194 431 }
dewantkatare 0:35581ea6b194 432
dewantkatare 0:35581ea6b194 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
dewantkatare 0:35581ea6b194 434 {
dewantkatare 0:35581ea6b194 435 return STATUS_CRC_WRONG;
dewantkatare 0:35581ea6b194 436 }
dewantkatare 0:35581ea6b194 437 }
dewantkatare 0:35581ea6b194 438
dewantkatare 0:35581ea6b194 439 return STATUS_OK;
dewantkatare 0:35581ea6b194 440 } // End PCD_CommunicateWithPICC()
dewantkatare 0:35581ea6b194 441
dewantkatare 0:35581ea6b194 442 /*
dewantkatare 0:35581ea6b194 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
dewantkatare 0:35581ea6b194 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
dewantkatare 0:35581ea6b194 445 */
dewantkatare 0:35581ea6b194 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
dewantkatare 0:35581ea6b194 447 {
dewantkatare 0:35581ea6b194 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
dewantkatare 0:35581ea6b194 449 } // End PICC_RequestA()
dewantkatare 0:35581ea6b194 450
dewantkatare 0:35581ea6b194 451 /**
dewantkatare 0:35581ea6b194 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
dewantkatare 0:35581ea6b194 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
dewantkatare 0:35581ea6b194 454 */
dewantkatare 0:35581ea6b194 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
dewantkatare 0:35581ea6b194 456 {
dewantkatare 0:35581ea6b194 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
dewantkatare 0:35581ea6b194 458 } // End PICC_WakeupA()
dewantkatare 0:35581ea6b194 459
dewantkatare 0:35581ea6b194 460 /*
dewantkatare 0:35581ea6b194 461 * Transmits REQA or WUPA commands.
dewantkatare 0:35581ea6b194 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
dewantkatare 0:35581ea6b194 463 */
dewantkatare 0:35581ea6b194 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
dewantkatare 0:35581ea6b194 465 {
dewantkatare 0:35581ea6b194 466 uint8_t validBits;
dewantkatare 0:35581ea6b194 467 uint8_t status;
dewantkatare 0:35581ea6b194 468
dewantkatare 0:35581ea6b194 469 if (bufferATQA == NULL || *bufferSize < 2)
dewantkatare 0:35581ea6b194 470 { // The ATQA response is 2 bytes long.
dewantkatare 0:35581ea6b194 471 return STATUS_NO_ROOM;
dewantkatare 0:35581ea6b194 472 }
dewantkatare 0:35581ea6b194 473
dewantkatare 0:35581ea6b194 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
dewantkatare 0:35581ea6b194 475 PCD_ClrRegisterBits(CollReg, 0x80);
dewantkatare 0:35581ea6b194 476
dewantkatare 0:35581ea6b194 477 // For REQA and WUPA we need the short frame format
dewantkatare 0:35581ea6b194 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
dewantkatare 0:35581ea6b194 479 validBits = 7;
dewantkatare 0:35581ea6b194 480
dewantkatare 0:35581ea6b194 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
dewantkatare 0:35581ea6b194 482 if (status != STATUS_OK)
dewantkatare 0:35581ea6b194 483 {
dewantkatare 0:35581ea6b194 484 return status;
dewantkatare 0:35581ea6b194 485 }
dewantkatare 0:35581ea6b194 486
dewantkatare 0:35581ea6b194 487 if ((*bufferSize != 2) || (validBits != 0))
dewantkatare 0:35581ea6b194 488 { // ATQA must be exactly 16 bits.
dewantkatare 0:35581ea6b194 489 return STATUS_ERROR;
dewantkatare 0:35581ea6b194 490 }
dewantkatare 0:35581ea6b194 491
dewantkatare 0:35581ea6b194 492 return STATUS_OK;
dewantkatare 0:35581ea6b194 493 } // End PICC_REQA_or_WUPA()
dewantkatare 0:35581ea6b194 494
dewantkatare 0:35581ea6b194 495 /*
dewantkatare 0:35581ea6b194 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
dewantkatare 0:35581ea6b194 497 */
dewantkatare 0:35581ea6b194 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
dewantkatare 0:35581ea6b194 499 {
dewantkatare 0:35581ea6b194 500 bool uidComplete;
dewantkatare 0:35581ea6b194 501 bool selectDone;
dewantkatare 0:35581ea6b194 502 bool useCascadeTag;
dewantkatare 0:35581ea6b194 503 uint8_t cascadeLevel = 1;
dewantkatare 0:35581ea6b194 504 uint8_t result;
dewantkatare 0:35581ea6b194 505 uint8_t count;
dewantkatare 0:35581ea6b194 506 uint8_t index;
dewantkatare 0:35581ea6b194 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
dewantkatare 0:35581ea6b194 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
dewantkatare 0:35581ea6b194 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
dewantkatare 0:35581ea6b194 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
dewantkatare 0:35581ea6b194 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
dewantkatare 0:35581ea6b194 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
dewantkatare 0:35581ea6b194 513 uint8_t *responseBuffer;
dewantkatare 0:35581ea6b194 514 uint8_t responseLength;
dewantkatare 0:35581ea6b194 515
dewantkatare 0:35581ea6b194 516 // Description of buffer structure:
dewantkatare 0:35581ea6b194 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
dewantkatare 0:35581ea6b194 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
dewantkatare 0:35581ea6b194 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
dewantkatare 0:35581ea6b194 520 // Byte 3: UID-data
dewantkatare 0:35581ea6b194 521 // Byte 4: UID-data
dewantkatare 0:35581ea6b194 522 // Byte 5: UID-data
dewantkatare 0:35581ea6b194 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
dewantkatare 0:35581ea6b194 524 // Byte 7: CRC_A
dewantkatare 0:35581ea6b194 525 // Byte 8: CRC_A
dewantkatare 0:35581ea6b194 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
dewantkatare 0:35581ea6b194 527 //
dewantkatare 0:35581ea6b194 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
dewantkatare 0:35581ea6b194 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
dewantkatare 0:35581ea6b194 530 // ======== ============= ===== ===== ===== =====
dewantkatare 0:35581ea6b194 531 // 4 bytes 1 uid0 uid1 uid2 uid3
dewantkatare 0:35581ea6b194 532 // 7 bytes 1 CT uid0 uid1 uid2
dewantkatare 0:35581ea6b194 533 // 2 uid3 uid4 uid5 uid6
dewantkatare 0:35581ea6b194 534 // 10 bytes 1 CT uid0 uid1 uid2
dewantkatare 0:35581ea6b194 535 // 2 CT uid3 uid4 uid5
dewantkatare 0:35581ea6b194 536 // 3 uid6 uid7 uid8 uid9
dewantkatare 0:35581ea6b194 537
dewantkatare 0:35581ea6b194 538 // Sanity checks
dewantkatare 0:35581ea6b194 539 if (validBits > 80)
dewantkatare 0:35581ea6b194 540 {
dewantkatare 0:35581ea6b194 541 return STATUS_INVALID;
dewantkatare 0:35581ea6b194 542 }
dewantkatare 0:35581ea6b194 543
dewantkatare 0:35581ea6b194 544 // Prepare MFRC522
dewantkatare 0:35581ea6b194 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
dewantkatare 0:35581ea6b194 546 PCD_ClrRegisterBits(CollReg, 0x80);
dewantkatare 0:35581ea6b194 547
dewantkatare 0:35581ea6b194 548 // Repeat Cascade Level loop until we have a complete UID.
dewantkatare 0:35581ea6b194 549 uidComplete = false;
dewantkatare 0:35581ea6b194 550 while ( ! uidComplete)
dewantkatare 0:35581ea6b194 551 {
dewantkatare 0:35581ea6b194 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
dewantkatare 0:35581ea6b194 553 switch (cascadeLevel)
dewantkatare 0:35581ea6b194 554 {
dewantkatare 0:35581ea6b194 555 case 1:
dewantkatare 0:35581ea6b194 556 buffer[0] = PICC_CMD_SEL_CL1;
dewantkatare 0:35581ea6b194 557 uidIndex = 0;
dewantkatare 0:35581ea6b194 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
dewantkatare 0:35581ea6b194 559 break;
dewantkatare 0:35581ea6b194 560
dewantkatare 0:35581ea6b194 561 case 2:
dewantkatare 0:35581ea6b194 562 buffer[0] = PICC_CMD_SEL_CL2;
dewantkatare 0:35581ea6b194 563 uidIndex = 3;
dewantkatare 0:35581ea6b194 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
dewantkatare 0:35581ea6b194 565 break;
dewantkatare 0:35581ea6b194 566
dewantkatare 0:35581ea6b194 567 case 3:
dewantkatare 0:35581ea6b194 568 buffer[0] = PICC_CMD_SEL_CL3;
dewantkatare 0:35581ea6b194 569 uidIndex = 6;
dewantkatare 0:35581ea6b194 570 useCascadeTag = false; // Never used in CL3.
dewantkatare 0:35581ea6b194 571 break;
dewantkatare 0:35581ea6b194 572
dewantkatare 0:35581ea6b194 573 default:
dewantkatare 0:35581ea6b194 574 return STATUS_INTERNAL_ERROR;
dewantkatare 0:35581ea6b194 575 //break;
dewantkatare 0:35581ea6b194 576 }
dewantkatare 0:35581ea6b194 577
dewantkatare 0:35581ea6b194 578 // How many UID bits are known in this Cascade Level?
dewantkatare 0:35581ea6b194 579 if(validBits > (8 * uidIndex))
dewantkatare 0:35581ea6b194 580 {
dewantkatare 0:35581ea6b194 581 currentLevelKnownBits = validBits - (8 * uidIndex);
dewantkatare 0:35581ea6b194 582 }
dewantkatare 0:35581ea6b194 583 else
dewantkatare 0:35581ea6b194 584 {
dewantkatare 0:35581ea6b194 585 currentLevelKnownBits = 0;
dewantkatare 0:35581ea6b194 586 }
dewantkatare 0:35581ea6b194 587
dewantkatare 0:35581ea6b194 588 // Copy the known bits from uid->uidByte[] to buffer[]
dewantkatare 0:35581ea6b194 589 index = 2; // destination index in buffer[]
dewantkatare 0:35581ea6b194 590 if (useCascadeTag)
dewantkatare 0:35581ea6b194 591 {
dewantkatare 0:35581ea6b194 592 buffer[index++] = PICC_CMD_CT;
dewantkatare 0:35581ea6b194 593 }
dewantkatare 0:35581ea6b194 594
dewantkatare 0:35581ea6b194 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
dewantkatare 0:35581ea6b194 596 if (bytesToCopy)
dewantkatare 0:35581ea6b194 597 {
dewantkatare 0:35581ea6b194 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
dewantkatare 0:35581ea6b194 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
dewantkatare 0:35581ea6b194 600 if (bytesToCopy > maxBytes)
dewantkatare 0:35581ea6b194 601 {
dewantkatare 0:35581ea6b194 602 bytesToCopy = maxBytes;
dewantkatare 0:35581ea6b194 603 }
dewantkatare 0:35581ea6b194 604
dewantkatare 0:35581ea6b194 605 for (count = 0; count < bytesToCopy; count++)
dewantkatare 0:35581ea6b194 606 {
dewantkatare 0:35581ea6b194 607 buffer[index++] = uid->uidByte[uidIndex + count];
dewantkatare 0:35581ea6b194 608 }
dewantkatare 0:35581ea6b194 609 }
dewantkatare 0:35581ea6b194 610
dewantkatare 0:35581ea6b194 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
dewantkatare 0:35581ea6b194 612 if (useCascadeTag)
dewantkatare 0:35581ea6b194 613 {
dewantkatare 0:35581ea6b194 614 currentLevelKnownBits += 8;
dewantkatare 0:35581ea6b194 615 }
dewantkatare 0:35581ea6b194 616
dewantkatare 0:35581ea6b194 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
dewantkatare 0:35581ea6b194 618 selectDone = false;
dewantkatare 0:35581ea6b194 619 while ( ! selectDone)
dewantkatare 0:35581ea6b194 620 {
dewantkatare 0:35581ea6b194 621 // Find out how many bits and bytes to send and receive.
dewantkatare 0:35581ea6b194 622 if (currentLevelKnownBits >= 32)
dewantkatare 0:35581ea6b194 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
dewantkatare 0:35581ea6b194 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
dewantkatare 0:35581ea6b194 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
dewantkatare 0:35581ea6b194 626
dewantkatare 0:35581ea6b194 627 // Calulate BCC - Block Check Character
dewantkatare 0:35581ea6b194 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
dewantkatare 0:35581ea6b194 629
dewantkatare 0:35581ea6b194 630 // Calculate CRC_A
dewantkatare 0:35581ea6b194 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
dewantkatare 0:35581ea6b194 632 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 633 {
dewantkatare 0:35581ea6b194 634 return result;
dewantkatare 0:35581ea6b194 635 }
dewantkatare 0:35581ea6b194 636
dewantkatare 0:35581ea6b194 637 txLastBits = 0; // 0 => All 8 bits are valid.
dewantkatare 0:35581ea6b194 638 bufferUsed = 9;
dewantkatare 0:35581ea6b194 639
dewantkatare 0:35581ea6b194 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
dewantkatare 0:35581ea6b194 641 responseBuffer = &buffer[6];
dewantkatare 0:35581ea6b194 642 responseLength = 3;
dewantkatare 0:35581ea6b194 643 }
dewantkatare 0:35581ea6b194 644 else
dewantkatare 0:35581ea6b194 645 { // This is an ANTICOLLISION.
dewantkatare 0:35581ea6b194 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
dewantkatare 0:35581ea6b194 647 txLastBits = currentLevelKnownBits % 8;
dewantkatare 0:35581ea6b194 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
dewantkatare 0:35581ea6b194 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
dewantkatare 0:35581ea6b194 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
dewantkatare 0:35581ea6b194 651 bufferUsed = index + (txLastBits ? 1 : 0);
dewantkatare 0:35581ea6b194 652
dewantkatare 0:35581ea6b194 653 // Store response in the unused part of buffer
dewantkatare 0:35581ea6b194 654 responseBuffer = &buffer[index];
dewantkatare 0:35581ea6b194 655 responseLength = sizeof(buffer) - index;
dewantkatare 0:35581ea6b194 656 }
dewantkatare 0:35581ea6b194 657
dewantkatare 0:35581ea6b194 658 // Set bit adjustments
dewantkatare 0:35581ea6b194 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
dewantkatare 0:35581ea6b194 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
dewantkatare 0:35581ea6b194 661
dewantkatare 0:35581ea6b194 662 // Transmit the buffer and receive the response.
dewantkatare 0:35581ea6b194 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
dewantkatare 0:35581ea6b194 664 if (result == STATUS_COLLISION)
dewantkatare 0:35581ea6b194 665 { // More than one PICC in the field => collision.
dewantkatare 0:35581ea6b194 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
dewantkatare 0:35581ea6b194 667 if (result & 0x20)
dewantkatare 0:35581ea6b194 668 { // CollPosNotValid
dewantkatare 0:35581ea6b194 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
dewantkatare 0:35581ea6b194 670 }
dewantkatare 0:35581ea6b194 671
dewantkatare 0:35581ea6b194 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
dewantkatare 0:35581ea6b194 673 if (collisionPos == 0)
dewantkatare 0:35581ea6b194 674 {
dewantkatare 0:35581ea6b194 675 collisionPos = 32;
dewantkatare 0:35581ea6b194 676 }
dewantkatare 0:35581ea6b194 677
dewantkatare 0:35581ea6b194 678 if (collisionPos <= currentLevelKnownBits)
dewantkatare 0:35581ea6b194 679 { // No progress - should not happen
dewantkatare 0:35581ea6b194 680 return STATUS_INTERNAL_ERROR;
dewantkatare 0:35581ea6b194 681 }
dewantkatare 0:35581ea6b194 682
dewantkatare 0:35581ea6b194 683 // Choose the PICC with the bit set.
dewantkatare 0:35581ea6b194 684 currentLevelKnownBits = collisionPos;
dewantkatare 0:35581ea6b194 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
dewantkatare 0:35581ea6b194 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
dewantkatare 0:35581ea6b194 687 buffer[index] |= (1 << count);
dewantkatare 0:35581ea6b194 688 }
dewantkatare 0:35581ea6b194 689 else if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 690 {
dewantkatare 0:35581ea6b194 691 return result;
dewantkatare 0:35581ea6b194 692 }
dewantkatare 0:35581ea6b194 693 else
dewantkatare 0:35581ea6b194 694 { // STATUS_OK
dewantkatare 0:35581ea6b194 695 if (currentLevelKnownBits >= 32)
dewantkatare 0:35581ea6b194 696 { // This was a SELECT.
dewantkatare 0:35581ea6b194 697 selectDone = true; // No more anticollision
dewantkatare 0:35581ea6b194 698 // We continue below outside the while.
dewantkatare 0:35581ea6b194 699 }
dewantkatare 0:35581ea6b194 700 else
dewantkatare 0:35581ea6b194 701 { // This was an ANTICOLLISION.
dewantkatare 0:35581ea6b194 702 // We now have all 32 bits of the UID in this Cascade Level
dewantkatare 0:35581ea6b194 703 currentLevelKnownBits = 32;
dewantkatare 0:35581ea6b194 704 // Run loop again to do the SELECT.
dewantkatare 0:35581ea6b194 705 }
dewantkatare 0:35581ea6b194 706 }
dewantkatare 0:35581ea6b194 707 } // End of while ( ! selectDone)
dewantkatare 0:35581ea6b194 708
dewantkatare 0:35581ea6b194 709 // We do not check the CBB - it was constructed by us above.
dewantkatare 0:35581ea6b194 710
dewantkatare 0:35581ea6b194 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
dewantkatare 0:35581ea6b194 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
dewantkatare 0:35581ea6b194 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
dewantkatare 0:35581ea6b194 714 for (count = 0; count < bytesToCopy; count++)
dewantkatare 0:35581ea6b194 715 {
dewantkatare 0:35581ea6b194 716 uid->uidByte[uidIndex + count] = buffer[index++];
dewantkatare 0:35581ea6b194 717 }
dewantkatare 0:35581ea6b194 718
dewantkatare 0:35581ea6b194 719 // Check response SAK (Select Acknowledge)
dewantkatare 0:35581ea6b194 720 if (responseLength != 3 || txLastBits != 0)
dewantkatare 0:35581ea6b194 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
dewantkatare 0:35581ea6b194 722 return STATUS_ERROR;
dewantkatare 0:35581ea6b194 723 }
dewantkatare 0:35581ea6b194 724
dewantkatare 0:35581ea6b194 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
dewantkatare 0:35581ea6b194 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
dewantkatare 0:35581ea6b194 727 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 728 {
dewantkatare 0:35581ea6b194 729 return result;
dewantkatare 0:35581ea6b194 730 }
dewantkatare 0:35581ea6b194 731
dewantkatare 0:35581ea6b194 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
dewantkatare 0:35581ea6b194 733 {
dewantkatare 0:35581ea6b194 734 return STATUS_CRC_WRONG;
dewantkatare 0:35581ea6b194 735 }
dewantkatare 0:35581ea6b194 736
dewantkatare 0:35581ea6b194 737 if (responseBuffer[0] & 0x04)
dewantkatare 0:35581ea6b194 738 { // Cascade bit set - UID not complete yes
dewantkatare 0:35581ea6b194 739 cascadeLevel++;
dewantkatare 0:35581ea6b194 740 }
dewantkatare 0:35581ea6b194 741 else
dewantkatare 0:35581ea6b194 742 {
dewantkatare 0:35581ea6b194 743 uidComplete = true;
dewantkatare 0:35581ea6b194 744 uid->sak = responseBuffer[0];
dewantkatare 0:35581ea6b194 745 }
dewantkatare 0:35581ea6b194 746 } // End of while ( ! uidComplete)
dewantkatare 0:35581ea6b194 747
dewantkatare 0:35581ea6b194 748 // Set correct uid->size
dewantkatare 0:35581ea6b194 749 uid->size = 3 * cascadeLevel + 1;
dewantkatare 0:35581ea6b194 750
dewantkatare 0:35581ea6b194 751 return STATUS_OK;
dewantkatare 0:35581ea6b194 752 } // End PICC_Select()
dewantkatare 0:35581ea6b194 753
dewantkatare 0:35581ea6b194 754 /*
dewantkatare 0:35581ea6b194 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
dewantkatare 0:35581ea6b194 756 */
dewantkatare 0:35581ea6b194 757 uint8_t MFRC522::PICC_HaltA()
dewantkatare 0:35581ea6b194 758 {
dewantkatare 0:35581ea6b194 759 uint8_t result;
dewantkatare 0:35581ea6b194 760 uint8_t buffer[4];
dewantkatare 0:35581ea6b194 761
dewantkatare 0:35581ea6b194 762 // Build command buffer
dewantkatare 0:35581ea6b194 763 buffer[0] = PICC_CMD_HLTA;
dewantkatare 0:35581ea6b194 764 buffer[1] = 0;
dewantkatare 0:35581ea6b194 765
dewantkatare 0:35581ea6b194 766 // Calculate CRC_A
dewantkatare 0:35581ea6b194 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
dewantkatare 0:35581ea6b194 768 if (result == STATUS_OK)
dewantkatare 0:35581ea6b194 769 {
dewantkatare 0:35581ea6b194 770 // Send the command.
dewantkatare 0:35581ea6b194 771 // The standard says:
dewantkatare 0:35581ea6b194 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
dewantkatare 0:35581ea6b194 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
dewantkatare 0:35581ea6b194 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
dewantkatare 0:35581ea6b194 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
dewantkatare 0:35581ea6b194 776 if (result == STATUS_TIMEOUT)
dewantkatare 0:35581ea6b194 777 {
dewantkatare 0:35581ea6b194 778 result = STATUS_OK;
dewantkatare 0:35581ea6b194 779 }
dewantkatare 0:35581ea6b194 780 else if (result == STATUS_OK)
dewantkatare 0:35581ea6b194 781 { // That is ironically NOT ok in this case ;-)
dewantkatare 0:35581ea6b194 782 result = STATUS_ERROR;
dewantkatare 0:35581ea6b194 783 }
dewantkatare 0:35581ea6b194 784 }
dewantkatare 0:35581ea6b194 785
dewantkatare 0:35581ea6b194 786 return result;
dewantkatare 0:35581ea6b194 787 } // End PICC_HaltA()
dewantkatare 0:35581ea6b194 788
dewantkatare 0:35581ea6b194 789
dewantkatare 0:35581ea6b194 790 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 791 // Functions for communicating with MIFARE PICCs
dewantkatare 0:35581ea6b194 792 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 793
dewantkatare 0:35581ea6b194 794 /*
dewantkatare 0:35581ea6b194 795 * Executes the MFRC522 MFAuthent command.
dewantkatare 0:35581ea6b194 796 */
dewantkatare 0:35581ea6b194 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
dewantkatare 0:35581ea6b194 798 {
dewantkatare 0:35581ea6b194 799 uint8_t i, waitIRq = 0x10; // IdleIRq
dewantkatare 0:35581ea6b194 800
dewantkatare 0:35581ea6b194 801 // Build command buffer
dewantkatare 0:35581ea6b194 802 uint8_t sendData[12];
dewantkatare 0:35581ea6b194 803 sendData[0] = command;
dewantkatare 0:35581ea6b194 804 sendData[1] = blockAddr;
dewantkatare 0:35581ea6b194 805
dewantkatare 0:35581ea6b194 806 for (i = 0; i < MF_KEY_SIZE; i++)
dewantkatare 0:35581ea6b194 807 { // 6 key bytes
dewantkatare 0:35581ea6b194 808 sendData[2+i] = key->keyByte[i];
dewantkatare 0:35581ea6b194 809 }
dewantkatare 0:35581ea6b194 810
dewantkatare 0:35581ea6b194 811 for (i = 0; i < 4; i++)
dewantkatare 0:35581ea6b194 812 { // The first 4 bytes of the UID
dewantkatare 0:35581ea6b194 813 sendData[8+i] = uid->uidByte[i];
dewantkatare 0:35581ea6b194 814 }
dewantkatare 0:35581ea6b194 815
dewantkatare 0:35581ea6b194 816 // Start the authentication.
dewantkatare 0:35581ea6b194 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
dewantkatare 0:35581ea6b194 818 } // End PCD_Authenticate()
dewantkatare 0:35581ea6b194 819
dewantkatare 0:35581ea6b194 820 /*
dewantkatare 0:35581ea6b194 821 * Used to exit the PCD from its authenticated state.
dewantkatare 0:35581ea6b194 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
dewantkatare 0:35581ea6b194 823 */
dewantkatare 0:35581ea6b194 824 void MFRC522::PCD_StopCrypto1()
dewantkatare 0:35581ea6b194 825 {
dewantkatare 0:35581ea6b194 826 // Clear MFCrypto1On bit
dewantkatare 0:35581ea6b194 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
dewantkatare 0:35581ea6b194 828 } // End PCD_StopCrypto1()
dewantkatare 0:35581ea6b194 829
dewantkatare 0:35581ea6b194 830 /*
dewantkatare 0:35581ea6b194 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
dewantkatare 0:35581ea6b194 832 */
dewantkatare 0:35581ea6b194 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
dewantkatare 0:35581ea6b194 834 {
dewantkatare 0:35581ea6b194 835 uint8_t result = STATUS_NO_ROOM;
dewantkatare 0:35581ea6b194 836
dewantkatare 0:35581ea6b194 837 // Sanity check
dewantkatare 0:35581ea6b194 838 if ((buffer == NULL) || (*bufferSize < 18))
dewantkatare 0:35581ea6b194 839 {
dewantkatare 0:35581ea6b194 840 return result;
dewantkatare 0:35581ea6b194 841 }
dewantkatare 0:35581ea6b194 842
dewantkatare 0:35581ea6b194 843 // Build command buffer
dewantkatare 0:35581ea6b194 844 buffer[0] = PICC_CMD_MF_READ;
dewantkatare 0:35581ea6b194 845 buffer[1] = blockAddr;
dewantkatare 0:35581ea6b194 846
dewantkatare 0:35581ea6b194 847 // Calculate CRC_A
dewantkatare 0:35581ea6b194 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
dewantkatare 0:35581ea6b194 849 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 850 {
dewantkatare 0:35581ea6b194 851 return result;
dewantkatare 0:35581ea6b194 852 }
dewantkatare 0:35581ea6b194 853
dewantkatare 0:35581ea6b194 854 // Transmit the buffer and receive the response, validate CRC_A.
dewantkatare 0:35581ea6b194 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
dewantkatare 0:35581ea6b194 856 } // End MIFARE_Read()
dewantkatare 0:35581ea6b194 857
dewantkatare 0:35581ea6b194 858 /*
dewantkatare 0:35581ea6b194 859 * Writes 16 bytes to the active PICC.
dewantkatare 0:35581ea6b194 860 */
dewantkatare 0:35581ea6b194 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
dewantkatare 0:35581ea6b194 862 {
dewantkatare 0:35581ea6b194 863 uint8_t result;
dewantkatare 0:35581ea6b194 864
dewantkatare 0:35581ea6b194 865 // Sanity check
dewantkatare 0:35581ea6b194 866 if (buffer == NULL || bufferSize < 16)
dewantkatare 0:35581ea6b194 867 {
dewantkatare 0:35581ea6b194 868 return STATUS_INVALID;
dewantkatare 0:35581ea6b194 869 }
dewantkatare 0:35581ea6b194 870
dewantkatare 0:35581ea6b194 871 // Mifare Classic protocol requires two communications to perform a write.
dewantkatare 0:35581ea6b194 872 // Step 1: Tell the PICC we want to write to block blockAddr.
dewantkatare 0:35581ea6b194 873 uint8_t cmdBuffer[2];
dewantkatare 0:35581ea6b194 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
dewantkatare 0:35581ea6b194 875 cmdBuffer[1] = blockAddr;
dewantkatare 0:35581ea6b194 876 // Adds CRC_A and checks that the response is MF_ACK.
dewantkatare 0:35581ea6b194 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
dewantkatare 0:35581ea6b194 878 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 879 {
dewantkatare 0:35581ea6b194 880 return result;
dewantkatare 0:35581ea6b194 881 }
dewantkatare 0:35581ea6b194 882
dewantkatare 0:35581ea6b194 883 // Step 2: Transfer the data
dewantkatare 0:35581ea6b194 884 // Adds CRC_A and checks that the response is MF_ACK.
dewantkatare 0:35581ea6b194 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
dewantkatare 0:35581ea6b194 886 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 887 {
dewantkatare 0:35581ea6b194 888 return result;
dewantkatare 0:35581ea6b194 889 }
dewantkatare 0:35581ea6b194 890
dewantkatare 0:35581ea6b194 891 return STATUS_OK;
dewantkatare 0:35581ea6b194 892 } // End MIFARE_Write()
dewantkatare 0:35581ea6b194 893
dewantkatare 0:35581ea6b194 894 /*
dewantkatare 0:35581ea6b194 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
dewantkatare 0:35581ea6b194 896 */
dewantkatare 0:35581ea6b194 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
dewantkatare 0:35581ea6b194 898 {
dewantkatare 0:35581ea6b194 899 uint8_t result;
dewantkatare 0:35581ea6b194 900
dewantkatare 0:35581ea6b194 901 // Sanity check
dewantkatare 0:35581ea6b194 902 if (buffer == NULL || bufferSize < 4)
dewantkatare 0:35581ea6b194 903 {
dewantkatare 0:35581ea6b194 904 return STATUS_INVALID;
dewantkatare 0:35581ea6b194 905 }
dewantkatare 0:35581ea6b194 906
dewantkatare 0:35581ea6b194 907 // Build commmand buffer
dewantkatare 0:35581ea6b194 908 uint8_t cmdBuffer[6];
dewantkatare 0:35581ea6b194 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
dewantkatare 0:35581ea6b194 910 cmdBuffer[1] = page;
dewantkatare 0:35581ea6b194 911 memcpy(&cmdBuffer[2], buffer, 4);
dewantkatare 0:35581ea6b194 912
dewantkatare 0:35581ea6b194 913 // Perform the write
dewantkatare 0:35581ea6b194 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
dewantkatare 0:35581ea6b194 915 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 916 {
dewantkatare 0:35581ea6b194 917 return result;
dewantkatare 0:35581ea6b194 918 }
dewantkatare 0:35581ea6b194 919
dewantkatare 0:35581ea6b194 920 return STATUS_OK;
dewantkatare 0:35581ea6b194 921 } // End MIFARE_Ultralight_Write()
dewantkatare 0:35581ea6b194 922
dewantkatare 0:35581ea6b194 923 /*
dewantkatare 0:35581ea6b194 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
dewantkatare 0:35581ea6b194 925 */
dewantkatare 0:35581ea6b194 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
dewantkatare 0:35581ea6b194 927 {
dewantkatare 0:35581ea6b194 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
dewantkatare 0:35581ea6b194 929 } // End MIFARE_Decrement()
dewantkatare 0:35581ea6b194 930
dewantkatare 0:35581ea6b194 931 /*
dewantkatare 0:35581ea6b194 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
dewantkatare 0:35581ea6b194 933 */
dewantkatare 0:35581ea6b194 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
dewantkatare 0:35581ea6b194 935 {
dewantkatare 0:35581ea6b194 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
dewantkatare 0:35581ea6b194 937 } // End MIFARE_Increment()
dewantkatare 0:35581ea6b194 938
dewantkatare 0:35581ea6b194 939 /**
dewantkatare 0:35581ea6b194 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
dewantkatare 0:35581ea6b194 941 */
dewantkatare 0:35581ea6b194 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
dewantkatare 0:35581ea6b194 943 {
dewantkatare 0:35581ea6b194 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
dewantkatare 0:35581ea6b194 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
dewantkatare 0:35581ea6b194 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
dewantkatare 0:35581ea6b194 947 } // End MIFARE_Restore()
dewantkatare 0:35581ea6b194 948
dewantkatare 0:35581ea6b194 949 /*
dewantkatare 0:35581ea6b194 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
dewantkatare 0:35581ea6b194 951 */
dewantkatare 0:35581ea6b194 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
dewantkatare 0:35581ea6b194 953 {
dewantkatare 0:35581ea6b194 954 uint8_t result;
dewantkatare 0:35581ea6b194 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
dewantkatare 0:35581ea6b194 956
dewantkatare 0:35581ea6b194 957 // Step 1: Tell the PICC the command and block address
dewantkatare 0:35581ea6b194 958 cmdBuffer[0] = command;
dewantkatare 0:35581ea6b194 959 cmdBuffer[1] = blockAddr;
dewantkatare 0:35581ea6b194 960
dewantkatare 0:35581ea6b194 961 // Adds CRC_A and checks that the response is MF_ACK.
dewantkatare 0:35581ea6b194 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
dewantkatare 0:35581ea6b194 963 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 964 {
dewantkatare 0:35581ea6b194 965 return result;
dewantkatare 0:35581ea6b194 966 }
dewantkatare 0:35581ea6b194 967
dewantkatare 0:35581ea6b194 968 // Step 2: Transfer the data
dewantkatare 0:35581ea6b194 969 // Adds CRC_A and accept timeout as success.
dewantkatare 0:35581ea6b194 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
dewantkatare 0:35581ea6b194 971 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 972 {
dewantkatare 0:35581ea6b194 973 return result;
dewantkatare 0:35581ea6b194 974 }
dewantkatare 0:35581ea6b194 975
dewantkatare 0:35581ea6b194 976 return STATUS_OK;
dewantkatare 0:35581ea6b194 977 } // End MIFARE_TwoStepHelper()
dewantkatare 0:35581ea6b194 978
dewantkatare 0:35581ea6b194 979 /*
dewantkatare 0:35581ea6b194 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
dewantkatare 0:35581ea6b194 981 */
dewantkatare 0:35581ea6b194 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
dewantkatare 0:35581ea6b194 983 {
dewantkatare 0:35581ea6b194 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
dewantkatare 0:35581ea6b194 985
dewantkatare 0:35581ea6b194 986 // Tell the PICC we want to transfer the result into block blockAddr.
dewantkatare 0:35581ea6b194 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
dewantkatare 0:35581ea6b194 988 cmdBuffer[1] = blockAddr;
dewantkatare 0:35581ea6b194 989
dewantkatare 0:35581ea6b194 990 // Adds CRC_A and checks that the response is MF_ACK.
dewantkatare 0:35581ea6b194 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
dewantkatare 0:35581ea6b194 992 } // End MIFARE_Transfer()
dewantkatare 0:35581ea6b194 993
dewantkatare 0:35581ea6b194 994
dewantkatare 0:35581ea6b194 995 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 996 // Support functions
dewantkatare 0:35581ea6b194 997 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 998
dewantkatare 0:35581ea6b194 999 /*
dewantkatare 0:35581ea6b194 1000 * Wrapper for MIFARE protocol communication.
dewantkatare 0:35581ea6b194 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
dewantkatare 0:35581ea6b194 1002 */
dewantkatare 0:35581ea6b194 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
dewantkatare 0:35581ea6b194 1004 {
dewantkatare 0:35581ea6b194 1005 uint8_t result;
dewantkatare 0:35581ea6b194 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
dewantkatare 0:35581ea6b194 1007
dewantkatare 0:35581ea6b194 1008 // Sanity check
dewantkatare 0:35581ea6b194 1009 if (sendData == NULL || sendLen > 16)
dewantkatare 0:35581ea6b194 1010 {
dewantkatare 0:35581ea6b194 1011 return STATUS_INVALID;
dewantkatare 0:35581ea6b194 1012 }
dewantkatare 0:35581ea6b194 1013
dewantkatare 0:35581ea6b194 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
dewantkatare 0:35581ea6b194 1015 memcpy(cmdBuffer, sendData, sendLen);
dewantkatare 0:35581ea6b194 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
dewantkatare 0:35581ea6b194 1017 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 1018 {
dewantkatare 0:35581ea6b194 1019 return result;
dewantkatare 0:35581ea6b194 1020 }
dewantkatare 0:35581ea6b194 1021
dewantkatare 0:35581ea6b194 1022 sendLen += 2;
dewantkatare 0:35581ea6b194 1023
dewantkatare 0:35581ea6b194 1024 // Transceive the data, store the reply in cmdBuffer[]
dewantkatare 0:35581ea6b194 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
dewantkatare 0:35581ea6b194 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
dewantkatare 0:35581ea6b194 1027 uint8_t validBits = 0;
dewantkatare 0:35581ea6b194 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
dewantkatare 0:35581ea6b194 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
dewantkatare 0:35581ea6b194 1030 {
dewantkatare 0:35581ea6b194 1031 return STATUS_OK;
dewantkatare 0:35581ea6b194 1032 }
dewantkatare 0:35581ea6b194 1033
dewantkatare 0:35581ea6b194 1034 if (result != STATUS_OK)
dewantkatare 0:35581ea6b194 1035 {
dewantkatare 0:35581ea6b194 1036 return result;
dewantkatare 0:35581ea6b194 1037 }
dewantkatare 0:35581ea6b194 1038
dewantkatare 0:35581ea6b194 1039 // The PICC must reply with a 4 bit ACK
dewantkatare 0:35581ea6b194 1040 if (cmdBufferSize != 1 || validBits != 4)
dewantkatare 0:35581ea6b194 1041 {
dewantkatare 0:35581ea6b194 1042 return STATUS_ERROR;
dewantkatare 0:35581ea6b194 1043 }
dewantkatare 0:35581ea6b194 1044
dewantkatare 0:35581ea6b194 1045 if (cmdBuffer[0] != MF_ACK)
dewantkatare 0:35581ea6b194 1046 {
dewantkatare 0:35581ea6b194 1047 return STATUS_MIFARE_NACK;
dewantkatare 0:35581ea6b194 1048 }
dewantkatare 0:35581ea6b194 1049
dewantkatare 0:35581ea6b194 1050 return STATUS_OK;
dewantkatare 0:35581ea6b194 1051 } // End PCD_MIFARE_Transceive()
dewantkatare 0:35581ea6b194 1052
dewantkatare 0:35581ea6b194 1053
dewantkatare 0:35581ea6b194 1054 /*
dewantkatare 0:35581ea6b194 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
dewantkatare 0:35581ea6b194 1056 */
dewantkatare 0:35581ea6b194 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
dewantkatare 0:35581ea6b194 1058 {
dewantkatare 0:35581ea6b194 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
dewantkatare 0:35581ea6b194 1060
dewantkatare 0:35581ea6b194 1061 if (sak & 0x04)
dewantkatare 0:35581ea6b194 1062 { // UID not complete
dewantkatare 0:35581ea6b194 1063 retType = PICC_TYPE_NOT_COMPLETE;
dewantkatare 0:35581ea6b194 1064 }
dewantkatare 0:35581ea6b194 1065 else
dewantkatare 0:35581ea6b194 1066 {
dewantkatare 0:35581ea6b194 1067 switch (sak)
dewantkatare 0:35581ea6b194 1068 {
dewantkatare 0:35581ea6b194 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
dewantkatare 0:35581ea6b194 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
dewantkatare 0:35581ea6b194 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
dewantkatare 0:35581ea6b194 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
dewantkatare 0:35581ea6b194 1073 case 0x10:
dewantkatare 0:35581ea6b194 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
dewantkatare 0:35581ea6b194 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
dewantkatare 0:35581ea6b194 1076 default:
dewantkatare 0:35581ea6b194 1077 if (sak & 0x20)
dewantkatare 0:35581ea6b194 1078 {
dewantkatare 0:35581ea6b194 1079 retType = PICC_TYPE_ISO_14443_4;
dewantkatare 0:35581ea6b194 1080 }
dewantkatare 0:35581ea6b194 1081 else if (sak & 0x40)
dewantkatare 0:35581ea6b194 1082 {
dewantkatare 0:35581ea6b194 1083 retType = PICC_TYPE_ISO_18092;
dewantkatare 0:35581ea6b194 1084 }
dewantkatare 0:35581ea6b194 1085 break;
dewantkatare 0:35581ea6b194 1086 }
dewantkatare 0:35581ea6b194 1087 }
dewantkatare 0:35581ea6b194 1088
dewantkatare 0:35581ea6b194 1089 return (retType);
dewantkatare 0:35581ea6b194 1090 } // End PICC_GetType()
dewantkatare 0:35581ea6b194 1091
dewantkatare 0:35581ea6b194 1092 /*
dewantkatare 0:35581ea6b194 1093 * Returns a string pointer to the PICC type name.
dewantkatare 0:35581ea6b194 1094 */
dewantkatare 0:35581ea6b194 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
dewantkatare 0:35581ea6b194 1096 {
dewantkatare 0:35581ea6b194 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
dewantkatare 0:35581ea6b194 1098 {
dewantkatare 0:35581ea6b194 1099 piccType = MFRC522_MaxPICCs - 1;
dewantkatare 0:35581ea6b194 1100 }
dewantkatare 0:35581ea6b194 1101
dewantkatare 0:35581ea6b194 1102 return((char *) _TypeNamePICC[piccType]);
dewantkatare 0:35581ea6b194 1103 } // End PICC_GetTypeName()
dewantkatare 0:35581ea6b194 1104
dewantkatare 0:35581ea6b194 1105 /*
dewantkatare 0:35581ea6b194 1106 * Returns a string pointer to a status code name.
dewantkatare 0:35581ea6b194 1107 */
dewantkatare 0:35581ea6b194 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
dewantkatare 0:35581ea6b194 1109 {
dewantkatare 0:35581ea6b194 1110 return((char *) _ErrorMessage[code]);
dewantkatare 0:35581ea6b194 1111 } // End GetStatusCodeName()
dewantkatare 0:35581ea6b194 1112
dewantkatare 0:35581ea6b194 1113 /*
dewantkatare 0:35581ea6b194 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
dewantkatare 0:35581ea6b194 1115 */
dewantkatare 0:35581ea6b194 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
dewantkatare 0:35581ea6b194 1117 uint8_t g0,
dewantkatare 0:35581ea6b194 1118 uint8_t g1,
dewantkatare 0:35581ea6b194 1119 uint8_t g2,
dewantkatare 0:35581ea6b194 1120 uint8_t g3)
dewantkatare 0:35581ea6b194 1121 {
dewantkatare 0:35581ea6b194 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
dewantkatare 0:35581ea6b194 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
dewantkatare 0:35581ea6b194 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
dewantkatare 0:35581ea6b194 1125
dewantkatare 0:35581ea6b194 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
dewantkatare 0:35581ea6b194 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
dewantkatare 0:35581ea6b194 1128 accessBitBuffer[2] = c3 << 4 | c2;
dewantkatare 0:35581ea6b194 1129 } // End MIFARE_SetAccessBits()
dewantkatare 0:35581ea6b194 1130
dewantkatare 0:35581ea6b194 1131 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 1132 // Convenience functions - does not add extra functionality
dewantkatare 0:35581ea6b194 1133 /////////////////////////////////////////////////////////////////////////////////////
dewantkatare 0:35581ea6b194 1134
dewantkatare 0:35581ea6b194 1135 /*
dewantkatare 0:35581ea6b194 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
dewantkatare 0:35581ea6b194 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
dewantkatare 0:35581ea6b194 1138 */
dewantkatare 0:35581ea6b194 1139 bool MFRC522::PICC_IsNewCardPresent(void)
dewantkatare 0:35581ea6b194 1140 {
dewantkatare 0:35581ea6b194 1141 uint8_t bufferATQA[2];
dewantkatare 0:35581ea6b194 1142 uint8_t bufferSize = sizeof(bufferATQA);
dewantkatare 0:35581ea6b194 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
dewantkatare 0:35581ea6b194 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
dewantkatare 0:35581ea6b194 1145 } // End PICC_IsNewCardPresent()
dewantkatare 0:35581ea6b194 1146
dewantkatare 0:35581ea6b194 1147 /*
dewantkatare 0:35581ea6b194 1148 * Simple wrapper around PICC_Select.
dewantkatare 0:35581ea6b194 1149 */
dewantkatare 0:35581ea6b194 1150 bool MFRC522::PICC_ReadCardSerial(void)
dewantkatare 0:35581ea6b194 1151 {
dewantkatare 0:35581ea6b194 1152 uint8_t result = PICC_Select(&uid);
dewantkatare 0:35581ea6b194 1153 return (result == STATUS_OK);
dewantkatare 0:35581ea6b194 1154 } // End PICC_ReadCardSerial()