MCUFRIEND_kbv library for MBED depends on ADA_GFX_kbv library
Dependents: TFT_Touch_botao_v1 TFT_Touch_exemplo5_git_touch TESTE_1 TFT_Touch_exemplo6_git_touch_button_3_ ... more
utility/pin_shield_8.h@1:06c4b34a5a61, 2021-04-28 (annotated)
- Committer:
- davidprentice
- Date:
- Wed Apr 28 11:24:54 2021 +0000
- Revision:
- 1:06c4b34a5a61
- Parent:
- 0:6f633078852b
recognise TARGET_LPC1768 in pin_1.h, pin_8.h
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
davidprentice | 0:6f633078852b | 1 | #ifndef PIN_SHIELD_8_H_ |
davidprentice | 0:6f633078852b | 2 | #define PIN_SHIELD_8_H_ |
davidprentice | 0:6f633078852b | 3 | |
davidprentice | 0:6f633078852b | 4 | // just provide macros for the 8-bit data bus |
davidprentice | 0:6f633078852b | 5 | // i.e. write_8(), read_8(), setWriteDir(), setReadDir() |
davidprentice | 0:6f633078852b | 6 | |
davidprentice | 0:6f633078852b | 7 | |
davidprentice | 0:6f633078852b | 8 | #define LPC810 810 |
davidprentice | 0:6f633078852b | 9 | #define LPC812 812 |
davidprentice | 0:6f633078852b | 10 | #define LPC1343 1343 |
davidprentice | 0:6f633078852b | 11 | #define LPC1768 1768 |
davidprentice | 0:6f633078852b | 12 | #define LPC2103 2103 |
davidprentice | 0:6f633078852b | 13 | #define LPC2148 2148 |
davidprentice | 0:6f633078852b | 14 | |
davidprentice | 0:6f633078852b | 15 | #define ISTARGET_NUCLEO64 (0 \ |
davidprentice | 0:6f633078852b | 16 | || defined(TARGET_NUCLEO_F072RB) \ |
davidprentice | 0:6f633078852b | 17 | || defined(TARGET_NUCLEO_F103RB) \ |
davidprentice | 0:6f633078852b | 18 | || defined(TARGET_NUCLEO_F401RE) \ |
davidprentice | 0:6f633078852b | 19 | || defined(TARGET_NUCLEO_F411RE) \ |
davidprentice | 0:6f633078852b | 20 | || defined(TARGET_NUCLEO_F446RE) \ |
davidprentice | 0:6f633078852b | 21 | || defined(TARGET_NUCLEO_L433RC_P) \ |
davidprentice | 0:6f633078852b | 22 | || defined(TARGET_NUCLEO_L476RG) \ |
davidprentice | 0:6f633078852b | 23 | ) |
davidprentice | 0:6f633078852b | 24 | |
davidprentice | 0:6f633078852b | 25 | #define ISTARGET_NUCLEO144 (0 \ |
davidprentice | 0:6f633078852b | 26 | || defined(TARGET_NUCLEO_F767ZI) \ |
davidprentice | 0:6f633078852b | 27 | ) |
davidprentice | 0:6f633078852b | 28 | |
davidprentice | 0:6f633078852b | 29 | //#warning Using pin_SHIELD_8.h |
davidprentice | 0:6f633078852b | 30 | |
davidprentice | 0:6f633078852b | 31 | #if 0 |
davidprentice | 0:6f633078852b | 32 | |
davidprentice | 0:6f633078852b | 33 | #elif defined(MY_BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER |
davidprentice | 0:6f633078852b | 34 | #warning Uno Shield on MY_BLUEPILL_ADAPTER |
davidprentice | 0:6f633078852b | 35 | |
davidprentice | 0:6f633078852b | 36 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 37 | #define AMASK 0x060F |
davidprentice | 0:6f633078852b | 38 | #define BMASK 0x00C0 |
davidprentice | 0:6f633078852b | 39 | #define write_8(d) { GPIOA->BSRR = AMASK << 16; GPIOB->BSRR = BMASK << 16; \ |
davidprentice | 0:6f633078852b | 40 | GPIOA->BSRR = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \ |
davidprentice | 0:6f633078852b | 41 | GPIOB->BSRR = (((d) & 0x0C) << 4); \ |
davidprentice | 0:6f633078852b | 42 | } |
davidprentice | 0:6f633078852b | 43 | #define read_8() (((GPIOA->IDR & (3<<9)) >> 9) | ((GPIOA->IDR & (0x0F)) << 4) | ((GPIOB->IDR & (3<<6)) >> 4)) |
davidprentice | 0:6f633078852b | 44 | |
davidprentice | 0:6f633078852b | 45 | #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } |
davidprentice | 0:6f633078852b | 46 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
davidprentice | 0:6f633078852b | 47 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
davidprentice | 0:6f633078852b | 48 | // PA10,PA9 PA3-PA0 PB7,PB6 |
davidprentice | 0:6f633078852b | 49 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); } |
davidprentice | 0:6f633078852b | 50 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); } |
davidprentice | 0:6f633078852b | 51 | |
davidprentice | 0:6f633078852b | 52 | #elif defined(BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER |
davidprentice | 0:6f633078852b | 53 | #warning Uno Shield on BLUEPILL_ADAPTER |
davidprentice | 0:6f633078852b | 54 | |
davidprentice | 0:6f633078852b | 55 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 56 | #define write_8(d) { GPIOA->BSRR = 0x00FF << 16; GPIOA->BSRR = (d) & 0xFF; } |
davidprentice | 0:6f633078852b | 57 | #define read_8() (GPIOA->IDR & 0xFF) |
davidprentice | 0:6f633078852b | 58 | |
davidprentice | 0:6f633078852b | 59 | #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } |
davidprentice | 0:6f633078852b | 60 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
davidprentice | 0:6f633078852b | 61 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
davidprentice | 0:6f633078852b | 62 | // PA7 ..PA0 |
davidprentice | 0:6f633078852b | 63 | #define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); } |
davidprentice | 0:6f633078852b | 64 | #define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); } |
davidprentice | 0:6f633078852b | 65 | |
davidprentice | 0:6f633078852b | 66 | #elif defined(ITEADMAPLE) // Uno Shield on MAPLE_REV3 board |
davidprentice | 0:6f633078852b | 67 | #warning Uno Shield on MAPLE_REV3 board |
davidprentice | 0:6f633078852b | 68 | |
davidprentice | 0:6f633078852b | 69 | #define REGS(x) x |
davidprentice | 0:6f633078852b | 70 | #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); } |
davidprentice | 0:6f633078852b | 71 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
davidprentice | 0:6f633078852b | 72 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
davidprentice | 0:6f633078852b | 73 | |
davidprentice | 0:6f633078852b | 74 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 75 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 76 | GPIOA->REGS(BSRR) = 0x0703 << 16; \ |
davidprentice | 0:6f633078852b | 77 | GPIOB->REGS(BSRR) = 0x00E0 << 16; \ |
davidprentice | 0:6f633078852b | 78 | GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \ |
davidprentice | 0:6f633078852b | 79 | | (((d) & (1<<2)) >> 2) \ |
davidprentice | 0:6f633078852b | 80 | | (((d) & (1<<3)) >> 2) \ |
davidprentice | 0:6f633078852b | 81 | | (((d) & (1<<6)) << 2) \ |
davidprentice | 0:6f633078852b | 82 | | (((d) & (1<<7)) << 2); \ |
davidprentice | 0:6f633078852b | 83 | GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \ |
davidprentice | 0:6f633078852b | 84 | | (((d) & (1<<4)) << 1) \ |
davidprentice | 0:6f633078852b | 85 | | (((d) & (1<<5)) << 1); \ |
davidprentice | 0:6f633078852b | 86 | } |
davidprentice | 0:6f633078852b | 87 | |
davidprentice | 0:6f633078852b | 88 | #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \ |
davidprentice | 0:6f633078852b | 89 | | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \ |
davidprentice | 0:6f633078852b | 90 | | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \ |
davidprentice | 0:6f633078852b | 91 | | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \ |
davidprentice | 0:6f633078852b | 92 | | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ |
davidprentice | 0:6f633078852b | 93 | | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \ |
davidprentice | 0:6f633078852b | 94 | | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \ |
davidprentice | 0:6f633078852b | 95 | | ((GPIOA->REGS(IDR) & (1<<9)) >> 2))) |
davidprentice | 0:6f633078852b | 96 | |
davidprentice | 0:6f633078852b | 97 | // PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5 |
davidprentice | 0:6f633078852b | 98 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); } |
davidprentice | 0:6f633078852b | 99 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); } |
davidprentice | 0:6f633078852b | 100 | |
davidprentice | 0:6f633078852b | 101 | #elif defined(NUCLEO144) || ISTARGET_NUCLEO144 |
davidprentice | 0:6f633078852b | 102 | #if __MBED__ |
davidprentice | 0:6f633078852b | 103 | #warning MBED knows everything |
davidprentice | 0:6f633078852b | 104 | #elif defined(STM32F767xx) |
davidprentice | 0:6f633078852b | 105 | #include <STM32F7XX.h> |
davidprentice | 0:6f633078852b | 106 | #endif |
davidprentice | 0:6f633078852b | 107 | |
davidprentice | 0:6f633078852b | 108 | #define REGS(x) x |
davidprentice | 0:6f633078852b | 109 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 110 | #define DMASK ((1<<15)) //#1 |
davidprentice | 0:6f633078852b | 111 | #define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6 |
davidprentice | 0:6f633078852b | 112 | #define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7 |
davidprentice | 0:6f633078852b | 113 | |
davidprentice | 0:6f633078852b | 114 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 115 | GPIOD->REGS(BSRR) = DMASK << 16; \ |
davidprentice | 0:6f633078852b | 116 | GPIOE->REGS(BSRR) = EMASK << 16; \ |
davidprentice | 0:6f633078852b | 117 | GPIOF->REGS(BSRR) = FMASK << 16; \ |
davidprentice | 0:6f633078852b | 118 | GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \ |
davidprentice | 0:6f633078852b | 119 | GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \ |
davidprentice | 0:6f633078852b | 120 | | (((d) & (1<<5)) << 6) \ |
davidprentice | 0:6f633078852b | 121 | | (((d) & (1<<6)) << 3); \ |
davidprentice | 0:6f633078852b | 122 | GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \ |
davidprentice | 0:6f633078852b | 123 | | (((d) & (1<<2)) << 13) \ |
davidprentice | 0:6f633078852b | 124 | | (((d) & (1<<4)) << 10) \ |
davidprentice | 0:6f633078852b | 125 | | (((d) & (1<<7)) << 6); \ |
davidprentice | 0:6f633078852b | 126 | } |
davidprentice | 0:6f633078852b | 127 | |
davidprentice | 0:6f633078852b | 128 | #define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \ |
davidprentice | 0:6f633078852b | 129 | | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \ |
davidprentice | 0:6f633078852b | 130 | | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \ |
davidprentice | 0:6f633078852b | 131 | | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \ |
davidprentice | 0:6f633078852b | 132 | | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \ |
davidprentice | 0:6f633078852b | 133 | | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \ |
davidprentice | 0:6f633078852b | 134 | | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \ |
davidprentice | 0:6f633078852b | 135 | | ((GPIOF->REGS(IDR) & (1<<13)) >> 6))) |
davidprentice | 0:6f633078852b | 136 | |
davidprentice | 0:6f633078852b | 137 | |
davidprentice | 0:6f633078852b | 138 | // PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12 |
davidprentice | 0:6f633078852b | 139 | #define setWriteDir() { setReadDir(); \ |
davidprentice | 0:6f633078852b | 140 | GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; } |
davidprentice | 0:6f633078852b | 141 | #define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; } |
davidprentice | 0:6f633078852b | 142 | |
davidprentice | 0:6f633078852b | 143 | |
davidprentice | 0:6f633078852b | 144 | #elif defined(NUCLEO) || ISTARGET_NUCLEO64 |
davidprentice | 0:6f633078852b | 145 | #if __MBED__ |
davidprentice | 0:6f633078852b | 146 | #warning MBED knows everything |
davidprentice | 0:6f633078852b | 147 | #elif defined(STM32F072xB) |
davidprentice | 0:6f633078852b | 148 | #include <STM32F0XX.h> |
davidprentice | 0:6f633078852b | 149 | #elif defined(STM32F103xB) |
davidprentice | 0:6f633078852b | 150 | #if defined(__CC_ARM) |
davidprentice | 0:6f633078852b | 151 | #include <STM32F10X.h> |
davidprentice | 0:6f633078852b | 152 | #else |
davidprentice | 0:6f633078852b | 153 | #include <STM32F1XX.h> |
davidprentice | 0:6f633078852b | 154 | #endif |
davidprentice | 0:6f633078852b | 155 | #elif defined(STM32L476xx) || defined(STM32L433xx) |
davidprentice | 0:6f633078852b | 156 | #include <STM32L4XX.h> |
davidprentice | 0:6f633078852b | 157 | #elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) |
davidprentice | 0:6f633078852b | 158 | #include <STM32F4XX.h> |
davidprentice | 0:6f633078852b | 159 | #endif |
davidprentice | 0:6f633078852b | 160 | // configure macros for the data pins. -00=10.06, -O1=7.85, -O1t=7.21, -O2=7.87, -O3=7.45, -O3t=7.03 |
davidprentice | 0:6f633078852b | 161 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 162 | GPIOA->BSRR = 0x0700 << 16; \ |
davidprentice | 0:6f633078852b | 163 | GPIOB->BSRR = 0x0438 << 16; \ |
davidprentice | 0:6f633078852b | 164 | GPIOC->BSRR = 0x0080 << 16; \ |
davidprentice | 0:6f633078852b | 165 | GPIOA->BSRR = (((d) & (1<<0)) << 9) \ |
davidprentice | 0:6f633078852b | 166 | | (((d) & (1<<2)) << 8) \ |
davidprentice | 0:6f633078852b | 167 | | (((d) & (1<<7)) << 1); \ |
davidprentice | 0:6f633078852b | 168 | GPIOB->BSRR = (((d) & (1<<3)) << 0) \ |
davidprentice | 0:6f633078852b | 169 | | (((d) & (1<<4)) << 1) \ |
davidprentice | 0:6f633078852b | 170 | | (((d) & (1<<5)) >> 1) \ |
davidprentice | 0:6f633078852b | 171 | | (((d) & (1<<6)) << 4); \ |
davidprentice | 0:6f633078852b | 172 | GPIOC->BSRR = (((d) & (1<<1)) << 6); \ |
davidprentice | 0:6f633078852b | 173 | } |
davidprentice | 0:6f633078852b | 174 | #define read_8() ( (((GPIOA->IDR & (1<<9)) >> 9) \ |
davidprentice | 0:6f633078852b | 175 | | ((GPIOC->IDR & (1<<7)) >> 6) \ |
davidprentice | 0:6f633078852b | 176 | | ((GPIOA->IDR & (1<<10)) >> 8) \ |
davidprentice | 0:6f633078852b | 177 | | ((GPIOB->IDR & (1<<3)) >> 0) \ |
davidprentice | 0:6f633078852b | 178 | | ((GPIOB->IDR & (1<<5)) >> 1) \ |
davidprentice | 0:6f633078852b | 179 | | ((GPIOB->IDR & (1<<4)) << 1) \ |
davidprentice | 0:6f633078852b | 180 | | ((GPIOB->IDR & (1<<10)) >> 4) \ |
davidprentice | 0:6f633078852b | 181 | | ((GPIOA->IDR & (1<<8)) >> 1))) |
davidprentice | 0:6f633078852b | 182 | // be wise to clear both MODER bits properly. |
davidprentice | 0:6f633078852b | 183 | #if defined(STM32F103xB) |
davidprentice | 0:6f633078852b | 184 | #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } |
davidprentice | 0:6f633078852b | 185 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
davidprentice | 0:6f633078852b | 186 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
davidprentice | 0:6f633078852b | 187 | // PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7 |
davidprentice | 0:6f633078852b | 188 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); } |
davidprentice | 0:6f633078852b | 189 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); } |
davidprentice | 0:6f633078852b | 190 | #else |
davidprentice | 0:6f633078852b | 191 | #define setWriteDir() { setReadDir(); \ |
davidprentice | 0:6f633078852b | 192 | GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; } |
davidprentice | 0:6f633078852b | 193 | #define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; } |
davidprentice | 0:6f633078852b | 194 | #endif |
davidprentice | 0:6f633078852b | 195 | |
davidprentice | 0:6f633078852b | 196 | |
davidprentice | 1:06c4b34a5a61 | 197 | #elif __TARGET_PROCESSOR == LPC1768 || defined(TARGET_LPC1768) |
davidprentice | 0:6f633078852b | 198 | #include <LPC17xx.h> |
davidprentice | 0:6f633078852b | 199 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 200 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 201 | LPC_GPIO0->FIOPIN = (LPC_GPIO0->FIOPIN & ~0x01878003) \ |
davidprentice | 0:6f633078852b | 202 | | (((d) & (1<<0)) << 1) \ |
davidprentice | 0:6f633078852b | 203 | | (((d) & (1<<1)) >> 1) \ |
davidprentice | 0:6f633078852b | 204 | | (((d) & (1<<2)) << 22) \ |
davidprentice | 0:6f633078852b | 205 | | (((d) & (1<<3)) << 20) \ |
davidprentice | 0:6f633078852b | 206 | | (((d) & (1<<4)) << 12) \ |
davidprentice | 0:6f633078852b | 207 | | (((d) & (1<<5)) << 10) \ |
davidprentice | 0:6f633078852b | 208 | | (((d) & (1<<6)) << 11) \ |
davidprentice | 0:6f633078852b | 209 | | (((d) & (1<<7)) << 11); \ |
davidprentice | 0:6f633078852b | 210 | } |
davidprentice | 0:6f633078852b | 211 | #define read_8() ( (((LPC_GPIO0->FIOPIN & (1<<1)) >> 1) \ |
davidprentice | 0:6f633078852b | 212 | | ((LPC_GPIO0->FIOPIN & (1<<0)) << 1) \ |
davidprentice | 0:6f633078852b | 213 | | ((LPC_GPIO0->FIOPIN & (1<<24)) >> 22) \ |
davidprentice | 0:6f633078852b | 214 | | ((LPC_GPIO0->FIOPIN & (1<<23)) >> 20) \ |
davidprentice | 0:6f633078852b | 215 | | ((LPC_GPIO0->FIOPIN & (1<<16)) >> 12) \ |
davidprentice | 0:6f633078852b | 216 | | ((LPC_GPIO0->FIOPIN & (1<<15)) >> 10) \ |
davidprentice | 0:6f633078852b | 217 | | ((LPC_GPIO0->FIOPIN & (1<<17)) >> 11) \ |
davidprentice | 0:6f633078852b | 218 | | ((LPC_GPIO0->FIOPIN & (1<<18)) >> 11))) |
davidprentice | 0:6f633078852b | 219 | #define setWriteDir() {LPC_GPIO0->FIODIR |= 0x01878003; } |
davidprentice | 0:6f633078852b | 220 | #define setReadDir() {LPC_GPIO0->FIODIR &= ~0x01878003; } |
davidprentice | 0:6f633078852b | 221 | |
davidprentice | 0:6f633078852b | 222 | |
davidprentice | 0:6f633078852b | 223 | #elif defined(MKL25Z4) || defined(TARGET_KL25Z) |
davidprentice | 0:6f633078852b | 224 | #include <MKL25Z4.h> |
davidprentice | 0:6f633078852b | 225 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 226 | #if 1 |
davidprentice | 0:6f633078852b | 227 | #define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4)) |
davidprentice | 0:6f633078852b | 228 | #define CMASK ((1<<9)|(1<<8)) |
davidprentice | 0:6f633078852b | 229 | #define DMASK ((1<<5)|(1<<4)) |
davidprentice | 0:6f633078852b | 230 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 231 | PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ |
davidprentice | 0:6f633078852b | 232 | PTA->PSOR = (((d) & (1<<0)) << 13) \ |
davidprentice | 0:6f633078852b | 233 | | (((d) & (1<<3)) << 9) \ |
davidprentice | 0:6f633078852b | 234 | | (((d) & (1<<4)) >> 0) \ |
davidprentice | 0:6f633078852b | 235 | | (((d) & (1<<5)) >> 0); \ |
davidprentice | 0:6f633078852b | 236 | PTC->PSOR = (((d) & (1<<6)) << 2) \ |
davidprentice | 0:6f633078852b | 237 | | (((d) & (1<<7)) << 2); \ |
davidprentice | 0:6f633078852b | 238 | PTD->PSOR = (((d) & (1<<1)) << 4) \ |
davidprentice | 0:6f633078852b | 239 | | (((d) & (1<<2)) << 2); \ |
davidprentice | 0:6f633078852b | 240 | } |
davidprentice | 0:6f633078852b | 241 | #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ |
davidprentice | 0:6f633078852b | 242 | | ((PTA->PDIR & (1<<12)) >> 9) \ |
davidprentice | 0:6f633078852b | 243 | | ((PTA->PDIR & (3<<4)) >> 0) \ |
davidprentice | 0:6f633078852b | 244 | | ((PTC->PDIR & (3<<8)) >> 2) \ |
davidprentice | 0:6f633078852b | 245 | | ((PTD->PDIR & (1<<4)) >> 2) \ |
davidprentice | 0:6f633078852b | 246 | | ((PTD->PDIR & (1<<5)) >> 4))) |
davidprentice | 0:6f633078852b | 247 | #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } |
davidprentice | 0:6f633078852b | 248 | #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } |
davidprentice | 0:6f633078852b | 249 | #else |
davidprentice | 0:6f633078852b | 250 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 251 | PTA->PDOR = (PTA->PDOR & ~0x3030) \ |
davidprentice | 0:6f633078852b | 252 | | (((d) & (1<<0)) << 13) \ |
davidprentice | 0:6f633078852b | 253 | | (((d) & (1<<3)) << 9) \ |
davidprentice | 0:6f633078852b | 254 | | (((d) & (3<<4)) << 0); \ |
davidprentice | 0:6f633078852b | 255 | PTC->PDOR = (PTC->PDOR & ~0x0300) \ |
davidprentice | 0:6f633078852b | 256 | | (((d) & (3<<6)) << 2); \ |
davidprentice | 0:6f633078852b | 257 | PTD->PDOR = (PTD->PDOR & ~0x0030) \ |
davidprentice | 0:6f633078852b | 258 | | (((d) & (1<<1)) << 4) \ |
davidprentice | 0:6f633078852b | 259 | | (((d) & (1<<2)) << 2); \ |
davidprentice | 0:6f633078852b | 260 | } |
davidprentice | 0:6f633078852b | 261 | #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ |
davidprentice | 0:6f633078852b | 262 | | ((PTA->PDIR & (1<<12)) >> 9) \ |
davidprentice | 0:6f633078852b | 263 | | ((PTA->PDIR & (3<<4)) >> 0) \ |
davidprentice | 0:6f633078852b | 264 | | ((PTC->PDIR & (3<<8)) >> 2) \ |
davidprentice | 0:6f633078852b | 265 | | ((PTD->PDIR & (1<<4)) >> 2) \ |
davidprentice | 0:6f633078852b | 266 | | ((PTD->PDIR & (1<<5)) >> 4))) |
davidprentice | 0:6f633078852b | 267 | #define setWriteDir() {PTA->PDDR |= 0x3030;PTC->PDDR |= 0x0300;PTD->PDDR |= 0x0030; } |
davidprentice | 0:6f633078852b | 268 | #define setReadDir() {PTA->PDDR &= ~0x3030;PTC->PDDR &= ~0x0300;PTD->PDDR &= ~0x0030; } |
davidprentice | 0:6f633078852b | 269 | #endif |
davidprentice | 0:6f633078852b | 270 | |
davidprentice | 0:6f633078852b | 271 | #elif defined(MKL26Z4) |
davidprentice | 0:6f633078852b | 272 | #include <MKL26Z4.h> |
davidprentice | 0:6f633078852b | 273 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 274 | #define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4)) |
davidprentice | 0:6f633078852b | 275 | #define CMASK ((1<<9)|(1<<8)) |
davidprentice | 0:6f633078852b | 276 | #define DMASK ((1<<3)|(1<<2)) //PTD5, PTD4 on KL25Z |
davidprentice | 0:6f633078852b | 277 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 278 | PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ |
davidprentice | 0:6f633078852b | 279 | PTA->PSOR = (((d) & (1<<0)) << 13) \ |
davidprentice | 0:6f633078852b | 280 | | (((d) & (1<<3)) << 9) \ |
davidprentice | 0:6f633078852b | 281 | | (((d) & (1<<4)) >> 0) \ |
davidprentice | 0:6f633078852b | 282 | | (((d) & (1<<5)) >> 0); \ |
davidprentice | 0:6f633078852b | 283 | PTC->PSOR = (((d) & (1<<6)) << 2) \ |
davidprentice | 0:6f633078852b | 284 | | (((d) & (1<<7)) << 2); \ |
davidprentice | 0:6f633078852b | 285 | PTD->PSOR = (((d) & (1<<1)) << 1) \ |
davidprentice | 0:6f633078852b | 286 | | (((d) & (1<<2)) << 1); \ |
davidprentice | 0:6f633078852b | 287 | } |
davidprentice | 0:6f633078852b | 288 | #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ |
davidprentice | 0:6f633078852b | 289 | | ((PTA->PDIR & (1<<12)) >> 9) \ |
davidprentice | 0:6f633078852b | 290 | | ((PTA->PDIR & (3<<4)) >> 0) \ |
davidprentice | 0:6f633078852b | 291 | | ((PTC->PDIR & (3<<8)) >> 2) \ |
davidprentice | 0:6f633078852b | 292 | | ((PTD->PDIR & (1<<3)) >> 1) \ |
davidprentice | 0:6f633078852b | 293 | | ((PTD->PDIR & (1<<2)) >> 1))) |
davidprentice | 0:6f633078852b | 294 | #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } |
davidprentice | 0:6f633078852b | 295 | #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } |
davidprentice | 0:6f633078852b | 296 | |
davidprentice | 0:6f633078852b | 297 | #elif defined(MKL05Z4) || defined(TARGET_KL05Z) |
davidprentice | 0:6f633078852b | 298 | #include <MKL05Z4.h> |
davidprentice | 0:6f633078852b | 299 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 300 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 301 | PTA->PDOR = (PTA->PDOR & ~0x1C00) \ |
davidprentice | 0:6f633078852b | 302 | | (((d) & (1<<2)) << 9) \ |
davidprentice | 0:6f633078852b | 303 | | (((d) & (1<<4)) << 6) \ |
davidprentice | 0:6f633078852b | 304 | | (((d) & (1<<5)) << 7); \ |
davidprentice | 0:6f633078852b | 305 | PTB->PDOR = (PTB->PDOR & ~0x0CE0) \ |
davidprentice | 0:6f633078852b | 306 | | (((d) & (3<<0)) << 10) \ |
davidprentice | 0:6f633078852b | 307 | | (((d) & (1<<3)) << 2) \ |
davidprentice | 0:6f633078852b | 308 | | (((d) & (3<<6)) << 0); \ |
davidprentice | 0:6f633078852b | 309 | } |
davidprentice | 0:6f633078852b | 310 | #define read_8() ( (((PTA->PDIR & (1<<11)) >> 9) \ |
davidprentice | 0:6f633078852b | 311 | | ((PTA->PDIR & (1<<10)) >> 6) \ |
davidprentice | 0:6f633078852b | 312 | | ((PTA->PDIR & (1<<12)) >> 7) \ |
davidprentice | 0:6f633078852b | 313 | | ((PTB->PDIR & (3<<10)) >> 10) \ |
davidprentice | 0:6f633078852b | 314 | | ((PTB->PDIR & (1<<5)) >> 2) \ |
davidprentice | 0:6f633078852b | 315 | | ((PTB->PDIR & (3<<6)) >> 0))) |
davidprentice | 0:6f633078852b | 316 | #define setWriteDir() { PTA->PDDR |= 0x1C00; PTB->PDDR |= 0x0CE0; } |
davidprentice | 0:6f633078852b | 317 | #define setReadDir() { PTA->PDDR &= ~0x1C00; PTB->PDDR &= ~0x0CE0; } |
davidprentice | 0:6f633078852b | 318 | |
davidprentice | 0:6f633078852b | 319 | |
davidprentice | 0:6f633078852b | 320 | #elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1) |
davidprentice | 0:6f633078852b | 321 | #if __MBED__ |
davidprentice | 0:6f633078852b | 322 | #warning MBED knows everything |
davidprentice | 0:6f633078852b | 323 | #else |
davidprentice | 0:6f633078852b | 324 | #include <MK20D5.h> |
davidprentice | 0:6f633078852b | 325 | #endif |
davidprentice | 0:6f633078852b | 326 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 327 | #define AMASK ((1<<12)|(1<<13)) |
davidprentice | 0:6f633078852b | 328 | #define CMASK ((1<<3)) |
davidprentice | 0:6f633078852b | 329 | #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7)) |
davidprentice | 0:6f633078852b | 330 | |
davidprentice | 0:6f633078852b | 331 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 332 | PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ |
davidprentice | 0:6f633078852b | 333 | PTA->PSOR = (((d) & (1<<3)) << 9) \ |
davidprentice | 0:6f633078852b | 334 | | (((d) & (1<<4)) << 9); \ |
davidprentice | 0:6f633078852b | 335 | PTC->PSOR = (((d) & (1<<1)) << 2); \ |
davidprentice | 0:6f633078852b | 336 | PTD->PSOR = (((d) & (1<<0)) << 3) \ |
davidprentice | 0:6f633078852b | 337 | | (((d) & (1<<2)) >> 2) \ |
davidprentice | 0:6f633078852b | 338 | | (((d) & (1<<5)) << 2) \ |
davidprentice | 0:6f633078852b | 339 | | (((d) & (1<<6)) >> 2) \ |
davidprentice | 0:6f633078852b | 340 | | (((d) & (1<<7)) >> 5); \ |
davidprentice | 0:6f633078852b | 341 | } |
davidprentice | 0:6f633078852b | 342 | #define read_8() ( (((PTD->PDIR & (1<<3)) >> 3) \ |
davidprentice | 0:6f633078852b | 343 | | ((PTC->PDIR & (1<<3)) >> 2) \ |
davidprentice | 0:6f633078852b | 344 | | ((PTD->PDIR & (1<<0)) << 2) \ |
davidprentice | 0:6f633078852b | 345 | | ((PTA->PDIR & (1<<12)) >> 9) \ |
davidprentice | 0:6f633078852b | 346 | | ((PTA->PDIR & (1<<13)) >> 9) \ |
davidprentice | 0:6f633078852b | 347 | | ((PTD->PDIR & (1<<7)) >> 2) \ |
davidprentice | 0:6f633078852b | 348 | | ((PTD->PDIR & (1<<4)) << 2) \ |
davidprentice | 0:6f633078852b | 349 | | ((PTD->PDIR & (1<<2)) << 5))) |
davidprentice | 0:6f633078852b | 350 | #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } |
davidprentice | 0:6f633078852b | 351 | #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } |
davidprentice | 0:6f633078852b | 352 | |
davidprentice | 0:6f633078852b | 353 | #elif defined(MK20D5) || defined(TARGET_K20D50M) |
davidprentice | 0:6f633078852b | 354 | #include <MK20D5.h> |
davidprentice | 0:6f633078852b | 355 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 356 | #define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1)) |
davidprentice | 0:6f633078852b | 357 | #define CMASK ((1<<8)|(1<<4)|(1<<3)) |
davidprentice | 0:6f633078852b | 358 | #define DMASK ((1<<4)) |
davidprentice | 0:6f633078852b | 359 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 360 | PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ |
davidprentice | 0:6f633078852b | 361 | PTA->PSOR = (((d) & (1<<0)) << 12) \ |
davidprentice | 0:6f633078852b | 362 | | (((d) & (1<<1)) << 1) \ |
davidprentice | 0:6f633078852b | 363 | | (((d) & (1<<2)) << 3) \ |
davidprentice | 0:6f633078852b | 364 | | (((d) & (1<<5)) >> 4); \ |
davidprentice | 0:6f633078852b | 365 | PTC->PSOR = (((d) & (1<<4)) << 4) \ |
davidprentice | 0:6f633078852b | 366 | | (((d) & (3<<6)) >> 3); \ |
davidprentice | 0:6f633078852b | 367 | PTD->PSOR = (((d) & (1<<3)) << 1); \ |
davidprentice | 0:6f633078852b | 368 | } |
davidprentice | 0:6f633078852b | 369 | #define read_8() ( (((PTA->PDIR & (1<<5)) >> 3) \ |
davidprentice | 0:6f633078852b | 370 | | ((PTA->PDIR & (1<<1)) << 4) \ |
davidprentice | 0:6f633078852b | 371 | | ((PTA->PDIR & (1<<12)) >> 12) \ |
davidprentice | 0:6f633078852b | 372 | | ((PTA->PDIR & (1<<2)) >> 1) \ |
davidprentice | 0:6f633078852b | 373 | | ((PTC->PDIR & (1<<8)) >> 4) \ |
davidprentice | 0:6f633078852b | 374 | | ((PTC->PDIR & (3<<3)) << 3) \ |
davidprentice | 0:6f633078852b | 375 | | ((PTD->PDIR & (1<<4)) >> 1))) |
davidprentice | 0:6f633078852b | 376 | #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } |
davidprentice | 0:6f633078852b | 377 | #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } |
davidprentice | 0:6f633078852b | 378 | |
davidprentice | 0:6f633078852b | 379 | #elif defined(ZERO) |
davidprentice | 0:6f633078852b | 380 | #include <samd21.h> |
davidprentice | 0:6f633078852b | 381 | |
davidprentice | 0:6f633078852b | 382 | #ifndef PORTA |
davidprentice | 0:6f633078852b | 383 | #define PORTA PORT->Group[0] |
davidprentice | 0:6f633078852b | 384 | #define PORTB PORT->Group[1] |
davidprentice | 0:6f633078852b | 385 | #endif |
davidprentice | 0:6f633078852b | 386 | // configure macros for the data pins |
davidprentice | 0:6f633078852b | 387 | #if defined(D21_XPRO) |
davidprentice | 0:6f633078852b | 388 | #define AMASK 0x00220000 |
davidprentice | 0:6f633078852b | 389 | #define BMASK 0x0000C0E4 |
davidprentice | 0:6f633078852b | 390 | #define write_8(d) { \ |
davidprentice | 0:6f633078852b | 391 | PORTA.OUT.reg = (PORTA.OUT.reg & ~AMASK) \ |
davidprentice | 0:6f633078852b | 392 | | (((d) & (1<<5)) << 16) \ |
davidprentice | 0:6f633078852b | 393 | | (((d) & (1<<7)) << 10); \ |
davidprentice | 0:6f633078852b | 394 | PORTB.OUT.reg = (PORTB.OUT.reg & ~BMASK) \ |
davidprentice | 0:6f633078852b | 395 | | (((d) & (3<<0)) << 6) \ |
davidprentice | 0:6f633078852b | 396 | | (((d) & (1<<2)) << 12) \ |
davidprentice | 0:6f633078852b | 397 | | (((d) & (1<<3)) >> 1) \ |
davidprentice | 0:6f633078852b | 398 | | (((d) & (1<<4)) << 1) \ |
davidprentice | 0:6f633078852b | 399 | | (((d) & (1<<6)) << 9); \ |
davidprentice | 0:6f633078852b | 400 | } |
davidprentice | 0:6f633078852b | 401 | #define read_8() ( (((PORTA.IN.reg & (1<<21)) >> 16) \ |
davidprentice | 0:6f633078852b | 402 | | ((PORTA.IN.reg & (1<<17)) >> 10) \ |
davidprentice | 0:6f633078852b | 403 | | ((PORTB.IN.reg & (3<<6)) >> 6) \ |
davidprentice | 0:6f633078852b | 404 | | ((PORTB.IN.reg & (1<<14)) >> 12) \ |
davidprentice | 0:6f633078852b | 405 | | ((PORTB.IN.reg & (1<<2)) << 1) \ |
davidprentice | 0:6f633078852b | 406 | | ((PORTB.IN.reg & (1<<5)) >> 1) \ |
davidprentice | 0:6f633078852b | 407 | | ((PORTB.IN.reg & (1<<15)) >> 9))) |
davidprentice | 0:6f633078852b | 408 | #define setWriteDir() { \ |
davidprentice | 0:6f633078852b | 409 | PORTA.DIRSET.reg = AMASK; \ |
davidprentice | 0:6f633078852b | 410 | PORTB.DIRSET.reg = BMASK; \ |
davidprentice | 0:6f633078852b | 411 | PORTA.WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:6f633078852b | 412 | PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \ |
davidprentice | 0:6f633078852b | 413 | } |
davidprentice | 0:6f633078852b | 414 | #define setReadDir() { \ |
davidprentice | 0:6f633078852b | 415 | PORTA.DIRCLR.reg = AMASK; \ |
davidprentice | 0:6f633078852b | 416 | PORTB.DIRCLR.reg = BMASK; \ |
davidprentice | 0:6f633078852b | 417 | PORTA.WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:6f633078852b | 418 | PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \ |
davidprentice | 0:6f633078852b | 419 | } |
davidprentice | 0:6f633078852b | 420 | #else |
davidprentice | 0:6f633078852b | 421 | #define DMASK 0x0030C3C0 |
davidprentice | 0:6f633078852b | 422 | #define write_8(x) {PORTA.OUTCLR.reg = (DMASK); \ |
davidprentice | 0:6f633078852b | 423 | PORTA.OUTSET.reg = (((x) & 0x0F) << 6) \ |
davidprentice | 0:6f633078852b | 424 | | (((x) & 0x30) << 10) \ |
davidprentice | 0:6f633078852b | 425 | | (((x) & 0xC0)<<14); } |
davidprentice | 0:6f633078852b | 426 | #define read_8() (((PORTA.IN.reg >> 6) & 0x0F) \ |
davidprentice | 0:6f633078852b | 427 | | ((PORTA.IN.reg >> 10) & 0x30) \ |
davidprentice | 0:6f633078852b | 428 | | ((PORTA.IN.reg >> 14) & 0xC0)) |
davidprentice | 0:6f633078852b | 429 | #define setWriteDir() { PORTA.DIRSET.reg = DMASK; \ |
davidprentice | 0:6f633078852b | 430 | PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \ |
davidprentice | 0:6f633078852b | 431 | PORTA.WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:6f633078852b | 432 | } |
davidprentice | 0:6f633078852b | 433 | #define setReadDir() { PORTA.DIRCLR.reg = DMASK; \ |
davidprentice | 0:6f633078852b | 434 | PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \ |
davidprentice | 0:6f633078852b | 435 | PORTA.WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:6f633078852b | 436 | } |
davidprentice | 0:6f633078852b | 437 | #endif |
davidprentice | 0:6f633078852b | 438 | |
davidprentice | 0:6f633078852b | 439 | //####################################### DUE ############################ |
davidprentice | 0:6f633078852b | 440 | #elif defined(__SAM3X8E__) //regular UNO shield on DUE |
davidprentice | 0:6f633078852b | 441 | // configure macros for data bus |
davidprentice | 0:6f633078852b | 442 | #define BMASK (1<<25) |
davidprentice | 0:6f633078852b | 443 | #define CMASK (0xBF << 21) |
davidprentice | 0:6f633078852b | 444 | #define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \ |
davidprentice | 0:6f633078852b | 445 | PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \ |
davidprentice | 0:6f633078852b | 446 | PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \ |
davidprentice | 0:6f633078852b | 447 | | (((x) & (1<<1)) << 20) \ |
davidprentice | 0:6f633078852b | 448 | | (((x) & (1<<3)) << 25) \ |
davidprentice | 0:6f633078852b | 449 | | (((x) & (1<<4)) << 22) \ |
davidprentice | 0:6f633078852b | 450 | | (((x) & (1<<5)) << 20) \ |
davidprentice | 0:6f633078852b | 451 | | (((x) & (1<<6)) << 18) \ |
davidprentice | 0:6f633078852b | 452 | | (((x) & (1<<7)) << 16); \ |
davidprentice | 0:6f633078852b | 453 | } |
davidprentice | 0:6f633078852b | 454 | |
davidprentice | 0:6f633078852b | 455 | #define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\ |
davidprentice | 0:6f633078852b | 456 | | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\ |
davidprentice | 0:6f633078852b | 457 | | ((PIOB->PIO_PDSR & (1<<25)) >> 23)\ |
davidprentice | 0:6f633078852b | 458 | | ((PIOC->PIO_PDSR & (1<<28)) >> 25)\ |
davidprentice | 0:6f633078852b | 459 | | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\ |
davidprentice | 0:6f633078852b | 460 | | ((PIOC->PIO_PDSR & (1<<25)) >> 20)\ |
davidprentice | 0:6f633078852b | 461 | | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\ |
davidprentice | 0:6f633078852b | 462 | | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\ |
davidprentice | 0:6f633078852b | 463 | ) |
davidprentice | 0:6f633078852b | 464 | #define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; } |
davidprentice | 0:6f633078852b | 465 | #define setReadDir() { \ |
davidprentice | 0:6f633078852b | 466 | PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\ |
davidprentice | 0:6f633078852b | 467 | PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\ |
davidprentice | 0:6f633078852b | 468 | } |
davidprentice | 0:6f633078852b | 469 | |
davidprentice | 0:6f633078852b | 470 | #else |
davidprentice | 0:6f633078852b | 471 | #error MCU unselected |
davidprentice | 0:6f633078852b | 472 | #endif // MCUs |
davidprentice | 0:6f633078852b | 473 | |
davidprentice | 0:6f633078852b | 474 | #endif //PIN_SHIELD_8_H |
davidprentice | 0:6f633078852b | 475 |