Dave Van Wagner / USBHOST

ST/USBHOST forked to add another HID handler for raw keyboard data to get more detail not available with current handlers (all pressed keys, all releases, and periodic updates)

Dependents:   C64-stm429_discovery

USBHostSerial/MtxCircBuffer.h@7:9dc1cb9d5e12, 2020-04-13 (annotated)

Committer:
davervw
Date:
Mon Apr 13 05:25:10 2020 +0000
Revision:
7:9dc1cb9d5e12
Parent:
1:ab240722d7ef 
Added handler to USBHostHID/USBHostKeyboard.cpp:;    void (*onKeyData)(uint8_t len, uint8_t* data);; so can get raw keyboard data for all keys simultaneously pressed, and all releases and periodic data

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 1 /* mbed USBHost Library
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 2 * Copyright (c) 2006-2013 ARM Limited
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 3 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 4 * Licensed under the Apache License, Version 2.0 (the "License");
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 5 * you may not use this file except in compliance with the License.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 6 * You may obtain a copy of the License at
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 7 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 8 * http://www.apache.org/licenses/LICENSE-2.0
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 9 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 10 * Unless required by applicable law or agreed to in writing, software
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 11 * distributed under the License is distributed on an "AS IS" BASIS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 13 * See the License for the specific language governing permissions and
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 14 * limitations under the License.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 15 */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 16
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 17 #ifndef MTXCIRCBUFFER_H
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 18 #define MTXCIRCBUFFER_H
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 19
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 20 #include "stdint.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 21 #include "rtos.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 22
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 23 //Mutex protected circular buffer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 24 template<typename T, int size>
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 25 class MtxCircBuffer {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 26 public:
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 27
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 28 MtxCircBuffer() {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 29 write = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 30 read = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 31 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 32
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 33 bool isFull() {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 34 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 35 bool r = (((write + 1) % size) == read);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 36 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 37 return r;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 38 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 39
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 40 bool isEmpty() {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 41 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 42 bool r = (read == write);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 43 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 44 return r;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 45 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 46
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 47 void flush() {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 48 write = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 49 read = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 50 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 51
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 52 void queue(T k) {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 53 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 54 while (((write + 1) % size) == read) {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 55 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 56 Thread::wait(10);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 57 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 58 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 59 buf[write++] = k;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 60 write %= size;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 61 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 62 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 63
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 64 uint16_t available() {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 65 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 66 uint16_t a = (write >= read) ? (write - read) : (size - read + write);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 67 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 68 return a;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 69 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 70
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 71 bool dequeue(T * c) {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 72 mtx.lock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 73 bool empty = (read == write);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 74 if (!empty) {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 75 *c = buf[read++];
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 76 read %= size;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 77 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 78 mtx.unlock();
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 79 return (!empty);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 80 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 81
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 82 private:
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 83 volatile uint16_t write;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 84 volatile uint16_t read;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 85 volatile T buf[size];
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 86 Mutex mtx;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 87 };
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 88
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 89 #endif