Application - lol

Users » danix » Code » Application

lol

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c@10:41552d038a69, 2017-01-10 (annotated)

Committer:: Zaitsev
Date:: Tue Jan 10 20:42:26 2017 +0000
Revision:: 10:41552d038a69

USB Serial bi-directional bridge

Who changed what in which revision?

User	Revision	Line number	New contents of line
Zaitsev	10:41552d038a69	1	/*******************************************************************************
Zaitsev	10:41552d038a69	2	* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Zaitsev	10:41552d038a69	3	*
Zaitsev	10:41552d038a69	4	* Permission is hereby granted, free of charge, to any person obtaining a
Zaitsev	10:41552d038a69	5	* copy of this software and associated documentation files (the "Software"),
Zaitsev	10:41552d038a69	6	* to deal in the Software without restriction, including without limitation
Zaitsev	10:41552d038a69	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
Zaitsev	10:41552d038a69	8	* and/or sell copies of the Software, and to permit persons to whom the
Zaitsev	10:41552d038a69	9	* Software is furnished to do so, subject to the following conditions:
Zaitsev	10:41552d038a69	10	*
Zaitsev	10:41552d038a69	11	* The above copyright notice and this permission notice shall be included
Zaitsev	10:41552d038a69	12	* in all copies or substantial portions of the Software.
Zaitsev	10:41552d038a69	13	*
Zaitsev	10:41552d038a69	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Zaitsev	10:41552d038a69	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Zaitsev	10:41552d038a69	16	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Zaitsev	10:41552d038a69	17	* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Zaitsev	10:41552d038a69	18	* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Zaitsev	10:41552d038a69	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Zaitsev	10:41552d038a69	20	* OTHER DEALINGS IN THE SOFTWARE.
Zaitsev	10:41552d038a69	21	*
Zaitsev	10:41552d038a69	22	* Except as contained in this notice, the name of Maxim Integrated
Zaitsev	10:41552d038a69	23	* Products, Inc. shall not be used except as stated in the Maxim Integrated
Zaitsev	10:41552d038a69	24	* Products, Inc. Branding Policy.
Zaitsev	10:41552d038a69	25	*
Zaitsev	10:41552d038a69	26	* The mere transfer of this software does not imply any licenses
Zaitsev	10:41552d038a69	27	* of trade secrets, proprietary technology, copyrights, patents,
Zaitsev	10:41552d038a69	28	* trademarks, maskwork rights, or any other form of intellectual
Zaitsev	10:41552d038a69	29	* property whatsoever. Maxim Integrated Products, Inc. retains all
Zaitsev	10:41552d038a69	30	* ownership rights.
Zaitsev	10:41552d038a69	31	*******************************************************************************
Zaitsev	10:41552d038a69	32	*/
Zaitsev	10:41552d038a69	33
Zaitsev	10:41552d038a69	34	#include "device.h"
Zaitsev	10:41552d038a69	35	#include "PeripheralPins.h"
Zaitsev	10:41552d038a69	36	#include "ioman_regs.h"
Zaitsev	10:41552d038a69	37
Zaitsev	10:41552d038a69	38	/*
Zaitsev	10:41552d038a69	39	* To select a peripheral function on Maxim microcontrollers, multiple
Zaitsev	10:41552d038a69	40	* configurations must be made. The mbed PinMap structure only includes one
Zaitsev	10:41552d038a69	41	* data member to hold this information. To extend the configuration storage,
Zaitsev	10:41552d038a69	42	* the "function" data member is used as a pointer to a pin_function_t
Zaitsev	10:41552d038a69	43	* structure. This structure is defined in objects.h. The definitions below
Zaitsev	10:41552d038a69	44	* include the creation of the pin_function_t structures and the assignment of
Zaitsev	10:41552d038a69	45	* the pointers to the "function" data members.
Zaitsev	10:41552d038a69	46	*/
Zaitsev	10:41552d038a69	47
Zaitsev	10:41552d038a69	48	#ifdef TOOLCHAIN_ARM_STD
Zaitsev	10:41552d038a69	49	#pragma diag_suppress 1296
Zaitsev	10:41552d038a69	50	#endif
Zaitsev	10:41552d038a69	51
Zaitsev	10:41552d038a69	52	/**********I2C*************/
Zaitsev	10:41552d038a69	53	const PinMap PinMap_I2C_SDA[] = {
Zaitsev	10:41552d038a69	54	{ P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	55	{ P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	56	{ P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	57	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	58	};
Zaitsev	10:41552d038a69	59
Zaitsev	10:41552d038a69	60	const PinMap PinMap_I2C_SCL[] = {
Zaitsev	10:41552d038a69	61	{ P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	62	{ P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	63	{ P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) },
Zaitsev	10:41552d038a69	64	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	65	};
Zaitsev	10:41552d038a69	66
Zaitsev	10:41552d038a69	67	/**********UART*************/
Zaitsev	10:41552d038a69	68	/*
Zaitsev	10:41552d038a69	69	*/
Zaitsev	10:41552d038a69	70	const PinMap PinMap_UART_TX[] = {
Zaitsev	10:41552d038a69	71	{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	72	{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	73	{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	74	{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	75	{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	76	{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	77	{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	78	{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	79	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	80	};
Zaitsev	10:41552d038a69	81
Zaitsev	10:41552d038a69	82	const PinMap PinMap_UART_RX[] = {
Zaitsev	10:41552d038a69	83	{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	84	{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	85	{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	86	{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	87	{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	88	{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	89	{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	90	{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP \| MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
Zaitsev	10:41552d038a69	91	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	92	};
Zaitsev	10:41552d038a69	93
Zaitsev	10:41552d038a69	94	const PinMap PinMap_UART_CTS[] = {
Zaitsev	10:41552d038a69	95	{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	96	{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	97	{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	98	{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	99	{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	100	{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	101	{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	102	{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP \| MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	103	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	104	};
Zaitsev	10:41552d038a69	105
Zaitsev	10:41552d038a69	106	const PinMap PinMap_UART_RTS[] = {
Zaitsev	10:41552d038a69	107	{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	108	{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	109	{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	110	{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	111	{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	112	{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	113	{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	114	{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP \| MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) },
Zaitsev	10:41552d038a69	115	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	116	};
Zaitsev	10:41552d038a69	117
Zaitsev	10:41552d038a69	118	/**********SPI*************/
Zaitsev	10:41552d038a69	119	const PinMap PinMap_SPI_SCLK[] = {
Zaitsev	10:41552d038a69	120	{ P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	121	{ P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	122	{ P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	123	{ P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	124	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	125	};
Zaitsev	10:41552d038a69	126
Zaitsev	10:41552d038a69	127	const PinMap PinMap_SPI_MOSI[] = {
Zaitsev	10:41552d038a69	128	{ P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	129	{ P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	130	{ P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	131	{ P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	132	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	133	};
Zaitsev	10:41552d038a69	134
Zaitsev	10:41552d038a69	135	const PinMap PinMap_SPI_MISO[] = {
Zaitsev	10:41552d038a69	136	{ P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	137	{ P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) },
Zaitsev	10:41552d038a69	138	{ P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	139	{ P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) },
Zaitsev	10:41552d038a69	140	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	141	};
Zaitsev	10:41552d038a69	142
Zaitsev	10:41552d038a69	143	const PinMap PinMap_SPI_SSEL[] = {
Zaitsev	10:41552d038a69	144	{ P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) },
Zaitsev	10:41552d038a69	145	{ P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) },
Zaitsev	10:41552d038a69	146	{ P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK)}) },
Zaitsev	10:41552d038a69	147	{ P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ \| MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK \| MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK)}) },
Zaitsev	10:41552d038a69	148	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	149	};
Zaitsev	10:41552d038a69	150
Zaitsev	10:41552d038a69	151	const PinMap PinMap_SPI_QUAD[] = {
Zaitsev	10:41552d038a69	152	{ P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) },
Zaitsev	10:41552d038a69	153	{ P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) },
Zaitsev	10:41552d038a69	154	{ P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ \| MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ \| MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK \| MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK)}) },
Zaitsev	10:41552d038a69	155	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	156	};
Zaitsev	10:41552d038a69	157
Zaitsev	10:41552d038a69	158	/**********PWM*************/
Zaitsev	10:41552d038a69	159	const PinMap PinMap_PWM[] = {
Zaitsev	10:41552d038a69	160	{ P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1},
Zaitsev	10:41552d038a69	161	{ P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 },
Zaitsev	10:41552d038a69	162	{ P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 },
Zaitsev	10:41552d038a69	163	{ P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 },
Zaitsev	10:41552d038a69	164	{ P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 },
Zaitsev	10:41552d038a69	165	{ P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 },
Zaitsev	10:41552d038a69	166	{ P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 },
Zaitsev	10:41552d038a69	167	{ P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 },
Zaitsev	10:41552d038a69	168	{ P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 },
Zaitsev	10:41552d038a69	169	{ P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 },
Zaitsev	10:41552d038a69	170	{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
Zaitsev	10:41552d038a69	171	{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
Zaitsev	10:41552d038a69	172	{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
Zaitsev	10:41552d038a69	173	{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
Zaitsev	10:41552d038a69	174	{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
Zaitsev	10:41552d038a69	175	{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
Zaitsev	10:41552d038a69	176	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	177	};
Zaitsev	10:41552d038a69	178
Zaitsev	10:41552d038a69	179	/**********ADC*************/
Zaitsev	10:41552d038a69	180	const PinMap PinMap_ADC[] = {
Zaitsev	10:41552d038a69	181	{ AIN_0, ADC, 0 },
Zaitsev	10:41552d038a69	182	{ AIN_1, ADC, 0 },
Zaitsev	10:41552d038a69	183	{ AIN_2, ADC, 0 },
Zaitsev	10:41552d038a69	184	{ AIN_3, ADC, 0 },
Zaitsev	10:41552d038a69	185	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	186	};

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Created:	21 Jan 2018
Imports:	2
Forks:	1
Commits:	13
Dependents:	0
Dependencies:	1
Followers:	1

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c@10:41552d038a69, 2017-01-10 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning