Daniele Lacamera / USB_Ethernet

CDC/ECM driver for mbed, based on USBDevice by mbed-official. Uses PicoTCP to access Ethernet USB device. License: GPLv2

Dependents:   USBEthernet_TEST

Fork of USB_Ethernet by Daniele Lacamera

USBDevice/USBHAL_LPC17.cpp@2:540f6e142d59, 2013-08-03 (annotated)

Committer:
daniele
Date:
Sat Aug 03 13:16:14 2013 +0000
Revision:
2:540f6e142d59
Moved to single package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniele 2:540f6e142d59 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
daniele 2:540f6e142d59 2 *
daniele 2:540f6e142d59 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
daniele 2:540f6e142d59 4 * and associated documentation files (the "Software"), to deal in the Software without
daniele 2:540f6e142d59 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
daniele 2:540f6e142d59 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
daniele 2:540f6e142d59 7 * Software is furnished to do so, subject to the following conditions:
daniele 2:540f6e142d59 8 *
daniele 2:540f6e142d59 9 * The above copyright notice and this permission notice shall be included in all copies or
daniele 2:540f6e142d59 10 * substantial portions of the Software.
daniele 2:540f6e142d59 11 *
daniele 2:540f6e142d59 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
daniele 2:540f6e142d59 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
daniele 2:540f6e142d59 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
daniele 2:540f6e142d59 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
daniele 2:540f6e142d59 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
daniele 2:540f6e142d59 17 */
daniele 2:540f6e142d59 18
daniele 2:540f6e142d59 19 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
daniele 2:540f6e142d59 20
daniele 2:540f6e142d59 21 #include "USBHAL.h"
daniele 2:540f6e142d59 22
daniele 2:540f6e142d59 23
daniele 2:540f6e142d59 24 // Get endpoint direction
daniele 2:540f6e142d59 25 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
daniele 2:540f6e142d59 26 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
daniele 2:540f6e142d59 27
daniele 2:540f6e142d59 28 // Convert physical endpoint number to register bit
daniele 2:540f6e142d59 29 #define EP(endpoint) (1UL<<endpoint)
daniele 2:540f6e142d59 30
daniele 2:540f6e142d59 31 // Power Control for Peripherals register
daniele 2:540f6e142d59 32 #define PCUSB (1UL<<31)
daniele 2:540f6e142d59 33
daniele 2:540f6e142d59 34 // USB Clock Control register
daniele 2:540f6e142d59 35 #define DEV_CLK_EN (1UL<<1)
daniele 2:540f6e142d59 36 #define AHB_CLK_EN (1UL<<4)
daniele 2:540f6e142d59 37
daniele 2:540f6e142d59 38 // USB Clock Status register
daniele 2:540f6e142d59 39 #define DEV_CLK_ON (1UL<<1)
daniele 2:540f6e142d59 40 #define AHB_CLK_ON (1UL<<4)
daniele 2:540f6e142d59 41
daniele 2:540f6e142d59 42 // USB Device Interupt registers
daniele 2:540f6e142d59 43 #define FRAME (1UL<<0)
daniele 2:540f6e142d59 44 #define EP_FAST (1UL<<1)
daniele 2:540f6e142d59 45 #define EP_SLOW (1UL<<2)
daniele 2:540f6e142d59 46 #define DEV_STAT (1UL<<3)
daniele 2:540f6e142d59 47 #define CCEMPTY (1UL<<4)
daniele 2:540f6e142d59 48 #define CDFULL (1UL<<5)
daniele 2:540f6e142d59 49 #define RxENDPKT (1UL<<6)
daniele 2:540f6e142d59 50 #define TxENDPKT (1UL<<7)
daniele 2:540f6e142d59 51 #define EP_RLZED (1UL<<8)
daniele 2:540f6e142d59 52 #define ERR_INT (1UL<<9)
daniele 2:540f6e142d59 53
daniele 2:540f6e142d59 54 // USB Control register
daniele 2:540f6e142d59 55 #define RD_EN (1<<0)
daniele 2:540f6e142d59 56 #define WR_EN (1<<1)
daniele 2:540f6e142d59 57 #define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
daniele 2:540f6e142d59 58
daniele 2:540f6e142d59 59 // USB Receive Packet Length register
daniele 2:540f6e142d59 60 #define DV (1UL<<10)
daniele 2:540f6e142d59 61 #define PKT_RDY (1UL<<11)
daniele 2:540f6e142d59 62 #define PKT_LNGTH_MASK (0x3ff)
daniele 2:540f6e142d59 63
daniele 2:540f6e142d59 64 // Serial Interface Engine (SIE)
daniele 2:540f6e142d59 65 #define SIE_WRITE (0x01)
daniele 2:540f6e142d59 66 #define SIE_READ (0x02)
daniele 2:540f6e142d59 67 #define SIE_COMMAND (0x05)
daniele 2:540f6e142d59 68 #define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
daniele 2:540f6e142d59 69
daniele 2:540f6e142d59 70 // SIE Command codes
daniele 2:540f6e142d59 71 #define SIE_CMD_SET_ADDRESS (0xD0)
daniele 2:540f6e142d59 72 #define SIE_CMD_CONFIGURE_DEVICE (0xD8)
daniele 2:540f6e142d59 73 #define SIE_CMD_SET_MODE (0xF3)
daniele 2:540f6e142d59 74 #define SIE_CMD_READ_FRAME_NUMBER (0xF5)
daniele 2:540f6e142d59 75 #define SIE_CMD_READ_TEST_REGISTER (0xFD)
daniele 2:540f6e142d59 76 #define SIE_CMD_SET_DEVICE_STATUS (0xFE)
daniele 2:540f6e142d59 77 #define SIE_CMD_GET_DEVICE_STATUS (0xFE)
daniele 2:540f6e142d59 78 #define SIE_CMD_GET_ERROR_CODE (0xFF)
daniele 2:540f6e142d59 79 #define SIE_CMD_READ_ERROR_STATUS (0xFB)
daniele 2:540f6e142d59 80
daniele 2:540f6e142d59 81 #define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
daniele 2:540f6e142d59 82 #define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
daniele 2:540f6e142d59 83 #define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
daniele 2:540f6e142d59 84
daniele 2:540f6e142d59 85 #define SIE_CMD_CLEAR_BUFFER (0xF2)
daniele 2:540f6e142d59 86 #define SIE_CMD_VALIDATE_BUFFER (0xFA)
daniele 2:540f6e142d59 87
daniele 2:540f6e142d59 88 // SIE Device Status register
daniele 2:540f6e142d59 89 #define SIE_DS_CON (1<<0)
daniele 2:540f6e142d59 90 #define SIE_DS_CON_CH (1<<1)
daniele 2:540f6e142d59 91 #define SIE_DS_SUS (1<<2)
daniele 2:540f6e142d59 92 #define SIE_DS_SUS_CH (1<<3)
daniele 2:540f6e142d59 93 #define SIE_DS_RST (1<<4)
daniele 2:540f6e142d59 94
daniele 2:540f6e142d59 95 // SIE Device Set Address register
daniele 2:540f6e142d59 96 #define SIE_DSA_DEV_EN (1<<7)
daniele 2:540f6e142d59 97
daniele 2:540f6e142d59 98 // SIE Configue Device register
daniele 2:540f6e142d59 99 #define SIE_CONF_DEVICE (1<<0)
daniele 2:540f6e142d59 100
daniele 2:540f6e142d59 101 // Select Endpoint register
daniele 2:540f6e142d59 102 #define SIE_SE_FE (1<<0)
daniele 2:540f6e142d59 103 #define SIE_SE_ST (1<<1)
daniele 2:540f6e142d59 104 #define SIE_SE_STP (1<<2)
daniele 2:540f6e142d59 105 #define SIE_SE_PO (1<<3)
daniele 2:540f6e142d59 106 #define SIE_SE_EPN (1<<4)
daniele 2:540f6e142d59 107 #define SIE_SE_B_1_FULL (1<<5)
daniele 2:540f6e142d59 108 #define SIE_SE_B_2_FULL (1<<6)
daniele 2:540f6e142d59 109
daniele 2:540f6e142d59 110 // Set Endpoint Status command
daniele 2:540f6e142d59 111 #define SIE_SES_ST (1<<0)
daniele 2:540f6e142d59 112 #define SIE_SES_DA (1<<5)
daniele 2:540f6e142d59 113 #define SIE_SES_RF_MO (1<<6)
daniele 2:540f6e142d59 114 #define SIE_SES_CND_ST (1<<7)
daniele 2:540f6e142d59 115
daniele 2:540f6e142d59 116
daniele 2:540f6e142d59 117 USBHAL * USBHAL::instance;
daniele 2:540f6e142d59 118
daniele 2:540f6e142d59 119 static volatile int epComplete;
daniele 2:540f6e142d59 120 static uint32_t endpointStallState;
daniele 2:540f6e142d59 121
daniele 2:540f6e142d59 122 static void SIECommand(uint32_t command) {
daniele 2:540f6e142d59 123 // The command phase of a SIE transaction
daniele 2:540f6e142d59 124 LPC_USB->USBDevIntClr = CCEMPTY;
daniele 2:540f6e142d59 125 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
daniele 2:540f6e142d59 126 while (!(LPC_USB->USBDevIntSt & CCEMPTY));
daniele 2:540f6e142d59 127 }
daniele 2:540f6e142d59 128
daniele 2:540f6e142d59 129 static void SIEWriteData(uint8_t data) {
daniele 2:540f6e142d59 130 // The data write phase of a SIE transaction
daniele 2:540f6e142d59 131 LPC_USB->USBDevIntClr = CCEMPTY;
daniele 2:540f6e142d59 132 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_WRITE, data);
daniele 2:540f6e142d59 133 while (!(LPC_USB->USBDevIntSt & CCEMPTY));
daniele 2:540f6e142d59 134 }
daniele 2:540f6e142d59 135
daniele 2:540f6e142d59 136 static uint8_t SIEReadData(uint32_t command) {
daniele 2:540f6e142d59 137 // The data read phase of a SIE transaction
daniele 2:540f6e142d59 138 LPC_USB->USBDevIntClr = CDFULL;
daniele 2:540f6e142d59 139 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_READ, command);
daniele 2:540f6e142d59 140 while (!(LPC_USB->USBDevIntSt & CDFULL));
daniele 2:540f6e142d59 141 return (uint8_t)LPC_USB->USBCmdData;
daniele 2:540f6e142d59 142 }
daniele 2:540f6e142d59 143
daniele 2:540f6e142d59 144 static void SIEsetDeviceStatus(uint8_t status) {
daniele 2:540f6e142d59 145 // Write SIE device status register
daniele 2:540f6e142d59 146 SIECommand(SIE_CMD_SET_DEVICE_STATUS);
daniele 2:540f6e142d59 147 SIEWriteData(status);
daniele 2:540f6e142d59 148 }
daniele 2:540f6e142d59 149
daniele 2:540f6e142d59 150 static uint8_t SIEgetDeviceStatus(void) {
daniele 2:540f6e142d59 151 // Read SIE device status register
daniele 2:540f6e142d59 152 SIECommand(SIE_CMD_GET_DEVICE_STATUS);
daniele 2:540f6e142d59 153 return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
daniele 2:540f6e142d59 154 }
daniele 2:540f6e142d59 155
daniele 2:540f6e142d59 156 void SIEsetAddress(uint8_t address) {
daniele 2:540f6e142d59 157 // Write SIE device address register
daniele 2:540f6e142d59 158 SIECommand(SIE_CMD_SET_ADDRESS);
daniele 2:540f6e142d59 159 SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
daniele 2:540f6e142d59 160 }
daniele 2:540f6e142d59 161
daniele 2:540f6e142d59 162 static uint8_t SIEselectEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 163 // SIE select endpoint command
daniele 2:540f6e142d59 164 SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
daniele 2:540f6e142d59 165 return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
daniele 2:540f6e142d59 166 }
daniele 2:540f6e142d59 167
daniele 2:540f6e142d59 168 static uint8_t SIEclearBuffer(void) {
daniele 2:540f6e142d59 169 // SIE clear buffer command
daniele 2:540f6e142d59 170 SIECommand(SIE_CMD_CLEAR_BUFFER);
daniele 2:540f6e142d59 171 return SIEReadData(SIE_CMD_CLEAR_BUFFER);
daniele 2:540f6e142d59 172 }
daniele 2:540f6e142d59 173
daniele 2:540f6e142d59 174 static void SIEvalidateBuffer(void) {
daniele 2:540f6e142d59 175 // SIE validate buffer command
daniele 2:540f6e142d59 176 SIECommand(SIE_CMD_VALIDATE_BUFFER);
daniele 2:540f6e142d59 177 }
daniele 2:540f6e142d59 178
daniele 2:540f6e142d59 179 static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
daniele 2:540f6e142d59 180 // SIE set endpoint status command
daniele 2:540f6e142d59 181 SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
daniele 2:540f6e142d59 182 SIEWriteData(status);
daniele 2:540f6e142d59 183 }
daniele 2:540f6e142d59 184
daniele 2:540f6e142d59 185 static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
daniele 2:540f6e142d59 186 static uint16_t SIEgetFrameNumber(void) {
daniele 2:540f6e142d59 187 // Read current frame number
daniele 2:540f6e142d59 188 uint16_t lowByte;
daniele 2:540f6e142d59 189 uint16_t highByte;
daniele 2:540f6e142d59 190
daniele 2:540f6e142d59 191 SIECommand(SIE_CMD_READ_FRAME_NUMBER);
daniele 2:540f6e142d59 192 lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
daniele 2:540f6e142d59 193 highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
daniele 2:540f6e142d59 194
daniele 2:540f6e142d59 195 return (highByte << 8) | lowByte;
daniele 2:540f6e142d59 196 }
daniele 2:540f6e142d59 197
daniele 2:540f6e142d59 198 static void SIEconfigureDevice(void) {
daniele 2:540f6e142d59 199 // SIE Configure device command
daniele 2:540f6e142d59 200 SIECommand(SIE_CMD_CONFIGURE_DEVICE);
daniele 2:540f6e142d59 201 SIEWriteData(SIE_CONF_DEVICE);
daniele 2:540f6e142d59 202 }
daniele 2:540f6e142d59 203
daniele 2:540f6e142d59 204 static void SIEunconfigureDevice(void) {
daniele 2:540f6e142d59 205 // SIE Configure device command
daniele 2:540f6e142d59 206 SIECommand(SIE_CMD_CONFIGURE_DEVICE);
daniele 2:540f6e142d59 207 SIEWriteData(0);
daniele 2:540f6e142d59 208 }
daniele 2:540f6e142d59 209
daniele 2:540f6e142d59 210 static void SIEconnect(void) {
daniele 2:540f6e142d59 211 // Connect USB device
daniele 2:540f6e142d59 212 uint8_t status = SIEgetDeviceStatus();
daniele 2:540f6e142d59 213 SIEsetDeviceStatus(status | SIE_DS_CON);
daniele 2:540f6e142d59 214 }
daniele 2:540f6e142d59 215
daniele 2:540f6e142d59 216
daniele 2:540f6e142d59 217 static void SIEdisconnect(void) {
daniele 2:540f6e142d59 218 // Disconnect USB device
daniele 2:540f6e142d59 219 uint8_t status = SIEgetDeviceStatus();
daniele 2:540f6e142d59 220 SIEsetDeviceStatus(status & ~SIE_DS_CON);
daniele 2:540f6e142d59 221 }
daniele 2:540f6e142d59 222
daniele 2:540f6e142d59 223
daniele 2:540f6e142d59 224 static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
daniele 2:540f6e142d59 225 // Implemented using using EP_INT_CLR.
daniele 2:540f6e142d59 226 LPC_USB->USBEpIntClr = EP(endpoint);
daniele 2:540f6e142d59 227 while (!(LPC_USB->USBDevIntSt & CDFULL));
daniele 2:540f6e142d59 228 return (uint8_t)LPC_USB->USBCmdData;
daniele 2:540f6e142d59 229 }
daniele 2:540f6e142d59 230
daniele 2:540f6e142d59 231
daniele 2:540f6e142d59 232 static void enableEndpointEvent(uint8_t endpoint) {
daniele 2:540f6e142d59 233 // Enable an endpoint interrupt
daniele 2:540f6e142d59 234 LPC_USB->USBEpIntEn |= EP(endpoint);
daniele 2:540f6e142d59 235 }
daniele 2:540f6e142d59 236
daniele 2:540f6e142d59 237 static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
daniele 2:540f6e142d59 238 static void disableEndpointEvent(uint8_t endpoint) {
daniele 2:540f6e142d59 239 // Disable an endpoint interrupt
daniele 2:540f6e142d59 240 LPC_USB->USBEpIntEn &= ~EP(endpoint);
daniele 2:540f6e142d59 241 }
daniele 2:540f6e142d59 242
daniele 2:540f6e142d59 243 static volatile uint32_t __attribute__((used)) dummyRead;
daniele 2:540f6e142d59 244 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
daniele 2:540f6e142d59 245 // Read from an OUT endpoint
daniele 2:540f6e142d59 246 uint32_t size;
daniele 2:540f6e142d59 247 uint32_t i;
daniele 2:540f6e142d59 248 uint32_t data = 0;
daniele 2:540f6e142d59 249 uint8_t offset;
daniele 2:540f6e142d59 250
daniele 2:540f6e142d59 251 LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | RD_EN;
daniele 2:540f6e142d59 252 while (!(LPC_USB->USBRxPLen & PKT_RDY));
daniele 2:540f6e142d59 253
daniele 2:540f6e142d59 254 size = LPC_USB->USBRxPLen & PKT_LNGTH_MASK;
daniele 2:540f6e142d59 255
daniele 2:540f6e142d59 256 offset = 0;
daniele 2:540f6e142d59 257
daniele 2:540f6e142d59 258 if (size > 0) {
daniele 2:540f6e142d59 259 for (i=0; i<size; i++) {
daniele 2:540f6e142d59 260 if (offset==0) {
daniele 2:540f6e142d59 261 // Fetch up to four bytes of data as a word
daniele 2:540f6e142d59 262 data = LPC_USB->USBRxData;
daniele 2:540f6e142d59 263 }
daniele 2:540f6e142d59 264
daniele 2:540f6e142d59 265 // extract a byte
daniele 2:540f6e142d59 266 *buffer = (data>>offset) & 0xff;
daniele 2:540f6e142d59 267 buffer++;
daniele 2:540f6e142d59 268
daniele 2:540f6e142d59 269 // move on to the next byte
daniele 2:540f6e142d59 270 offset = (offset + 8) % 32;
daniele 2:540f6e142d59 271 }
daniele 2:540f6e142d59 272 } else {
daniele 2:540f6e142d59 273 dummyRead = LPC_USB->USBRxData;
daniele 2:540f6e142d59 274 }
daniele 2:540f6e142d59 275
daniele 2:540f6e142d59 276 LPC_USB->USBCtrl = 0;
daniele 2:540f6e142d59 277
daniele 2:540f6e142d59 278 if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
daniele 2:540f6e142d59 279 SIEselectEndpoint(endpoint);
daniele 2:540f6e142d59 280 SIEclearBuffer();
daniele 2:540f6e142d59 281 }
daniele 2:540f6e142d59 282
daniele 2:540f6e142d59 283 return size;
daniele 2:540f6e142d59 284 }
daniele 2:540f6e142d59 285
daniele 2:540f6e142d59 286 static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
daniele 2:540f6e142d59 287 // Write to an IN endpoint
daniele 2:540f6e142d59 288 uint32_t temp, data;
daniele 2:540f6e142d59 289 uint8_t offset;
daniele 2:540f6e142d59 290
daniele 2:540f6e142d59 291 LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | WR_EN;
daniele 2:540f6e142d59 292
daniele 2:540f6e142d59 293 LPC_USB->USBTxPLen = size;
daniele 2:540f6e142d59 294 offset = 0;
daniele 2:540f6e142d59 295 data = 0;
daniele 2:540f6e142d59 296
daniele 2:540f6e142d59 297 if (size>0) {
daniele 2:540f6e142d59 298 do {
daniele 2:540f6e142d59 299 // Fetch next data byte into a word-sized temporary variable
daniele 2:540f6e142d59 300 temp = *buffer++;
daniele 2:540f6e142d59 301
daniele 2:540f6e142d59 302 // Add to current data word
daniele 2:540f6e142d59 303 temp = temp << offset;
daniele 2:540f6e142d59 304 data = data | temp;
daniele 2:540f6e142d59 305
daniele 2:540f6e142d59 306 // move on to the next byte
daniele 2:540f6e142d59 307 offset = (offset + 8) % 32;
daniele 2:540f6e142d59 308 size--;
daniele 2:540f6e142d59 309
daniele 2:540f6e142d59 310 if ((offset==0) || (size==0)) {
daniele 2:540f6e142d59 311 // Write the word to the endpoint
daniele 2:540f6e142d59 312 LPC_USB->USBTxData = data;
daniele 2:540f6e142d59 313 data = 0;
daniele 2:540f6e142d59 314 }
daniele 2:540f6e142d59 315 } while (size>0);
daniele 2:540f6e142d59 316 } else {
daniele 2:540f6e142d59 317 LPC_USB->USBTxData = 0;
daniele 2:540f6e142d59 318 }
daniele 2:540f6e142d59 319
daniele 2:540f6e142d59 320 // Clear WR_EN to cover zero length packet case
daniele 2:540f6e142d59 321 LPC_USB->USBCtrl=0;
daniele 2:540f6e142d59 322
daniele 2:540f6e142d59 323 SIEselectEndpoint(endpoint);
daniele 2:540f6e142d59 324 SIEvalidateBuffer();
daniele 2:540f6e142d59 325 }
daniele 2:540f6e142d59 326
daniele 2:540f6e142d59 327 USBHAL::USBHAL(void) {
daniele 2:540f6e142d59 328 // Disable IRQ
daniele 2:540f6e142d59 329 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 330
daniele 2:540f6e142d59 331 // fill in callback array
daniele 2:540f6e142d59 332 epCallback[0] = &USBHAL::EP1_OUT_callback;
daniele 2:540f6e142d59 333 epCallback[1] = &USBHAL::EP1_IN_callback;
daniele 2:540f6e142d59 334 epCallback[2] = &USBHAL::EP2_OUT_callback;
daniele 2:540f6e142d59 335 epCallback[3] = &USBHAL::EP2_IN_callback;
daniele 2:540f6e142d59 336 epCallback[4] = &USBHAL::EP3_OUT_callback;
daniele 2:540f6e142d59 337 epCallback[5] = &USBHAL::EP3_IN_callback;
daniele 2:540f6e142d59 338 epCallback[6] = &USBHAL::EP4_OUT_callback;
daniele 2:540f6e142d59 339 epCallback[7] = &USBHAL::EP4_IN_callback;
daniele 2:540f6e142d59 340 epCallback[8] = &USBHAL::EP5_OUT_callback;
daniele 2:540f6e142d59 341 epCallback[9] = &USBHAL::EP5_IN_callback;
daniele 2:540f6e142d59 342 epCallback[10] = &USBHAL::EP6_OUT_callback;
daniele 2:540f6e142d59 343 epCallback[11] = &USBHAL::EP6_IN_callback;
daniele 2:540f6e142d59 344 epCallback[12] = &USBHAL::EP7_OUT_callback;
daniele 2:540f6e142d59 345 epCallback[13] = &USBHAL::EP7_IN_callback;
daniele 2:540f6e142d59 346 epCallback[14] = &USBHAL::EP8_OUT_callback;
daniele 2:540f6e142d59 347 epCallback[15] = &USBHAL::EP8_IN_callback;
daniele 2:540f6e142d59 348 epCallback[16] = &USBHAL::EP9_OUT_callback;
daniele 2:540f6e142d59 349 epCallback[17] = &USBHAL::EP9_IN_callback;
daniele 2:540f6e142d59 350 epCallback[18] = &USBHAL::EP10_OUT_callback;
daniele 2:540f6e142d59 351 epCallback[19] = &USBHAL::EP10_IN_callback;
daniele 2:540f6e142d59 352 epCallback[20] = &USBHAL::EP11_OUT_callback;
daniele 2:540f6e142d59 353 epCallback[21] = &USBHAL::EP11_IN_callback;
daniele 2:540f6e142d59 354 epCallback[22] = &USBHAL::EP12_OUT_callback;
daniele 2:540f6e142d59 355 epCallback[23] = &USBHAL::EP12_IN_callback;
daniele 2:540f6e142d59 356 epCallback[24] = &USBHAL::EP13_OUT_callback;
daniele 2:540f6e142d59 357 epCallback[25] = &USBHAL::EP13_IN_callback;
daniele 2:540f6e142d59 358 epCallback[26] = &USBHAL::EP14_OUT_callback;
daniele 2:540f6e142d59 359 epCallback[27] = &USBHAL::EP14_IN_callback;
daniele 2:540f6e142d59 360 epCallback[28] = &USBHAL::EP15_OUT_callback;
daniele 2:540f6e142d59 361 epCallback[29] = &USBHAL::EP15_IN_callback;
daniele 2:540f6e142d59 362
daniele 2:540f6e142d59 363 // Enable power to USB device controller
daniele 2:540f6e142d59 364 LPC_SC->PCONP |= PCUSB;
daniele 2:540f6e142d59 365
daniele 2:540f6e142d59 366 // Enable USB clocks
daniele 2:540f6e142d59 367 LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
daniele 2:540f6e142d59 368 while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
daniele 2:540f6e142d59 369
daniele 2:540f6e142d59 370 // Configure pins P0.29 and P0.30 to be USB D+ and USB D-
daniele 2:540f6e142d59 371 LPC_PINCON->PINSEL1 &= 0xc3ffffff;
daniele 2:540f6e142d59 372 LPC_PINCON->PINSEL1 |= 0x14000000;
daniele 2:540f6e142d59 373
daniele 2:540f6e142d59 374 // Disconnect USB device
daniele 2:540f6e142d59 375 SIEdisconnect();
daniele 2:540f6e142d59 376
daniele 2:540f6e142d59 377 // Configure pin P2.9 to be Connect
daniele 2:540f6e142d59 378 LPC_PINCON->PINSEL4 &= 0xfffcffff;
daniele 2:540f6e142d59 379 LPC_PINCON->PINSEL4 |= 0x00040000;
daniele 2:540f6e142d59 380
daniele 2:540f6e142d59 381 // Connect must be low for at least 2.5uS
daniele 2:540f6e142d59 382 wait(0.3);
daniele 2:540f6e142d59 383
daniele 2:540f6e142d59 384 // Set the maximum packet size for the control endpoints
daniele 2:540f6e142d59 385 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
daniele 2:540f6e142d59 386 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
daniele 2:540f6e142d59 387
daniele 2:540f6e142d59 388 // Attach IRQ
daniele 2:540f6e142d59 389 instance = this;
daniele 2:540f6e142d59 390 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
daniele 2:540f6e142d59 391
daniele 2:540f6e142d59 392 // Enable interrupts for device events and EP0
daniele 2:540f6e142d59 393 LPC_USB->USBDevIntEn = EP_SLOW | DEV_STAT | FRAME;
daniele 2:540f6e142d59 394 enableEndpointEvent(EP0IN);
daniele 2:540f6e142d59 395 enableEndpointEvent(EP0OUT);
daniele 2:540f6e142d59 396 }
daniele 2:540f6e142d59 397
daniele 2:540f6e142d59 398 USBHAL::~USBHAL(void) {
daniele 2:540f6e142d59 399 // Ensure device disconnected
daniele 2:540f6e142d59 400 SIEdisconnect();
daniele 2:540f6e142d59 401 // Disable USB interrupts
daniele 2:540f6e142d59 402 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 403 }
daniele 2:540f6e142d59 404
daniele 2:540f6e142d59 405 void USBHAL::connect(void) {
daniele 2:540f6e142d59 406 NVIC_EnableIRQ(USB_IRQn);
daniele 2:540f6e142d59 407 // Connect USB device
daniele 2:540f6e142d59 408 SIEconnect();
daniele 2:540f6e142d59 409 }
daniele 2:540f6e142d59 410
daniele 2:540f6e142d59 411 void USBHAL::disconnect(void) {
daniele 2:540f6e142d59 412 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 413 // Disconnect USB device
daniele 2:540f6e142d59 414 SIEdisconnect();
daniele 2:540f6e142d59 415 }
daniele 2:540f6e142d59 416
daniele 2:540f6e142d59 417 void USBHAL::configureDevice(void) {
daniele 2:540f6e142d59 418 SIEconfigureDevice();
daniele 2:540f6e142d59 419 }
daniele 2:540f6e142d59 420
daniele 2:540f6e142d59 421 void USBHAL::unconfigureDevice(void) {
daniele 2:540f6e142d59 422 SIEunconfigureDevice();
daniele 2:540f6e142d59 423 }
daniele 2:540f6e142d59 424
daniele 2:540f6e142d59 425 void USBHAL::setAddress(uint8_t address) {
daniele 2:540f6e142d59 426 SIEsetAddress(address);
daniele 2:540f6e142d59 427 }
daniele 2:540f6e142d59 428
daniele 2:540f6e142d59 429 void USBHAL::EP0setup(uint8_t *buffer) {
daniele 2:540f6e142d59 430 endpointReadcore(EP0OUT, buffer);
daniele 2:540f6e142d59 431 }
daniele 2:540f6e142d59 432
daniele 2:540f6e142d59 433 void USBHAL::EP0read(void) {
daniele 2:540f6e142d59 434 // Not required
daniele 2:540f6e142d59 435 }
daniele 2:540f6e142d59 436
daniele 2:540f6e142d59 437 void USBHAL::EP0readStage(void) {
daniele 2:540f6e142d59 438 // Not required
daniele 2:540f6e142d59 439 }
daniele 2:540f6e142d59 440
daniele 2:540f6e142d59 441 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
daniele 2:540f6e142d59 442 return endpointReadcore(EP0OUT, buffer);
daniele 2:540f6e142d59 443 }
daniele 2:540f6e142d59 444
daniele 2:540f6e142d59 445 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
daniele 2:540f6e142d59 446 endpointWritecore(EP0IN, buffer, size);
daniele 2:540f6e142d59 447 }
daniele 2:540f6e142d59 448
daniele 2:540f6e142d59 449 void USBHAL::EP0getWriteResult(void) {
daniele 2:540f6e142d59 450 // Not required
daniele 2:540f6e142d59 451 }
daniele 2:540f6e142d59 452
daniele 2:540f6e142d59 453 void USBHAL::EP0stall(void) {
daniele 2:540f6e142d59 454 // This will stall both control endpoints
daniele 2:540f6e142d59 455 stallEndpoint(EP0OUT);
daniele 2:540f6e142d59 456 }
daniele 2:540f6e142d59 457
daniele 2:540f6e142d59 458 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
daniele 2:540f6e142d59 459 return EP_PENDING;
daniele 2:540f6e142d59 460 }
daniele 2:540f6e142d59 461
daniele 2:540f6e142d59 462 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
daniele 2:540f6e142d59 463
daniele 2:540f6e142d59 464 //for isochronous endpoint, we don't wait an interrupt
daniele 2:540f6e142d59 465 if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
daniele 2:540f6e142d59 466 if (!(epComplete & EP(endpoint)))
daniele 2:540f6e142d59 467 return EP_PENDING;
daniele 2:540f6e142d59 468 }
daniele 2:540f6e142d59 469
daniele 2:540f6e142d59 470 *bytesRead = endpointReadcore(endpoint, buffer);
daniele 2:540f6e142d59 471 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 472 return EP_COMPLETED;
daniele 2:540f6e142d59 473 }
daniele 2:540f6e142d59 474
daniele 2:540f6e142d59 475 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
daniele 2:540f6e142d59 476 if (getEndpointStallState(endpoint)) {
daniele 2:540f6e142d59 477 return EP_STALLED;
daniele 2:540f6e142d59 478 }
daniele 2:540f6e142d59 479
daniele 2:540f6e142d59 480 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 481
daniele 2:540f6e142d59 482 endpointWritecore(endpoint, data, size);
daniele 2:540f6e142d59 483 return EP_PENDING;
daniele 2:540f6e142d59 484 }
daniele 2:540f6e142d59 485
daniele 2:540f6e142d59 486 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
daniele 2:540f6e142d59 487 if (epComplete & EP(endpoint)) {
daniele 2:540f6e142d59 488 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 489 return EP_COMPLETED;
daniele 2:540f6e142d59 490 }
daniele 2:540f6e142d59 491
daniele 2:540f6e142d59 492 return EP_PENDING;
daniele 2:540f6e142d59 493 }
daniele 2:540f6e142d59 494
daniele 2:540f6e142d59 495 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
daniele 2:540f6e142d59 496 // Realise an endpoint
daniele 2:540f6e142d59 497 LPC_USB->USBDevIntClr = EP_RLZED;
daniele 2:540f6e142d59 498 LPC_USB->USBReEp |= EP(endpoint);
daniele 2:540f6e142d59 499 LPC_USB->USBEpInd = endpoint;
daniele 2:540f6e142d59 500 LPC_USB->USBMaxPSize = maxPacket;
daniele 2:540f6e142d59 501
daniele 2:540f6e142d59 502 while (!(LPC_USB->USBDevIntSt & EP_RLZED));
daniele 2:540f6e142d59 503 LPC_USB->USBDevIntClr = EP_RLZED;
daniele 2:540f6e142d59 504
daniele 2:540f6e142d59 505 // Clear stall state
daniele 2:540f6e142d59 506 endpointStallState &= ~EP(endpoint);
daniele 2:540f6e142d59 507
daniele 2:540f6e142d59 508 enableEndpointEvent(endpoint);
daniele 2:540f6e142d59 509 return true;
daniele 2:540f6e142d59 510 }
daniele 2:540f6e142d59 511
daniele 2:540f6e142d59 512 void USBHAL::stallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 513 // Stall an endpoint
daniele 2:540f6e142d59 514 if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
daniele 2:540f6e142d59 515 // Conditionally stall both control endpoints
daniele 2:540f6e142d59 516 SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
daniele 2:540f6e142d59 517 } else {
daniele 2:540f6e142d59 518 SIEsetEndpointStatus(endpoint, SIE_SES_ST);
daniele 2:540f6e142d59 519
daniele 2:540f6e142d59 520 // Update stall state
daniele 2:540f6e142d59 521 endpointStallState |= EP(endpoint);
daniele 2:540f6e142d59 522 }
daniele 2:540f6e142d59 523 }
daniele 2:540f6e142d59 524
daniele 2:540f6e142d59 525 void USBHAL::unstallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 526 // Unstall an endpoint. The endpoint will also be reinitialised
daniele 2:540f6e142d59 527 SIEsetEndpointStatus(endpoint, 0);
daniele 2:540f6e142d59 528
daniele 2:540f6e142d59 529 // Update stall state
daniele 2:540f6e142d59 530 endpointStallState &= ~EP(endpoint);
daniele 2:540f6e142d59 531 }
daniele 2:540f6e142d59 532
daniele 2:540f6e142d59 533 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
daniele 2:540f6e142d59 534 // Returns true if endpoint stalled
daniele 2:540f6e142d59 535 return endpointStallState & EP(endpoint);
daniele 2:540f6e142d59 536 }
daniele 2:540f6e142d59 537
daniele 2:540f6e142d59 538 void USBHAL::remoteWakeup(void) {
daniele 2:540f6e142d59 539 // Remote wakeup
daniele 2:540f6e142d59 540 uint8_t status;
daniele 2:540f6e142d59 541
daniele 2:540f6e142d59 542 // Enable USB clocks
daniele 2:540f6e142d59 543 LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
daniele 2:540f6e142d59 544 while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
daniele 2:540f6e142d59 545
daniele 2:540f6e142d59 546 status = SIEgetDeviceStatus();
daniele 2:540f6e142d59 547 SIEsetDeviceStatus(status & ~SIE_DS_SUS);
daniele 2:540f6e142d59 548 }
daniele 2:540f6e142d59 549
daniele 2:540f6e142d59 550 void USBHAL::_usbisr(void) {
daniele 2:540f6e142d59 551 instance->usbisr();
daniele 2:540f6e142d59 552 }
daniele 2:540f6e142d59 553
daniele 2:540f6e142d59 554
daniele 2:540f6e142d59 555 void USBHAL::usbisr(void) {
daniele 2:540f6e142d59 556 uint8_t devStat;
daniele 2:540f6e142d59 557
daniele 2:540f6e142d59 558 if (LPC_USB->USBDevIntSt & FRAME) {
daniele 2:540f6e142d59 559 // Start of frame event
daniele 2:540f6e142d59 560 SOF(SIEgetFrameNumber());
daniele 2:540f6e142d59 561 // Clear interrupt status flag
daniele 2:540f6e142d59 562 LPC_USB->USBDevIntClr = FRAME;
daniele 2:540f6e142d59 563 }
daniele 2:540f6e142d59 564
daniele 2:540f6e142d59 565 if (LPC_USB->USBDevIntSt & DEV_STAT) {
daniele 2:540f6e142d59 566 // Device Status interrupt
daniele 2:540f6e142d59 567 // Must clear the interrupt status flag before reading the device status from the SIE
daniele 2:540f6e142d59 568 LPC_USB->USBDevIntClr = DEV_STAT;
daniele 2:540f6e142d59 569
daniele 2:540f6e142d59 570 // Read device status from SIE
daniele 2:540f6e142d59 571 devStat = SIEgetDeviceStatus();
daniele 2:540f6e142d59 572 //printf("devStat: %d\r\n", devStat);
daniele 2:540f6e142d59 573
daniele 2:540f6e142d59 574 if (devStat & SIE_DS_SUS_CH) {
daniele 2:540f6e142d59 575 // Suspend status changed
daniele 2:540f6e142d59 576 if((devStat & SIE_DS_SUS) != 0) {
daniele 2:540f6e142d59 577 suspendStateChanged(0);
daniele 2:540f6e142d59 578 }
daniele 2:540f6e142d59 579 }
daniele 2:540f6e142d59 580
daniele 2:540f6e142d59 581 if (devStat & SIE_DS_RST) {
daniele 2:540f6e142d59 582 // Bus reset
daniele 2:540f6e142d59 583 if((devStat & SIE_DS_SUS) == 0) {
daniele 2:540f6e142d59 584 suspendStateChanged(1);
daniele 2:540f6e142d59 585 }
daniele 2:540f6e142d59 586 busReset();
daniele 2:540f6e142d59 587 }
daniele 2:540f6e142d59 588 }
daniele 2:540f6e142d59 589
daniele 2:540f6e142d59 590 if (LPC_USB->USBDevIntSt & EP_SLOW) {
daniele 2:540f6e142d59 591 // (Slow) Endpoint Interrupt
daniele 2:540f6e142d59 592
daniele 2:540f6e142d59 593 // Process each endpoint interrupt
daniele 2:540f6e142d59 594 if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
daniele 2:540f6e142d59 595 if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
daniele 2:540f6e142d59 596 // this is a setup packet
daniele 2:540f6e142d59 597 EP0setupCallback();
daniele 2:540f6e142d59 598 } else {
daniele 2:540f6e142d59 599 EP0out();
daniele 2:540f6e142d59 600 }
daniele 2:540f6e142d59 601 LPC_USB->USBDevIntClr = EP_SLOW;
daniele 2:540f6e142d59 602 }
daniele 2:540f6e142d59 603
daniele 2:540f6e142d59 604 if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
daniele 2:540f6e142d59 605 selectEndpointClearInterrupt(EP0IN);
daniele 2:540f6e142d59 606 LPC_USB->USBDevIntClr = EP_SLOW;
daniele 2:540f6e142d59 607 EP0in();
daniele 2:540f6e142d59 608 }
daniele 2:540f6e142d59 609
daniele 2:540f6e142d59 610 for (uint8_t num = 2; num < 16*2; num++) {
daniele 2:540f6e142d59 611 if (LPC_USB->USBEpIntSt & EP(num)) {
daniele 2:540f6e142d59 612 selectEndpointClearInterrupt(num);
daniele 2:540f6e142d59 613 epComplete |= EP(num);
daniele 2:540f6e142d59 614 LPC_USB->USBDevIntClr = EP_SLOW;
daniele 2:540f6e142d59 615 if ((instance->*(epCallback[num - 2]))()) {
daniele 2:540f6e142d59 616 epComplete &= ~EP(num);
daniele 2:540f6e142d59 617 }
daniele 2:540f6e142d59 618 }
daniele 2:540f6e142d59 619 }
daniele 2:540f6e142d59 620 }
daniele 2:540f6e142d59 621 }
daniele 2:540f6e142d59 622
daniele 2:540f6e142d59 623 #endif