Daniele Lacamera / USB_Ethernet

CDC/ECM driver for mbed, based on USBDevice by mbed-official. Uses PicoTCP to access Ethernet USB device. License: GPLv2

Dependents:   USBEthernet_TEST

Fork of USB_Ethernet by Daniele Lacamera

USBDevice/USBHAL_LPC11U.cpp@2:540f6e142d59, 2013-08-03 (annotated)

Committer:
daniele
Date:
Sat Aug 03 13:16:14 2013 +0000
Revision:
2:540f6e142d59
Moved to single package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniele 2:540f6e142d59 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
daniele 2:540f6e142d59 2 *
daniele 2:540f6e142d59 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
daniele 2:540f6e142d59 4 * and associated documentation files (the "Software"), to deal in the Software without
daniele 2:540f6e142d59 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
daniele 2:540f6e142d59 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
daniele 2:540f6e142d59 7 * Software is furnished to do so, subject to the following conditions:
daniele 2:540f6e142d59 8 *
daniele 2:540f6e142d59 9 * The above copyright notice and this permission notice shall be included in all copies or
daniele 2:540f6e142d59 10 * substantial portions of the Software.
daniele 2:540f6e142d59 11 *
daniele 2:540f6e142d59 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
daniele 2:540f6e142d59 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
daniele 2:540f6e142d59 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
daniele 2:540f6e142d59 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
daniele 2:540f6e142d59 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
daniele 2:540f6e142d59 17 */
daniele 2:540f6e142d59 18
daniele 2:540f6e142d59 19 #ifdef TARGET_LPC11U24
daniele 2:540f6e142d59 20
daniele 2:540f6e142d59 21 #include "USBHAL.h"
daniele 2:540f6e142d59 22
daniele 2:540f6e142d59 23 USBHAL * USBHAL::instance;
daniele 2:540f6e142d59 24
daniele 2:540f6e142d59 25 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
daniele 2:540f6e142d59 26 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
daniele 2:540f6e142d59 27
daniele 2:540f6e142d59 28 // Convert physical endpoint number to register bit
daniele 2:540f6e142d59 29 #define EP(endpoint) (1UL<<endpoint)
daniele 2:540f6e142d59 30
daniele 2:540f6e142d59 31 // Convert physical to logical
daniele 2:540f6e142d59 32 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
daniele 2:540f6e142d59 33
daniele 2:540f6e142d59 34 // Get endpoint direction
daniele 2:540f6e142d59 35 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
daniele 2:540f6e142d59 36 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
daniele 2:540f6e142d59 37
daniele 2:540f6e142d59 38 // USB RAM
daniele 2:540f6e142d59 39 #define USB_RAM_START (0x20004000)
daniele 2:540f6e142d59 40 #define USB_RAM_SIZE (0x00000800)
daniele 2:540f6e142d59 41
daniele 2:540f6e142d59 42 // SYSAHBCLKCTRL
daniele 2:540f6e142d59 43 #define CLK_USB (1UL<<14)
daniele 2:540f6e142d59 44 #define CLK_USBRAM (1UL<<27)
daniele 2:540f6e142d59 45
daniele 2:540f6e142d59 46 // USB Information register
daniele 2:540f6e142d59 47 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
daniele 2:540f6e142d59 48
daniele 2:540f6e142d59 49 // USB Device Command/Status register
daniele 2:540f6e142d59 50 #define DEV_ADDR_MASK (0x7f) // Device address
daniele 2:540f6e142d59 51 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
daniele 2:540f6e142d59 52 #define DEV_EN (1UL<<7) // Device enable
daniele 2:540f6e142d59 53 #define SETUP (1UL<<8) // SETUP token received
daniele 2:540f6e142d59 54 #define PLL_ON (1UL<<9) // PLL enabled in suspend
daniele 2:540f6e142d59 55 #define DCON (1UL<<16) // Device status - connect
daniele 2:540f6e142d59 56 #define DSUS (1UL<<17) // Device status - suspend
daniele 2:540f6e142d59 57 #define DCON_C (1UL<<24) // Connect change
daniele 2:540f6e142d59 58 #define DSUS_C (1UL<<25) // Suspend change
daniele 2:540f6e142d59 59 #define DRES_C (1UL<<26) // Reset change
daniele 2:540f6e142d59 60 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
daniele 2:540f6e142d59 61
daniele 2:540f6e142d59 62 // Endpoint Command/Status list
daniele 2:540f6e142d59 63 #define CMDSTS_A (1UL<<31) // Active
daniele 2:540f6e142d59 64 #define CMDSTS_D (1UL<<30) // Disable
daniele 2:540f6e142d59 65 #define CMDSTS_S (1UL<<29) // Stall
daniele 2:540f6e142d59 66 #define CMDSTS_TR (1UL<<28) // Toggle Reset
daniele 2:540f6e142d59 67 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
daniele 2:540f6e142d59 68 #define CMDSTS_TV (1UL<<27) // Toggle Value
daniele 2:540f6e142d59 69 #define CMDSTS_T (1UL<<26) // Endpoint Type
daniele 2:540f6e142d59 70 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
daniele 2:540f6e142d59 71 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
daniele 2:540f6e142d59 72
daniele 2:540f6e142d59 73 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
daniele 2:540f6e142d59 74
daniele 2:540f6e142d59 75 // USB Non-endpoint interrupt sources
daniele 2:540f6e142d59 76 #define FRAME_INT (1UL<<30)
daniele 2:540f6e142d59 77 #define DEV_INT (1UL<<31)
daniele 2:540f6e142d59 78
daniele 2:540f6e142d59 79 static volatile int epComplete = 0;
daniele 2:540f6e142d59 80
daniele 2:540f6e142d59 81 // One entry for a double-buffered logical endpoint in the endpoint
daniele 2:540f6e142d59 82 // command/status list. Endpoint 0 is single buffered, out[1] is used
daniele 2:540f6e142d59 83 // for the SETUP packet and in[1] is not used
daniele 2:540f6e142d59 84 typedef __packed struct {
daniele 2:540f6e142d59 85 uint32_t out[2];
daniele 2:540f6e142d59 86 uint32_t in[2];
daniele 2:540f6e142d59 87 } EP_COMMAND_STATUS;
daniele 2:540f6e142d59 88
daniele 2:540f6e142d59 89 typedef __packed struct {
daniele 2:540f6e142d59 90 uint8_t out[MAX_PACKET_SIZE_EP0];
daniele 2:540f6e142d59 91 uint8_t in[MAX_PACKET_SIZE_EP0];
daniele 2:540f6e142d59 92 uint8_t setup[SETUP_PACKET_SIZE];
daniele 2:540f6e142d59 93 } CONTROL_TRANSFER;
daniele 2:540f6e142d59 94
daniele 2:540f6e142d59 95 typedef __packed struct {
daniele 2:540f6e142d59 96 uint32_t maxPacket;
daniele 2:540f6e142d59 97 uint32_t buffer[2];
daniele 2:540f6e142d59 98 uint32_t options;
daniele 2:540f6e142d59 99 } EP_STATE;
daniele 2:540f6e142d59 100
daniele 2:540f6e142d59 101 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
daniele 2:540f6e142d59 102
daniele 2:540f6e142d59 103 // Pointer to the endpoint command/status list
daniele 2:540f6e142d59 104 static EP_COMMAND_STATUS *ep = NULL;
daniele 2:540f6e142d59 105
daniele 2:540f6e142d59 106 // Pointer to endpoint 0 data (IN/OUT and SETUP)
daniele 2:540f6e142d59 107 static CONTROL_TRANSFER *ct = NULL;
daniele 2:540f6e142d59 108
daniele 2:540f6e142d59 109 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
daniele 2:540f6e142d59 110 // initiating a remote wakeup event.
daniele 2:540f6e142d59 111 static volatile uint32_t devCmdStat;
daniele 2:540f6e142d59 112
daniele 2:540f6e142d59 113 // Pointers used to allocate USB RAM
daniele 2:540f6e142d59 114 static uint32_t usbRamPtr = USB_RAM_START;
daniele 2:540f6e142d59 115 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
daniele 2:540f6e142d59 116
daniele 2:540f6e142d59 117 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
daniele 2:540f6e142d59 118
daniele 2:540f6e142d59 119 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
daniele 2:540f6e142d59 120 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
daniele 2:540f6e142d59 121 if (size > 0) {
daniele 2:540f6e142d59 122 do {
daniele 2:540f6e142d59 123 *dst++ = *src++;
daniele 2:540f6e142d59 124 } while (--size > 0);
daniele 2:540f6e142d59 125 }
daniele 2:540f6e142d59 126 }
daniele 2:540f6e142d59 127
daniele 2:540f6e142d59 128
daniele 2:540f6e142d59 129 USBHAL::USBHAL(void) {
daniele 2:540f6e142d59 130 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 131
daniele 2:540f6e142d59 132 // fill in callback array
daniele 2:540f6e142d59 133 epCallback[0] = &USBHAL::EP1_OUT_callback;
daniele 2:540f6e142d59 134 epCallback[1] = &USBHAL::EP1_IN_callback;
daniele 2:540f6e142d59 135 epCallback[2] = &USBHAL::EP2_OUT_callback;
daniele 2:540f6e142d59 136 epCallback[3] = &USBHAL::EP2_IN_callback;
daniele 2:540f6e142d59 137 epCallback[4] = &USBHAL::EP3_OUT_callback;
daniele 2:540f6e142d59 138 epCallback[5] = &USBHAL::EP3_IN_callback;
daniele 2:540f6e142d59 139 epCallback[6] = &USBHAL::EP4_OUT_callback;
daniele 2:540f6e142d59 140 epCallback[7] = &USBHAL::EP4_IN_callback;
daniele 2:540f6e142d59 141
daniele 2:540f6e142d59 142 // nUSB_CONNECT output
daniele 2:540f6e142d59 143 LPC_IOCON->PIO0_6 = 0x00000001;
daniele 2:540f6e142d59 144
daniele 2:540f6e142d59 145 // Enable clocks (USB registers, USB RAM)
daniele 2:540f6e142d59 146 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
daniele 2:540f6e142d59 147
daniele 2:540f6e142d59 148 // Ensure device disconnected (DCON not set)
daniele 2:540f6e142d59 149 LPC_USB->DEVCMDSTAT = 0;
daniele 2:540f6e142d59 150
daniele 2:540f6e142d59 151 // to ensure that the USB host sees the device as
daniele 2:540f6e142d59 152 // disconnected if the target CPU is reset.
daniele 2:540f6e142d59 153 wait(0.3);
daniele 2:540f6e142d59 154
daniele 2:540f6e142d59 155 // Reserve space in USB RAM for endpoint command/status list
daniele 2:540f6e142d59 156 // Must be 256 byte aligned
daniele 2:540f6e142d59 157 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
daniele 2:540f6e142d59 158 ep = (EP_COMMAND_STATUS *)usbRamPtr;
daniele 2:540f6e142d59 159 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
daniele 2:540f6e142d59 160 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
daniele 2:540f6e142d59 161
daniele 2:540f6e142d59 162 // Reserve space in USB RAM for Endpoint 0
daniele 2:540f6e142d59 163 // Must be 64 byte aligned
daniele 2:540f6e142d59 164 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
daniele 2:540f6e142d59 165 ct = (CONTROL_TRANSFER *)usbRamPtr;
daniele 2:540f6e142d59 166 usbRamPtr += sizeof(CONTROL_TRANSFER);
daniele 2:540f6e142d59 167 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
daniele 2:540f6e142d59 168
daniele 2:540f6e142d59 169 // Setup command/status list for EP0
daniele 2:540f6e142d59 170 ep[0].out[0] = 0;
daniele 2:540f6e142d59 171 ep[0].in[0] = 0;
daniele 2:540f6e142d59 172 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
daniele 2:540f6e142d59 173
daniele 2:540f6e142d59 174 // Route all interrupts to IRQ, some can be routed to
daniele 2:540f6e142d59 175 // USB_FIQ if you wish.
daniele 2:540f6e142d59 176 LPC_USB->INTROUTING = 0;
daniele 2:540f6e142d59 177
daniele 2:540f6e142d59 178 // Set device address 0, enable USB device, no remote wakeup
daniele 2:540f6e142d59 179 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
daniele 2:540f6e142d59 180 LPC_USB->DEVCMDSTAT = devCmdStat;
daniele 2:540f6e142d59 181
daniele 2:540f6e142d59 182 // Enable interrupts for device events and EP0
daniele 2:540f6e142d59 183 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
daniele 2:540f6e142d59 184 instance = this;
daniele 2:540f6e142d59 185
daniele 2:540f6e142d59 186 //attach IRQ handler and enable interrupts
daniele 2:540f6e142d59 187 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
daniele 2:540f6e142d59 188 }
daniele 2:540f6e142d59 189
daniele 2:540f6e142d59 190 USBHAL::~USBHAL(void) {
daniele 2:540f6e142d59 191 // Ensure device disconnected (DCON not set)
daniele 2:540f6e142d59 192 LPC_USB->DEVCMDSTAT = 0;
daniele 2:540f6e142d59 193 // Disable USB interrupts
daniele 2:540f6e142d59 194 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 195 }
daniele 2:540f6e142d59 196
daniele 2:540f6e142d59 197 void USBHAL::connect(void) {
daniele 2:540f6e142d59 198 NVIC_EnableIRQ(USB_IRQn);
daniele 2:540f6e142d59 199 devCmdStat |= DCON;
daniele 2:540f6e142d59 200 LPC_USB->DEVCMDSTAT = devCmdStat;
daniele 2:540f6e142d59 201 }
daniele 2:540f6e142d59 202
daniele 2:540f6e142d59 203 void USBHAL::disconnect(void) {
daniele 2:540f6e142d59 204 NVIC_DisableIRQ(USB_IRQn);
daniele 2:540f6e142d59 205 devCmdStat &= ~DCON;
daniele 2:540f6e142d59 206 LPC_USB->DEVCMDSTAT = devCmdStat;
daniele 2:540f6e142d59 207 }
daniele 2:540f6e142d59 208
daniele 2:540f6e142d59 209 void USBHAL::configureDevice(void) {
daniele 2:540f6e142d59 210 // Not required
daniele 2:540f6e142d59 211 }
daniele 2:540f6e142d59 212
daniele 2:540f6e142d59 213 void USBHAL::unconfigureDevice(void) {
daniele 2:540f6e142d59 214 // Not required
daniele 2:540f6e142d59 215 }
daniele 2:540f6e142d59 216
daniele 2:540f6e142d59 217 void USBHAL::EP0setup(uint8_t *buffer) {
daniele 2:540f6e142d59 218 // Copy setup packet data
daniele 2:540f6e142d59 219 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
daniele 2:540f6e142d59 220 }
daniele 2:540f6e142d59 221
daniele 2:540f6e142d59 222 void USBHAL::EP0read(void) {
daniele 2:540f6e142d59 223 // Start an endpoint 0 read
daniele 2:540f6e142d59 224
daniele 2:540f6e142d59 225 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
daniele 2:540f6e142d59 226 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
daniele 2:540f6e142d59 227 // read the data.
daniele 2:540f6e142d59 228
daniele 2:540f6e142d59 229 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
daniele 2:540f6e142d59 230 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
daniele 2:540f6e142d59 231 }
daniele 2:540f6e142d59 232
daniele 2:540f6e142d59 233 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
daniele 2:540f6e142d59 234 // Complete an endpoint 0 read
daniele 2:540f6e142d59 235 uint32_t bytesRead;
daniele 2:540f6e142d59 236
daniele 2:540f6e142d59 237 // Find how many bytes were read
daniele 2:540f6e142d59 238 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
daniele 2:540f6e142d59 239
daniele 2:540f6e142d59 240 // Copy data
daniele 2:540f6e142d59 241 USBMemCopy(buffer, ct->out, bytesRead);
daniele 2:540f6e142d59 242 return bytesRead;
daniele 2:540f6e142d59 243 }
daniele 2:540f6e142d59 244
daniele 2:540f6e142d59 245
daniele 2:540f6e142d59 246 void USBHAL::EP0readStage(void) {
daniele 2:540f6e142d59 247 // Not required
daniele 2:540f6e142d59 248 }
daniele 2:540f6e142d59 249
daniele 2:540f6e142d59 250 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
daniele 2:540f6e142d59 251 // Start and endpoint 0 write
daniele 2:540f6e142d59 252
daniele 2:540f6e142d59 253 // The USB ISR will call USBDevice_EP0in() when the data has
daniele 2:540f6e142d59 254 // been written, the USBDevice layer then calls
daniele 2:540f6e142d59 255 // USBBusInterface_EP0getWriteResult() to complete the transaction.
daniele 2:540f6e142d59 256
daniele 2:540f6e142d59 257 // Copy data
daniele 2:540f6e142d59 258 USBMemCopy(ct->in, buffer, size);
daniele 2:540f6e142d59 259
daniele 2:540f6e142d59 260 // Start transfer
daniele 2:540f6e142d59 261 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
daniele 2:540f6e142d59 262 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
daniele 2:540f6e142d59 263 }
daniele 2:540f6e142d59 264
daniele 2:540f6e142d59 265
daniele 2:540f6e142d59 266 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
daniele 2:540f6e142d59 267 uint8_t bf = 0;
daniele 2:540f6e142d59 268 uint32_t flags = 0;
daniele 2:540f6e142d59 269
daniele 2:540f6e142d59 270 //check which buffer must be filled
daniele 2:540f6e142d59 271 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
daniele 2:540f6e142d59 272 // Double buffered
daniele 2:540f6e142d59 273 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 274 bf = 1;
daniele 2:540f6e142d59 275 } else {
daniele 2:540f6e142d59 276 bf = 0;
daniele 2:540f6e142d59 277 }
daniele 2:540f6e142d59 278 }
daniele 2:540f6e142d59 279
daniele 2:540f6e142d59 280 // if isochronous endpoint, T = 1
daniele 2:540f6e142d59 281 if(endpointState[endpoint].options & ISOCHRONOUS)
daniele 2:540f6e142d59 282 {
daniele 2:540f6e142d59 283 flags |= CMDSTS_T;
daniele 2:540f6e142d59 284 }
daniele 2:540f6e142d59 285
daniele 2:540f6e142d59 286 //Active the endpoint for reading
daniele 2:540f6e142d59 287 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
daniele 2:540f6e142d59 288 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
daniele 2:540f6e142d59 289 return EP_PENDING;
daniele 2:540f6e142d59 290 }
daniele 2:540f6e142d59 291
daniele 2:540f6e142d59 292 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
daniele 2:540f6e142d59 293
daniele 2:540f6e142d59 294 uint8_t bf = 0;
daniele 2:540f6e142d59 295
daniele 2:540f6e142d59 296 if (!(epComplete & EP(endpoint)))
daniele 2:540f6e142d59 297 return EP_PENDING;
daniele 2:540f6e142d59 298 else {
daniele 2:540f6e142d59 299 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 300
daniele 2:540f6e142d59 301 //check which buffer has been filled
daniele 2:540f6e142d59 302 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
daniele 2:540f6e142d59 303 // Double buffered (here we read the previous buffer which was used)
daniele 2:540f6e142d59 304 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 305 bf = 0;
daniele 2:540f6e142d59 306 } else {
daniele 2:540f6e142d59 307 bf = 1;
daniele 2:540f6e142d59 308 }
daniele 2:540f6e142d59 309 }
daniele 2:540f6e142d59 310
daniele 2:540f6e142d59 311 // Find how many bytes were read
daniele 2:540f6e142d59 312 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
daniele 2:540f6e142d59 313
daniele 2:540f6e142d59 314 // Copy data
daniele 2:540f6e142d59 315 USBMemCopy(data, ct->out, *bytesRead);
daniele 2:540f6e142d59 316 return EP_COMPLETED;
daniele 2:540f6e142d59 317 }
daniele 2:540f6e142d59 318 }
daniele 2:540f6e142d59 319
daniele 2:540f6e142d59 320 void USBHAL::EP0getWriteResult(void) {
daniele 2:540f6e142d59 321 // Not required
daniele 2:540f6e142d59 322 }
daniele 2:540f6e142d59 323
daniele 2:540f6e142d59 324 void USBHAL::EP0stall(void) {
daniele 2:540f6e142d59 325 ep[0].in[0] = CMDSTS_S;
daniele 2:540f6e142d59 326 ep[0].out[0] = CMDSTS_S;
daniele 2:540f6e142d59 327 }
daniele 2:540f6e142d59 328
daniele 2:540f6e142d59 329 void USBHAL::setAddress(uint8_t address) {
daniele 2:540f6e142d59 330 devCmdStat &= ~DEV_ADDR_MASK;
daniele 2:540f6e142d59 331 devCmdStat |= DEV_ADDR(address);
daniele 2:540f6e142d59 332 LPC_USB->DEVCMDSTAT = devCmdStat;
daniele 2:540f6e142d59 333 }
daniele 2:540f6e142d59 334
daniele 2:540f6e142d59 335 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
daniele 2:540f6e142d59 336 uint32_t flags = 0;
daniele 2:540f6e142d59 337 uint32_t bf;
daniele 2:540f6e142d59 338
daniele 2:540f6e142d59 339 // Validate parameters
daniele 2:540f6e142d59 340 if (data == NULL) {
daniele 2:540f6e142d59 341 return EP_INVALID;
daniele 2:540f6e142d59 342 }
daniele 2:540f6e142d59 343
daniele 2:540f6e142d59 344 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
daniele 2:540f6e142d59 345 return EP_INVALID;
daniele 2:540f6e142d59 346 }
daniele 2:540f6e142d59 347
daniele 2:540f6e142d59 348 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
daniele 2:540f6e142d59 349 return EP_INVALID;
daniele 2:540f6e142d59 350 }
daniele 2:540f6e142d59 351
daniele 2:540f6e142d59 352 if (size > endpointState[endpoint].maxPacket) {
daniele 2:540f6e142d59 353 return EP_INVALID;
daniele 2:540f6e142d59 354 }
daniele 2:540f6e142d59 355
daniele 2:540f6e142d59 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
daniele 2:540f6e142d59 357 // Double buffered
daniele 2:540f6e142d59 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 359 bf = 1;
daniele 2:540f6e142d59 360 } else {
daniele 2:540f6e142d59 361 bf = 0;
daniele 2:540f6e142d59 362 }
daniele 2:540f6e142d59 363 } else {
daniele 2:540f6e142d59 364 // Single buffered
daniele 2:540f6e142d59 365 bf = 0;
daniele 2:540f6e142d59 366 }
daniele 2:540f6e142d59 367
daniele 2:540f6e142d59 368 // Check if already active
daniele 2:540f6e142d59 369 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
daniele 2:540f6e142d59 370 return EP_INVALID;
daniele 2:540f6e142d59 371 }
daniele 2:540f6e142d59 372
daniele 2:540f6e142d59 373 // Check if stalled
daniele 2:540f6e142d59 374 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
daniele 2:540f6e142d59 375 return EP_STALLED;
daniele 2:540f6e142d59 376 }
daniele 2:540f6e142d59 377
daniele 2:540f6e142d59 378 // Copy data to USB RAM
daniele 2:540f6e142d59 379 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
daniele 2:540f6e142d59 380
daniele 2:540f6e142d59 381 // Add options
daniele 2:540f6e142d59 382 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
daniele 2:540f6e142d59 383 flags |= CMDSTS_RF;
daniele 2:540f6e142d59 384 }
daniele 2:540f6e142d59 385
daniele 2:540f6e142d59 386 if (endpointState[endpoint].options & ISOCHRONOUS) {
daniele 2:540f6e142d59 387 flags |= CMDSTS_T;
daniele 2:540f6e142d59 388 }
daniele 2:540f6e142d59 389
daniele 2:540f6e142d59 390 // Add transfer
daniele 2:540f6e142d59 391 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
daniele 2:540f6e142d59 392 endpointState[endpoint].buffer[bf]) \
daniele 2:540f6e142d59 393 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
daniele 2:540f6e142d59 394
daniele 2:540f6e142d59 395 return EP_PENDING;
daniele 2:540f6e142d59 396 }
daniele 2:540f6e142d59 397
daniele 2:540f6e142d59 398 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
daniele 2:540f6e142d59 399 uint32_t bf;
daniele 2:540f6e142d59 400
daniele 2:540f6e142d59 401 // Validate parameters
daniele 2:540f6e142d59 402 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
daniele 2:540f6e142d59 403 return EP_INVALID;
daniele 2:540f6e142d59 404 }
daniele 2:540f6e142d59 405
daniele 2:540f6e142d59 406 if (OUT_EP(endpoint)) {
daniele 2:540f6e142d59 407 return EP_INVALID;
daniele 2:540f6e142d59 408 }
daniele 2:540f6e142d59 409
daniele 2:540f6e142d59 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
daniele 2:540f6e142d59 411 // Double buffered // TODO: FIX THIS
daniele 2:540f6e142d59 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 413 bf = 1;
daniele 2:540f6e142d59 414 } else {
daniele 2:540f6e142d59 415 bf = 0;
daniele 2:540f6e142d59 416 }
daniele 2:540f6e142d59 417 } else {
daniele 2:540f6e142d59 418 // Single buffered
daniele 2:540f6e142d59 419 bf = 0;
daniele 2:540f6e142d59 420 }
daniele 2:540f6e142d59 421
daniele 2:540f6e142d59 422 // Check if endpoint still active
daniele 2:540f6e142d59 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
daniele 2:540f6e142d59 424 return EP_PENDING;
daniele 2:540f6e142d59 425 }
daniele 2:540f6e142d59 426
daniele 2:540f6e142d59 427 // Check if stalled
daniele 2:540f6e142d59 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
daniele 2:540f6e142d59 429 return EP_STALLED;
daniele 2:540f6e142d59 430 }
daniele 2:540f6e142d59 431
daniele 2:540f6e142d59 432 return EP_COMPLETED;
daniele 2:540f6e142d59 433 }
daniele 2:540f6e142d59 434
daniele 2:540f6e142d59 435 void USBHAL::stallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 436
daniele 2:540f6e142d59 437 // FIX: should this clear active bit?
daniele 2:540f6e142d59 438 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 439 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
daniele 2:540f6e142d59 440 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
daniele 2:540f6e142d59 441 } else {
daniele 2:540f6e142d59 442 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
daniele 2:540f6e142d59 443 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
daniele 2:540f6e142d59 444 }
daniele 2:540f6e142d59 445 }
daniele 2:540f6e142d59 446
daniele 2:540f6e142d59 447 void USBHAL::unstallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 448 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
daniele 2:540f6e142d59 449 // Double buffered
daniele 2:540f6e142d59 450 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 451 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
daniele 2:540f6e142d59 452 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
daniele 2:540f6e142d59 453
daniele 2:540f6e142d59 454 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 455 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 456 } else {
daniele 2:540f6e142d59 457 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 458 }
daniele 2:540f6e142d59 459 } else {
daniele 2:540f6e142d59 460 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
daniele 2:540f6e142d59 461 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
daniele 2:540f6e142d59 462
daniele 2:540f6e142d59 463 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 464 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 465 } else {
daniele 2:540f6e142d59 466 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 467 }
daniele 2:540f6e142d59 468 }
daniele 2:540f6e142d59 469 } else {
daniele 2:540f6e142d59 470 // Single buffered
daniele 2:540f6e142d59 471 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 472 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 473 } else {
daniele 2:540f6e142d59 474 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
daniele 2:540f6e142d59 475 }
daniele 2:540f6e142d59 476 }
daniele 2:540f6e142d59 477 }
daniele 2:540f6e142d59 478
daniele 2:540f6e142d59 479 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
daniele 2:540f6e142d59 480 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 481 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 482 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
daniele 2:540f6e142d59 483 return true;
daniele 2:540f6e142d59 484 }
daniele 2:540f6e142d59 485 } else {
daniele 2:540f6e142d59 486 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
daniele 2:540f6e142d59 487 return true;
daniele 2:540f6e142d59 488 }
daniele 2:540f6e142d59 489 }
daniele 2:540f6e142d59 490 } else {
daniele 2:540f6e142d59 491 if (LPC_USB->EPINUSE & EP(endpoint)) {
daniele 2:540f6e142d59 492 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
daniele 2:540f6e142d59 493 return true;
daniele 2:540f6e142d59 494 }
daniele 2:540f6e142d59 495 } else {
daniele 2:540f6e142d59 496 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
daniele 2:540f6e142d59 497 return true;
daniele 2:540f6e142d59 498 }
daniele 2:540f6e142d59 499 }
daniele 2:540f6e142d59 500 }
daniele 2:540f6e142d59 501
daniele 2:540f6e142d59 502 return false;
daniele 2:540f6e142d59 503 }
daniele 2:540f6e142d59 504
daniele 2:540f6e142d59 505 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
daniele 2:540f6e142d59 506 uint32_t tmpEpRamPtr;
daniele 2:540f6e142d59 507
daniele 2:540f6e142d59 508 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
daniele 2:540f6e142d59 509 return false;
daniele 2:540f6e142d59 510 }
daniele 2:540f6e142d59 511
daniele 2:540f6e142d59 512 // Not applicable to the control endpoints
daniele 2:540f6e142d59 513 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
daniele 2:540f6e142d59 514 return false;
daniele 2:540f6e142d59 515 }
daniele 2:540f6e142d59 516
daniele 2:540f6e142d59 517 // Allocate buffers in USB RAM
daniele 2:540f6e142d59 518 tmpEpRamPtr = epRamPtr;
daniele 2:540f6e142d59 519
daniele 2:540f6e142d59 520 // Must be 64 byte aligned
daniele 2:540f6e142d59 521 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
daniele 2:540f6e142d59 522
daniele 2:540f6e142d59 523 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
daniele 2:540f6e142d59 524 // Out of memory
daniele 2:540f6e142d59 525 return false;
daniele 2:540f6e142d59 526 }
daniele 2:540f6e142d59 527
daniele 2:540f6e142d59 528 // Allocate first buffer
daniele 2:540f6e142d59 529 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
daniele 2:540f6e142d59 530 tmpEpRamPtr += maxPacket;
daniele 2:540f6e142d59 531
daniele 2:540f6e142d59 532 if (!(options & SINGLE_BUFFERED)) {
daniele 2:540f6e142d59 533 // Must be 64 byte aligned
daniele 2:540f6e142d59 534 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
daniele 2:540f6e142d59 535
daniele 2:540f6e142d59 536 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
daniele 2:540f6e142d59 537 // Out of memory
daniele 2:540f6e142d59 538 return false;
daniele 2:540f6e142d59 539 }
daniele 2:540f6e142d59 540
daniele 2:540f6e142d59 541 // Allocate second buffer
daniele 2:540f6e142d59 542 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
daniele 2:540f6e142d59 543 tmpEpRamPtr += maxPacket;
daniele 2:540f6e142d59 544 }
daniele 2:540f6e142d59 545
daniele 2:540f6e142d59 546 // Commit to this USB RAM allocation
daniele 2:540f6e142d59 547 epRamPtr = tmpEpRamPtr;
daniele 2:540f6e142d59 548
daniele 2:540f6e142d59 549 // Remaining endpoint state values
daniele 2:540f6e142d59 550 endpointState[endpoint].maxPacket = maxPacket;
daniele 2:540f6e142d59 551 endpointState[endpoint].options = options;
daniele 2:540f6e142d59 552
daniele 2:540f6e142d59 553 // Enable double buffering if required
daniele 2:540f6e142d59 554 if (options & SINGLE_BUFFERED) {
daniele 2:540f6e142d59 555 LPC_USB->EPBUFCFG &= ~EP(endpoint);
daniele 2:540f6e142d59 556 } else {
daniele 2:540f6e142d59 557 // Double buffered
daniele 2:540f6e142d59 558 LPC_USB->EPBUFCFG |= EP(endpoint);
daniele 2:540f6e142d59 559 }
daniele 2:540f6e142d59 560
daniele 2:540f6e142d59 561 // Enable interrupt
daniele 2:540f6e142d59 562 LPC_USB->INTEN |= EP(endpoint);
daniele 2:540f6e142d59 563
daniele 2:540f6e142d59 564 // Enable endpoint
daniele 2:540f6e142d59 565 unstallEndpoint(endpoint);
daniele 2:540f6e142d59 566 return true;
daniele 2:540f6e142d59 567 }
daniele 2:540f6e142d59 568
daniele 2:540f6e142d59 569 void USBHAL::remoteWakeup(void) {
daniele 2:540f6e142d59 570 // Clearing DSUS bit initiates a remote wakeup if the
daniele 2:540f6e142d59 571 // device is currently enabled and suspended - otherwise
daniele 2:540f6e142d59 572 // it has no effect.
daniele 2:540f6e142d59 573 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
daniele 2:540f6e142d59 574 }
daniele 2:540f6e142d59 575
daniele 2:540f6e142d59 576
daniele 2:540f6e142d59 577 static void disableEndpoints(void) {
daniele 2:540f6e142d59 578 uint32_t logEp;
daniele 2:540f6e142d59 579
daniele 2:540f6e142d59 580 // Ref. Table 158 "When a bus reset is received, software
daniele 2:540f6e142d59 581 // must set the disable bit of all endpoints to 1".
daniele 2:540f6e142d59 582
daniele 2:540f6e142d59 583 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
daniele 2:540f6e142d59 584 ep[logEp].out[0] = CMDSTS_D;
daniele 2:540f6e142d59 585 ep[logEp].out[1] = CMDSTS_D;
daniele 2:540f6e142d59 586 ep[logEp].in[0] = CMDSTS_D;
daniele 2:540f6e142d59 587 ep[logEp].in[1] = CMDSTS_D;
daniele 2:540f6e142d59 588 }
daniele 2:540f6e142d59 589
daniele 2:540f6e142d59 590 // Start of USB RAM for endpoints > 0
daniele 2:540f6e142d59 591 epRamPtr = usbRamPtr;
daniele 2:540f6e142d59 592 }
daniele 2:540f6e142d59 593
daniele 2:540f6e142d59 594
daniele 2:540f6e142d59 595
daniele 2:540f6e142d59 596 void USBHAL::_usbisr(void) {
daniele 2:540f6e142d59 597 instance->usbisr();
daniele 2:540f6e142d59 598 }
daniele 2:540f6e142d59 599
daniele 2:540f6e142d59 600 void USBHAL::usbisr(void) {
daniele 2:540f6e142d59 601 // Start of frame
daniele 2:540f6e142d59 602 if (LPC_USB->INTSTAT & FRAME_INT) {
daniele 2:540f6e142d59 603 // Clear SOF interrupt
daniele 2:540f6e142d59 604 LPC_USB->INTSTAT = FRAME_INT;
daniele 2:540f6e142d59 605
daniele 2:540f6e142d59 606 // SOF event, read frame number
daniele 2:540f6e142d59 607 SOF(FRAME_NR(LPC_USB->INFO));
daniele 2:540f6e142d59 608 }
daniele 2:540f6e142d59 609
daniele 2:540f6e142d59 610 // Device state
daniele 2:540f6e142d59 611 if (LPC_USB->INTSTAT & DEV_INT) {
daniele 2:540f6e142d59 612 LPC_USB->INTSTAT = DEV_INT;
daniele 2:540f6e142d59 613
daniele 2:540f6e142d59 614 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
daniele 2:540f6e142d59 615 // Suspend status changed
daniele 2:540f6e142d59 616 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
daniele 2:540f6e142d59 617 if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
daniele 2:540f6e142d59 618 suspendStateChanged(1);
daniele 2:540f6e142d59 619 }
daniele 2:540f6e142d59 620 }
daniele 2:540f6e142d59 621
daniele 2:540f6e142d59 622 if (LPC_USB->DEVCMDSTAT & DRES_C) {
daniele 2:540f6e142d59 623 // Bus reset
daniele 2:540f6e142d59 624 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
daniele 2:540f6e142d59 625
daniele 2:540f6e142d59 626 suspendStateChanged(0);
daniele 2:540f6e142d59 627
daniele 2:540f6e142d59 628 // Disable endpoints > 0
daniele 2:540f6e142d59 629 disableEndpoints();
daniele 2:540f6e142d59 630
daniele 2:540f6e142d59 631 // Bus reset event
daniele 2:540f6e142d59 632 busReset();
daniele 2:540f6e142d59 633 }
daniele 2:540f6e142d59 634 }
daniele 2:540f6e142d59 635
daniele 2:540f6e142d59 636 // Endpoint 0
daniele 2:540f6e142d59 637 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
daniele 2:540f6e142d59 638 // Clear EP0OUT/SETUP interrupt
daniele 2:540f6e142d59 639 LPC_USB->INTSTAT = EP(EP0OUT);
daniele 2:540f6e142d59 640
daniele 2:540f6e142d59 641 // Check if SETUP
daniele 2:540f6e142d59 642 if (LPC_USB->DEVCMDSTAT & SETUP) {
daniele 2:540f6e142d59 643 // Clear Active and Stall bits for EP0
daniele 2:540f6e142d59 644 // Documentation does not make it clear if we must use the
daniele 2:540f6e142d59 645 // EPSKIP register to achieve this, Fig. 16 and NXP reference
daniele 2:540f6e142d59 646 // code suggests we can just clear the Active bits - check with
daniele 2:540f6e142d59 647 // NXP to be sure.
daniele 2:540f6e142d59 648 ep[0].in[0] = 0;
daniele 2:540f6e142d59 649 ep[0].out[0] = 0;
daniele 2:540f6e142d59 650
daniele 2:540f6e142d59 651 // Clear EP0IN interrupt
daniele 2:540f6e142d59 652 LPC_USB->INTSTAT = EP(EP0IN);
daniele 2:540f6e142d59 653
daniele 2:540f6e142d59 654 // Clear SETUP (and INTONNAK_CI/O) in device status register
daniele 2:540f6e142d59 655 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
daniele 2:540f6e142d59 656
daniele 2:540f6e142d59 657 // EP0 SETUP event (SETUP data received)
daniele 2:540f6e142d59 658 EP0setupCallback();
daniele 2:540f6e142d59 659 } else {
daniele 2:540f6e142d59 660 // EP0OUT ACK event (OUT data received)
daniele 2:540f6e142d59 661 EP0out();
daniele 2:540f6e142d59 662 }
daniele 2:540f6e142d59 663 }
daniele 2:540f6e142d59 664
daniele 2:540f6e142d59 665 if (LPC_USB->INTSTAT & EP(EP0IN)) {
daniele 2:540f6e142d59 666 // Clear EP0IN interrupt
daniele 2:540f6e142d59 667 LPC_USB->INTSTAT = EP(EP0IN);
daniele 2:540f6e142d59 668
daniele 2:540f6e142d59 669 // EP0IN ACK event (IN data sent)
daniele 2:540f6e142d59 670 EP0in();
daniele 2:540f6e142d59 671 }
daniele 2:540f6e142d59 672
daniele 2:540f6e142d59 673 for (uint8_t num = 2; num < 5*2; num++) {
daniele 2:540f6e142d59 674 if (LPC_USB->INTSTAT & EP(num)) {
daniele 2:540f6e142d59 675 LPC_USB->INTSTAT = EP(num);
daniele 2:540f6e142d59 676 epComplete |= EP(num);
daniele 2:540f6e142d59 677 if ((instance->*(epCallback[num - 2]))()) {
daniele 2:540f6e142d59 678 epComplete &= ~EP(num);
daniele 2:540f6e142d59 679 }
daniele 2:540f6e142d59 680 }
daniele 2:540f6e142d59 681 }
daniele 2:540f6e142d59 682 }
daniele 2:540f6e142d59 683
daniele 2:540f6e142d59 684 #endif