Daniel Geonsi Jeong / max8971

MAX8971 1-Cell LI+ DC-DC Charger Driver. Datasheet is available at https://datasheets.maximintegrated.com/en/ds/MAX8971.pdf. And it was tested using MAX32630FTHR Board.

Fork of max77801 by Daniel Geonsi Jeong

max8971.cpp@1:96e05ce748c1, 2018-06-26 (annotated)

Committer:
daniel_gs_jeong
Date:
Tue Jun 26 08:05:21 2018 +0000
Revision:
1:96e05ce748c1
MAX8971 1-Cell Li+ DC-DC Charger Driver. This Driver was tested using MAX32630FTHR Board.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniel_gs_jeong 1:96e05ce748c1 1 /*******************************************************************************
daniel_gs_jeong 1:96e05ce748c1 2 * Copyright (C) 2018 Maxim Integrated Products, Inc., All Rights Reserved.
daniel_gs_jeong 1:96e05ce748c1 3 *
daniel_gs_jeong 1:96e05ce748c1 4 * Permission is hereby granted, free of charge, to any person obtaining a
daniel_gs_jeong 1:96e05ce748c1 5 * copy of this software and associated documentation files (the "Software"),
daniel_gs_jeong 1:96e05ce748c1 6 * to deal in the Software without restriction, including without limitation
daniel_gs_jeong 1:96e05ce748c1 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
daniel_gs_jeong 1:96e05ce748c1 8 * and/or sell copies of the Software, and to permit persons to whom the
daniel_gs_jeong 1:96e05ce748c1 9 * Software is furnished to do so, subject to the following conditions:
daniel_gs_jeong 1:96e05ce748c1 10 *
daniel_gs_jeong 1:96e05ce748c1 11 * The above copyright notice and this permission notice shall be included
daniel_gs_jeong 1:96e05ce748c1 12 * in all copies or substantial portions of the Software.
daniel_gs_jeong 1:96e05ce748c1 13 *
daniel_gs_jeong 1:96e05ce748c1 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
daniel_gs_jeong 1:96e05ce748c1 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
daniel_gs_jeong 1:96e05ce748c1 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
daniel_gs_jeong 1:96e05ce748c1 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
daniel_gs_jeong 1:96e05ce748c1 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
daniel_gs_jeong 1:96e05ce748c1 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
daniel_gs_jeong 1:96e05ce748c1 20 * OTHER DEALINGS IN THE SOFTWARE.
daniel_gs_jeong 1:96e05ce748c1 21 *
daniel_gs_jeong 1:96e05ce748c1 22 * Except as contained in this notice, the name of Maxim Integrated
daniel_gs_jeong 1:96e05ce748c1 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
daniel_gs_jeong 1:96e05ce748c1 24 * Products, Inc. Branding Policy.
daniel_gs_jeong 1:96e05ce748c1 25 *
daniel_gs_jeong 1:96e05ce748c1 26 * The mere transfer of this software does not imply any licenses
daniel_gs_jeong 1:96e05ce748c1 27 * of trade secrets, proprietary technology, copyrights, patents,
daniel_gs_jeong 1:96e05ce748c1 28 * trademarks, maskwork rights, or any other form of intellectual
daniel_gs_jeong 1:96e05ce748c1 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
daniel_gs_jeong 1:96e05ce748c1 30 * ownership rights.
daniel_gs_jeong 1:96e05ce748c1 31 *******************************************************************************
daniel_gs_jeong 1:96e05ce748c1 32 */
daniel_gs_jeong 1:96e05ce748c1 33 #include "max8971.h"
daniel_gs_jeong 1:96e05ce748c1 34
daniel_gs_jeong 1:96e05ce748c1 35 /***** Definitions *****/
daniel_gs_jeong 1:96e05ce748c1 36 #define I2C_ADDR (0x35<<1)
daniel_gs_jeong 1:96e05ce748c1 37
daniel_gs_jeong 1:96e05ce748c1 38 /**
daniel_gs_jeong 1:96e05ce748c1 39 * max8971 constructor.
daniel_gs_jeong 1:96e05ce748c1 40 *
daniel_gs_jeong 1:96e05ce748c1 41 * @param i2c I2C object to use.
daniel_gs_jeong 1:96e05ce748c1 42 */
daniel_gs_jeong 1:96e05ce748c1 43 MAX8971::MAX8971(I2C *i2c) :
daniel_gs_jeong 1:96e05ce748c1 44 i2c_(i2c)
daniel_gs_jeong 1:96e05ce748c1 45 {
daniel_gs_jeong 1:96e05ce748c1 46 i2c_owner = false;
daniel_gs_jeong 1:96e05ce748c1 47 }
daniel_gs_jeong 1:96e05ce748c1 48
daniel_gs_jeong 1:96e05ce748c1 49 /**
daniel_gs_jeong 1:96e05ce748c1 50 * max8971 destructor.
daniel_gs_jeong 1:96e05ce748c1 51 */
daniel_gs_jeong 1:96e05ce748c1 52 MAX8971::~MAX8971()
daniel_gs_jeong 1:96e05ce748c1 53 {
daniel_gs_jeong 1:96e05ce748c1 54 if(i2c_owner) {
daniel_gs_jeong 1:96e05ce748c1 55 delete i2c_;
daniel_gs_jeong 1:96e05ce748c1 56 }
daniel_gs_jeong 1:96e05ce748c1 57 }
daniel_gs_jeong 1:96e05ce748c1 58
daniel_gs_jeong 1:96e05ce748c1 59 /**
daniel_gs_jeong 1:96e05ce748c1 60 * @brief Initialize max8971
daniel_gs_jeong 1:96e05ce748c1 61 */
daniel_gs_jeong 1:96e05ce748c1 62 int32_t MAX8971::init()
daniel_gs_jeong 1:96e05ce748c1 63 {
daniel_gs_jeong 1:96e05ce748c1 64 // insert initial setting functions
daniel_gs_jeong 1:96e05ce748c1 65 return 0;
daniel_gs_jeong 1:96e05ce748c1 66 }
daniel_gs_jeong 1:96e05ce748c1 67
daniel_gs_jeong 1:96e05ce748c1 68 /**
daniel_gs_jeong 1:96e05ce748c1 69 * @brief Read Register
daniel_gs_jeong 1:96e05ce748c1 70 * @details Reads data from max8971 register
daniel_gs_jeong 1:96e05ce748c1 71 *
daniel_gs_jeong 1:96e05ce748c1 72 * @param reg_addr Register to read
daniel_gs_jeong 1:96e05ce748c1 73 * @returns data if no errors, -1 if error.
daniel_gs_jeong 1:96e05ce748c1 74 */
daniel_gs_jeong 1:96e05ce748c1 75 int32_t MAX8971::read_register(MAX8971::registers_t reg_no)
daniel_gs_jeong 1:96e05ce748c1 76 {
daniel_gs_jeong 1:96e05ce748c1 77 char data;
daniel_gs_jeong 1:96e05ce748c1 78
daniel_gs_jeong 1:96e05ce748c1 79 data = reg_no;
daniel_gs_jeong 1:96e05ce748c1 80 if (i2c_->write(I2C_ADDR, &data, 1, true) != 0) {
daniel_gs_jeong 1:96e05ce748c1 81 return -1;
daniel_gs_jeong 1:96e05ce748c1 82 }
daniel_gs_jeong 1:96e05ce748c1 83
daniel_gs_jeong 1:96e05ce748c1 84 if (i2c_->read(I2C_ADDR | 0x01, &data, 1) != 0) {
daniel_gs_jeong 1:96e05ce748c1 85 return -1;
daniel_gs_jeong 1:96e05ce748c1 86 }
daniel_gs_jeong 1:96e05ce748c1 87
daniel_gs_jeong 1:96e05ce748c1 88 return (0x0 + data);
daniel_gs_jeong 1:96e05ce748c1 89 }
daniel_gs_jeong 1:96e05ce748c1 90
daniel_gs_jeong 1:96e05ce748c1 91 /**
daniel_gs_jeong 1:96e05ce748c1 92 * @brief Write Register
daniel_gs_jeong 1:96e05ce748c1 93 * @details Writes data to MAX77756 register
daniel_gs_jeong 1:96e05ce748c1 94 *
daniel_gs_jeong 1:96e05ce748c1 95 * @param reg_addr Register to write
daniel_gs_jeong 1:96e05ce748c1 96 * @param reg_data Data to write
daniel_gs_jeong 1:96e05ce748c1 97 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 1:96e05ce748c1 98 */
daniel_gs_jeong 1:96e05ce748c1 99 int32_t MAX8971::write_register(MAX8971::registers_t reg_no, char reg_data)
daniel_gs_jeong 1:96e05ce748c1 100 {
daniel_gs_jeong 1:96e05ce748c1 101 char data[2];
daniel_gs_jeong 1:96e05ce748c1 102
daniel_gs_jeong 1:96e05ce748c1 103 data[0] = reg_no;
daniel_gs_jeong 1:96e05ce748c1 104 data[1] = reg_data;
daniel_gs_jeong 1:96e05ce748c1 105 if (i2c_->write(I2C_ADDR, data, 2) != 0) {
daniel_gs_jeong 1:96e05ce748c1 106 return -1;
daniel_gs_jeong 1:96e05ce748c1 107 }
daniel_gs_jeong 1:96e05ce748c1 108
daniel_gs_jeong 1:96e05ce748c1 109 return 0;
daniel_gs_jeong 1:96e05ce748c1 110 }
daniel_gs_jeong 1:96e05ce748c1 111
daniel_gs_jeong 1:96e05ce748c1 112 /**
daniel_gs_jeong 1:96e05ce748c1 113 * @brief Update Register data
daniel_gs_jeong 1:96e05ce748c1 114 * @details Update bits data of a register
daniel_gs_jeong 1:96e05ce748c1 115 *
daniel_gs_jeong 1:96e05ce748c1 116 * @param reg_no Register Number to be updated
daniel_gs_jeong 1:96e05ce748c1 117 * @param mask Mask Data
daniel_gs_jeong 1:96e05ce748c1 118 * @param reg_data bit data
daniel_gs_jeong 1:96e05ce748c1 119 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 1:96e05ce748c1 120 */
daniel_gs_jeong 1:96e05ce748c1 121 int32_t MAX8971::update_register
daniel_gs_jeong 1:96e05ce748c1 122 (MAX8971::registers_t reg_no, char reg_mask, char reg_data)
daniel_gs_jeong 1:96e05ce748c1 123 {
daniel_gs_jeong 1:96e05ce748c1 124 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 125
daniel_gs_jeong 1:96e05ce748c1 126 data = read_register(reg_no);
daniel_gs_jeong 1:96e05ce748c1 127 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 128 return -1;
daniel_gs_jeong 1:96e05ce748c1 129
daniel_gs_jeong 1:96e05ce748c1 130 data &= ~reg_mask;
daniel_gs_jeong 1:96e05ce748c1 131 data |= reg_data;
daniel_gs_jeong 1:96e05ce748c1 132
daniel_gs_jeong 1:96e05ce748c1 133 data = write_register(reg_no, (char)(data & 0xff));
daniel_gs_jeong 1:96e05ce748c1 134 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 135 return -1;
daniel_gs_jeong 1:96e05ce748c1 136 return 0;
daniel_gs_jeong 1:96e05ce748c1 137 }
daniel_gs_jeong 1:96e05ce748c1 138
daniel_gs_jeong 1:96e05ce748c1 139 /**
daniel_gs_jeong 1:96e05ce748c1 140 * @brief Get Interrupt
daniel_gs_jeong 1:96e05ce748c1 141 * @details Get status register data
daniel_gs_jeong 1:96e05ce748c1 142 * BIT7 : AICL_I DC Interrupt
daniel_gs_jeong 1:96e05ce748c1 143 * BIT6 : TOPOFF Topoff Interrupt
daniel_gs_jeong 1:96e05ce748c1 144 * BIT5 : DC Overvolatage Interrupt
daniel_gs_jeong 1:96e05ce748c1 145 * BIT4 : DC Undervoltage Interrupt
daniel_gs_jeong 1:96e05ce748c1 146 * BIT3 : Charge Current Interrupt
daniel_gs_jeong 1:96e05ce748c1 147 * BIT2 : Battery Interrupt
daniel_gs_jeong 1:96e05ce748c1 148 * BIT1 : Thermistor Interrupt
daniel_gs_jeong 1:96e05ce748c1 149 * BIT0 : Power-Up OK Interrupt
daniel_gs_jeong 1:96e05ce748c1 150 * @param None
daniel_gs_jeong 1:96e05ce748c1 151 * @returns Interrupt register data.
daniel_gs_jeong 1:96e05ce748c1 152 */
daniel_gs_jeong 1:96e05ce748c1 153 int32_t MAX8971::get_interrupt()
daniel_gs_jeong 1:96e05ce748c1 154 {
daniel_gs_jeong 1:96e05ce748c1 155 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 156
daniel_gs_jeong 1:96e05ce748c1 157 data = read_register(REG_CHG_STAT);
daniel_gs_jeong 1:96e05ce748c1 158 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 159 return -1;
daniel_gs_jeong 1:96e05ce748c1 160 return (data & 0xFF);
daniel_gs_jeong 1:96e05ce748c1 161 }
daniel_gs_jeong 1:96e05ce748c1 162
daniel_gs_jeong 1:96e05ce748c1 163 /**
daniel_gs_jeong 1:96e05ce748c1 164 * @brief Set Interrupt Mask
daniel_gs_jeong 1:96e05ce748c1 165 * @details Get status register data
daniel_gs_jeong 1:96e05ce748c1 166 * BIT7 : AICL_I DC Interrupt
daniel_gs_jeong 1:96e05ce748c1 167 * BIT6 : TOPOFF Topoff Interrupt
daniel_gs_jeong 1:96e05ce748c1 168 * BIT5 : DC Overvolatage Interrupt
daniel_gs_jeong 1:96e05ce748c1 169 * BIT4 : DC Undervoltage Interrupt
daniel_gs_jeong 1:96e05ce748c1 170 * BIT3 : Charge Current Interrupt
daniel_gs_jeong 1:96e05ce748c1 171 * BIT2 : Battery Interrupt
daniel_gs_jeong 1:96e05ce748c1 172 * BIT1 : Thermistor Interrupt
daniel_gs_jeong 1:96e05ce748c1 173 * BIT0 : Reserved
daniel_gs_jeong 1:96e05ce748c1 174 * @param Register Number, Interrupt Bit
daniel_gs_jeong 1:96e05ce748c1 175 * @returns Interrupt register data.
daniel_gs_jeong 1:96e05ce748c1 176 */
daniel_gs_jeong 1:96e05ce748c1 177 int32_t MAX8971::set_interrupt_mask
daniel_gs_jeong 1:96e05ce748c1 178 (MAX8971::registers_t reg_no, MAX8971::int_bit_t interrupt_bit)
daniel_gs_jeong 1:96e05ce748c1 179 {
daniel_gs_jeong 1:96e05ce748c1 180 char mask_bit;
daniel_gs_jeong 1:96e05ce748c1 181 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 182
daniel_gs_jeong 1:96e05ce748c1 183 if(interrupt_bit <VAL_THM_I_BIT)
daniel_gs_jeong 1:96e05ce748c1 184 return -1;
daniel_gs_jeong 1:96e05ce748c1 185
daniel_gs_jeong 1:96e05ce748c1 186 mask_bit = 0x01 << interrupt_bit;
daniel_gs_jeong 1:96e05ce748c1 187 data = update_register(REG_CHGINT_MASK, mask_bit, mask_bit);
daniel_gs_jeong 1:96e05ce748c1 188 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 189 return -1;
daniel_gs_jeong 1:96e05ce748c1 190
daniel_gs_jeong 1:96e05ce748c1 191 data = read_register(REG_CHGINT_MASK);
daniel_gs_jeong 1:96e05ce748c1 192 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 193 return -1;
daniel_gs_jeong 1:96e05ce748c1 194 return (data & 0xFF);
daniel_gs_jeong 1:96e05ce748c1 195 }
daniel_gs_jeong 1:96e05ce748c1 196
daniel_gs_jeong 1:96e05ce748c1 197 /**
daniel_gs_jeong 1:96e05ce748c1 198 * @brief Set Interrupt UnMask
daniel_gs_jeong 1:96e05ce748c1 199 * @details Get status register data
daniel_gs_jeong 1:96e05ce748c1 200 * BIT7 : AICL_I DC Interrupt
daniel_gs_jeong 1:96e05ce748c1 201 * BIT6 : TOPOFF Topoff Interrupt
daniel_gs_jeong 1:96e05ce748c1 202 * BIT5 : DC Overvolatage Interrupt
daniel_gs_jeong 1:96e05ce748c1 203 * BIT4 : DC Undervoltage Interrupt
daniel_gs_jeong 1:96e05ce748c1 204 * BIT3 : Charge Current Interrupt
daniel_gs_jeong 1:96e05ce748c1 205 * BIT2 : Battery Interrupt
daniel_gs_jeong 1:96e05ce748c1 206 * BIT1 : Thermistor Interrupt
daniel_gs_jeong 1:96e05ce748c1 207 * BIT0 : Reserved
daniel_gs_jeong 1:96e05ce748c1 208 * @param Register Number, Interrupt Bit
daniel_gs_jeong 1:96e05ce748c1 209 * @returns Interrupt register data.
daniel_gs_jeong 1:96e05ce748c1 210 */
daniel_gs_jeong 1:96e05ce748c1 211 int32_t MAX8971::set_interrupt_unmask
daniel_gs_jeong 1:96e05ce748c1 212 (MAX8971::registers_t reg_no, MAX8971::int_bit_t interrupt_bit)
daniel_gs_jeong 1:96e05ce748c1 213 {
daniel_gs_jeong 1:96e05ce748c1 214 char mask_bit;
daniel_gs_jeong 1:96e05ce748c1 215 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 216
daniel_gs_jeong 1:96e05ce748c1 217 if(interrupt_bit <VAL_THM_I_BIT)
daniel_gs_jeong 1:96e05ce748c1 218 return -1;
daniel_gs_jeong 1:96e05ce748c1 219
daniel_gs_jeong 1:96e05ce748c1 220 mask_bit = 0x01 << interrupt_bit;
daniel_gs_jeong 1:96e05ce748c1 221 data = update_register(REG_CHGINT_MASK, mask_bit, 0);
daniel_gs_jeong 1:96e05ce748c1 222 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 223 return -1;
daniel_gs_jeong 1:96e05ce748c1 224
daniel_gs_jeong 1:96e05ce748c1 225 data = read_register(REG_CHGINT_MASK);
daniel_gs_jeong 1:96e05ce748c1 226 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 227 return -1;
daniel_gs_jeong 1:96e05ce748c1 228 return (data & 0xFF);
daniel_gs_jeong 1:96e05ce748c1 229 }
daniel_gs_jeong 1:96e05ce748c1 230
daniel_gs_jeong 1:96e05ce748c1 231 /**
daniel_gs_jeong 1:96e05ce748c1 232 * @brief Get status
daniel_gs_jeong 1:96e05ce748c1 233 * @details Get status register data
daniel_gs_jeong 1:96e05ce748c1 234 * BIT7 : DCV_OK DC Input Voltage Status
daniel_gs_jeong 1:96e05ce748c1 235 * BIT6 : DCI_OK DC Input Current Status
daniel_gs_jeong 1:96e05ce748c1 236 * BIT5 : DCOVP_OK DC OVP Status
daniel_gs_jeong 1:96e05ce748c1 237 * BIT4 : DCUVP_OK DC UVP Status
daniel_gs_jeong 1:96e05ce748c1 238 * BIT3 : CHG_OK Charger Status
daniel_gs_jeong 1:96e05ce748c1 239 * BIT2 : BAT_OK Battery Status
daniel_gs_jeong 1:96e05ce748c1 240 * BIT1 : THM_OK Thermistor Status
daniel_gs_jeong 1:96e05ce748c1 241 * BIT0 : RESERVED
daniel_gs_jeong 1:96e05ce748c1 242 * @param None
daniel_gs_jeong 1:96e05ce748c1 243 * @returns status register data.
daniel_gs_jeong 1:96e05ce748c1 244 */
daniel_gs_jeong 1:96e05ce748c1 245 int32_t MAX8971::get_status()
daniel_gs_jeong 1:96e05ce748c1 246 {
daniel_gs_jeong 1:96e05ce748c1 247 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 248
daniel_gs_jeong 1:96e05ce748c1 249 data = read_register(REG_CHG_STAT);
daniel_gs_jeong 1:96e05ce748c1 250 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 251 return -1;
daniel_gs_jeong 1:96e05ce748c1 252 return (data & 0xFE);
daniel_gs_jeong 1:96e05ce748c1 253 }
daniel_gs_jeong 1:96e05ce748c1 254
daniel_gs_jeong 1:96e05ce748c1 255
daniel_gs_jeong 1:96e05ce748c1 256 /**
daniel_gs_jeong 1:96e05ce748c1 257 * @brief Get Details 1
daniel_gs_jeong 1:96e05ce748c1 258 * @details Get Details 1 register data
daniel_gs_jeong 1:96e05ce748c1 259 * BIT7 : DC Details
daniel_gs_jeong 1:96e05ce748c1 260 * BIT6 : DC Current
daniel_gs_jeong 1:96e05ce748c1 261 * BIT5 : DC OVP
daniel_gs_jeong 1:96e05ce748c1 262 * BIT4 : DC UVP
daniel_gs_jeong 1:96e05ce748c1 263 * BIT3 : RESERVED
daniel_gs_jeong 1:96e05ce748c1 264 * BIT2-0 : Thermistor Details
daniel_gs_jeong 1:96e05ce748c1 265 * @param None
daniel_gs_jeong 1:96e05ce748c1 266 * @returns status details 1 register data.
daniel_gs_jeong 1:96e05ce748c1 267 */
daniel_gs_jeong 1:96e05ce748c1 268 int32_t MAX8971::get_details1()
daniel_gs_jeong 1:96e05ce748c1 269 {
daniel_gs_jeong 1:96e05ce748c1 270 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 271
daniel_gs_jeong 1:96e05ce748c1 272 data = read_register(REG_DETAILS1);
daniel_gs_jeong 1:96e05ce748c1 273 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 274 return -1;
daniel_gs_jeong 1:96e05ce748c1 275 return (data & 0xF7);
daniel_gs_jeong 1:96e05ce748c1 276 }
daniel_gs_jeong 1:96e05ce748c1 277
daniel_gs_jeong 1:96e05ce748c1 278 /**
daniel_gs_jeong 1:96e05ce748c1 279 * @brief Get Details 2
daniel_gs_jeong 1:96e05ce748c1 280 * @details Get Details 2 register data
daniel_gs_jeong 1:96e05ce748c1 281 * BIT7-6 : Reserved
daniel_gs_jeong 1:96e05ce748c1 282 * BIT5-4 : Battery Details
daniel_gs_jeong 1:96e05ce748c1 283 * BIT3-0 : Charger Details
daniel_gs_jeong 1:96e05ce748c1 284 * @param None
daniel_gs_jeong 1:96e05ce748c1 285 * @returns status details 2 register data.
daniel_gs_jeong 1:96e05ce748c1 286 */
daniel_gs_jeong 1:96e05ce748c1 287 int32_t MAX8971::get_details2()
daniel_gs_jeong 1:96e05ce748c1 288 {
daniel_gs_jeong 1:96e05ce748c1 289 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 290
daniel_gs_jeong 1:96e05ce748c1 291 data = read_register(REG_DETAILS2);
daniel_gs_jeong 1:96e05ce748c1 292 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 293 return -1;
daniel_gs_jeong 1:96e05ce748c1 294 return (data & 0x3F);
daniel_gs_jeong 1:96e05ce748c1 295 }
daniel_gs_jeong 1:96e05ce748c1 296
daniel_gs_jeong 1:96e05ce748c1 297 /**
daniel_gs_jeong 1:96e05ce748c1 298 * @brief Set DCMON_DIS
daniel_gs_jeong 1:96e05ce748c1 299 * @details Set to disable the monitoring of input voltage
daniel_gs_jeong 1:96e05ce748c1 300 * by the input power limiter
daniel_gs_jeong 1:96e05ce748c1 301 * @param None
daniel_gs_jeong 1:96e05ce748c1 302 * @returns DCMON_DIS bit data.
daniel_gs_jeong 1:96e05ce748c1 303 */
daniel_gs_jeong 1:96e05ce748c1 304 int32_t MAX8971::set_disable_dc_monitor()
daniel_gs_jeong 1:96e05ce748c1 305 {
daniel_gs_jeong 1:96e05ce748c1 306 int32_t shift = 1;
daniel_gs_jeong 1:96e05ce748c1 307 char mask_bit = 0x01 << shift;
daniel_gs_jeong 1:96e05ce748c1 308 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 309
daniel_gs_jeong 1:96e05ce748c1 310 data = update_register(REG_CHGCNTL1, mask_bit, 1);
daniel_gs_jeong 1:96e05ce748c1 311 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 312 return -1;
daniel_gs_jeong 1:96e05ce748c1 313
daniel_gs_jeong 1:96e05ce748c1 314 data = read_register(REG_CHGCNTL1);
daniel_gs_jeong 1:96e05ce748c1 315 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 316 return -1;
daniel_gs_jeong 1:96e05ce748c1 317 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 318 }
daniel_gs_jeong 1:96e05ce748c1 319
daniel_gs_jeong 1:96e05ce748c1 320 /**
daniel_gs_jeong 1:96e05ce748c1 321 * @brief UnSet DCMON_DIS
daniel_gs_jeong 1:96e05ce748c1 322 * @details UnSet to enable the monitoring of input voltage
daniel_gs_jeong 1:96e05ce748c1 323 * by the input power limiter
daniel_gs_jeong 1:96e05ce748c1 324 * @param None
daniel_gs_jeong 1:96e05ce748c1 325 * @returns DCMON_DIS bit data.
daniel_gs_jeong 1:96e05ce748c1 326 */
daniel_gs_jeong 1:96e05ce748c1 327 int32_t MAX8971::unset_disable_dc_monitor()
daniel_gs_jeong 1:96e05ce748c1 328 {
daniel_gs_jeong 1:96e05ce748c1 329 int32_t shift = 1;
daniel_gs_jeong 1:96e05ce748c1 330 char mask_bit = 0x01 << shift;
daniel_gs_jeong 1:96e05ce748c1 331 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 332
daniel_gs_jeong 1:96e05ce748c1 333 data = update_register(REG_CHGCNTL1, mask_bit, 0);
daniel_gs_jeong 1:96e05ce748c1 334 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 335 return -1;
daniel_gs_jeong 1:96e05ce748c1 336
daniel_gs_jeong 1:96e05ce748c1 337 data = read_register(REG_CHGCNTL1);
daniel_gs_jeong 1:96e05ce748c1 338 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 339 return -1;
daniel_gs_jeong 1:96e05ce748c1 340 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 341 }
daniel_gs_jeong 1:96e05ce748c1 342
daniel_gs_jeong 1:96e05ce748c1 343 /**
daniel_gs_jeong 1:96e05ce748c1 344 * @brief Set USB SUSPEND
daniel_gs_jeong 1:96e05ce748c1 345 * @details Set to USB Suspend bit
daniel_gs_jeong 1:96e05ce748c1 346 * @param None
daniel_gs_jeong 1:96e05ce748c1 347 * @returns USB SUSPEND bit data.
daniel_gs_jeong 1:96e05ce748c1 348 */
daniel_gs_jeong 1:96e05ce748c1 349 int32_t MAX8971::set_usb_suspend()
daniel_gs_jeong 1:96e05ce748c1 350 {
daniel_gs_jeong 1:96e05ce748c1 351 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 352
daniel_gs_jeong 1:96e05ce748c1 353 data = update_register(REG_CHGCNTL1, 0x01, 1);
daniel_gs_jeong 1:96e05ce748c1 354 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 355 return -1;
daniel_gs_jeong 1:96e05ce748c1 356
daniel_gs_jeong 1:96e05ce748c1 357 data = read_register(REG_CHGCNTL1);
daniel_gs_jeong 1:96e05ce748c1 358 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 359 return -1;
daniel_gs_jeong 1:96e05ce748c1 360 return ( data & 0x01);
daniel_gs_jeong 1:96e05ce748c1 361 }
daniel_gs_jeong 1:96e05ce748c1 362
daniel_gs_jeong 1:96e05ce748c1 363 /**
daniel_gs_jeong 1:96e05ce748c1 364 * @brief UnSet USB SUSPEND
daniel_gs_jeong 1:96e05ce748c1 365 * @details UnSet to USB Suspend bit
daniel_gs_jeong 1:96e05ce748c1 366 * @param None
daniel_gs_jeong 1:96e05ce748c1 367 * @returns USB SUSPEND bit data.
daniel_gs_jeong 1:96e05ce748c1 368 */
daniel_gs_jeong 1:96e05ce748c1 369 int32_t MAX8971::unset_usb_suspend()
daniel_gs_jeong 1:96e05ce748c1 370 {
daniel_gs_jeong 1:96e05ce748c1 371 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 372
daniel_gs_jeong 1:96e05ce748c1 373 data = update_register(REG_CHGCNTL1, 0x01, 0);
daniel_gs_jeong 1:96e05ce748c1 374 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 375 return -1;
daniel_gs_jeong 1:96e05ce748c1 376
daniel_gs_jeong 1:96e05ce748c1 377 data = read_register(REG_CHGCNTL1);
daniel_gs_jeong 1:96e05ce748c1 378 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 379 return -1;
daniel_gs_jeong 1:96e05ce748c1 380 return ( data & 0x01);
daniel_gs_jeong 1:96e05ce748c1 381 }
daniel_gs_jeong 1:96e05ce748c1 382
daniel_gs_jeong 1:96e05ce748c1 383
daniel_gs_jeong 1:96e05ce748c1 384 /**
daniel_gs_jeong 1:96e05ce748c1 385 * @brief Set Fast Charge Current
daniel_gs_jeong 1:96e05ce748c1 386 * @details Set to CHGCC bit to control Fast Charge Current
daniel_gs_jeong 1:96e05ce748c1 387 * @param int 0-1550
daniel_gs_jeong 1:96e05ce748c1 388 * @returns Fast Charge Current Bit Data.
daniel_gs_jeong 1:96e05ce748c1 389 */
daniel_gs_jeong 1:96e05ce748c1 390 int32_t MAX8971::set_fast_charge_current(int current)
daniel_gs_jeong 1:96e05ce748c1 391 {
daniel_gs_jeong 1:96e05ce748c1 392 char mask_bit = 0x1f;
daniel_gs_jeong 1:96e05ce748c1 393 char value_bit = 0x0;
daniel_gs_jeong 1:96e05ce748c1 394 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 395
daniel_gs_jeong 1:96e05ce748c1 396 switch(current)
daniel_gs_jeong 1:96e05ce748c1 397 {
daniel_gs_jeong 1:96e05ce748c1 398 case 0 ... 249:
daniel_gs_jeong 1:96e05ce748c1 399 value_bit = 0x0;
daniel_gs_jeong 1:96e05ce748c1 400 break;
daniel_gs_jeong 1:96e05ce748c1 401 case 250 ... 1550:
daniel_gs_jeong 1:96e05ce748c1 402 value_bit = current/50;
daniel_gs_jeong 1:96e05ce748c1 403 break;
daniel_gs_jeong 1:96e05ce748c1 404 default:
daniel_gs_jeong 1:96e05ce748c1 405 value_bit = 0x1f;
daniel_gs_jeong 1:96e05ce748c1 406 break;
daniel_gs_jeong 1:96e05ce748c1 407 }
daniel_gs_jeong 1:96e05ce748c1 408
daniel_gs_jeong 1:96e05ce748c1 409 data = update_register(REG_FCHGCRNT, mask_bit, value_bit);
daniel_gs_jeong 1:96e05ce748c1 410 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 411 return -1;
daniel_gs_jeong 1:96e05ce748c1 412
daniel_gs_jeong 1:96e05ce748c1 413 data = read_register(REG_FCHGCRNT);
daniel_gs_jeong 1:96e05ce748c1 414 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 415 return -1;
daniel_gs_jeong 1:96e05ce748c1 416 return ( data & mask_bit);
daniel_gs_jeong 1:96e05ce748c1 417 }
daniel_gs_jeong 1:96e05ce748c1 418
daniel_gs_jeong 1:96e05ce748c1 419 /**
daniel_gs_jeong 1:96e05ce748c1 420 * @brief Set Fast Charge Timer Duration
daniel_gs_jeong 1:96e05ce748c1 421 * @details Set to FCHGT bit to control Fast Charge Timer
daniel_gs_jeong 1:96e05ce748c1 422 * @param fast_charge_timer_t
daniel_gs_jeong 1:96e05ce748c1 423 * @returns Fast Charge Timer Bit Data.
daniel_gs_jeong 1:96e05ce748c1 424 */
daniel_gs_jeong 1:96e05ce748c1 425 int32_t MAX8971::set_fast_charge_timer(MAX8971::fast_charge_timer_t fc_time)
daniel_gs_jeong 1:96e05ce748c1 426 {
daniel_gs_jeong 1:96e05ce748c1 427 char mask_bit = 0xE0;
daniel_gs_jeong 1:96e05ce748c1 428 int32_t shift = 5;
daniel_gs_jeong 1:96e05ce748c1 429 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 430
daniel_gs_jeong 1:96e05ce748c1 431 data = update_register(REG_FCHGCRNT, mask_bit, fc_time<<shift);
daniel_gs_jeong 1:96e05ce748c1 432 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 433 return -1;
daniel_gs_jeong 1:96e05ce748c1 434
daniel_gs_jeong 1:96e05ce748c1 435 data = read_register(REG_FCHGCRNT);
daniel_gs_jeong 1:96e05ce748c1 436 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 437 return -1;
daniel_gs_jeong 1:96e05ce748c1 438 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 439 }
daniel_gs_jeong 1:96e05ce748c1 440
daniel_gs_jeong 1:96e05ce748c1 441 /**
daniel_gs_jeong 1:96e05ce748c1 442 * @brief Set Fast Restart Threshold
daniel_gs_jeong 1:96e05ce748c1 443 * @details Set to CHGRSTRT bit to control Fast Restart Threshold
daniel_gs_jeong 1:96e05ce748c1 444 * @param fast_charge_restart_threshold_t
daniel_gs_jeong 1:96e05ce748c1 445 * @returns CHGRSTRT bit Data.
daniel_gs_jeong 1:96e05ce748c1 446 */
daniel_gs_jeong 1:96e05ce748c1 447 int32_t MAX8971::set_fast_charge_restart_threshold
daniel_gs_jeong 1:96e05ce748c1 448 (MAX8971::fast_charge_restart_threshold_t voltage)
daniel_gs_jeong 1:96e05ce748c1 449 {
daniel_gs_jeong 1:96e05ce748c1 450 char mask_bit = 0x40;
daniel_gs_jeong 1:96e05ce748c1 451 int32_t shift = 6;
daniel_gs_jeong 1:96e05ce748c1 452 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 453
daniel_gs_jeong 1:96e05ce748c1 454 data = update_register(REG_DCCRNT, mask_bit, voltage<<shift);
daniel_gs_jeong 1:96e05ce748c1 455 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 456 return -1;
daniel_gs_jeong 1:96e05ce748c1 457
daniel_gs_jeong 1:96e05ce748c1 458 data = read_register(REG_DCCRNT);
daniel_gs_jeong 1:96e05ce748c1 459 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 460 return -1;
daniel_gs_jeong 1:96e05ce748c1 461 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 462 }
daniel_gs_jeong 1:96e05ce748c1 463
daniel_gs_jeong 1:96e05ce748c1 464 /**
daniel_gs_jeong 1:96e05ce748c1 465 * @brief Set Input Current Limit
daniel_gs_jeong 1:96e05ce748c1 466 * @details Set to DCILMT to control Input Current Limit
daniel_gs_jeong 1:96e05ce748c1 467 * 0x00 - 0x09 : 100mA
daniel_gs_jeong 1:96e05ce748c1 468 * 0x10 - 1x3C : 250 mA - 1500 mA with 25m A
daniel_gs_jeong 1:96e05ce748c1 469 * @param int 0-1500
daniel_gs_jeong 1:96e05ce748c1 470 * @returns DCILMT bit Data.
daniel_gs_jeong 1:96e05ce748c1 471 */
daniel_gs_jeong 1:96e05ce748c1 472 int32_t MAX8971::set_input_current_limit(int limit)
daniel_gs_jeong 1:96e05ce748c1 473 {
daniel_gs_jeong 1:96e05ce748c1 474 char mask_bit = 0x3F;
daniel_gs_jeong 1:96e05ce748c1 475 char value_bit = 0;
daniel_gs_jeong 1:96e05ce748c1 476 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 477
daniel_gs_jeong 1:96e05ce748c1 478 switch(limit)
daniel_gs_jeong 1:96e05ce748c1 479 {
daniel_gs_jeong 1:96e05ce748c1 480 case 0 ... 99:
daniel_gs_jeong 1:96e05ce748c1 481 value_bit = 0x3f; // disable
daniel_gs_jeong 1:96e05ce748c1 482 break;
daniel_gs_jeong 1:96e05ce748c1 483 case 100 ... 249:
daniel_gs_jeong 1:96e05ce748c1 484 value_bit = 0x09;
daniel_gs_jeong 1:96e05ce748c1 485 break;
daniel_gs_jeong 1:96e05ce748c1 486 case 250 ... 1500:
daniel_gs_jeong 1:96e05ce748c1 487 value_bit = limit/25;
daniel_gs_jeong 1:96e05ce748c1 488 break;
daniel_gs_jeong 1:96e05ce748c1 489 default:
daniel_gs_jeong 1:96e05ce748c1 490 value_bit = 0x3c; //maximum current is 1500mA(0x3C)
daniel_gs_jeong 1:96e05ce748c1 491 break;
daniel_gs_jeong 1:96e05ce748c1 492 }
daniel_gs_jeong 1:96e05ce748c1 493
daniel_gs_jeong 1:96e05ce748c1 494 data = update_register(REG_DCCRNT, mask_bit, value_bit);
daniel_gs_jeong 1:96e05ce748c1 495 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 496 return -1;
daniel_gs_jeong 1:96e05ce748c1 497
daniel_gs_jeong 1:96e05ce748c1 498 data = read_register(REG_DCCRNT);
daniel_gs_jeong 1:96e05ce748c1 499 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 500 return -1;
daniel_gs_jeong 1:96e05ce748c1 501 return ( data & mask_bit);
daniel_gs_jeong 1:96e05ce748c1 502 }
daniel_gs_jeong 1:96e05ce748c1 503
daniel_gs_jeong 1:96e05ce748c1 504 /**
daniel_gs_jeong 1:96e05ce748c1 505 * @brief Set Topoff Timer
daniel_gs_jeong 1:96e05ce748c1 506 * @details Set to TOFFT bit to control Topoff Timer
daniel_gs_jeong 1:96e05ce748c1 507 * @param top_off_timer_t
daniel_gs_jeong 1:96e05ce748c1 508 * @returns TOFFT bit Data.
daniel_gs_jeong 1:96e05ce748c1 509 */
daniel_gs_jeong 1:96e05ce748c1 510 int32_t MAX8971::set_top_off_timer(MAX8971::top_off_timer_t time)
daniel_gs_jeong 1:96e05ce748c1 511 {
daniel_gs_jeong 1:96e05ce748c1 512 char mask_bit = 0xE0;
daniel_gs_jeong 1:96e05ce748c1 513 int32_t shift = 5;
daniel_gs_jeong 1:96e05ce748c1 514 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 515
daniel_gs_jeong 1:96e05ce748c1 516 data = update_register(REG_TOPOFF, mask_bit, time<<shift);
daniel_gs_jeong 1:96e05ce748c1 517 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 518 return -1;
daniel_gs_jeong 1:96e05ce748c1 519
daniel_gs_jeong 1:96e05ce748c1 520 data = read_register(REG_TOPOFF);
daniel_gs_jeong 1:96e05ce748c1 521 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 522 return -1;
daniel_gs_jeong 1:96e05ce748c1 523 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 524 }
daniel_gs_jeong 1:96e05ce748c1 525
daniel_gs_jeong 1:96e05ce748c1 526
daniel_gs_jeong 1:96e05ce748c1 527 /**
daniel_gs_jeong 1:96e05ce748c1 528 * @brief Set Topoff Current Threshold
daniel_gs_jeong 1:96e05ce748c1 529 * @details Set to TOFFS bit to control Topoff Current Threshold
daniel_gs_jeong 1:96e05ce748c1 530 * @param top_off_current_threshold_t
daniel_gs_jeong 1:96e05ce748c1 531 * @returns TOFFS bit Data.
daniel_gs_jeong 1:96e05ce748c1 532 */
daniel_gs_jeong 1:96e05ce748c1 533 int32_t MAX8971::set_top_off_current_threshold
daniel_gs_jeong 1:96e05ce748c1 534 (MAX8971::top_off_current_threshold_t current)
daniel_gs_jeong 1:96e05ce748c1 535 {
daniel_gs_jeong 1:96e05ce748c1 536 char mask_bit = 0x0C;
daniel_gs_jeong 1:96e05ce748c1 537 int32_t shift = 2;
daniel_gs_jeong 1:96e05ce748c1 538 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 539
daniel_gs_jeong 1:96e05ce748c1 540 data = update_register(REG_TOPOFF, mask_bit, current<<shift);
daniel_gs_jeong 1:96e05ce748c1 541 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 542 return -1;
daniel_gs_jeong 1:96e05ce748c1 543
daniel_gs_jeong 1:96e05ce748c1 544 data = read_register(REG_TOPOFF);
daniel_gs_jeong 1:96e05ce748c1 545 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 546 return -1;
daniel_gs_jeong 1:96e05ce748c1 547 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 548 }
daniel_gs_jeong 1:96e05ce748c1 549
daniel_gs_jeong 1:96e05ce748c1 550
daniel_gs_jeong 1:96e05ce748c1 551 /**
daniel_gs_jeong 1:96e05ce748c1 552 * @brief Set Charge Termination Voltage
daniel_gs_jeong 1:96e05ce748c1 553 * @details Set to CHGCV bit to control Charge Termination Voltage in CV Mode
daniel_gs_jeong 1:96e05ce748c1 554 * @param charger_termination_voltage_t
daniel_gs_jeong 1:96e05ce748c1 555 * @returns CHGCV bit Data.
daniel_gs_jeong 1:96e05ce748c1 556 */
daniel_gs_jeong 1:96e05ce748c1 557 int32_t MAX8971::set_charge_termination_voltage
daniel_gs_jeong 1:96e05ce748c1 558 (MAX8971::charger_termination_voltage_t voltage)
daniel_gs_jeong 1:96e05ce748c1 559 {
daniel_gs_jeong 1:96e05ce748c1 560 char mask_bit = 0x03;
daniel_gs_jeong 1:96e05ce748c1 561 int32_t shift = 0;
daniel_gs_jeong 1:96e05ce748c1 562 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 563
daniel_gs_jeong 1:96e05ce748c1 564 data = update_register(REG_TOPOFF, mask_bit, voltage<<shift);
daniel_gs_jeong 1:96e05ce748c1 565 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 566 return -1;
daniel_gs_jeong 1:96e05ce748c1 567
daniel_gs_jeong 1:96e05ce748c1 568 data = read_register(REG_TOPOFF);
daniel_gs_jeong 1:96e05ce748c1 569 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 570 return -1;
daniel_gs_jeong 1:96e05ce748c1 571 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 572 }
daniel_gs_jeong 1:96e05ce748c1 573
daniel_gs_jeong 1:96e05ce748c1 574 /**
daniel_gs_jeong 1:96e05ce748c1 575 * @brief Set Die-Temperature Regulation Loop Set Point
daniel_gs_jeong 1:96e05ce748c1 576 * @details Set to REGTEMP bit to control
daniel_gs_jeong 1:96e05ce748c1 577 * Die-Temperature Regulation Loop Set Point
daniel_gs_jeong 1:96e05ce748c1 578 * @param die_temp_reggulation_point_t
daniel_gs_jeong 1:96e05ce748c1 579 * @returns REGTEMP bit Data.
daniel_gs_jeong 1:96e05ce748c1 580 */
daniel_gs_jeong 1:96e05ce748c1 581 int32_t MAX8971::set_charge_termination_voltage
daniel_gs_jeong 1:96e05ce748c1 582 (MAX8971::die_temp_reggulation_point_t degree)
daniel_gs_jeong 1:96e05ce748c1 583 {
daniel_gs_jeong 1:96e05ce748c1 584 char mask_bit = 0xC0;
daniel_gs_jeong 1:96e05ce748c1 585 int32_t shift = 6;
daniel_gs_jeong 1:96e05ce748c1 586 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 587
daniel_gs_jeong 1:96e05ce748c1 588 data = update_register(REG_TEMPREG, mask_bit, degree<<shift);
daniel_gs_jeong 1:96e05ce748c1 589 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 590 return -1;
daniel_gs_jeong 1:96e05ce748c1 591
daniel_gs_jeong 1:96e05ce748c1 592 data = read_register(REG_TEMPREG);
daniel_gs_jeong 1:96e05ce748c1 593 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 594 return -1;
daniel_gs_jeong 1:96e05ce748c1 595 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 596 }
daniel_gs_jeong 1:96e05ce748c1 597
daniel_gs_jeong 1:96e05ce748c1 598 /**
daniel_gs_jeong 1:96e05ce748c1 599 * @brief Set Thermistor Monitor Configuration
daniel_gs_jeong 1:96e05ce748c1 600 * @details Set to THM_CNFG bit to control Thermistor Monitor Configuration
daniel_gs_jeong 1:96e05ce748c1 601 * @param thermistor_monitor_config_t
daniel_gs_jeong 1:96e05ce748c1 602 * @returns REGTEMP bit Data.
daniel_gs_jeong 1:96e05ce748c1 603 */
daniel_gs_jeong 1:96e05ce748c1 604 int32_t MAX8971::set_thermistor_monitor
daniel_gs_jeong 1:96e05ce748c1 605 (MAX8971::thermistor_monitor_config_t enable)
daniel_gs_jeong 1:96e05ce748c1 606 {
daniel_gs_jeong 1:96e05ce748c1 607 char mask_bit = 0x08;
daniel_gs_jeong 1:96e05ce748c1 608 int32_t shift = 3;
daniel_gs_jeong 1:96e05ce748c1 609 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 610
daniel_gs_jeong 1:96e05ce748c1 611 data = update_register(REG_TEMPREG, mask_bit, enable<<shift);
daniel_gs_jeong 1:96e05ce748c1 612 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 613 return -1;
daniel_gs_jeong 1:96e05ce748c1 614
daniel_gs_jeong 1:96e05ce748c1 615 data = read_register(REG_TEMPREG);
daniel_gs_jeong 1:96e05ce748c1 616 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 617 return -1;
daniel_gs_jeong 1:96e05ce748c1 618 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 619 }
daniel_gs_jeong 1:96e05ce748c1 620
daniel_gs_jeong 1:96e05ce748c1 621 /**
daniel_gs_jeong 1:96e05ce748c1 622 * @brief Set JEITA Safty Region
daniel_gs_jeong 1:96e05ce748c1 623 * @details Set SAFETYREG bit to control JEITA Safty Region
daniel_gs_jeong 1:96e05ce748c1 624 * @param jeita_safety_selection_t
daniel_gs_jeong 1:96e05ce748c1 625 * @returns SAFETYREG bit Data.
daniel_gs_jeong 1:96e05ce748c1 626 */
daniel_gs_jeong 1:96e05ce748c1 627 int32_t MAX8971::set_jeita_safety_region
daniel_gs_jeong 1:96e05ce748c1 628 (MAX8971::jeita_safety_selection_t enable)
daniel_gs_jeong 1:96e05ce748c1 629 {
daniel_gs_jeong 1:96e05ce748c1 630 char mask_bit = 0x01;
daniel_gs_jeong 1:96e05ce748c1 631 int32_t shift = 0;
daniel_gs_jeong 1:96e05ce748c1 632 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 633
daniel_gs_jeong 1:96e05ce748c1 634 data = update_register(REG_TEMPREG, mask_bit, enable<<shift);
daniel_gs_jeong 1:96e05ce748c1 635 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 636 return -1;
daniel_gs_jeong 1:96e05ce748c1 637
daniel_gs_jeong 1:96e05ce748c1 638 data = read_register(REG_TEMPREG);
daniel_gs_jeong 1:96e05ce748c1 639 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 640 return -1;
daniel_gs_jeong 1:96e05ce748c1 641 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 642 }
daniel_gs_jeong 1:96e05ce748c1 643
daniel_gs_jeong 1:96e05ce748c1 644 /**
daniel_gs_jeong 1:96e05ce748c1 645 * @brief Set Charger-Setting Protection
daniel_gs_jeong 1:96e05ce748c1 646 * @details Set CPROT bit to control Charger-Setting Protection
daniel_gs_jeong 1:96e05ce748c1 647 * @param charger_setting_protection_t
daniel_gs_jeong 1:96e05ce748c1 648 * @returns CPROT bit Data.
daniel_gs_jeong 1:96e05ce748c1 649 */
daniel_gs_jeong 1:96e05ce748c1 650 int32_t MAX8971::set_charger_setting_protection
daniel_gs_jeong 1:96e05ce748c1 651 (MAX8971::charger_setting_protection_t enable)
daniel_gs_jeong 1:96e05ce748c1 652 {
daniel_gs_jeong 1:96e05ce748c1 653 char mask_bit = 0x0C;
daniel_gs_jeong 1:96e05ce748c1 654 int32_t shift = 2;
daniel_gs_jeong 1:96e05ce748c1 655 int32_t data;
daniel_gs_jeong 1:96e05ce748c1 656
daniel_gs_jeong 1:96e05ce748c1 657 data = update_register(REG_PROTCMD, mask_bit, enable<<shift);
daniel_gs_jeong 1:96e05ce748c1 658 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 659 return -1;
daniel_gs_jeong 1:96e05ce748c1 660
daniel_gs_jeong 1:96e05ce748c1 661 data = read_register(REG_PROTCMD);
daniel_gs_jeong 1:96e05ce748c1 662 if(data < 0)
daniel_gs_jeong 1:96e05ce748c1 663 return -1;
daniel_gs_jeong 1:96e05ce748c1 664 return ( (data & mask_bit) >> shift);
daniel_gs_jeong 1:96e05ce748c1 665 }