Daniel Geonsi Jeong / max77950

Driver File to control MAX77950, The MAX77950 is an advanced wireless power receiver IC that meets the specification requirements for WPC low-power (v1.2) and PMA SR1 (v2.0) communication protocols. This device operates using near-field magnetic induction when coupled with a WPC or PMA transmitter and provides output power up to 12 watts.

max77950.h@0:005ee97a1572, 2019-10-02 (annotated)

Committer:
daniel_gs_jeong
Date:
Wed Oct 02 08:22:22 2019 +0000
Revision:
0:005ee97a1572
MAX77950 Wireless Power Receiver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniel_gs_jeong 0:005ee97a1572 1 /*******************************************************************************
daniel_gs_jeong 0:005ee97a1572 2 * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
daniel_gs_jeong 0:005ee97a1572 3 *
daniel_gs_jeong 0:005ee97a1572 4 * Permission is hereby granted, free of charge, to any person obtaining a
daniel_gs_jeong 0:005ee97a1572 5 * copy of this software and associated documentation files (the "Software"),
daniel_gs_jeong 0:005ee97a1572 6 * to deal in the Software without restriction, including without limitation
daniel_gs_jeong 0:005ee97a1572 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
daniel_gs_jeong 0:005ee97a1572 8 * and/or sell copies of the Software, and to permit persons to whom the
daniel_gs_jeong 0:005ee97a1572 9 * Software is furnished to do so, subject to the following conditions:
daniel_gs_jeong 0:005ee97a1572 10 *
daniel_gs_jeong 0:005ee97a1572 11 * The above copyright notice and this permission notice shall be included
daniel_gs_jeong 0:005ee97a1572 12 * in all copies or substantial portions of the Software.
daniel_gs_jeong 0:005ee97a1572 13 *
daniel_gs_jeong 0:005ee97a1572 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
daniel_gs_jeong 0:005ee97a1572 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
daniel_gs_jeong 0:005ee97a1572 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
daniel_gs_jeong 0:005ee97a1572 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
daniel_gs_jeong 0:005ee97a1572 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
daniel_gs_jeong 0:005ee97a1572 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
daniel_gs_jeong 0:005ee97a1572 20 * OTHER DEALINGS IN THE SOFTWARE.
daniel_gs_jeong 0:005ee97a1572 21 *
daniel_gs_jeong 0:005ee97a1572 22 * Except as contained in this notice, the name of Maxim Integrated
daniel_gs_jeong 0:005ee97a1572 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
daniel_gs_jeong 0:005ee97a1572 24 * Products, Inc. Branding Policy.
daniel_gs_jeong 0:005ee97a1572 25 *
daniel_gs_jeong 0:005ee97a1572 26 * The mere transfer of this software does not imply any licenses
daniel_gs_jeong 0:005ee97a1572 27 * of trade secrets, proprietary technology, copyrights, patents,
daniel_gs_jeong 0:005ee97a1572 28 * trademarks, maskwork rights, or any other form of intellectual
daniel_gs_jeong 0:005ee97a1572 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
daniel_gs_jeong 0:005ee97a1572 30 * ownership rights.
daniel_gs_jeong 0:005ee97a1572 31 *******************************************************************************
daniel_gs_jeong 0:005ee97a1572 32 */
daniel_gs_jeong 0:005ee97a1572 33 #ifndef _MAX77950_H_
daniel_gs_jeong 0:005ee97a1572 34 #define _MAX77950_H_
daniel_gs_jeong 0:005ee97a1572 35
daniel_gs_jeong 0:005ee97a1572 36 #include "mbed.h"
daniel_gs_jeong 0:005ee97a1572 37
daniel_gs_jeong 0:005ee97a1572 38 class MAX77950
daniel_gs_jeong 0:005ee97a1572 39 {
daniel_gs_jeong 0:005ee97a1572 40
daniel_gs_jeong 0:005ee97a1572 41 public:
daniel_gs_jeong 0:005ee97a1572 42
daniel_gs_jeong 0:005ee97a1572 43 /**
daniel_gs_jeong 0:005ee97a1572 44 * @brief Register Addresses
daniel_gs_jeong 0:005ee97a1572 45 * @details Enumerated MAX77950 register addresses
daniel_gs_jeong 0:005ee97a1572 46 */
daniel_gs_jeong 0:005ee97a1572 47 typedef enum {
daniel_gs_jeong 0:005ee97a1572 48 REG_CHIP_ID = 0x00,
daniel_gs_jeong 0:005ee97a1572 49 REG_OTP_REV = 0x05,
daniel_gs_jeong 0:005ee97a1572 50 REG_STATUS_L,
daniel_gs_jeong 0:005ee97a1572 51 REG_STATUS_H,
daniel_gs_jeong 0:005ee97a1572 52 REG_INT_L,
daniel_gs_jeong 0:005ee97a1572 53 REG_INT_H,
daniel_gs_jeong 0:005ee97a1572 54 REG_INT_ENABLE_L,
daniel_gs_jeong 0:005ee97a1572 55 REG_INT_ENABLE_H,
daniel_gs_jeong 0:005ee97a1572 56 REG_INT_CLEAR_L,
daniel_gs_jeong 0:005ee97a1572 57 REG_INT_CLEAR_H,
daniel_gs_jeong 0:005ee97a1572 58 REG_CHARGE_STATUS,
daniel_gs_jeong 0:005ee97a1572 59 REG_EPT_REASON,
daniel_gs_jeong 0:005ee97a1572 60
daniel_gs_jeong 0:005ee97a1572 61 REG_VOUTVAL_H = 0x10,
daniel_gs_jeong 0:005ee97a1572 62 REG_VOUTVAL_L,
daniel_gs_jeong 0:005ee97a1572 63 REG_VOUTSET,
daniel_gs_jeong 0:005ee97a1572 64 REG_VRECT_ADJ,
daniel_gs_jeong 0:005ee97a1572 65 REG_VRECTVAL_H,
daniel_gs_jeong 0:005ee97a1572 66 REG_VRECTVAL_L,
daniel_gs_jeong 0:005ee97a1572 67 REG_ISENSEVAL_H,
daniel_gs_jeong 0:005ee97a1572 68 REG_ISENSEVAL_L,
daniel_gs_jeong 0:005ee97a1572 69 REG_TDIE_VALUE,
daniel_gs_jeong 0:005ee97a1572 70 REG_OP_FREQ_L,
daniel_gs_jeong 0:005ee97a1572 71 REG_OP_FREQ_H,
daniel_gs_jeong 0:005ee97a1572 72 REG_PING_OP_FREQ_L,
daniel_gs_jeong 0:005ee97a1572 73 REG_PING_OP_FREQ_H,
daniel_gs_jeong 0:005ee97a1572 74 REG_LDO_ILIMSET,
daniel_gs_jeong 0:005ee97a1572 75 REG_TX_ILIMSET,
daniel_gs_jeong 0:005ee97a1572 76 REG_SYS_OP_MODE,
daniel_gs_jeong 0:005ee97a1572 77 REG_RX_COM = 0x20,
daniel_gs_jeong 0:005ee97a1572 78 REG_PPP_HEADER,
daniel_gs_jeong 0:005ee97a1572 79 REG_RX_DATA_VALUE0,
daniel_gs_jeong 0:005ee97a1572 80 REG_RX_DATA_VALUE1,
daniel_gs_jeong 0:005ee97a1572 81 REG_RX_DATA_VALUE2,
daniel_gs_jeong 0:005ee97a1572 82 REG_RX_DATA_VALUE3,
daniel_gs_jeong 0:005ee97a1572 83 REG_RX_DATA_VALUE4,
daniel_gs_jeong 0:005ee97a1572 84 REG_FSK_DATA_VALUE0,
daniel_gs_jeong 0:005ee97a1572 85 REG_FSK_DATA_VALUE1,
daniel_gs_jeong 0:005ee97a1572 86 REG_FSK_DATA_VALUE2,
daniel_gs_jeong 0:005ee97a1572 87
daniel_gs_jeong 0:005ee97a1572 88 REG_TX_FOP_SET_L,
daniel_gs_jeong 0:005ee97a1572 89 REG_TX_FOP_SET_H,
daniel_gs_jeong 0:005ee97a1572 90 REG_TX_FOP_TON_SET_L,
daniel_gs_jeong 0:005ee97a1572 91 REG_TX_FOP_TON_SET_H,
daniel_gs_jeong 0:005ee97a1572 92 REG_TX_WPC_HEADER = 0x34,
daniel_gs_jeong 0:005ee97a1572 93 REG_TX_WPC_DATA0,
daniel_gs_jeong 0:005ee97a1572 94 REG_TX_WPC_DATA1,
daniel_gs_jeong 0:005ee97a1572 95 REG_TX_WPC_DATA2,
daniel_gs_jeong 0:005ee97a1572 96 REG_TX_WPC_DATA3,
daniel_gs_jeong 0:005ee97a1572 97 REG_TX_WPC_DATA4,
daniel_gs_jeong 0:005ee97a1572 98 REG_TX_WPC_DATA5,
daniel_gs_jeong 0:005ee97a1572 99 REG_TX_WPC_DATA6,
daniel_gs_jeong 0:005ee97a1572 100 REG_TX_WPC_DATA7,
daniel_gs_jeong 0:005ee97a1572 101 REG_TX_WPC_CHECKSUM,
daniel_gs_jeong 0:005ee97a1572 102
daniel_gs_jeong 0:005ee97a1572 103 REG_FOD_X0 = 0x3E,
daniel_gs_jeong 0:005ee97a1572 104 REG_FOD_Y0,
daniel_gs_jeong 0:005ee97a1572 105 REG_FOD_X1,
daniel_gs_jeong 0:005ee97a1572 106 REG_FOD_Y1,
daniel_gs_jeong 0:005ee97a1572 107 REG_FOD_X2,
daniel_gs_jeong 0:005ee97a1572 108 REG_FOD_Y2,
daniel_gs_jeong 0:005ee97a1572 109 REG_FOD_X3,
daniel_gs_jeong 0:005ee97a1572 110 REG_FOD_Y3,
daniel_gs_jeong 0:005ee97a1572 111 REG_FOD_X4,
daniel_gs_jeong 0:005ee97a1572 112 REG_FOD_Y4,
daniel_gs_jeong 0:005ee97a1572 113 REG_FOD_X5,
daniel_gs_jeong 0:005ee97a1572 114 REG_FOD_Y5,
daniel_gs_jeong 0:005ee97a1572 115 REG_FOD_X6,
daniel_gs_jeong 0:005ee97a1572 116 REG_FOD_Y6,
daniel_gs_jeong 0:005ee97a1572 117 REG_FOD_X7,
daniel_gs_jeong 0:005ee97a1572 118 REG_FOD_Y7,
daniel_gs_jeong 0:005ee97a1572 119 REG_FOD_X8,
daniel_gs_jeong 0:005ee97a1572 120 REG_FOD_Y8,
daniel_gs_jeong 0:005ee97a1572 121 REG_FOD_X9,
daniel_gs_jeong 0:005ee97a1572 122 REG_FOD_Y9,
daniel_gs_jeong 0:005ee97a1572 123 REG_FOD_X10,
daniel_gs_jeong 0:005ee97a1572 124 REG_FOD_Y10,
daniel_gs_jeong 0:005ee97a1572 125 REG_FOD_X11,
daniel_gs_jeong 0:005ee97a1572 126 REG_FOD_Y11,
daniel_gs_jeong 0:005ee97a1572 127 REG_FOD_X12,
daniel_gs_jeong 0:005ee97a1572 128 REG_FOD_Y12,
daniel_gs_jeong 0:005ee97a1572 129 REG_FOD_X13,
daniel_gs_jeong 0:005ee97a1572 130 REG_FOD_Y13,
daniel_gs_jeong 0:005ee97a1572 131 REG_FOD_X14,
daniel_gs_jeong 0:005ee97a1572 132 REG_FOD_Y14,
daniel_gs_jeong 0:005ee97a1572 133 REG_FOD_X15,
daniel_gs_jeong 0:005ee97a1572 134 REG_FOD_Y15,
daniel_gs_jeong 0:005ee97a1572 135
daniel_gs_jeong 0:005ee97a1572 136 REG_OV_CLAMP_VOLTAGE = 0x62,
daniel_gs_jeong 0:005ee97a1572 137 REG_TX_LAST_CEP = 0x63,
daniel_gs_jeong 0:005ee97a1572 138 REG_TX_LAST_RPP,
daniel_gs_jeong 0:005ee97a1572 139 REG_TX_LAST_PCHP,
daniel_gs_jeong 0:005ee97a1572 140
daniel_gs_jeong 0:005ee97a1572 141 REG_LDO_WPDET_CNFG = 0x70,
daniel_gs_jeong 0:005ee97a1572 142
daniel_gs_jeong 0:005ee97a1572 143 REG_VRECT_TARGET_X0 = 0xBA,
daniel_gs_jeong 0:005ee97a1572 144 REG_VRECT_TARGET_Y0,
daniel_gs_jeong 0:005ee97a1572 145 REG_VRECT_TARGET_PMA_Y0,
daniel_gs_jeong 0:005ee97a1572 146 REG_VRECT_TARGET_X1,
daniel_gs_jeong 0:005ee97a1572 147 REG_VRECT_TARGET_Y1,
daniel_gs_jeong 0:005ee97a1572 148 REG_VRECT_TARGET_PMA_Y2,
daniel_gs_jeong 0:005ee97a1572 149 REG_VRECT_TARGET_X3,
daniel_gs_jeong 0:005ee97a1572 150 REG_VRECT_TARGET_Y3,
daniel_gs_jeong 0:005ee97a1572 151 REG_VRECT_TARGET_PMA_Y3,
daniel_gs_jeong 0:005ee97a1572 152 REG_VRECT_TARGET_X4,
daniel_gs_jeong 0:005ee97a1572 153 REG_VRECT_TARGET_Y4,
daniel_gs_jeong 0:005ee97a1572 154 REG_VRECT_TARGET_PMA_Y4,
daniel_gs_jeong 0:005ee97a1572 155 REG_VRECT_TARGET_X5,
daniel_gs_jeong 0:005ee97a1572 156 REG_VRECT_TARGET_Y5,
daniel_gs_jeong 0:005ee97a1572 157 REG_VRECT_TARGET_PMA_Y5,
daniel_gs_jeong 0:005ee97a1572 158 REG_VRECT_TARGET_X6,
daniel_gs_jeong 0:005ee97a1572 159 REG_VRECT_TARGET_Y6,
daniel_gs_jeong 0:005ee97a1572 160 REG_VRECT_TARGET_PMA_Y6,
daniel_gs_jeong 0:005ee97a1572 161 REG_VRECT_TARGET_X7,
daniel_gs_jeong 0:005ee97a1572 162 REG_VRECT_TARGET_Y7,
daniel_gs_jeong 0:005ee97a1572 163 REG_VRECT_TARGET_PMA_Y7,
daniel_gs_jeong 0:005ee97a1572 164
daniel_gs_jeong 0:005ee97a1572 165 REG_PMA_ADV_DATA,
daniel_gs_jeong 0:005ee97a1572 166 REG_PMA_ADV_CRC,
daniel_gs_jeong 0:005ee97a1572 167
daniel_gs_jeong 0:005ee97a1572 168 } registers_t;
daniel_gs_jeong 0:005ee97a1572 169
daniel_gs_jeong 0:005ee97a1572 170 /**
daniel_gs_jeong 0:005ee97a1572 171 * @brief Interrupt Bit
daniel_gs_jeong 0:005ee97a1572 172 * @details Interrupt Bit Low
daniel_gs_jeong 0:005ee97a1572 173 */
daniel_gs_jeong 0:005ee97a1572 174 typedef enum {
daniel_gs_jeong 0:005ee97a1572 175 INT_VOUT = 0x80,
daniel_gs_jeong 0:005ee97a1572 176 INT_VRECT = 0x40,
daniel_gs_jeong 0:005ee97a1572 177 INT_WDOG = 0x20,
daniel_gs_jeong 0:005ee97a1572 178 INT_FSK_RCVD = 0x10,
daniel_gs_jeong 0:005ee97a1572 179 INT_OV = 0x02,
daniel_gs_jeong 0:005ee97a1572 180 INT_OC = 0x01,
daniel_gs_jeong 0:005ee97a1572 181 } interrupt_low_t;
daniel_gs_jeong 0:005ee97a1572 182
daniel_gs_jeong 0:005ee97a1572 183 /**
daniel_gs_jeong 0:005ee97a1572 184 * @brief Interrupt Bit
daniel_gs_jeong 0:005ee97a1572 185 * @details Interrupt Bit Low
daniel_gs_jeong 0:005ee97a1572 186 */
daniel_gs_jeong 0:005ee97a1572 187 typedef enum {
daniel_gs_jeong 0:005ee97a1572 188 INT_OT = 0x80,
daniel_gs_jeong 0:005ee97a1572 189 INT_TX_OC = 0x40,
daniel_gs_jeong 0:005ee97a1572 190 INT_TX_OT = 0x20,
daniel_gs_jeong 0:005ee97a1572 191 INT_TX_CONN = 0x08,
daniel_gs_jeong 0:005ee97a1572 192 INT_TX_DEMOD_PING = 0x04,
daniel_gs_jeong 0:005ee97a1572 193 INT_ASK_DEMOD_IDCF = 0x02,
daniel_gs_jeong 0:005ee97a1572 194 INT_ASK_DEMOD_PT = 0x01,
daniel_gs_jeong 0:005ee97a1572 195 } interrupt_high_t;
daniel_gs_jeong 0:005ee97a1572 196
daniel_gs_jeong 0:005ee97a1572 197 /**
daniel_gs_jeong 0:005ee97a1572 198 * @brief ENABLE/DISABLE
daniel_gs_jeong 0:005ee97a1572 199 * @details Enumerated ENABLE/DISABLE
daniel_gs_jeong 0:005ee97a1572 200 */
daniel_gs_jeong 0:005ee97a1572 201 typedef enum {
daniel_gs_jeong 0:005ee97a1572 202 VAL_DISABLE = 0x00,
daniel_gs_jeong 0:005ee97a1572 203 VAL_ENABLE
daniel_gs_jeong 0:005ee97a1572 204 } enable_t;
daniel_gs_jeong 0:005ee97a1572 205
daniel_gs_jeong 0:005ee97a1572 206 /**
daniel_gs_jeong 0:005ee97a1572 207 * @brief LOW/HIGH
daniel_gs_jeong 0:005ee97a1572 208 * @details Enumerated LOW/HIGH
daniel_gs_jeong 0:005ee97a1572 209 */
daniel_gs_jeong 0:005ee97a1572 210 typedef enum {
daniel_gs_jeong 0:005ee97a1572 211 VAL_LOW = 0x00,
daniel_gs_jeong 0:005ee97a1572 212 VAL_HIGH
daniel_gs_jeong 0:005ee97a1572 213 } low_high_t;
daniel_gs_jeong 0:005ee97a1572 214
daniel_gs_jeong 0:005ee97a1572 215 /**
daniel_gs_jeong 0:005ee97a1572 216 * @brief System Operation Mode
daniel_gs_jeong 0:005ee97a1572 217 * @details Enumerated System Operation
daniel_gs_jeong 0:005ee97a1572 218 */
daniel_gs_jeong 0:005ee97a1572 219 typedef enum {
daniel_gs_jeong 0:005ee97a1572 220 SYS_MODE_INITIAL = 0x00,
daniel_gs_jeong 0:005ee97a1572 221 SYS_MODE_WPC_RX,
daniel_gs_jeong 0:005ee97a1572 222 SYS_MODE_PMA_RX,
daniel_gs_jeong 0:005ee97a1572 223 SYS_MODE_RESERVED,
daniel_gs_jeong 0:005ee97a1572 224 SYS_MODE_TX_PEER_PWR,
daniel_gs_jeong 0:005ee97a1572 225 } system_opmode_t;
daniel_gs_jeong 0:005ee97a1572 226
daniel_gs_jeong 0:005ee97a1572 227 /**
daniel_gs_jeong 0:005ee97a1572 228 * MAX77950 constructor.
daniel_gs_jeong 0:005ee97a1572 229 *
daniel_gs_jeong 0:005ee97a1572 230 * @param i2c I2C object to use.
daniel_gs_jeong 0:005ee97a1572 231 */
daniel_gs_jeong 0:005ee97a1572 232 MAX77950(I2C *i2c);
daniel_gs_jeong 0:005ee97a1572 233
daniel_gs_jeong 0:005ee97a1572 234 /**
daniel_gs_jeong 0:005ee97a1572 235 * MAX77950 destructor.
daniel_gs_jeong 0:005ee97a1572 236 */
daniel_gs_jeong 0:005ee97a1572 237 ~MAX77950();
daniel_gs_jeong 0:005ee97a1572 238
daniel_gs_jeong 0:005ee97a1572 239 /**
daniel_gs_jeong 0:005ee97a1572 240 * @brief Initialize MAX77950
daniel_gs_jeong 0:005ee97a1572 241 */
daniel_gs_jeong 0:005ee97a1572 242 int32_t init();
daniel_gs_jeong 0:005ee97a1572 243
daniel_gs_jeong 0:005ee97a1572 244 /**
daniel_gs_jeong 0:005ee97a1572 245 * @brief Write Register
daniel_gs_jeong 0:005ee97a1572 246 * @details Writes data to MAX77950 register
daniel_gs_jeong 0:005ee97a1572 247 *
daniel_gs_jeong 0:005ee97a1572 248 * @param reg_addr Register to write
daniel_gs_jeong 0:005ee97a1572 249 * @param reg_data Data to write
daniel_gs_jeong 0:005ee97a1572 250 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 251 */
daniel_gs_jeong 0:005ee97a1572 252 int32_t write_register(MAX77950::registers_t reg_addr, char reg_data);
daniel_gs_jeong 0:005ee97a1572 253
daniel_gs_jeong 0:005ee97a1572 254 /**
daniel_gs_jeong 0:005ee97a1572 255 * @brief Read Register
daniel_gs_jeong 0:005ee97a1572 256 * @details Reads data from MAX77950 register
daniel_gs_jeong 0:005ee97a1572 257 *
daniel_gs_jeong 0:005ee97a1572 258 * @param reg_addr Register to read
daniel_gs_jeong 0:005ee97a1572 259 * @returns data if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 260 */
daniel_gs_jeong 0:005ee97a1572 261 int32_t read_register(MAX77950::registers_t reg_addr);
daniel_gs_jeong 0:005ee97a1572 262
daniel_gs_jeong 0:005ee97a1572 263 /**
daniel_gs_jeong 0:005ee97a1572 264 * @brief Update Register data
daniel_gs_jeong 0:005ee97a1572 265 * @details Update bits data of a register
daniel_gs_jeong 0:005ee97a1572 266 *
daniel_gs_jeong 0:005ee97a1572 267 * @param reg_no Register Number to be updated
daniel_gs_jeong 0:005ee97a1572 268 * @param mask Mask Data
daniel_gs_jeong 0:005ee97a1572 269 * @param reg_data bit data
daniel_gs_jeong 0:005ee97a1572 270 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 271 */
daniel_gs_jeong 0:005ee97a1572 272
daniel_gs_jeong 0:005ee97a1572 273 int32_t update_register
daniel_gs_jeong 0:005ee97a1572 274 (MAX77950::registers_t reg_no, char reg_mask, char reg_data);
daniel_gs_jeong 0:005ee97a1572 275
daniel_gs_jeong 0:005ee97a1572 276 /**
daniel_gs_jeong 0:005ee97a1572 277 * @brief Get Status Low
daniel_gs_jeong 0:005ee97a1572 278 * @details Get status register data
daniel_gs_jeong 0:005ee97a1572 279 * BIT7 : LDO is ON
daniel_gs_jeong 0:005ee97a1572 280 * BIT6 : V_rect is over UVLO
daniel_gs_jeong 0:005ee97a1572 281 * BIT5 : Watchdog timer
daniel_gs_jeong 0:005ee97a1572 282 * BIT4 : FSK Data
daniel_gs_jeong 0:005ee97a1572 283 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 284 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 285 * BIT1 : Over Voltage Status
daniel_gs_jeong 0:005ee97a1572 286 * BIT0 : Over Current Status
daniel_gs_jeong 0:005ee97a1572 287 * @param None
daniel_gs_jeong 0:005ee97a1572 288 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 289 */
daniel_gs_jeong 0:005ee97a1572 290 int32_t get_status_low();
daniel_gs_jeong 0:005ee97a1572 291
daniel_gs_jeong 0:005ee97a1572 292 /**
daniel_gs_jeong 0:005ee97a1572 293 * @brief Get Status high
daniel_gs_jeong 0:005ee97a1572 294 * @details Get status register data
daniel_gs_jeong 0:005ee97a1572 295 * BIT7 : Over Temp
daniel_gs_jeong 0:005ee97a1572 296 * BIT6 : Over Current in TX Mode
daniel_gs_jeong 0:005ee97a1572 297 * BIT5 : Over Temp in TX Mode
daniel_gs_jeong 0:005ee97a1572 298 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 299 * BIT3 : Power Transfer Established in Tx Mode
daniel_gs_jeong 0:005ee97a1572 300 * BIT2 : Packet Received in Ping Phase
daniel_gs_jeong 0:005ee97a1572 301 * BIT1 : Packet Received in ID
daniel_gs_jeong 0:005ee97a1572 302 * BIT0 : Packet Received in Power Transfer Phase
daniel_gs_jeong 0:005ee97a1572 303 * @param None
daniel_gs_jeong 0:005ee97a1572 304 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 305 */
daniel_gs_jeong 0:005ee97a1572 306 int32_t get_status_high();
daniel_gs_jeong 0:005ee97a1572 307
daniel_gs_jeong 0:005ee97a1572 308 /**
daniel_gs_jeong 0:005ee97a1572 309 * @brief Get Interrupt low
daniel_gs_jeong 0:005ee97a1572 310 * @details Get Interrupt register data
daniel_gs_jeong 0:005ee97a1572 311 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 312 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 313 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 314 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 315 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 316 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 317 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 318 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 319 * @param None
daniel_gs_jeong 0:005ee97a1572 320 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 321 */
daniel_gs_jeong 0:005ee97a1572 322 int32_t get_interrupt_low();
daniel_gs_jeong 0:005ee97a1572 323
daniel_gs_jeong 0:005ee97a1572 324 /**
daniel_gs_jeong 0:005ee97a1572 325 * @brief Get Interrupt high
daniel_gs_jeong 0:005ee97a1572 326 * @details Get Interrupt register data
daniel_gs_jeong 0:005ee97a1572 327 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 328 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 329 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 330 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 331 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 332 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 333 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 334 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 335 * @param None
daniel_gs_jeong 0:005ee97a1572 336 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 337 */
daniel_gs_jeong 0:005ee97a1572 338 int32_t get_interrupt_high();
daniel_gs_jeong 0:005ee97a1572 339
daniel_gs_jeong 0:005ee97a1572 340 /**
daniel_gs_jeong 0:005ee97a1572 341 * @brief Interrupt enable low
daniel_gs_jeong 0:005ee97a1572 342 * @details
daniel_gs_jeong 0:005ee97a1572 343 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 344 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 345 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 346 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 347 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 348 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 349 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 350 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 351 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 352 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 353 */
daniel_gs_jeong 0:005ee97a1572 354 int32_t set_interrupt_low(MAX77950::interrupt_low_t _int);
daniel_gs_jeong 0:005ee97a1572 355
daniel_gs_jeong 0:005ee97a1572 356 /**
daniel_gs_jeong 0:005ee97a1572 357 * @brief Interrupt enable high
daniel_gs_jeong 0:005ee97a1572 358 * @details
daniel_gs_jeong 0:005ee97a1572 359 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 360 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 361 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 362 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 363 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 364 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 365 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 366 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 367 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 368 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 369 */
daniel_gs_jeong 0:005ee97a1572 370 int32_t set_interrupt_high(MAX77950::interrupt_high_t _int);
daniel_gs_jeong 0:005ee97a1572 371
daniel_gs_jeong 0:005ee97a1572 372 /**
daniel_gs_jeong 0:005ee97a1572 373 * @brief Interrupt disable low
daniel_gs_jeong 0:005ee97a1572 374 * @details
daniel_gs_jeong 0:005ee97a1572 375 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 376 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 377 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 378 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 379 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 380 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 381 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 382 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 383 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 384 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 385 */
daniel_gs_jeong 0:005ee97a1572 386 int32_t disable_interrupt_low(MAX77950::interrupt_low_t _int);
daniel_gs_jeong 0:005ee97a1572 387
daniel_gs_jeong 0:005ee97a1572 388 /**
daniel_gs_jeong 0:005ee97a1572 389 * @brief Interrupt disable high
daniel_gs_jeong 0:005ee97a1572 390 * @details
daniel_gs_jeong 0:005ee97a1572 391 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 392 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 393 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 394 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 395 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 396 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 397 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 398 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 399 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 400 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 401 */
daniel_gs_jeong 0:005ee97a1572 402 int32_t disable_interrupt_high(MAX77950::interrupt_high_t _int);
daniel_gs_jeong 0:005ee97a1572 403
daniel_gs_jeong 0:005ee97a1572 404 /**
daniel_gs_jeong 0:005ee97a1572 405 * @brief Interrupt Clear low
daniel_gs_jeong 0:005ee97a1572 406 * @details
daniel_gs_jeong 0:005ee97a1572 407 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 408 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 409 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 410 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 411 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 412 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 413 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 414 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 415 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 416 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 417 */
daniel_gs_jeong 0:005ee97a1572 418 int32_t clear_interrupt_low(MAX77950::interrupt_low_t _int);
daniel_gs_jeong 0:005ee97a1572 419
daniel_gs_jeong 0:005ee97a1572 420 /**
daniel_gs_jeong 0:005ee97a1572 421 * @brief Interrupt Clear high
daniel_gs_jeong 0:005ee97a1572 422 * @details
daniel_gs_jeong 0:005ee97a1572 423 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 424 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 425 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 426 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 427 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 428 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 429 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 430 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 431 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 432 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 433 */
daniel_gs_jeong 0:005ee97a1572 434 int32_t clear_interrupt_high(MAX77950::interrupt_high_t _int);
daniel_gs_jeong 0:005ee97a1572 435
daniel_gs_jeong 0:005ee97a1572 436 /**
daniel_gs_jeong 0:005ee97a1572 437 * @brief Get SOC(Charge Status);
daniel_gs_jeong 0:005ee97a1572 438 * @details
daniel_gs_jeong 0:005ee97a1572 439 * 0x00, 0x65~0xFE : Reserved
daniel_gs_jeong 0:005ee97a1572 440 * 0x01 ~ 0x64 : 1 ~ 100%
daniel_gs_jeong 0:005ee97a1572 441 * 0xFF : No battery
daniel_gs_jeong 0:005ee97a1572 442 * @param None
daniel_gs_jeong 0:005ee97a1572 443 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 444 0x00: out of range
daniel_gs_jeong 0:005ee97a1572 445 0x01 ~ 0x64: SOC 1~ 100
daniel_gs_jeong 0:005ee97a1572 446 0xff: there is no battery to charge.
daniel_gs_jeong 0:005ee97a1572 447 */
daniel_gs_jeong 0:005ee97a1572 448 int32_t get_charge_status();
daniel_gs_jeong 0:005ee97a1572 449
daniel_gs_jeong 0:005ee97a1572 450 /**
daniel_gs_jeong 0:005ee97a1572 451 * @brief Get VOUT Value
daniel_gs_jeong 0:005ee97a1572 452 * @details
daniel_gs_jeong 0:005ee97a1572 453 * Vout Value 12bit data
daniel_gs_jeong 0:005ee97a1572 454 * @param None
daniel_gs_jeong 0:005ee97a1572 455 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 456 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 457 */
daniel_gs_jeong 0:005ee97a1572 458 int32_t get_vout_value();
daniel_gs_jeong 0:005ee97a1572 459
daniel_gs_jeong 0:005ee97a1572 460 /**
daniel_gs_jeong 0:005ee97a1572 461 * @brief Get VRECT Value
daniel_gs_jeong 0:005ee97a1572 462 * @details
daniel_gs_jeong 0:005ee97a1572 463 * V_rect Value 12bit data
daniel_gs_jeong 0:005ee97a1572 464 * @param None
daniel_gs_jeong 0:005ee97a1572 465 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 466 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 467 */
daniel_gs_jeong 0:005ee97a1572 468 int32_t get_vrect_value();
daniel_gs_jeong 0:005ee97a1572 469
daniel_gs_jeong 0:005ee97a1572 470 /**
daniel_gs_jeong 0:005ee97a1572 471 * @brief Get ISense Value
daniel_gs_jeong 0:005ee97a1572 472 * @details
daniel_gs_jeong 0:005ee97a1572 473 * ISense Value 12bit data
daniel_gs_jeong 0:005ee97a1572 474 * @param None
daniel_gs_jeong 0:005ee97a1572 475 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 476 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 477 */
daniel_gs_jeong 0:005ee97a1572 478 int32_t get_isense_value();
daniel_gs_jeong 0:005ee97a1572 479
daniel_gs_jeong 0:005ee97a1572 480 /**
daniel_gs_jeong 0:005ee97a1572 481 * @brief Get Die Temp Value
daniel_gs_jeong 0:005ee97a1572 482 * @details
daniel_gs_jeong 0:005ee97a1572 483 * Die Temp
daniel_gs_jeong 0:005ee97a1572 484 * @param None
daniel_gs_jeong 0:005ee97a1572 485 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 486 0x00~0xFF
daniel_gs_jeong 0:005ee97a1572 487 */
daniel_gs_jeong 0:005ee97a1572 488 int32_t get_die_temp_value();
daniel_gs_jeong 0:005ee97a1572 489
daniel_gs_jeong 0:005ee97a1572 490 /**
daniel_gs_jeong 0:005ee97a1572 491 * @brief Get AC Operation Frequency
daniel_gs_jeong 0:005ee97a1572 492 * @details
daniel_gs_jeong 0:005ee97a1572 493 * AC Operation Frequency
daniel_gs_jeong 0:005ee97a1572 494 * @param None
daniel_gs_jeong 0:005ee97a1572 495 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 496 0x00~0xFFFF
daniel_gs_jeong 0:005ee97a1572 497 */
daniel_gs_jeong 0:005ee97a1572 498 int32_t get_op_freq_value();
daniel_gs_jeong 0:005ee97a1572 499
daniel_gs_jeong 0:005ee97a1572 500 /**
daniel_gs_jeong 0:005ee97a1572 501 * @brief Get System Operation Mode
daniel_gs_jeong 0:005ee97a1572 502 * @details
daniel_gs_jeong 0:005ee97a1572 503 * read System Operation Mode
daniel_gs_jeong 0:005ee97a1572 504 * @param None
daniel_gs_jeong 0:005ee97a1572 505 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 506 0x00: Initial State
daniel_gs_jeong 0:005ee97a1572 507 0x01: WPC Rx Mode
daniel_gs_jeong 0:005ee97a1572 508 0x02: PMA Rx Mode
daniel_gs_jeong 0:005ee97a1572 509 0x03: Tx Mode(PeerPower);
daniel_gs_jeong 0:005ee97a1572 510 */
daniel_gs_jeong 0:005ee97a1572 511 int32_t get_systme_opmode();
daniel_gs_jeong 0:005ee97a1572 512
daniel_gs_jeong 0:005ee97a1572 513 /**
daniel_gs_jeong 0:005ee97a1572 514 * @brief Global Interrtup Clear
daniel_gs_jeong 0:005ee97a1572 515 * @details
daniel_gs_jeong 0:005ee97a1572 516 * Clears all interrupt bits. After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 517 * @param None
daniel_gs_jeong 0:005ee97a1572 518 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 519 */
daniel_gs_jeong 0:005ee97a1572 520 int32_t set_gloabl_interrupt_clear();
daniel_gs_jeong 0:005ee97a1572 521
daniel_gs_jeong 0:005ee97a1572 522 /**
daniel_gs_jeong 0:005ee97a1572 523 * @brief Send Charger Status
daniel_gs_jeong 0:005ee97a1572 524 * @details
daniel_gs_jeong 0:005ee97a1572 525 Send charge status packet. After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 526 * @param None
daniel_gs_jeong 0:005ee97a1572 527 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 528 */
daniel_gs_jeong 0:005ee97a1572 529 int32_t set_send_charger_status();
daniel_gs_jeong 0:005ee97a1572 530
daniel_gs_jeong 0:005ee97a1572 531 /**
daniel_gs_jeong 0:005ee97a1572 532 * @brief Send "End Power Transfer" Packet
daniel_gs_jeong 0:005ee97a1572 533 * @details
daniel_gs_jeong 0:005ee97a1572 534 Send End Power Transfer Packet.
daniel_gs_jeong 0:005ee97a1572 535 After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 536 * @param None
daniel_gs_jeong 0:005ee97a1572 537 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 538 */
daniel_gs_jeong 0:005ee97a1572 539 int32_t set_send_ept_packet();
daniel_gs_jeong 0:005ee97a1572 540
daniel_gs_jeong 0:005ee97a1572 541 /**
daniel_gs_jeong 0:005ee97a1572 542 * @brief Toggle LDO output
daniel_gs_jeong 0:005ee97a1572 543 * @details
daniel_gs_jeong 0:005ee97a1572 544 Toggle LDO output once (on to off, off to on);.
daniel_gs_jeong 0:005ee97a1572 545 After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 546 * @param None
daniel_gs_jeong 0:005ee97a1572 547 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 548 */
daniel_gs_jeong 0:005ee97a1572 549 int32_t set_toggle_ldo();
daniel_gs_jeong 0:005ee97a1572 550
daniel_gs_jeong 0:005ee97a1572 551 /**
daniel_gs_jeong 0:005ee97a1572 552 * @brief Sed Rx Data
daniel_gs_jeong 0:005ee97a1572 553 * @details
daniel_gs_jeong 0:005ee97a1572 554 Send WPC proprietary packet that includes PPP_Header (0x21);,
daniel_gs_jeong 0:005ee97a1572 555 data command (0x22);, and data values (0x23 to 0x26);.
daniel_gs_jeong 0:005ee97a1572 556 After the set, it resets automatically
daniel_gs_jeong 0:005ee97a1572 557 * @param None
daniel_gs_jeong 0:005ee97a1572 558 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 559 */
daniel_gs_jeong 0:005ee97a1572 560 int32_t set_send_rx_data();
daniel_gs_jeong 0:005ee97a1572 561
daniel_gs_jeong 0:005ee97a1572 562 private:
daniel_gs_jeong 0:005ee97a1572 563
daniel_gs_jeong 0:005ee97a1572 564 I2C *i2c_;
daniel_gs_jeong 0:005ee97a1572 565 bool i2c_owner;
daniel_gs_jeong 0:005ee97a1572 566
daniel_gs_jeong 0:005ee97a1572 567 };
daniel_gs_jeong 0:005ee97a1572 568
daniel_gs_jeong 0:005ee97a1572 569 #endif /* _MAX77950_H_ */