Daniel Geonsi Jeong / max77950

Driver File to control MAX77950, The MAX77950 is an advanced wireless power receiver IC that meets the specification requirements for WPC low-power (v1.2) and PMA SR1 (v2.0) communication protocols. This device operates using near-field magnetic induction when coupled with a WPC or PMA transmitter and provides output power up to 12 watts.

max77950.cpp@0:005ee97a1572, 2019-10-02 (annotated)

Committer:
daniel_gs_jeong
Date:
Wed Oct 02 08:22:22 2019 +0000
Revision:
0:005ee97a1572
MAX77950 Wireless Power Receiver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniel_gs_jeong 0:005ee97a1572 1 /*******************************************************************************
daniel_gs_jeong 0:005ee97a1572 2 * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
daniel_gs_jeong 0:005ee97a1572 3 *
daniel_gs_jeong 0:005ee97a1572 4 * Permission is hereby granted, free of charge, to any person obtaining a
daniel_gs_jeong 0:005ee97a1572 5 * copy of this software and associated documentation files (the "Software"),
daniel_gs_jeong 0:005ee97a1572 6 * to deal in the Software without restriction, including without limitation
daniel_gs_jeong 0:005ee97a1572 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
daniel_gs_jeong 0:005ee97a1572 8 * and/or sell copies of the Software, and to permit persons to whom the
daniel_gs_jeong 0:005ee97a1572 9 * Software is furnished to do so, subject to the following conditions:
daniel_gs_jeong 0:005ee97a1572 10 *
daniel_gs_jeong 0:005ee97a1572 11 * The above copyright notice and this permission notice shall be included
daniel_gs_jeong 0:005ee97a1572 12 * in all copies or substantial portions of the Software.
daniel_gs_jeong 0:005ee97a1572 13 *
daniel_gs_jeong 0:005ee97a1572 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
daniel_gs_jeong 0:005ee97a1572 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
daniel_gs_jeong 0:005ee97a1572 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
daniel_gs_jeong 0:005ee97a1572 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
daniel_gs_jeong 0:005ee97a1572 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
daniel_gs_jeong 0:005ee97a1572 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
daniel_gs_jeong 0:005ee97a1572 20 * OTHER DEALINGS IN THE SOFTWARE.
daniel_gs_jeong 0:005ee97a1572 21 *
daniel_gs_jeong 0:005ee97a1572 22 * Except as contained in this notice, the name of Maxim Integrated
daniel_gs_jeong 0:005ee97a1572 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
daniel_gs_jeong 0:005ee97a1572 24 * Products, Inc. Branding Policy.
daniel_gs_jeong 0:005ee97a1572 25 *
daniel_gs_jeong 0:005ee97a1572 26 * The mere transfer of this software does not imply any licenses
daniel_gs_jeong 0:005ee97a1572 27 * of trade secrets, proprietary technology, copyrights, patents,
daniel_gs_jeong 0:005ee97a1572 28 * trademarks, maskwork rights, or any other form of intellectual
daniel_gs_jeong 0:005ee97a1572 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
daniel_gs_jeong 0:005ee97a1572 30 * ownership rights.
daniel_gs_jeong 0:005ee97a1572 31 *******************************************************************************
daniel_gs_jeong 0:005ee97a1572 32 */
daniel_gs_jeong 0:005ee97a1572 33 #include "max77950.h"
daniel_gs_jeong 0:005ee97a1572 34
daniel_gs_jeong 0:005ee97a1572 35 /***** Definitions *****/
daniel_gs_jeong 0:005ee97a1572 36 #define I2C_ADDR (0x61<<1)
daniel_gs_jeong 0:005ee97a1572 37
daniel_gs_jeong 0:005ee97a1572 38 /**
daniel_gs_jeong 0:005ee97a1572 39 * MAX77950 constructor.
daniel_gs_jeong 0:005ee97a1572 40 *
daniel_gs_jeong 0:005ee97a1572 41 * @param i2c I2C object to use.
daniel_gs_jeong 0:005ee97a1572 42 */
daniel_gs_jeong 0:005ee97a1572 43 MAX77950::MAX77950(I2C *i2c) :
daniel_gs_jeong 0:005ee97a1572 44 i2c_(i2c)
daniel_gs_jeong 0:005ee97a1572 45 {
daniel_gs_jeong 0:005ee97a1572 46 i2c_owner = false;
daniel_gs_jeong 0:005ee97a1572 47 }
daniel_gs_jeong 0:005ee97a1572 48
daniel_gs_jeong 0:005ee97a1572 49 /**
daniel_gs_jeong 0:005ee97a1572 50 * MAX77950 destructor.
daniel_gs_jeong 0:005ee97a1572 51 */
daniel_gs_jeong 0:005ee97a1572 52 MAX77950::~MAX77950()
daniel_gs_jeong 0:005ee97a1572 53 {
daniel_gs_jeong 0:005ee97a1572 54 if(i2c_owner) {
daniel_gs_jeong 0:005ee97a1572 55 delete i2c_;
daniel_gs_jeong 0:005ee97a1572 56 }
daniel_gs_jeong 0:005ee97a1572 57 }
daniel_gs_jeong 0:005ee97a1572 58
daniel_gs_jeong 0:005ee97a1572 59
daniel_gs_jeong 0:005ee97a1572 60 /**
daniel_gs_jeong 0:005ee97a1572 61 * @brief Initialize MAX77950
daniel_gs_jeong 0:005ee97a1572 62 */
daniel_gs_jeong 0:005ee97a1572 63 int32_t MAX77950::init()
daniel_gs_jeong 0:005ee97a1572 64 {
daniel_gs_jeong 0:005ee97a1572 65 // initial code position.
daniel_gs_jeong 0:005ee97a1572 66 return 0;
daniel_gs_jeong 0:005ee97a1572 67 }
daniel_gs_jeong 0:005ee97a1572 68
daniel_gs_jeong 0:005ee97a1572 69 /**
daniel_gs_jeong 0:005ee97a1572 70 * @brief Read Register
daniel_gs_jeong 0:005ee97a1572 71 * @details Reads data from MAX77950 register
daniel_gs_jeong 0:005ee97a1572 72 *
daniel_gs_jeong 0:005ee97a1572 73 * @param reg_addr Register to read
daniel_gs_jeong 0:005ee97a1572 74 * @returns data if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 75 */
daniel_gs_jeong 0:005ee97a1572 76 int32_t MAX77950::read_register(MAX77950::registers_t reg_no)
daniel_gs_jeong 0:005ee97a1572 77 {
daniel_gs_jeong 0:005ee97a1572 78 char data;
daniel_gs_jeong 0:005ee97a1572 79
daniel_gs_jeong 0:005ee97a1572 80 data = reg_no;
daniel_gs_jeong 0:005ee97a1572 81 if (i2c_->write(I2C_ADDR, &data, 1, true) != 0) {
daniel_gs_jeong 0:005ee97a1572 82 return -1;
daniel_gs_jeong 0:005ee97a1572 83 }
daniel_gs_jeong 0:005ee97a1572 84
daniel_gs_jeong 0:005ee97a1572 85 if (i2c_->read(I2C_ADDR | 0x01, &data, 1) != 0) {
daniel_gs_jeong 0:005ee97a1572 86 return -1;
daniel_gs_jeong 0:005ee97a1572 87 }
daniel_gs_jeong 0:005ee97a1572 88
daniel_gs_jeong 0:005ee97a1572 89 return (0x0 + data);
daniel_gs_jeong 0:005ee97a1572 90 }
daniel_gs_jeong 0:005ee97a1572 91
daniel_gs_jeong 0:005ee97a1572 92 /**
daniel_gs_jeong 0:005ee97a1572 93 * @brief Write Register
daniel_gs_jeong 0:005ee97a1572 94 * @details Writes data to MAX77950 register
daniel_gs_jeong 0:005ee97a1572 95 *
daniel_gs_jeong 0:005ee97a1572 96 * @param reg_addr Register to write
daniel_gs_jeong 0:005ee97a1572 97 * @param reg_data Data to write
daniel_gs_jeong 0:005ee97a1572 98 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 99 */
daniel_gs_jeong 0:005ee97a1572 100 int32_t MAX77950::write_register(MAX77950::registers_t reg_no, char reg_data)
daniel_gs_jeong 0:005ee97a1572 101 {
daniel_gs_jeong 0:005ee97a1572 102 char data[2];
daniel_gs_jeong 0:005ee97a1572 103
daniel_gs_jeong 0:005ee97a1572 104 data[0] = reg_no;
daniel_gs_jeong 0:005ee97a1572 105 data[1] = reg_data;
daniel_gs_jeong 0:005ee97a1572 106 if (i2c_->write(I2C_ADDR, data, 2) != 0) {
daniel_gs_jeong 0:005ee97a1572 107 return -1;
daniel_gs_jeong 0:005ee97a1572 108 }
daniel_gs_jeong 0:005ee97a1572 109
daniel_gs_jeong 0:005ee97a1572 110 return 0;
daniel_gs_jeong 0:005ee97a1572 111 }
daniel_gs_jeong 0:005ee97a1572 112
daniel_gs_jeong 0:005ee97a1572 113 /**
daniel_gs_jeong 0:005ee97a1572 114 * @brief Update Register data
daniel_gs_jeong 0:005ee97a1572 115 * @details Update bits data of a register
daniel_gs_jeong 0:005ee97a1572 116 *
daniel_gs_jeong 0:005ee97a1572 117 * @param reg_no Register Number to be updated
daniel_gs_jeong 0:005ee97a1572 118 * @param mask Mask Data
daniel_gs_jeong 0:005ee97a1572 119 * @param reg_data bit data
daniel_gs_jeong 0:005ee97a1572 120 * @returns 0 if no errors, -1 if error.
daniel_gs_jeong 0:005ee97a1572 121 */
daniel_gs_jeong 0:005ee97a1572 122 int32_t MAX77950::update_register
daniel_gs_jeong 0:005ee97a1572 123 (MAX77950::registers_t reg_no, char reg_mask, char reg_data)
daniel_gs_jeong 0:005ee97a1572 124 {
daniel_gs_jeong 0:005ee97a1572 125 int32_t data;
daniel_gs_jeong 0:005ee97a1572 126
daniel_gs_jeong 0:005ee97a1572 127 data = read_register(reg_no);
daniel_gs_jeong 0:005ee97a1572 128 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 129 return -1;
daniel_gs_jeong 0:005ee97a1572 130
daniel_gs_jeong 0:005ee97a1572 131 data &= ~reg_mask;
daniel_gs_jeong 0:005ee97a1572 132 data |= reg_data;
daniel_gs_jeong 0:005ee97a1572 133
daniel_gs_jeong 0:005ee97a1572 134 data = write_register(reg_no, (char)(data & 0xff));
daniel_gs_jeong 0:005ee97a1572 135 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 136 return -1;
daniel_gs_jeong 0:005ee97a1572 137 return 0;
daniel_gs_jeong 0:005ee97a1572 138 }
daniel_gs_jeong 0:005ee97a1572 139
daniel_gs_jeong 0:005ee97a1572 140 /**
daniel_gs_jeong 0:005ee97a1572 141 * @brief Get Status Low
daniel_gs_jeong 0:005ee97a1572 142 * @details Get status register data
daniel_gs_jeong 0:005ee97a1572 143 * BIT7 : LDO is ON
daniel_gs_jeong 0:005ee97a1572 144 * BIT6 : V_rect is over UVLO
daniel_gs_jeong 0:005ee97a1572 145 * BIT5 : Watchdog timer
daniel_gs_jeong 0:005ee97a1572 146 * BIT4 : FSK Data
daniel_gs_jeong 0:005ee97a1572 147 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 148 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 149 * BIT1 : Over Voltage Status
daniel_gs_jeong 0:005ee97a1572 150 * BIT0 : Over Current Status
daniel_gs_jeong 0:005ee97a1572 151 * @param None
daniel_gs_jeong 0:005ee97a1572 152 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 153 */
daniel_gs_jeong 0:005ee97a1572 154 int32_t MAX77950::get_status_low()
daniel_gs_jeong 0:005ee97a1572 155 {
daniel_gs_jeong 0:005ee97a1572 156 int32_t data;
daniel_gs_jeong 0:005ee97a1572 157
daniel_gs_jeong 0:005ee97a1572 158 data = read_register(REG_STATUS_L);
daniel_gs_jeong 0:005ee97a1572 159 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 160 return -1;
daniel_gs_jeong 0:005ee97a1572 161 return (data & 0xf3);
daniel_gs_jeong 0:005ee97a1572 162 }
daniel_gs_jeong 0:005ee97a1572 163
daniel_gs_jeong 0:005ee97a1572 164 /**
daniel_gs_jeong 0:005ee97a1572 165 * @brief Get Status high
daniel_gs_jeong 0:005ee97a1572 166 * @details Get status register data
daniel_gs_jeong 0:005ee97a1572 167 * BIT7 : Over Temp
daniel_gs_jeong 0:005ee97a1572 168 * BIT6 : Over Current in TX Mode
daniel_gs_jeong 0:005ee97a1572 169 * BIT5 : Over Temp in TX Mode
daniel_gs_jeong 0:005ee97a1572 170 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 171 * BIT3 : Power Transfer Established in Tx Mode
daniel_gs_jeong 0:005ee97a1572 172 * BIT2 : Packet Received in Ping Phase
daniel_gs_jeong 0:005ee97a1572 173 * BIT1 : Packet Received in ID
daniel_gs_jeong 0:005ee97a1572 174 * BIT0 : Packet Received in Power Transfer Phase
daniel_gs_jeong 0:005ee97a1572 175 * @param None
daniel_gs_jeong 0:005ee97a1572 176 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 177 */
daniel_gs_jeong 0:005ee97a1572 178 int32_t MAX77950::get_status_high()
daniel_gs_jeong 0:005ee97a1572 179 {
daniel_gs_jeong 0:005ee97a1572 180 int32_t data;
daniel_gs_jeong 0:005ee97a1572 181
daniel_gs_jeong 0:005ee97a1572 182 data = read_register(REG_STATUS_H);
daniel_gs_jeong 0:005ee97a1572 183 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 184 return -1;
daniel_gs_jeong 0:005ee97a1572 185 return (data & 0xef);
daniel_gs_jeong 0:005ee97a1572 186 }
daniel_gs_jeong 0:005ee97a1572 187
daniel_gs_jeong 0:005ee97a1572 188 /**
daniel_gs_jeong 0:005ee97a1572 189 * @brief Get Interrupt low
daniel_gs_jeong 0:005ee97a1572 190 * @details Get Interrupt register data
daniel_gs_jeong 0:005ee97a1572 191 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 192 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 193 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 194 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 195 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 196 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 197 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 198 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 199 * @param None
daniel_gs_jeong 0:005ee97a1572 200 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 201 */
daniel_gs_jeong 0:005ee97a1572 202 int32_t MAX77950::get_interrupt_low()
daniel_gs_jeong 0:005ee97a1572 203 {
daniel_gs_jeong 0:005ee97a1572 204 int32_t data;
daniel_gs_jeong 0:005ee97a1572 205
daniel_gs_jeong 0:005ee97a1572 206 data = read_register(REG_INT_L);
daniel_gs_jeong 0:005ee97a1572 207 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 208 return -1;
daniel_gs_jeong 0:005ee97a1572 209 return (data & 0xf3);
daniel_gs_jeong 0:005ee97a1572 210 }
daniel_gs_jeong 0:005ee97a1572 211
daniel_gs_jeong 0:005ee97a1572 212 /**
daniel_gs_jeong 0:005ee97a1572 213 * @brief Get Interrupt high
daniel_gs_jeong 0:005ee97a1572 214 * @details Get Interrupt register data
daniel_gs_jeong 0:005ee97a1572 215 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 216 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 217 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 218 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 219 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 220 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 221 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 222 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 223 * @param None
daniel_gs_jeong 0:005ee97a1572 224 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 225 */
daniel_gs_jeong 0:005ee97a1572 226 int32_t MAX77950::get_interrupt_high()
daniel_gs_jeong 0:005ee97a1572 227 {
daniel_gs_jeong 0:005ee97a1572 228 int32_t data;
daniel_gs_jeong 0:005ee97a1572 229
daniel_gs_jeong 0:005ee97a1572 230 data = read_register(REG_INT_H);
daniel_gs_jeong 0:005ee97a1572 231 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 232 return -1;
daniel_gs_jeong 0:005ee97a1572 233 return (data & 0xef);
daniel_gs_jeong 0:005ee97a1572 234 }
daniel_gs_jeong 0:005ee97a1572 235
daniel_gs_jeong 0:005ee97a1572 236 /**
daniel_gs_jeong 0:005ee97a1572 237 * @brief Interrupt enable low
daniel_gs_jeong 0:005ee97a1572 238 * @details
daniel_gs_jeong 0:005ee97a1572 239 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 240 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 241 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 242 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 243 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 244 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 245 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 246 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 247 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 248 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 249 */
daniel_gs_jeong 0:005ee97a1572 250 int32_t MAX77950::set_interrupt_low(MAX77950::interrupt_low_t _int)
daniel_gs_jeong 0:005ee97a1572 251 {
daniel_gs_jeong 0:005ee97a1572 252 int32_t data;
daniel_gs_jeong 0:005ee97a1572 253
daniel_gs_jeong 0:005ee97a1572 254 data = update_register(REG_INT_ENABLE_L, (char)_int, (char)_int);
daniel_gs_jeong 0:005ee97a1572 255 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 256 return -1;
daniel_gs_jeong 0:005ee97a1572 257 return 0;
daniel_gs_jeong 0:005ee97a1572 258 }
daniel_gs_jeong 0:005ee97a1572 259
daniel_gs_jeong 0:005ee97a1572 260 /**
daniel_gs_jeong 0:005ee97a1572 261 * @brief Interrupt enable high
daniel_gs_jeong 0:005ee97a1572 262 * @details
daniel_gs_jeong 0:005ee97a1572 263 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 264 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 265 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 266 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 267 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 268 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 269 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 270 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 271 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 272 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 273 */
daniel_gs_jeong 0:005ee97a1572 274 int32_t MAX77950::set_interrupt_high(MAX77950::interrupt_high_t _int)
daniel_gs_jeong 0:005ee97a1572 275 {
daniel_gs_jeong 0:005ee97a1572 276 int32_t data;
daniel_gs_jeong 0:005ee97a1572 277
daniel_gs_jeong 0:005ee97a1572 278 data = update_register(REG_INT_ENABLE_H, (char)_int, (char)_int);
daniel_gs_jeong 0:005ee97a1572 279 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 280 return -1;
daniel_gs_jeong 0:005ee97a1572 281 return 0;
daniel_gs_jeong 0:005ee97a1572 282 }
daniel_gs_jeong 0:005ee97a1572 283
daniel_gs_jeong 0:005ee97a1572 284 /**
daniel_gs_jeong 0:005ee97a1572 285 * @brief Interrupt disable low
daniel_gs_jeong 0:005ee97a1572 286 * @details
daniel_gs_jeong 0:005ee97a1572 287 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 288 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 289 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 290 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 291 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 292 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 293 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 294 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 295 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 296 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 297 */
daniel_gs_jeong 0:005ee97a1572 298 int32_t MAX77950::disable_interrupt_low(MAX77950::interrupt_low_t _int)
daniel_gs_jeong 0:005ee97a1572 299 {
daniel_gs_jeong 0:005ee97a1572 300 int32_t data;
daniel_gs_jeong 0:005ee97a1572 301
daniel_gs_jeong 0:005ee97a1572 302 data = update_register(REG_INT_ENABLE_L, (char)_int, 0);
daniel_gs_jeong 0:005ee97a1572 303 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 304 return -1;
daniel_gs_jeong 0:005ee97a1572 305 return 0;
daniel_gs_jeong 0:005ee97a1572 306 }
daniel_gs_jeong 0:005ee97a1572 307
daniel_gs_jeong 0:005ee97a1572 308 /**
daniel_gs_jeong 0:005ee97a1572 309 * @brief Interrupt disable high
daniel_gs_jeong 0:005ee97a1572 310 * @details
daniel_gs_jeong 0:005ee97a1572 311 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 312 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 313 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 314 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 315 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 316 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 317 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 318 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 319 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 320 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 321 */
daniel_gs_jeong 0:005ee97a1572 322 int32_t MAX77950::disable_interrupt_high(MAX77950::interrupt_high_t _int)
daniel_gs_jeong 0:005ee97a1572 323 {
daniel_gs_jeong 0:005ee97a1572 324 int32_t data;
daniel_gs_jeong 0:005ee97a1572 325
daniel_gs_jeong 0:005ee97a1572 326 data = update_register(REG_INT_ENABLE_H, (char)_int, 0);
daniel_gs_jeong 0:005ee97a1572 327 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 328 return -1;
daniel_gs_jeong 0:005ee97a1572 329 return 0;
daniel_gs_jeong 0:005ee97a1572 330 }
daniel_gs_jeong 0:005ee97a1572 331
daniel_gs_jeong 0:005ee97a1572 332 /**
daniel_gs_jeong 0:005ee97a1572 333 * @brief Interrupt Clear low
daniel_gs_jeong 0:005ee97a1572 334 * @details
daniel_gs_jeong 0:005ee97a1572 335 * BIT7 : LDO state change Interrupt
daniel_gs_jeong 0:005ee97a1572 336 * BIT6 : V_rect is over UVLO Interrupt
daniel_gs_jeong 0:005ee97a1572 337 * BIT5 : Watchdog timer Interrupt
daniel_gs_jeong 0:005ee97a1572 338 * BIT4 : FSK Data Interrupt
daniel_gs_jeong 0:005ee97a1572 339 * BIT3 : Reserved
daniel_gs_jeong 0:005ee97a1572 340 * BIT2 : Reserved
daniel_gs_jeong 0:005ee97a1572 341 * BIT1 : Over Voltage Interrupt
daniel_gs_jeong 0:005ee97a1572 342 * BIT0 : Over Current Interrupt
daniel_gs_jeong 0:005ee97a1572 343 * @param interrupt_low_t
daniel_gs_jeong 0:005ee97a1572 344 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 345 */
daniel_gs_jeong 0:005ee97a1572 346 int32_t MAX77950::clear_interrupt_low(MAX77950::interrupt_low_t _int)
daniel_gs_jeong 0:005ee97a1572 347 {
daniel_gs_jeong 0:005ee97a1572 348 int32_t data;
daniel_gs_jeong 0:005ee97a1572 349
daniel_gs_jeong 0:005ee97a1572 350 data = update_register(REG_INT_CLEAR_L, (char)_int, (char)_int);
daniel_gs_jeong 0:005ee97a1572 351 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 352 return -1;
daniel_gs_jeong 0:005ee97a1572 353 return 0;
daniel_gs_jeong 0:005ee97a1572 354 }
daniel_gs_jeong 0:005ee97a1572 355
daniel_gs_jeong 0:005ee97a1572 356 /**
daniel_gs_jeong 0:005ee97a1572 357 * @brief Interrupt Clear high
daniel_gs_jeong 0:005ee97a1572 358 * @details
daniel_gs_jeong 0:005ee97a1572 359 * BIT7 : Over Temp Interrupt
daniel_gs_jeong 0:005ee97a1572 360 * BIT6 : Over Current in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 361 * BIT5 : Over Temp in TX Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 362 * BIT4 : Reserved
daniel_gs_jeong 0:005ee97a1572 363 * BIT3 : Power Transfer Established in Tx Mode Interrupt
daniel_gs_jeong 0:005ee97a1572 364 * BIT2 : Packet Received in Ping Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 365 * BIT1 : Packet Received in ID Interrupt
daniel_gs_jeong 0:005ee97a1572 366 * BIT0 : Packet Received in Power Transfer Phase Interrupt
daniel_gs_jeong 0:005ee97a1572 367 * @param interrupt_high_t
daniel_gs_jeong 0:005ee97a1572 368 * @returns status register data.
daniel_gs_jeong 0:005ee97a1572 369 */
daniel_gs_jeong 0:005ee97a1572 370 int32_t MAX77950::clear_interrupt_high(MAX77950::interrupt_high_t _int)
daniel_gs_jeong 0:005ee97a1572 371 {
daniel_gs_jeong 0:005ee97a1572 372 int32_t data;
daniel_gs_jeong 0:005ee97a1572 373
daniel_gs_jeong 0:005ee97a1572 374 data = update_register(REG_INT_CLEAR_H, (char)_int, (char)_int);
daniel_gs_jeong 0:005ee97a1572 375 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 376 return -1;
daniel_gs_jeong 0:005ee97a1572 377 return 0;
daniel_gs_jeong 0:005ee97a1572 378 }
daniel_gs_jeong 0:005ee97a1572 379
daniel_gs_jeong 0:005ee97a1572 380 /**
daniel_gs_jeong 0:005ee97a1572 381 * @brief Get SOC(Charge Status)
daniel_gs_jeong 0:005ee97a1572 382 * @details
daniel_gs_jeong 0:005ee97a1572 383 * 0x00, 0x65~0xFE : Reserved
daniel_gs_jeong 0:005ee97a1572 384 * 0x01 ~ 0x64 : 1 ~ 100%
daniel_gs_jeong 0:005ee97a1572 385 * 0xFF : No battery
daniel_gs_jeong 0:005ee97a1572 386 * @param None
daniel_gs_jeong 0:005ee97a1572 387 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 388 0x00: out of range
daniel_gs_jeong 0:005ee97a1572 389 0x01 ~ 0x64: SOC 1~ 100
daniel_gs_jeong 0:005ee97a1572 390 0xff: there is no battery to charge.
daniel_gs_jeong 0:005ee97a1572 391 */
daniel_gs_jeong 0:005ee97a1572 392 int32_t MAX77950::get_charge_status()
daniel_gs_jeong 0:005ee97a1572 393 {
daniel_gs_jeong 0:005ee97a1572 394 int32_t data;
daniel_gs_jeong 0:005ee97a1572 395
daniel_gs_jeong 0:005ee97a1572 396 data = read_register(REG_CHARGE_STATUS);
daniel_gs_jeong 0:005ee97a1572 397 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 398 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 399
daniel_gs_jeong 0:005ee97a1572 400 if( (data & 0xff) == 0xff )
daniel_gs_jeong 0:005ee97a1572 401 return 0xff; // here is no battery to charge
daniel_gs_jeong 0:005ee97a1572 402
daniel_gs_jeong 0:005ee97a1572 403 if( (data &0xff) < 0x01 || (data &0xff)>0x64 )
daniel_gs_jeong 0:005ee97a1572 404 return 0;
daniel_gs_jeong 0:005ee97a1572 405
daniel_gs_jeong 0:005ee97a1572 406 return ((data &0xff));
daniel_gs_jeong 0:005ee97a1572 407 }
daniel_gs_jeong 0:005ee97a1572 408
daniel_gs_jeong 0:005ee97a1572 409 /**
daniel_gs_jeong 0:005ee97a1572 410 * @brief Get VOUT Value
daniel_gs_jeong 0:005ee97a1572 411 * @details
daniel_gs_jeong 0:005ee97a1572 412 * Vout Value 12bit data
daniel_gs_jeong 0:005ee97a1572 413 * @param None
daniel_gs_jeong 0:005ee97a1572 414 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 415 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 416 */
daniel_gs_jeong 0:005ee97a1572 417 int32_t MAX77950::get_vout_value()
daniel_gs_jeong 0:005ee97a1572 418 {
daniel_gs_jeong 0:005ee97a1572 419 int32_t data_h, data_l;
daniel_gs_jeong 0:005ee97a1572 420
daniel_gs_jeong 0:005ee97a1572 421 data_h = read_register(REG_VOUTVAL_H);
daniel_gs_jeong 0:005ee97a1572 422 if(data_h < 0)
daniel_gs_jeong 0:005ee97a1572 423 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 424
daniel_gs_jeong 0:005ee97a1572 425 data_l = read_register(REG_VOUTVAL_L);
daniel_gs_jeong 0:005ee97a1572 426 if(data_l < 0)
daniel_gs_jeong 0:005ee97a1572 427 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 428
daniel_gs_jeong 0:005ee97a1572 429 return (((data_h << 4) & 0xff0) |(data_l & 0xf));
daniel_gs_jeong 0:005ee97a1572 430 }
daniel_gs_jeong 0:005ee97a1572 431
daniel_gs_jeong 0:005ee97a1572 432 /**
daniel_gs_jeong 0:005ee97a1572 433 * @brief Get VRECT Value
daniel_gs_jeong 0:005ee97a1572 434 * @details
daniel_gs_jeong 0:005ee97a1572 435 * V_rect Value 12bit data
daniel_gs_jeong 0:005ee97a1572 436 * @param None
daniel_gs_jeong 0:005ee97a1572 437 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 438 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 439 */
daniel_gs_jeong 0:005ee97a1572 440 int32_t MAX77950::get_vrect_value()
daniel_gs_jeong 0:005ee97a1572 441 {
daniel_gs_jeong 0:005ee97a1572 442 int32_t data_h, data_l;
daniel_gs_jeong 0:005ee97a1572 443
daniel_gs_jeong 0:005ee97a1572 444 data_h = read_register(REG_VRECTVAL_H);
daniel_gs_jeong 0:005ee97a1572 445 if(data_h < 0)
daniel_gs_jeong 0:005ee97a1572 446 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 447
daniel_gs_jeong 0:005ee97a1572 448 data_l = read_register(REG_VRECTVAL_L);
daniel_gs_jeong 0:005ee97a1572 449 if(data_l < 0)
daniel_gs_jeong 0:005ee97a1572 450 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 451
daniel_gs_jeong 0:005ee97a1572 452 return (((data_h << 4) & 0xff0) |(data_l & 0xf));
daniel_gs_jeong 0:005ee97a1572 453 }
daniel_gs_jeong 0:005ee97a1572 454
daniel_gs_jeong 0:005ee97a1572 455 /**
daniel_gs_jeong 0:005ee97a1572 456 * @brief Get ISense Value
daniel_gs_jeong 0:005ee97a1572 457 * @details
daniel_gs_jeong 0:005ee97a1572 458 * ISense Value 12bit data
daniel_gs_jeong 0:005ee97a1572 459 * @param None
daniel_gs_jeong 0:005ee97a1572 460 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 461 0x00~0xFFF
daniel_gs_jeong 0:005ee97a1572 462 */
daniel_gs_jeong 0:005ee97a1572 463 int32_t MAX77950::get_isense_value()
daniel_gs_jeong 0:005ee97a1572 464 {
daniel_gs_jeong 0:005ee97a1572 465 int32_t data_h, data_l;
daniel_gs_jeong 0:005ee97a1572 466
daniel_gs_jeong 0:005ee97a1572 467 data_h = read_register(REG_ISENSEVAL_H);
daniel_gs_jeong 0:005ee97a1572 468 if(data_h < 0)
daniel_gs_jeong 0:005ee97a1572 469 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 470
daniel_gs_jeong 0:005ee97a1572 471 data_l = read_register(REG_ISENSEVAL_L);
daniel_gs_jeong 0:005ee97a1572 472 if(data_l < 0)
daniel_gs_jeong 0:005ee97a1572 473 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 474
daniel_gs_jeong 0:005ee97a1572 475 return (((data_h << 4) & 0xff0) |(data_l & 0xf));
daniel_gs_jeong 0:005ee97a1572 476 }
daniel_gs_jeong 0:005ee97a1572 477
daniel_gs_jeong 0:005ee97a1572 478 /**
daniel_gs_jeong 0:005ee97a1572 479 * @brief Get Die Temp Value
daniel_gs_jeong 0:005ee97a1572 480 * @details
daniel_gs_jeong 0:005ee97a1572 481 * Die Temp
daniel_gs_jeong 0:005ee97a1572 482 * @param None
daniel_gs_jeong 0:005ee97a1572 483 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 484 0x00~0xFF
daniel_gs_jeong 0:005ee97a1572 485 */
daniel_gs_jeong 0:005ee97a1572 486 int32_t MAX77950::get_die_temp_value()
daniel_gs_jeong 0:005ee97a1572 487 {
daniel_gs_jeong 0:005ee97a1572 488 int32_t data_h, data_l;
daniel_gs_jeong 0:005ee97a1572 489
daniel_gs_jeong 0:005ee97a1572 490 data_h = read_register(REG_ISENSEVAL_H);
daniel_gs_jeong 0:005ee97a1572 491 if(data_h < 0)
daniel_gs_jeong 0:005ee97a1572 492 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 493
daniel_gs_jeong 0:005ee97a1572 494 data_l = read_register(REG_ISENSEVAL_L);
daniel_gs_jeong 0:005ee97a1572 495 if(data_l < 0)
daniel_gs_jeong 0:005ee97a1572 496 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 497
daniel_gs_jeong 0:005ee97a1572 498 return (((data_h << 4) & 0xff0) |(data_l & 0xf));
daniel_gs_jeong 0:005ee97a1572 499 }
daniel_gs_jeong 0:005ee97a1572 500
daniel_gs_jeong 0:005ee97a1572 501 /**
daniel_gs_jeong 0:005ee97a1572 502 * @brief Get AC Operation Frequency
daniel_gs_jeong 0:005ee97a1572 503 * @details
daniel_gs_jeong 0:005ee97a1572 504 * AC Operation Frequency
daniel_gs_jeong 0:005ee97a1572 505 * @param None
daniel_gs_jeong 0:005ee97a1572 506 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 507 0x00~0xFFFF
daniel_gs_jeong 0:005ee97a1572 508 */
daniel_gs_jeong 0:005ee97a1572 509 int32_t MAX77950::get_op_freq_value()
daniel_gs_jeong 0:005ee97a1572 510 {
daniel_gs_jeong 0:005ee97a1572 511 int32_t data_h, data_l;
daniel_gs_jeong 0:005ee97a1572 512
daniel_gs_jeong 0:005ee97a1572 513 data_h = read_register(REG_OP_FREQ_H);
daniel_gs_jeong 0:005ee97a1572 514 if(data_h < 0)
daniel_gs_jeong 0:005ee97a1572 515 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 516
daniel_gs_jeong 0:005ee97a1572 517 data_l = read_register(REG_OP_FREQ_L);
daniel_gs_jeong 0:005ee97a1572 518 if(data_l < 0)
daniel_gs_jeong 0:005ee97a1572 519 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 520
daniel_gs_jeong 0:005ee97a1572 521 return (((data_h << 8) & 0xff00) |(data_l & 0xff));
daniel_gs_jeong 0:005ee97a1572 522 }
daniel_gs_jeong 0:005ee97a1572 523
daniel_gs_jeong 0:005ee97a1572 524 /**
daniel_gs_jeong 0:005ee97a1572 525 * @brief Get System Operation Mode
daniel_gs_jeong 0:005ee97a1572 526 * @details
daniel_gs_jeong 0:005ee97a1572 527 * read System Operation Mode
daniel_gs_jeong 0:005ee97a1572 528 * @param None
daniel_gs_jeong 0:005ee97a1572 529 * @returns -1: Communication Error
daniel_gs_jeong 0:005ee97a1572 530 0x00: Initial State
daniel_gs_jeong 0:005ee97a1572 531 0x01: WPC Rx Mode
daniel_gs_jeong 0:005ee97a1572 532 0x02: PMA Rx Mode
daniel_gs_jeong 0:005ee97a1572 533 0x03: Tx Mode(PeerPower)
daniel_gs_jeong 0:005ee97a1572 534 */
daniel_gs_jeong 0:005ee97a1572 535 int32_t MAX77950::get_systme_opmode()
daniel_gs_jeong 0:005ee97a1572 536 {
daniel_gs_jeong 0:005ee97a1572 537 int32_t data;
daniel_gs_jeong 0:005ee97a1572 538
daniel_gs_jeong 0:005ee97a1572 539 data = read_register(REG_SYS_OP_MODE);
daniel_gs_jeong 0:005ee97a1572 540 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 541 return -1; // communication Error
daniel_gs_jeong 0:005ee97a1572 542
daniel_gs_jeong 0:005ee97a1572 543 return (data & 0x07);
daniel_gs_jeong 0:005ee97a1572 544 }
daniel_gs_jeong 0:005ee97a1572 545
daniel_gs_jeong 0:005ee97a1572 546 /**
daniel_gs_jeong 0:005ee97a1572 547 * @brief Global Interrtup Clear
daniel_gs_jeong 0:005ee97a1572 548 * @details
daniel_gs_jeong 0:005ee97a1572 549 * Clears all interrupt bits. After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 550 * @param None
daniel_gs_jeong 0:005ee97a1572 551 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 552 */
daniel_gs_jeong 0:005ee97a1572 553 int32_t MAX77950::set_gloabl_interrupt_clear()
daniel_gs_jeong 0:005ee97a1572 554 {
daniel_gs_jeong 0:005ee97a1572 555 int32_t data;
daniel_gs_jeong 0:005ee97a1572 556
daniel_gs_jeong 0:005ee97a1572 557 data = update_register(REG_RX_COM, (char)0x20, (char)0x20);
daniel_gs_jeong 0:005ee97a1572 558 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 559 return -1;
daniel_gs_jeong 0:005ee97a1572 560 return 0;
daniel_gs_jeong 0:005ee97a1572 561 }
daniel_gs_jeong 0:005ee97a1572 562
daniel_gs_jeong 0:005ee97a1572 563 /**
daniel_gs_jeong 0:005ee97a1572 564 * @brief Send Charger Status
daniel_gs_jeong 0:005ee97a1572 565 * @details
daniel_gs_jeong 0:005ee97a1572 566 Send charge status packet. After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 567 * @param None
daniel_gs_jeong 0:005ee97a1572 568 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 569 */
daniel_gs_jeong 0:005ee97a1572 570 int32_t MAX77950::set_send_charger_status()
daniel_gs_jeong 0:005ee97a1572 571 {
daniel_gs_jeong 0:005ee97a1572 572 int32_t data;
daniel_gs_jeong 0:005ee97a1572 573
daniel_gs_jeong 0:005ee97a1572 574 data = update_register(REG_RX_COM, (char)0x10, (char)0x10);
daniel_gs_jeong 0:005ee97a1572 575 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 576 return -1;
daniel_gs_jeong 0:005ee97a1572 577 return 0;
daniel_gs_jeong 0:005ee97a1572 578 }
daniel_gs_jeong 0:005ee97a1572 579
daniel_gs_jeong 0:005ee97a1572 580 /**
daniel_gs_jeong 0:005ee97a1572 581 * @brief Send "End Power Transfer" Packet
daniel_gs_jeong 0:005ee97a1572 582 * @details
daniel_gs_jeong 0:005ee97a1572 583 Send End Power Transfer Packet.
daniel_gs_jeong 0:005ee97a1572 584 After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 585 * @param None
daniel_gs_jeong 0:005ee97a1572 586 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 587 */
daniel_gs_jeong 0:005ee97a1572 588 int32_t MAX77950::set_send_ept_packet()
daniel_gs_jeong 0:005ee97a1572 589 {
daniel_gs_jeong 0:005ee97a1572 590 int32_t data;
daniel_gs_jeong 0:005ee97a1572 591
daniel_gs_jeong 0:005ee97a1572 592 data = update_register(REG_RX_COM, (char)0x08, (char)0x08);
daniel_gs_jeong 0:005ee97a1572 593 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 594 return -1;
daniel_gs_jeong 0:005ee97a1572 595 return 0;
daniel_gs_jeong 0:005ee97a1572 596 }
daniel_gs_jeong 0:005ee97a1572 597
daniel_gs_jeong 0:005ee97a1572 598 /**
daniel_gs_jeong 0:005ee97a1572 599 * @brief Toggle LDO output
daniel_gs_jeong 0:005ee97a1572 600 * @details
daniel_gs_jeong 0:005ee97a1572 601 Toggle LDO output once (on to off, off to on).
daniel_gs_jeong 0:005ee97a1572 602 After the set, it resets automatically.
daniel_gs_jeong 0:005ee97a1572 603 * @param None
daniel_gs_jeong 0:005ee97a1572 604 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 605 */
daniel_gs_jeong 0:005ee97a1572 606 int32_t MAX77950::set_toggle_ldo()
daniel_gs_jeong 0:005ee97a1572 607 {
daniel_gs_jeong 0:005ee97a1572 608 int32_t data;
daniel_gs_jeong 0:005ee97a1572 609
daniel_gs_jeong 0:005ee97a1572 610 data = update_register(REG_RX_COM, (char)0x02, (char)0x02);
daniel_gs_jeong 0:005ee97a1572 611 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 612 return -1;
daniel_gs_jeong 0:005ee97a1572 613 return 0;
daniel_gs_jeong 0:005ee97a1572 614 }
daniel_gs_jeong 0:005ee97a1572 615
daniel_gs_jeong 0:005ee97a1572 616 /**
daniel_gs_jeong 0:005ee97a1572 617 * @brief Sed Rx Data
daniel_gs_jeong 0:005ee97a1572 618 * @details
daniel_gs_jeong 0:005ee97a1572 619 Send WPC proprietary packet that includes PPP_Header (0x21),
daniel_gs_jeong 0:005ee97a1572 620 data command (0x22), and data values (0x23 to 0x26).
daniel_gs_jeong 0:005ee97a1572 621 After the set, it resets automatically
daniel_gs_jeong 0:005ee97a1572 622 * @param None
daniel_gs_jeong 0:005ee97a1572 623 * @returns Communication status.
daniel_gs_jeong 0:005ee97a1572 624 */
daniel_gs_jeong 0:005ee97a1572 625 int32_t MAX77950::set_send_rx_data()
daniel_gs_jeong 0:005ee97a1572 626 {
daniel_gs_jeong 0:005ee97a1572 627 int32_t data;
daniel_gs_jeong 0:005ee97a1572 628
daniel_gs_jeong 0:005ee97a1572 629 data = update_register(REG_RX_COM, (char)0x01, (char)0x01);
daniel_gs_jeong 0:005ee97a1572 630 if(data < 0)
daniel_gs_jeong 0:005ee97a1572 631 return -1;
daniel_gs_jeong 0:005ee97a1572 632 return 0;
daniel_gs_jeong 0:005ee97a1572 633 }
daniel_gs_jeong 0:005ee97a1572 634
daniel_gs_jeong 0:005ee97a1572 635
daniel_gs_jeong 0:005ee97a1572 636