main.cpp

00001 #include "test_env.h"
00002 
00003 #if !DEVICE_PORTIN
00004   #error [NOT_SUPPORTED] PortIn is not supported
00005 #endif
00006 
00007 #if !DEVICE_PORTOUT
00008   #error [NOT_SUPPORTED] PortOut is not supported
00009 #endif
00010 
00011 #if defined(TARGET_K64F) || defined(TARGET_KL05Z)
00012 #define P1_1    (1 << 16)
00013 #define P1_2    (1 << 17)
00014 #define PORT_1  PortC
00015 
00016 #define P2_1    (1 << 2)
00017 #define P2_2    (1 << 3)
00018 #define PORT_2  PortC
00019 
00020 #elif defined(TARGET_K66F)
00021 #define P1_1    (1 << 3)
00022 #define P1_2    (1 << 4)
00023 #define PORT_1  PortC
00024 
00025 #define P2_1    (1 << 5)
00026 #define P2_2    (1 << 2)
00027 #define PORT_2  PortC
00028 
00029 #elif defined(TARGET_LPC11U24)
00030 #define P1_1    (1 <<  9) // p0.9
00031 #define P1_2    (1 <<  8) // p0.8
00032 #define PORT_1  Port0
00033 
00034 #define P2_1    (1 << 24) // p1.24
00035 #define P2_2    (1 << 25) // p1.25
00036 #define PORT_2  Port1
00037 
00038 #elif defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
00039 #define P1_1    (1 << 9)  // p0.9  -> p5
00040 #define P1_2    (1 << 8)  // p0.8  -> p6
00041 #define PORT_1  Port0
00042 
00043 #define P2_1    (1 << 1)  // p2.1 -> p25
00044 #define P2_2    (1 << 0)  // p2.0 -> p26
00045 #define PORT_2  Port2
00046 
00047 #elif defined(TARGET_LPC4088)
00048 #define P1_1    (1 << 7)  // p0.7  -> p13
00049 #define P1_2    (1 << 6)  // p0.6  -> p14
00050 #define PORT_1  Port0
00051 
00052 #define P2_1    (1 << 2)  // p1.2 -> p30
00053 #define P2_2    (1 << 3)  // p1.3 -> p29
00054 #define PORT_2  Port1
00055 
00056 #elif defined(TARGET_LPC1114)
00057 #define P1_1    (1 <<  9) // p0.9
00058 #define P1_2    (1 <<  8) // p0.8
00059 #define PORT_1  Port0
00060 
00061 #define P2_1    (1 << 1) // p1.1
00062 #define P2_2    (1 << 0) // p1.0
00063 #define PORT_2  Port1
00064 
00065 #elif defined(TARGET_KL25Z)
00066 #define P1_1    (1 << 4)  // PTA4
00067 #define P1_2    (1 << 5)  // PTA5
00068 #define PORT_1  PortA
00069 
00070 #define P2_1    (1 << 5)  // PTC5
00071 #define P2_2    (1 << 6)  // PTC6
00072 #define PORT_2  PortC
00073 
00074 #elif defined(TARGET_nRF51822)
00075 #define P1_1    (1 << 4)  // p4
00076 #define P1_2    (1 << 5)  // p5
00077 #define PORT_1  Port0
00078 
00079 #define P2_1    (1 << 24)  // p24
00080 #define P2_2    (1 << 25)  // p25
00081 #define PORT_2  Port0
00082 
00083 #elif defined(TARGET_MAXWSNENV)
00084 #define P1_1    (1 << 0)
00085 #define P1_2    (1 << 1)
00086 #define PORT_1  Port0
00087 
00088 #define P2_1    (1 << 0)
00089 #define P2_2    (1 << 1)
00090 #define PORT_2  Port1
00091 
00092 #elif defined(TARGET_MAX32600MBED)
00093 #define P1_1    (1 << 0)  // P1_0
00094 #define P1_2    (1 << 1)  // P1_1
00095 #define PORT_1  Port1
00096 
00097 #define P2_1    (1 << 7)  // P4_7
00098 #define P2_2    (1 << 6)  // P4_6
00099 #define PORT_2  Port4
00100 
00101 #elif defined(TARGET_DISCO_F469NI)
00102 
00103 #define P1_1    (1 << 2)  // PC_2
00104 #define P1_2    (1 << 3)  // PC_3
00105 #define PORT_1  PortC
00106 
00107 #define P2_1    (1 << 1)  // PA_1
00108 #define P2_2    (1 << 2)  // PA_2
00109 #define PORT_2  PortA
00110 
00111 #elif defined(TARGET_NUCLEO_F030R8) || \
00112       defined(TARGET_NUCLEO_F070RB) || \
00113       defined(TARGET_NUCLEO_F072RB) || \
00114       defined(TARGET_NUCLEO_F091RC) || \
00115       defined(TARGET_NUCLEO_F103RB) || \
00116       defined(TARGET_NUCLEO_F302R8) || \
00117       defined(TARGET_NUCLEO_F303RE) || \
00118       defined(TARGET_NUCLEO_F334R8) || \
00119       defined(TARGET_NUCLEO_F401RE) || \
00120       defined(TARGET_NUCLEO_F410RB) || \
00121       defined(TARGET_NUCLEO_F411RE) || \
00122       defined(TARGET_NUCLEO_L053R8) || \
00123       defined(TARGET_NUCLEO_L073RZ) || \
00124       defined(TARGET_NUCLEO_L152RE)
00125 #define P1_1    (1 << 6)  // PC_6
00126 #define P1_2    (1 << 5)  // PC_5
00127 #define PORT_1  PortC
00128 
00129 #define P2_1    (1 << 8)  // PB_8
00130 #define P2_2    (1 << 9)  // PB_9
00131 #define PORT_2  PortB
00132 
00133 #elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
00134 #define P1_1    (1 << 0)  // PD0
00135 #define P1_2    (1 << 1)  // PD1
00136 #define PORT_1  PortD
00137 
00138 #define P2_1    (1 << 3)  // PC3
00139 #define P2_2    (1 << 4)  // PC4
00140 #define PORT_2  PortC
00141 
00142 #elif defined(TARGET_EFM32ZG_STK3200)
00143 #define P1_1    (1 << 7)  // PD7
00144 #define P1_2    (1 << 6)  // PD6
00145 #define PORT_1  PortD
00146 
00147 #define P2_1    (1 << 1)  // PC1
00148 #define P2_2    (1 << 2)  // PC2
00149 #define PORT_2  PortC
00150 
00151 #elif defined(TARGET_EFM32HG_STK3400)
00152 #define P1_1    (1 << 10)  // PE10
00153 #define P1_2    (1 << 11)  // PE11
00154 #define PORT_1  PortE
00155 
00156 #define P2_1    (1 << 1)  // PC1
00157 #define P2_2    (1 << 2)  // PC2
00158 #define PORT_2  PortC
00159 
00160 #elif defined(TARGET_EFM32PG_STK3401)
00161 #define P1_1    (1 << 6)  // PC6
00162 #define P1_2    (1 << 7)  // PC7
00163 #define PORT_1  PortC
00164 
00165 #define P2_1    (1 << 3)  // PA3
00166 #define P2_2    (1 << 4)  // PA4
00167 #define PORT_2  PortA
00168 
00169 #elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A)
00170 #define P1_1    (1 << 6)  /*PA06*/
00171 #define P1_2    (1 << 7)  /*PA07*/
00172 #define PORT_1  PortA
00173 
00174 #define P2_1    (1 << 2)  /*PB02*/
00175 #define P2_2    (1 << 3)  /*PB03*/
00176 #define PORT_2  PortB
00177 
00178 #elif defined(TARGET_SAMD21G18A)
00179 #define P1_1    (1 << 2)  /*PA02*/
00180 #define P1_2    (1 << 3)  /*PA03*/
00181 #define PORT_1  PortA
00182 
00183 #define P2_1    (1 << 2)  /*PB02*/
00184 #define P2_2    (1 << 3)  /*PB03*/
00185 #define PORT_2  PortB
00186 
00187 #elif defined(TARGET_SAML21J18A)
00188 #define P1_1    (1 << 4)  /*PA04*/
00189 #define P1_2    (1 << 5)  /*PA05*/
00190 #define PORT_1  PortA
00191 
00192 #define P2_1    (1 << 0)  /*PB00*/
00193 #define P2_2    (1 << 1)  /*PB01*/
00194 #define PORT_2  PortB
00195 
00196 #elif defined(TARGET_SAMG55J19)
00197 #define P1_1    (1 << 17)  /*PA17*/
00198 #define P1_2    (1 << 18)  /*PA18*/
00199 #define PORT_1  PortA
00200 
00201 #define P2_1    (1 << 10)  /*PB10*/
00202 #define P2_2    (1 << 11)  /*PB11*/
00203 #define PORT_2  PortB
00204 
00205 #elif defined(TARGET_VK_RZ_A1H)
00206 #define P1_1    (1 << 2)  /*P3_2*/
00207 #define P1_2    (1 << 7)  /*P3_7*/
00208 #define PORT_1  Port3
00209 
00210 #define P2_1    (1 << 6)  /*P5_6*/
00211 #define P2_2    (1 << 1)  /*P5_1*/
00212 #define PORT_2  Port5
00213 
00214 #else
00215 #error [NOT_SUPPORTED] This test is not supported on this target
00216 #endif
00217 
00218 #define MASK_1   (P1_1 | P1_2)
00219 #define MASK_2   (P2_1 | P2_2)
00220 
00221 PortOut port_out(PORT_1, MASK_1);
00222 PortIn  port_in (PORT_2, MASK_2);
00223 
00224 int main() {
00225     MBED_HOSTTEST_TIMEOUT(20);
00226     MBED_HOSTTEST_SELECT(default_auto);
00227     MBED_HOSTTEST_DESCRIPTION(PortOut PortIn);
00228     MBED_HOSTTEST_START("MBED_A10");
00229 
00230     port_out = MASK_1;
00231     wait(0.1);
00232     int value = port_in.read();
00233     if (value != MASK_2) {
00234         printf("[Test high] expected (0x%x) received (0x%x)\n", MASK_2, value);
00235         notify_completion(false);
00236     }
00237 
00238     port_out = 0;
00239     wait(0.1);
00240     value = port_in.read();
00241     if (value != 0) {
00242         printf("[Test low] expected (0x%x) received (0x%x)\n", 0, value);
00243         notify_completion(false);
00244     }
00245 
00246     notify_completion(true);
00247 }