main.cpp

00001 #include "test_env.h"
00002 
00003 #if defined(TARGET_K64F)
00004 #define P1_1    (1 << 16)
00005 #define P1_2    (1 << 17)
00006 #define PORT_1  PortC
00007 
00008 #define P2_1    (1 << 2)
00009 #define P2_2    (1 << 3)
00010 #define PORT_2  PortC
00011 
00012 #elif defined(TARGET_K66F)
00013 #define P1_1    (1 << 3)
00014 #define P1_2    (1 << 4)
00015 #define PORT_1  PortC
00016 
00017 #define P2_1    (1 << 5)
00018 #define P2_2    (1 << 2)
00019 #define PORT_2  PortC
00020 
00021 #elif defined(TARGET_LPC11U24)
00022 #define P1_1    (1 <<  9) // p0.9
00023 #define P1_2    (1 <<  8) // p0.8
00024 #define PORT_1  Port0
00025 
00026 #define P2_1    (1 << 24) // p1.24
00027 #define P2_2    (1 << 25) // p1.25
00028 #define PORT_2  Port1
00029 
00030 #elif defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
00031 #define P1_1    (1 << 9)  // p0.9  -> p5
00032 #define P1_2    (1 << 8)  // p0.8  -> p6
00033 #define PORT_1  Port0
00034 
00035 #define P2_1    (1 << 1)  // p2.1 -> p25
00036 #define P2_2    (1 << 0)  // p2.0 -> p26
00037 #define PORT_2  Port2
00038 
00039 #elif defined(TARGET_LPC4088)
00040 #define P1_1    (1 << 7)  // p0.7  -> p13
00041 #define P1_2    (1 << 6)  // p0.6  -> p14
00042 #define PORT_1  Port0
00043 
00044 #define P2_1    (1 << 2)  // p1.2 -> p30
00045 #define P2_2    (1 << 3)  // p1.3 -> p29
00046 #define PORT_2  Port1
00047 
00048 #elif defined(TARGET_LPC1114)
00049 #define P1_1    (1 <<  9) // p0.9
00050 #define P1_2    (1 <<  8) // p0.8
00051 #define PORT_1  Port0
00052 
00053 #define P2_1    (1 << 1) // p1.1
00054 #define P2_2    (1 << 0) // p1.0
00055 #define PORT_2  Port1
00056 
00057 #elif defined(TARGET_KL25Z)
00058 #define P1_1    (1 << 4)  // PTA4
00059 #define P1_2    (1 << 5)  // PTA5
00060 #define PORT_1  PortA
00061 
00062 #define P2_1    (1 << 5)  // PTC5
00063 #define P2_2    (1 << 6)  // PTC6
00064 #define PORT_2  PortC
00065 
00066 #elif defined(TARGET_nRF51822)
00067 #define P1_1    (1 << 4)  // p4
00068 #define P1_2    (1 << 5)  // p5
00069 #define PORT_1  Port0
00070 
00071 #define P2_1    (1 << 24)  // p24
00072 #define P2_2    (1 << 25)  // p25
00073 #define PORT_2  Port0
00074 
00075 #elif defined(TARGET_MAXWSNENV)
00076 #define P1_1    (1 << 0)
00077 #define P1_2    (1 << 1)
00078 #define PORT_1  Port0
00079 
00080 #define P2_1    (1 << 0)
00081 #define P2_2    (1 << 1)
00082 #define PORT_2  Port1
00083 
00084 #elif defined(TARGET_MAX32600MBED)
00085 #define P1_1    (1 << 0)  // P1_0
00086 #define P1_2    (1 << 1)  // P1_1
00087 #define PORT_1  Port1
00088 
00089 #define P2_1    (1 << 7)  // P4_7
00090 #define P2_2    (1 << 6)  // P4_6
00091 #define PORT_2  Port4
00092 
00093 #elif defined(TARGET_NUCLEO_F030R8) || \
00094       defined(TARGET_NUCLEO_F070RB) || \
00095       defined(TARGET_NUCLEO_F072RB) || \
00096       defined(TARGET_NUCLEO_F091RC) || \
00097       defined(TARGET_NUCLEO_F103RB) || \
00098       defined(TARGET_NUCLEO_F302R8) || \
00099       defined(TARGET_NUCLEO_F303RE) || \
00100       defined(TARGET_NUCLEO_F334R8) || \
00101       defined(TARGET_NUCLEO_F401RE) || \
00102       defined(TARGET_NUCLEO_F410RB) || \
00103       defined(TARGET_NUCLEO_F411RE) || \
00104       defined(TARGET_NUCLEO_L053R8) || \
00105       defined(TARGET_NUCLEO_L073RZ) || \
00106       defined(TARGET_NUCLEO_L152RE)
00107 #define P1_1    (1 << 6)  // PC_6
00108 #define P1_2    (1 << 5)  // PC_5
00109 #define PORT_1  PortC
00110 
00111 #define P2_1    (1 << 8)  // PB_8
00112 #define P2_2    (1 << 9)  // PB_9
00113 #define PORT_2  PortB
00114 
00115 #elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
00116 #define P1_1    (1 << 0)  // PD0
00117 #define P1_2    (1 << 1)  // PD1
00118 #define PORT_1  PortD
00119 
00120 #define P2_1    (1 << 3)  // PC3
00121 #define P2_2    (1 << 4)  // PC4
00122 #define PORT_2  PortC
00123 
00124 #elif defined(TARGET_EFM32ZG_STK3200)
00125 #define P1_1    (1 << 7)  // PD7
00126 #define P1_2    (1 << 6)  // PD6
00127 #define PORT_1  PortD
00128 
00129 #define P2_1    (1 << 1)  // PC1
00130 #define P2_2    (1 << 2)  // PC2
00131 #define PORT_2  PortC
00132 
00133 #elif defined(TARGET_EFM32HG_STK3400)
00134 #define P1_1    (1 << 10)  // PE10
00135 #define P1_2    (1 << 11)  // PE11
00136 #define PORT_1  PortE
00137 
00138 #define P2_1    (1 << 1)  // PC1
00139 #define P2_2    (1 << 2)  // PC2
00140 #define PORT_2  PortC
00141 
00142 #elif defined(TARGET_EFM32PG_STK3401)
00143 #define P1_1    (1 << 6)  // PC6
00144 #define P1_2    (1 << 7)  // PC7
00145 #define PORT_1  PortC
00146 
00147 #define P2_1    (1 << 3)  // PA3
00148 #define P2_2    (1 << 4)  // PA4
00149 #define PORT_2  PortA
00150 
00151 #elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A)
00152 #define P1_1    (1 << 6)  /*PA06*/
00153 #define P1_2    (1 << 7)  /*PA07*/
00154 #define PORT_1  PortA
00155 
00156 #define P2_1    (1 << 2)  /*PB02*/
00157 #define P2_2    (1 << 3)  /*PB03*/
00158 #define PORT_2  PortB
00159 
00160 #elif defined(TARGET_SAMD21G18A)
00161 #define P1_1    (1 << 2)  /*PA02*/
00162 #define P1_2    (1 << 3)  /*PA03*/
00163 #define PORT_1  PortA
00164 
00165 #define P2_1    (1 << 2)  /*PB02*/
00166 #define P2_2    (1 << 3)  /*PB03*/
00167 #define PORT_2  PortB
00168 
00169 #elif defined(TARGET_SAML21J18A)
00170 #define P1_1    (1 << 4)  /*PA04*/
00171 #define P1_2    (1 << 5)  /*PA05*/
00172 #define PORT_1  PortA
00173 
00174 #define P2_1    (1 << 0)  /*PB00*/
00175 #define P2_2    (1 << 1)  /*PB01*/
00176 #define PORT_2  PortB
00177 
00178 #elif defined(TARGET_SAMG55J19)
00179 #define P1_1    (1 << 17)  /*PA17*/
00180 #define P1_2    (1 << 18)  /*PA18*/
00181 #define PORT_1  PortA
00182 
00183 #define P2_1    (1 << 10)  /*PB10*/
00184 #define P2_2    (1 << 11)  /*PB11*/
00185 #define PORT_2  PortB
00186 
00187 #elif defined(TARGET_VK_RZ_A1H)
00188 #define P1_1    (1 << 2)  /*P3_2*/
00189 #define P1_2    (1 << 7)  /*P3_7*/
00190 #define PORT_1  Port3
00191 
00192 #define P2_1    (1 << 6)  /*P5_6*/
00193 #define P2_2    (1 << 1)  /*P5_1*/
00194 #define PORT_2  Port5
00195 
00196 #endif
00197 
00198 #define MASK_1   (P1_1 | P1_2)
00199 #define MASK_2   (P2_1 | P2_2)
00200 
00201 PortInOut port1(PORT_1, MASK_1);
00202 PortInOut port2(PORT_2, MASK_2);
00203 
00204 int main() {
00205     MBED_HOSTTEST_TIMEOUT(20);
00206     MBED_HOSTTEST_SELECT(default_auto);
00207     MBED_HOSTTEST_DESCRIPTION(PortInOut);
00208     MBED_HOSTTEST_START("MBED_A11");
00209 
00210     bool check = true;
00211 
00212     port1.output();
00213     port2.input();
00214 
00215     port1 = MASK_1; wait(0.1);
00216     if (port2 != MASK_2) check = false;
00217 
00218     port1 = 0; wait(0.1);
00219     if (port2 != 0) check = false;
00220 
00221     port1.input();
00222     port2.output();
00223 
00224     port2 = MASK_2; wait(0.1);
00225     if (port1 != MASK_1) check = false;
00226 
00227     port2 = 0; wait(0.1);
00228     if (port1 != 0) check = false;
00229 
00230     MBED_HOSTTEST_RESULT(check);
00231 }