FT_GPU_Hal.cpp

00001 /* mbed Library for FTDI FT800  Enbedded Video Engine "EVE"
00002  * based on Original Code Sample from FTDI
00003  * ported to mbed by Peter Drescher, DC2PD 2014
00004  * Released under the MIT License: http://mbed.org/license/mit 
00005  * 19.09.14 changed to shorter function names  
00006  * FTDI was using very long names. 
00007  * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ...  */
00008 
00009 #include "FT_Platform.h"
00010 #include "mbed.h"
00011 #include "FT_LCD_Type.h"
00012 //Serial pc(USBTX, USBRX);
00013 
00014 FT800::FT800(PinName mosi,
00015             PinName miso,
00016             PinName sck,
00017             PinName ss,
00018             PinName intr,
00019             PinName pd)
00020     :
00021 
00022      _spi(mosi, miso, sck),
00023      _ss(ss),
00024      _pd(pd),
00025      _f800_isr(InterruptIn(intr))
00026      {
00027          _spi.format(8,0);                  // 8 bit spi mode 0
00028          _spi.frequency(1000000);          // start with 10 Mhz SPI clock
00029          _ss = 1;                           // cs high
00030          _pd = 1;                           // PD high
00031          Bootup();
00032      }
00033 
00034 
00035 ft_bool_t FT800::Bootup(void){
00036 //    terminal.printf("Bootup() entered\r\n");
00037     Open();
00038 
00039     BootupConfig();
00040 
00041     return(1);
00042     }
00043 
00044 
00045 ft_void_t FT800::BootupConfig(void){
00046     ft_uint8_t chipid;
00047     /* Do a power cycle for safer side */
00048     Powercycle( FT_TRUE);
00049     /*
00050     7/8/16: Curt added the sleep delay below...
00051     */
00052 //  Sleep(30);
00053     
00054     /* Set the clk to external clock */
00055     HostCommand( FT_GPU_EXTERNAL_OSC);
00056     Sleep(10);
00057     
00058     /* Access address 0 to wake up the FT800 */
00059     HostCommand( FT_GPU_ACTIVE_M);
00060     Sleep(500);
00061 
00062     /* Switch PLL output to 48MHz */
00063 //  HostCommand( FT_GPU_PLL_48M);
00064     Sleep(10);
00065 
00066     /* Do a core reset for safer side */
00067     HostCommand( FT_GPU_CORE_RESET);
00068     Sleep(500);
00069     //Read Register ID to check if FT800 is ready.
00070     chipid = Rd8(  REG_ID);
00071 //  chipid = Rd8(0x0C0000);
00072 //    pc.printf("ID%08X\n", chipid);
00073     while(chipid != 0x7C)
00074 
00075 
00076     // Speed up
00077     _spi.frequency(30000000);           // 30 Mhz SPI clock DC
00078 //    _spi.frequency(20000000);           // 20 Mhz SPI clock DC
00079 //  _spi.frequency(12000000);           // 12 Mhz SPI clock
00080     /* Configuration of LCD display */
00081     DispHCycle = my_DispHCycle;
00082     Wr16(  REG_HCYCLE, DispHCycle);
00083     DispHOffset = my_DispHOffset;
00084     Wr16(  REG_HOFFSET, DispHOffset);
00085     DispWidth = my_DispWidth;
00086     Wr16(  REG_HSIZE, DispWidth);
00087     DispHSync0 = my_DispHSync0;
00088     Wr16(  REG_HSYNC0, DispHSync0);
00089     DispHSync1 = my_DispHSync1;
00090     Wr16(  REG_HSYNC1, DispHSync1);
00091     DispVCycle = my_DispVCycle;
00092     Wr16(  REG_VCYCLE, DispVCycle);
00093     DispVOffset = my_DispVOffset;
00094     Wr16(  REG_VOFFSET, DispVOffset);
00095     DispHeight = my_DispHeight;
00096     Wr16(  REG_VSIZE, DispHeight);
00097     DispVSync0 = my_DispVSync0;
00098     Wr16(  REG_VSYNC0, DispVSync0);
00099     DispVSync1 = my_DispVSync1;
00100     Wr16(  REG_VSYNC1, DispVSync1);
00101     DispSwizzle = my_DispSwizzle;
00102     Wr8(  REG_SWIZZLE, DispSwizzle);
00103     DispPCLKPol = my_DispPCLKPol;
00104     Wr8(  REG_PCLK_POL, DispPCLKPol);
00105     Wr8(  REG_CSPREAD, 0);
00106     DispPCLK = my_DispPCLK;
00107     Wr8(  REG_PCLK, DispPCLK);//after this display is visible on the LCD
00108 
00109     Wr16(  REG_PWM_HZ, 10000);
00110 //#ifdef Inv_Backlite               // turn on backlite
00111 //    Wr16(  REG_PWM_DUTY, 0);
00112 //#else
00113     Wr16(  REG_PWM_DUTY, 127);
00114 //#endif
00115     Wr8(  REG_GPIO_DIR,0x82);  //| Rd8( REG_GPIO_DIR));
00116     Wr8(  REG_GPIO,0x080);     //| Rd8( REG_GPIO));
00117 
00118     Wr32(  RAM_DL, CLEAR(1,1,1));
00119     Wr32(  RAM_DL+4, DISPLAY());
00120     Wr32(  REG_DLSWAP,1);
00121 
00122     Wr16(  REG_PCLK, DispPCLK);
00123 
00124     /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
00125 //    Wr16(  REG_TOUCH_RZTHRESH,2400);
00126     Wr16(  REG_TOUCH_RZTHRESH,0xFFFF);
00127 
00128 }
00129 
00130 
00131 
00132 /* API to initialize the SPI interface */
00133 ft_bool_t  FT800::Init()
00134 {
00135     // is done in constructor
00136     return 1;
00137 }
00138 
00139 
00140 ft_bool_t  FT800::Open()
00141 {
00142     cmd_fifo_wp = dl_buff_wp = 0;
00143     status = OPENED;
00144     return 1;
00145 }
00146 
00147 ft_void_t  FT800::Close( )
00148 {
00149     status = CLOSED;
00150 }
00151 
00152 ft_void_t FT800::DeInit()
00153 {
00154 
00155 }
00156 
00157 /*The APIs for reading/writing transfer continuously only with small buffer system*/
00158 ft_void_t  FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
00159 {
00160     if (FT_GPU_READ == rw){
00161         _ss = 0;       // cs low
00162         _spi.write(addr >> 16);
00163         _spi.write(addr >> 8);
00164         _spi.write(addr & 0xff);
00165         _spi.write(0); //Dummy Read Byte
00166         status = READING;
00167     }else{
00168         _ss = 0;       // cs low
00169         _spi.write(0x80 | (addr >> 16));
00170         _spi.write(addr >> 8);
00171         _spi.write(addr & 0xff);
00172         status = WRITING;
00173     }
00174 }
00175 
00176 
00177 /*The APIs for writing transfer continuously only*/
00178 ft_void_t  FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
00179 {
00180     StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
00181 }
00182 
00183 ft_uint8_t  FT800::TransferString( const ft_char8_t *string)
00184 {
00185     ft_uint16_t length = strlen(string);
00186     while(length --){
00187        Transfer8( *string);
00188        string ++;
00189     }
00190     //Append one null as ending flag
00191     Transfer8( 0);
00192     return(1);
00193 }
00194 
00195 
00196 ft_uint8_t  FT800::Transfer8( ft_uint8_t value)
00197 {
00198         return _spi.write(value);
00199 }
00200 
00201 
00202 ft_uint16_t  FT800::Transfer16( ft_uint16_t value)
00203 {
00204     ft_uint16_t retVal = 0;
00205 
00206         if (status == WRITING){
00207         Transfer8( value & 0xFF);//LSB first
00208         Transfer8( (value >> 8) & 0xFF);
00209     }else{
00210         retVal = Transfer8( 0);
00211         retVal |= (ft_uint16_t)Transfer8( 0) << 8;
00212     }
00213 
00214     return retVal;
00215 }
00216 
00217 ft_uint32_t  FT800::Transfer32( ft_uint32_t value)
00218 {
00219     ft_uint32_t retVal = 0;
00220     if (status == WRITING){
00221         Transfer16( value & 0xFFFF);//LSB first
00222         Transfer16( (value >> 16) & 0xFFFF);
00223     }else{
00224         retVal = Transfer16( 0);
00225         retVal |= (ft_uint32_t)Transfer16( 0) << 16;
00226     }
00227     return retVal;
00228 }
00229 
00230 ft_void_t   FT800::EndTransfer( )
00231 {
00232     _ss = 1;
00233     status = OPENED;
00234 }
00235 
00236 
00237 ft_uint8_t  FT800::Rd8( ft_uint32_t addr)
00238 {
00239     ft_uint8_t value;
00240     StartTransfer( FT_GPU_READ,addr);
00241     value = Transfer8( 0);
00242     EndTransfer( );
00243     return value;
00244 }
00245 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
00246 {
00247     ft_uint16_t value;
00248     StartTransfer( FT_GPU_READ,addr);
00249     value = Transfer16( 0);
00250     EndTransfer( );
00251     return value;
00252 }
00253 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
00254 {
00255     ft_uint32_t value;
00256     StartTransfer( FT_GPU_READ,addr);
00257     value = Transfer32( 0);
00258     EndTransfer( );
00259     return value;
00260 }
00261 
00262 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
00263 {
00264     StartTransfer( FT_GPU_WRITE,addr);
00265     Transfer8( v);
00266     EndTransfer( );
00267 }
00268 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
00269 {
00270     StartTransfer( FT_GPU_WRITE,addr);
00271     Transfer16( v);
00272     EndTransfer( );
00273 }
00274 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
00275 {
00276     StartTransfer( FT_GPU_WRITE,addr);
00277     Transfer32( v);
00278     EndTransfer( );
00279 }
00280 
00281 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
00282 {
00283   _ss = 0;
00284   _spi.write(cmd);
00285   _spi.write(0);
00286   _spi.write(0);
00287   _ss = 1;
00288 }
00289 
00290 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
00291 {
00292    HostCommand( pllsource);
00293 }
00294 
00295 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
00296 {
00297    HostCommand( freq);
00298 }
00299 
00300 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
00301 {
00302    HostCommand( pwrmode);
00303 }
00304 
00305 ft_void_t FT800::CoreReset( )
00306 {
00307    HostCommand( 0x68);
00308 }
00309 
00310 
00311 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
00312 {
00313      cmd_fifo_wp  = ( cmd_fifo_wp + count) & 4095;
00314     //4 byte alignment
00315      cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
00316     Wr16( REG_CMD_WRITE, cmd_fifo_wp);
00317 }
00318 
00319 
00320 ft_uint16_t FT800::fifo_Freespace( )
00321 {
00322     ft_uint16_t fullness,retval;
00323 
00324     fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
00325     retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
00326     return (retval);
00327 }
00328 
00329 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
00330 {
00331     ft_uint32_t length =0, SizeTransfered = 0;
00332 
00333 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00334     do {
00335         length = count;
00336         if (length > MAX_CMD_FIFO_TRANSFER){
00337             length = MAX_CMD_FIFO_TRANSFER;
00338         }
00339                 CheckCmdBuffer( length);
00340 
00341                 StartCmdTransfer( FT_GPU_WRITE,length);
00342 
00343                 SizeTransfered = 0;
00344         while (length--) {
00345                     Transfer8( *buffer);
00346                     buffer++;
00347                     SizeTransfered ++;
00348         }
00349                 length = SizeTransfered;
00350 
00351         EndTransfer( );
00352         Updatecmdfifo( length);
00353 
00354         WaitCmdfifo_empty( );
00355 
00356         count -= length;
00357     }while (count > 0);
00358 }
00359 
00360 
00361 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
00362 {
00363     ft_uint32_t length =0, SizeTransfered = 0;
00364 
00365 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00366     do {
00367         length = count;
00368         if (length > MAX_CMD_FIFO_TRANSFER){
00369             length = MAX_CMD_FIFO_TRANSFER;
00370         }
00371                 CheckCmdBuffer( length);
00372 
00373                 StartCmdTransfer( FT_GPU_WRITE,length);
00374 
00375 
00376                 SizeTransfered = 0;
00377         while (length--) {
00378                     Transfer8( ft_pgm_read_byte_near(buffer));
00379             buffer++;
00380                     SizeTransfered ++;
00381         }
00382                 length = SizeTransfered;
00383 
00384                 EndTransfer( );
00385         Updatecmdfifo( length);
00386 
00387         WaitCmdfifo_empty( );
00388 
00389         count -= length;
00390     }while (count > 0);
00391 }
00392 
00393 
00394 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
00395 {
00396    ft_uint16_t getfreespace;
00397    do{
00398         getfreespace = fifo_Freespace( );
00399    }while(getfreespace < count);
00400 }
00401 
00402 ft_void_t FT800::WaitCmdfifo_empty( )
00403 {
00404    while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
00405 
00406     cmd_fifo_wp = Rd16( REG_CMD_WRITE);
00407 }
00408 
00409 ft_void_t FT800::WaitLogo_Finish( )
00410 {
00411     ft_int16_t cmdrdptr,cmdwrptr;
00412 
00413     do{
00414          cmdrdptr = Rd16( REG_CMD_READ);
00415          cmdwrptr = Rd16( REG_CMD_WRITE);
00416     }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
00417      cmd_fifo_wp = 0;
00418 }
00419 
00420 
00421 ft_void_t FT800::ResetCmdFifo( )
00422 {
00423     cmd_fifo_wp = 0;
00424 }
00425 
00426 
00427 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
00428 {
00429          CheckCmdBuffer( sizeof(cmd));
00430 
00431          Wr32( RAM_CMD +  cmd_fifo_wp,cmd);
00432 
00433          Updatecmdfifo( sizeof(cmd));
00434 }
00435 
00436 
00437 ft_void_t FT800::ResetDLBuffer( )
00438 {
00439             dl_buff_wp = 0;
00440 }
00441 
00442 /* Toggle PD_N pin of FT800 board for a power cycle*/
00443 ft_void_t FT800::Powercycle(  ft_bool_t up)
00444 {
00445     if (up)
00446     {
00447              //Toggle PD_N from low to high for power up switch
00448             _pd = 0;
00449             Sleep(20);
00450 
00451             _pd = 1;
00452             Sleep(20);
00453     }else
00454     {
00455              //Toggle PD_N from high to low for power down switch
00456             _pd = 1;
00457             Sleep(20);
00458 
00459             _pd = 0;
00460             Sleep(20);
00461     }
00462 }
00463 
00464 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
00465 {
00466     //ft_uint32_t SizeTransfered = 0;
00467 
00468     StartTransfer( FT_GPU_WRITE,addr);
00469 
00470     while (length--) {
00471             Transfer8( ft_pgm_read_byte_near(buffer));
00472         buffer++;
00473     }
00474 
00475     EndTransfer( );
00476 }
00477 
00478 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
00479 {
00480     //ft_uint32_t SizeTransfered = 0;
00481 
00482     StartTransfer( FT_GPU_WRITE,addr);
00483 
00484     while (length--) {
00485             Transfer8( *buffer);
00486         buffer++;
00487     }
00488 
00489     EndTransfer( );
00490 }
00491 
00492 
00493 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
00494 {
00495     //ft_uint32_t SizeTransfered = 0;
00496 
00497     StartTransfer( FT_GPU_READ,addr);
00498 
00499     while (length--) {
00500        *buffer = Transfer8( 0);
00501        buffer++;
00502     }
00503 
00504     EndTransfer( );
00505 }
00506 
00507 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
00508 {
00509     ft_int16_t Length;
00510     ft_char8_t *pdst,charval;
00511     ft_int32_t CurrVal = value,tmpval,i;
00512     ft_char8_t tmparray[16],idx = 0;
00513 
00514     Length = strlen(pSrc);
00515     pdst = pSrc + Length;
00516 
00517     if(0 == value)
00518     {
00519         *pdst++ = '0';
00520         *pdst++ = '\0';
00521         return 0;
00522     }
00523 
00524     if(CurrVal < 0)
00525     {
00526         *pdst++ = '-';
00527         CurrVal = - CurrVal;
00528     }
00529     /* insert the value */
00530     while(CurrVal > 0){
00531         tmpval = CurrVal;
00532         CurrVal /= 10;
00533         tmpval = tmpval - CurrVal*10;
00534         charval = '0' + tmpval;
00535         tmparray[idx++] = charval;
00536     }
00537 
00538     for(i=0;i<idx;i++)
00539     {
00540         *pdst++ = tmparray[idx - i - 1];
00541     }
00542     *pdst++ = '\0';
00543 
00544     return 0;
00545 }
00546 
00547 
00548 ft_void_t FT800::Sleep(ft_uint16_t ms)
00549 {
00550     wait_ms(ms);
00551 }
00552 
00553 ft_void_t FT800::Sound_ON(){
00554      Wr8(  REG_GPIO, 0x02 | Rd8( REG_GPIO));
00555 }
00556 
00557 ft_void_t FT800::Sound_OFF(){
00558      Wr8(  REG_GPIO, 0xFD & Rd8( REG_GPIO));
00559 }
00560 
00561 
00562 
00563