Simon Cooksey / mbed-os

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drivers/SPI.cpp@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:
Simon Cooksey
Date:
Thu Nov 17 16:43:53 2016 +0000
Revision:
0:fb7af294d5d9
Initial commit

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Simon Cooksey 0:fb7af294d5d9 1 /* mbed Microcontroller Library
Simon Cooksey 0:fb7af294d5d9 2 * Copyright (c) 2006-2013 ARM Limited
Simon Cooksey 0:fb7af294d5d9 3 *
Simon Cooksey 0:fb7af294d5d9 4 * Licensed under the Apache License, Version 2.0 (the "License");
Simon Cooksey 0:fb7af294d5d9 5 * you may not use this file except in compliance with the License.
Simon Cooksey 0:fb7af294d5d9 6 * You may obtain a copy of the License at
Simon Cooksey 0:fb7af294d5d9 7 *
Simon Cooksey 0:fb7af294d5d9 8 * http://www.apache.org/licenses/LICENSE-2.0
Simon Cooksey 0:fb7af294d5d9 9 *
Simon Cooksey 0:fb7af294d5d9 10 * Unless required by applicable law or agreed to in writing, software
Simon Cooksey 0:fb7af294d5d9 11 * distributed under the License is distributed on an "AS IS" BASIS,
Simon Cooksey 0:fb7af294d5d9 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Simon Cooksey 0:fb7af294d5d9 13 * See the License for the specific language governing permissions and
Simon Cooksey 0:fb7af294d5d9 14 * limitations under the License.
Simon Cooksey 0:fb7af294d5d9 15 */
Simon Cooksey 0:fb7af294d5d9 16 #include "drivers/SPI.h"
Simon Cooksey 0:fb7af294d5d9 17 #include "platform/critical.h"
Simon Cooksey 0:fb7af294d5d9 18
Simon Cooksey 0:fb7af294d5d9 19 #if DEVICE_SPI
Simon Cooksey 0:fb7af294d5d9 20
Simon Cooksey 0:fb7af294d5d9 21 namespace mbed {
Simon Cooksey 0:fb7af294d5d9 22
Simon Cooksey 0:fb7af294d5d9 23 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 24 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
Simon Cooksey 0:fb7af294d5d9 25 #endif
Simon Cooksey 0:fb7af294d5d9 26
Simon Cooksey 0:fb7af294d5d9 27 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
Simon Cooksey 0:fb7af294d5d9 28 _spi(),
Simon Cooksey 0:fb7af294d5d9 29 #if DEVICE_SPI_ASYNCH
Simon Cooksey 0:fb7af294d5d9 30 _irq(this),
Simon Cooksey 0:fb7af294d5d9 31 _usage(DMA_USAGE_NEVER),
Simon Cooksey 0:fb7af294d5d9 32 #endif
Simon Cooksey 0:fb7af294d5d9 33 _bits(8),
Simon Cooksey 0:fb7af294d5d9 34 _mode(0),
Simon Cooksey 0:fb7af294d5d9 35 _hz(1000000) {
Simon Cooksey 0:fb7af294d5d9 36 // No lock needed in the constructor
Simon Cooksey 0:fb7af294d5d9 37
Simon Cooksey 0:fb7af294d5d9 38 spi_init(&_spi, mosi, miso, sclk, ssel);
Simon Cooksey 0:fb7af294d5d9 39 aquire();
Simon Cooksey 0:fb7af294d5d9 40 }
Simon Cooksey 0:fb7af294d5d9 41
Simon Cooksey 0:fb7af294d5d9 42 void SPI::format(int bits, int mode) {
Simon Cooksey 0:fb7af294d5d9 43 lock();
Simon Cooksey 0:fb7af294d5d9 44 _bits = bits;
Simon Cooksey 0:fb7af294d5d9 45 _mode = mode;
Simon Cooksey 0:fb7af294d5d9 46 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
Simon Cooksey 0:fb7af294d5d9 47 aquire();
Simon Cooksey 0:fb7af294d5d9 48 unlock();
Simon Cooksey 0:fb7af294d5d9 49 }
Simon Cooksey 0:fb7af294d5d9 50
Simon Cooksey 0:fb7af294d5d9 51 void SPI::frequency(int hz) {
Simon Cooksey 0:fb7af294d5d9 52 lock();
Simon Cooksey 0:fb7af294d5d9 53 _hz = hz;
Simon Cooksey 0:fb7af294d5d9 54 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
Simon Cooksey 0:fb7af294d5d9 55 aquire();
Simon Cooksey 0:fb7af294d5d9 56 unlock();
Simon Cooksey 0:fb7af294d5d9 57 }
Simon Cooksey 0:fb7af294d5d9 58
Simon Cooksey 0:fb7af294d5d9 59 SPI* SPI::_owner = NULL;
Simon Cooksey 0:fb7af294d5d9 60 SingletonPtr<PlatformMutex> SPI::_mutex;
Simon Cooksey 0:fb7af294d5d9 61
Simon Cooksey 0:fb7af294d5d9 62 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
Simon Cooksey 0:fb7af294d5d9 63 void SPI::aquire() {
Simon Cooksey 0:fb7af294d5d9 64 lock();
Simon Cooksey 0:fb7af294d5d9 65 if (_owner != this) {
Simon Cooksey 0:fb7af294d5d9 66 spi_format(&_spi, _bits, _mode, 0);
Simon Cooksey 0:fb7af294d5d9 67 spi_frequency(&_spi, _hz);
Simon Cooksey 0:fb7af294d5d9 68 _owner = this;
Simon Cooksey 0:fb7af294d5d9 69 }
Simon Cooksey 0:fb7af294d5d9 70 unlock();
Simon Cooksey 0:fb7af294d5d9 71 }
Simon Cooksey 0:fb7af294d5d9 72
Simon Cooksey 0:fb7af294d5d9 73 int SPI::write(int value) {
Simon Cooksey 0:fb7af294d5d9 74 lock();
Simon Cooksey 0:fb7af294d5d9 75 aquire();
Simon Cooksey 0:fb7af294d5d9 76 int ret = spi_master_write(&_spi, value);
Simon Cooksey 0:fb7af294d5d9 77 unlock();
Simon Cooksey 0:fb7af294d5d9 78 return ret;
Simon Cooksey 0:fb7af294d5d9 79 }
Simon Cooksey 0:fb7af294d5d9 80
Simon Cooksey 0:fb7af294d5d9 81 void SPI::lock() {
Simon Cooksey 0:fb7af294d5d9 82 _mutex->lock();
Simon Cooksey 0:fb7af294d5d9 83 }
Simon Cooksey 0:fb7af294d5d9 84
Simon Cooksey 0:fb7af294d5d9 85 void SPI::unlock() {
Simon Cooksey 0:fb7af294d5d9 86 _mutex->unlock();
Simon Cooksey 0:fb7af294d5d9 87 }
Simon Cooksey 0:fb7af294d5d9 88
Simon Cooksey 0:fb7af294d5d9 89 #if DEVICE_SPI_ASYNCH
Simon Cooksey 0:fb7af294d5d9 90
Simon Cooksey 0:fb7af294d5d9 91 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
Simon Cooksey 0:fb7af294d5d9 92 {
Simon Cooksey 0:fb7af294d5d9 93 if (spi_active(&_spi)) {
Simon Cooksey 0:fb7af294d5d9 94 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
Simon Cooksey 0:fb7af294d5d9 95 }
Simon Cooksey 0:fb7af294d5d9 96 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
Simon Cooksey 0:fb7af294d5d9 97 return 0;
Simon Cooksey 0:fb7af294d5d9 98 }
Simon Cooksey 0:fb7af294d5d9 99
Simon Cooksey 0:fb7af294d5d9 100 void SPI::abort_transfer()
Simon Cooksey 0:fb7af294d5d9 101 {
Simon Cooksey 0:fb7af294d5d9 102 spi_abort_asynch(&_spi);
Simon Cooksey 0:fb7af294d5d9 103 #if TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 104 dequeue_transaction();
Simon Cooksey 0:fb7af294d5d9 105 #endif
Simon Cooksey 0:fb7af294d5d9 106 }
Simon Cooksey 0:fb7af294d5d9 107
Simon Cooksey 0:fb7af294d5d9 108
Simon Cooksey 0:fb7af294d5d9 109 void SPI::clear_transfer_buffer()
Simon Cooksey 0:fb7af294d5d9 110 {
Simon Cooksey 0:fb7af294d5d9 111 #if TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 112 _transaction_buffer.reset();
Simon Cooksey 0:fb7af294d5d9 113 #endif
Simon Cooksey 0:fb7af294d5d9 114 }
Simon Cooksey 0:fb7af294d5d9 115
Simon Cooksey 0:fb7af294d5d9 116 void SPI::abort_all_transfers()
Simon Cooksey 0:fb7af294d5d9 117 {
Simon Cooksey 0:fb7af294d5d9 118 clear_transfer_buffer();
Simon Cooksey 0:fb7af294d5d9 119 abort_transfer();
Simon Cooksey 0:fb7af294d5d9 120 }
Simon Cooksey 0:fb7af294d5d9 121
Simon Cooksey 0:fb7af294d5d9 122 int SPI::set_dma_usage(DMAUsage usage)
Simon Cooksey 0:fb7af294d5d9 123 {
Simon Cooksey 0:fb7af294d5d9 124 if (spi_active(&_spi)) {
Simon Cooksey 0:fb7af294d5d9 125 return -1;
Simon Cooksey 0:fb7af294d5d9 126 }
Simon Cooksey 0:fb7af294d5d9 127 _usage = usage;
Simon Cooksey 0:fb7af294d5d9 128 return 0;
Simon Cooksey 0:fb7af294d5d9 129 }
Simon Cooksey 0:fb7af294d5d9 130
Simon Cooksey 0:fb7af294d5d9 131 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
Simon Cooksey 0:fb7af294d5d9 132 {
Simon Cooksey 0:fb7af294d5d9 133 #if TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 134 transaction_t t;
Simon Cooksey 0:fb7af294d5d9 135
Simon Cooksey 0:fb7af294d5d9 136 t.tx_buffer = const_cast<void *>(tx_buffer);
Simon Cooksey 0:fb7af294d5d9 137 t.tx_length = tx_length;
Simon Cooksey 0:fb7af294d5d9 138 t.rx_buffer = rx_buffer;
Simon Cooksey 0:fb7af294d5d9 139 t.rx_length = rx_length;
Simon Cooksey 0:fb7af294d5d9 140 t.event = event;
Simon Cooksey 0:fb7af294d5d9 141 t.callback = callback;
Simon Cooksey 0:fb7af294d5d9 142 t.width = bit_width;
Simon Cooksey 0:fb7af294d5d9 143 Transaction<SPI> transaction(this, t);
Simon Cooksey 0:fb7af294d5d9 144 if (_transaction_buffer.full()) {
Simon Cooksey 0:fb7af294d5d9 145 return -1; // the buffer is full
Simon Cooksey 0:fb7af294d5d9 146 } else {
Simon Cooksey 0:fb7af294d5d9 147 core_util_critical_section_enter();
Simon Cooksey 0:fb7af294d5d9 148 _transaction_buffer.push(transaction);
Simon Cooksey 0:fb7af294d5d9 149 if (!spi_active(&_spi)) {
Simon Cooksey 0:fb7af294d5d9 150 dequeue_transaction();
Simon Cooksey 0:fb7af294d5d9 151 }
Simon Cooksey 0:fb7af294d5d9 152 core_util_critical_section_exit();
Simon Cooksey 0:fb7af294d5d9 153 return 0;
Simon Cooksey 0:fb7af294d5d9 154 }
Simon Cooksey 0:fb7af294d5d9 155 #else
Simon Cooksey 0:fb7af294d5d9 156 return -1;
Simon Cooksey 0:fb7af294d5d9 157 #endif
Simon Cooksey 0:fb7af294d5d9 158 }
Simon Cooksey 0:fb7af294d5d9 159
Simon Cooksey 0:fb7af294d5d9 160 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
Simon Cooksey 0:fb7af294d5d9 161 {
Simon Cooksey 0:fb7af294d5d9 162 aquire();
Simon Cooksey 0:fb7af294d5d9 163 _callback = callback;
Simon Cooksey 0:fb7af294d5d9 164 _irq.callback(&SPI::irq_handler_asynch);
Simon Cooksey 0:fb7af294d5d9 165 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
Simon Cooksey 0:fb7af294d5d9 166 }
Simon Cooksey 0:fb7af294d5d9 167
Simon Cooksey 0:fb7af294d5d9 168 #if TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 169
Simon Cooksey 0:fb7af294d5d9 170 void SPI::start_transaction(transaction_t *data)
Simon Cooksey 0:fb7af294d5d9 171 {
Simon Cooksey 0:fb7af294d5d9 172 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
Simon Cooksey 0:fb7af294d5d9 173 }
Simon Cooksey 0:fb7af294d5d9 174
Simon Cooksey 0:fb7af294d5d9 175 void SPI::dequeue_transaction()
Simon Cooksey 0:fb7af294d5d9 176 {
Simon Cooksey 0:fb7af294d5d9 177 Transaction<SPI> t;
Simon Cooksey 0:fb7af294d5d9 178 if (_transaction_buffer.pop(t)) {
Simon Cooksey 0:fb7af294d5d9 179 SPI* obj = t.get_object();
Simon Cooksey 0:fb7af294d5d9 180 transaction_t* data = t.get_transaction();
Simon Cooksey 0:fb7af294d5d9 181 obj->start_transaction(data);
Simon Cooksey 0:fb7af294d5d9 182 }
Simon Cooksey 0:fb7af294d5d9 183 }
Simon Cooksey 0:fb7af294d5d9 184
Simon Cooksey 0:fb7af294d5d9 185 #endif
Simon Cooksey 0:fb7af294d5d9 186
Simon Cooksey 0:fb7af294d5d9 187 void SPI::irq_handler_asynch(void)
Simon Cooksey 0:fb7af294d5d9 188 {
Simon Cooksey 0:fb7af294d5d9 189 int event = spi_irq_handler_asynch(&_spi);
Simon Cooksey 0:fb7af294d5d9 190 if (_callback && (event & SPI_EVENT_ALL)) {
Simon Cooksey 0:fb7af294d5d9 191 _callback.call(event & SPI_EVENT_ALL);
Simon Cooksey 0:fb7af294d5d9 192 }
Simon Cooksey 0:fb7af294d5d9 193 #if TRANSACTION_QUEUE_SIZE_SPI
Simon Cooksey 0:fb7af294d5d9 194 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
Simon Cooksey 0:fb7af294d5d9 195 // SPI peripheral is free (event happend), dequeue transaction
Simon Cooksey 0:fb7af294d5d9 196 dequeue_transaction();
Simon Cooksey 0:fb7af294d5d9 197 }
Simon Cooksey 0:fb7af294d5d9 198 #endif
Simon Cooksey 0:fb7af294d5d9 199 }
Simon Cooksey 0:fb7af294d5d9 200
Simon Cooksey 0:fb7af294d5d9 201 #endif
Simon Cooksey 0:fb7af294d5d9 202
Simon Cooksey 0:fb7af294d5d9 203 } // namespace mbed
Simon Cooksey 0:fb7af294d5d9 204
Simon Cooksey 0:fb7af294d5d9 205 #endif