config AX12
Fork of configure_ax12_test_bras_module by
mbed/LPC1768/core_cmInstr.h@0:c03cffe402df, 2016-02-03 (annotated)
- Committer:
- slowness
- Date:
- Wed Feb 03 14:01:53 2016 +0000
- Revision:
- 0:c03cffe402df
Pour configurer les AX12 avec la carte NXP1768 sur les Pin 9 et 10
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
slowness | 0:c03cffe402df | 1 | /**************************************************************************//** |
slowness | 0:c03cffe402df | 2 | * @file core_cmInstr.h |
slowness | 0:c03cffe402df | 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File |
slowness | 0:c03cffe402df | 4 | * @version V3.00 |
slowness | 0:c03cffe402df | 5 | * @date 09. December 2011 |
slowness | 0:c03cffe402df | 6 | * |
slowness | 0:c03cffe402df | 7 | * @note |
slowness | 0:c03cffe402df | 8 | * Copyright (C) 2009-2011 ARM Limited. All rights reserved. |
slowness | 0:c03cffe402df | 9 | * |
slowness | 0:c03cffe402df | 10 | * @par |
slowness | 0:c03cffe402df | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
slowness | 0:c03cffe402df | 12 | * processor based microcontrollers. This file can be freely distributed |
slowness | 0:c03cffe402df | 13 | * within development tools that are supporting such ARM based processors. |
slowness | 0:c03cffe402df | 14 | * |
slowness | 0:c03cffe402df | 15 | * @par |
slowness | 0:c03cffe402df | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
slowness | 0:c03cffe402df | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
slowness | 0:c03cffe402df | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
slowness | 0:c03cffe402df | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
slowness | 0:c03cffe402df | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
slowness | 0:c03cffe402df | 21 | * |
slowness | 0:c03cffe402df | 22 | ******************************************************************************/ |
slowness | 0:c03cffe402df | 23 | |
slowness | 0:c03cffe402df | 24 | #ifndef __CORE_CMINSTR_H |
slowness | 0:c03cffe402df | 25 | #define __CORE_CMINSTR_H |
slowness | 0:c03cffe402df | 26 | |
slowness | 0:c03cffe402df | 27 | |
slowness | 0:c03cffe402df | 28 | /* ########################## Core Instruction Access ######################### */ |
slowness | 0:c03cffe402df | 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
slowness | 0:c03cffe402df | 30 | Access to dedicated instructions |
slowness | 0:c03cffe402df | 31 | @{ |
slowness | 0:c03cffe402df | 32 | */ |
slowness | 0:c03cffe402df | 33 | |
slowness | 0:c03cffe402df | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
slowness | 0:c03cffe402df | 35 | /* ARM armcc specific functions */ |
slowness | 0:c03cffe402df | 36 | |
slowness | 0:c03cffe402df | 37 | #if (__ARMCC_VERSION < 400677) |
slowness | 0:c03cffe402df | 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
slowness | 0:c03cffe402df | 39 | #endif |
slowness | 0:c03cffe402df | 40 | |
slowness | 0:c03cffe402df | 41 | |
slowness | 0:c03cffe402df | 42 | /** \brief No Operation |
slowness | 0:c03cffe402df | 43 | |
slowness | 0:c03cffe402df | 44 | No Operation does nothing. This instruction can be used for code alignment purposes. |
slowness | 0:c03cffe402df | 45 | */ |
slowness | 0:c03cffe402df | 46 | #define __NOP __nop |
slowness | 0:c03cffe402df | 47 | |
slowness | 0:c03cffe402df | 48 | |
slowness | 0:c03cffe402df | 49 | /** \brief Wait For Interrupt |
slowness | 0:c03cffe402df | 50 | |
slowness | 0:c03cffe402df | 51 | Wait For Interrupt is a hint instruction that suspends execution |
slowness | 0:c03cffe402df | 52 | until one of a number of events occurs. |
slowness | 0:c03cffe402df | 53 | */ |
slowness | 0:c03cffe402df | 54 | #define __WFI __wfi |
slowness | 0:c03cffe402df | 55 | |
slowness | 0:c03cffe402df | 56 | |
slowness | 0:c03cffe402df | 57 | /** \brief Wait For Event |
slowness | 0:c03cffe402df | 58 | |
slowness | 0:c03cffe402df | 59 | Wait For Event is a hint instruction that permits the processor to enter |
slowness | 0:c03cffe402df | 60 | a low-power state until one of a number of events occurs. |
slowness | 0:c03cffe402df | 61 | */ |
slowness | 0:c03cffe402df | 62 | #define __WFE __wfe |
slowness | 0:c03cffe402df | 63 | |
slowness | 0:c03cffe402df | 64 | |
slowness | 0:c03cffe402df | 65 | /** \brief Send Event |
slowness | 0:c03cffe402df | 66 | |
slowness | 0:c03cffe402df | 67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
slowness | 0:c03cffe402df | 68 | */ |
slowness | 0:c03cffe402df | 69 | #define __SEV __sev |
slowness | 0:c03cffe402df | 70 | |
slowness | 0:c03cffe402df | 71 | |
slowness | 0:c03cffe402df | 72 | /** \brief Instruction Synchronization Barrier |
slowness | 0:c03cffe402df | 73 | |
slowness | 0:c03cffe402df | 74 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
slowness | 0:c03cffe402df | 75 | so that all instructions following the ISB are fetched from cache or |
slowness | 0:c03cffe402df | 76 | memory, after the instruction has been completed. |
slowness | 0:c03cffe402df | 77 | */ |
slowness | 0:c03cffe402df | 78 | #define __ISB() __isb(0xF) |
slowness | 0:c03cffe402df | 79 | |
slowness | 0:c03cffe402df | 80 | |
slowness | 0:c03cffe402df | 81 | /** \brief Data Synchronization Barrier |
slowness | 0:c03cffe402df | 82 | |
slowness | 0:c03cffe402df | 83 | This function acts as a special kind of Data Memory Barrier. |
slowness | 0:c03cffe402df | 84 | It completes when all explicit memory accesses before this instruction complete. |
slowness | 0:c03cffe402df | 85 | */ |
slowness | 0:c03cffe402df | 86 | #define __DSB() __dsb(0xF) |
slowness | 0:c03cffe402df | 87 | |
slowness | 0:c03cffe402df | 88 | |
slowness | 0:c03cffe402df | 89 | /** \brief Data Memory Barrier |
slowness | 0:c03cffe402df | 90 | |
slowness | 0:c03cffe402df | 91 | This function ensures the apparent order of the explicit memory operations before |
slowness | 0:c03cffe402df | 92 | and after the instruction, without ensuring their completion. |
slowness | 0:c03cffe402df | 93 | */ |
slowness | 0:c03cffe402df | 94 | #define __DMB() __dmb(0xF) |
slowness | 0:c03cffe402df | 95 | |
slowness | 0:c03cffe402df | 96 | |
slowness | 0:c03cffe402df | 97 | /** \brief Reverse byte order (32 bit) |
slowness | 0:c03cffe402df | 98 | |
slowness | 0:c03cffe402df | 99 | This function reverses the byte order in integer value. |
slowness | 0:c03cffe402df | 100 | |
slowness | 0:c03cffe402df | 101 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 102 | \return Reversed value |
slowness | 0:c03cffe402df | 103 | */ |
slowness | 0:c03cffe402df | 104 | #define __REV __rev |
slowness | 0:c03cffe402df | 105 | |
slowness | 0:c03cffe402df | 106 | |
slowness | 0:c03cffe402df | 107 | /** \brief Reverse byte order (16 bit) |
slowness | 0:c03cffe402df | 108 | |
slowness | 0:c03cffe402df | 109 | This function reverses the byte order in two unsigned short values. |
slowness | 0:c03cffe402df | 110 | |
slowness | 0:c03cffe402df | 111 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 112 | \return Reversed value |
slowness | 0:c03cffe402df | 113 | */ |
slowness | 0:c03cffe402df | 114 | static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value) |
slowness | 0:c03cffe402df | 115 | { |
slowness | 0:c03cffe402df | 116 | rev16 r0, r0 |
slowness | 0:c03cffe402df | 117 | bx lr |
slowness | 0:c03cffe402df | 118 | } |
slowness | 0:c03cffe402df | 119 | |
slowness | 0:c03cffe402df | 120 | |
slowness | 0:c03cffe402df | 121 | /** \brief Reverse byte order in signed short value |
slowness | 0:c03cffe402df | 122 | |
slowness | 0:c03cffe402df | 123 | This function reverses the byte order in a signed short value with sign extension to integer. |
slowness | 0:c03cffe402df | 124 | |
slowness | 0:c03cffe402df | 125 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 126 | \return Reversed value |
slowness | 0:c03cffe402df | 127 | */ |
slowness | 0:c03cffe402df | 128 | static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value) |
slowness | 0:c03cffe402df | 129 | { |
slowness | 0:c03cffe402df | 130 | revsh r0, r0 |
slowness | 0:c03cffe402df | 131 | bx lr |
slowness | 0:c03cffe402df | 132 | } |
slowness | 0:c03cffe402df | 133 | |
slowness | 0:c03cffe402df | 134 | |
slowness | 0:c03cffe402df | 135 | #if (__CORTEX_M >= 0x03) |
slowness | 0:c03cffe402df | 136 | |
slowness | 0:c03cffe402df | 137 | /** \brief Reverse bit order of value |
slowness | 0:c03cffe402df | 138 | |
slowness | 0:c03cffe402df | 139 | This function reverses the bit order of the given value. |
slowness | 0:c03cffe402df | 140 | |
slowness | 0:c03cffe402df | 141 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 142 | \return Reversed value |
slowness | 0:c03cffe402df | 143 | */ |
slowness | 0:c03cffe402df | 144 | #define __RBIT __rbit |
slowness | 0:c03cffe402df | 145 | |
slowness | 0:c03cffe402df | 146 | |
slowness | 0:c03cffe402df | 147 | /** \brief LDR Exclusive (8 bit) |
slowness | 0:c03cffe402df | 148 | |
slowness | 0:c03cffe402df | 149 | This function performs a exclusive LDR command for 8 bit value. |
slowness | 0:c03cffe402df | 150 | |
slowness | 0:c03cffe402df | 151 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 152 | \return value of type uint8_t at (*ptr) |
slowness | 0:c03cffe402df | 153 | */ |
slowness | 0:c03cffe402df | 154 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
slowness | 0:c03cffe402df | 155 | |
slowness | 0:c03cffe402df | 156 | |
slowness | 0:c03cffe402df | 157 | /** \brief LDR Exclusive (16 bit) |
slowness | 0:c03cffe402df | 158 | |
slowness | 0:c03cffe402df | 159 | This function performs a exclusive LDR command for 16 bit values. |
slowness | 0:c03cffe402df | 160 | |
slowness | 0:c03cffe402df | 161 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 162 | \return value of type uint16_t at (*ptr) |
slowness | 0:c03cffe402df | 163 | */ |
slowness | 0:c03cffe402df | 164 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
slowness | 0:c03cffe402df | 165 | |
slowness | 0:c03cffe402df | 166 | |
slowness | 0:c03cffe402df | 167 | /** \brief LDR Exclusive (32 bit) |
slowness | 0:c03cffe402df | 168 | |
slowness | 0:c03cffe402df | 169 | This function performs a exclusive LDR command for 32 bit values. |
slowness | 0:c03cffe402df | 170 | |
slowness | 0:c03cffe402df | 171 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 172 | \return value of type uint32_t at (*ptr) |
slowness | 0:c03cffe402df | 173 | */ |
slowness | 0:c03cffe402df | 174 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
slowness | 0:c03cffe402df | 175 | |
slowness | 0:c03cffe402df | 176 | |
slowness | 0:c03cffe402df | 177 | /** \brief STR Exclusive (8 bit) |
slowness | 0:c03cffe402df | 178 | |
slowness | 0:c03cffe402df | 179 | This function performs a exclusive STR command for 8 bit values. |
slowness | 0:c03cffe402df | 180 | |
slowness | 0:c03cffe402df | 181 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 182 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 183 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 184 | \return 1 Function failed |
slowness | 0:c03cffe402df | 185 | */ |
slowness | 0:c03cffe402df | 186 | #define __STREXB(value, ptr) __strex(value, ptr) |
slowness | 0:c03cffe402df | 187 | |
slowness | 0:c03cffe402df | 188 | |
slowness | 0:c03cffe402df | 189 | /** \brief STR Exclusive (16 bit) |
slowness | 0:c03cffe402df | 190 | |
slowness | 0:c03cffe402df | 191 | This function performs a exclusive STR command for 16 bit values. |
slowness | 0:c03cffe402df | 192 | |
slowness | 0:c03cffe402df | 193 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 194 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 195 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 196 | \return 1 Function failed |
slowness | 0:c03cffe402df | 197 | */ |
slowness | 0:c03cffe402df | 198 | #define __STREXH(value, ptr) __strex(value, ptr) |
slowness | 0:c03cffe402df | 199 | |
slowness | 0:c03cffe402df | 200 | |
slowness | 0:c03cffe402df | 201 | /** \brief STR Exclusive (32 bit) |
slowness | 0:c03cffe402df | 202 | |
slowness | 0:c03cffe402df | 203 | This function performs a exclusive STR command for 32 bit values. |
slowness | 0:c03cffe402df | 204 | |
slowness | 0:c03cffe402df | 205 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 206 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 207 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 208 | \return 1 Function failed |
slowness | 0:c03cffe402df | 209 | */ |
slowness | 0:c03cffe402df | 210 | #define __STREXW(value, ptr) __strex(value, ptr) |
slowness | 0:c03cffe402df | 211 | |
slowness | 0:c03cffe402df | 212 | |
slowness | 0:c03cffe402df | 213 | /** \brief Remove the exclusive lock |
slowness | 0:c03cffe402df | 214 | |
slowness | 0:c03cffe402df | 215 | This function removes the exclusive lock which is created by LDREX. |
slowness | 0:c03cffe402df | 216 | |
slowness | 0:c03cffe402df | 217 | */ |
slowness | 0:c03cffe402df | 218 | #define __CLREX __clrex |
slowness | 0:c03cffe402df | 219 | |
slowness | 0:c03cffe402df | 220 | |
slowness | 0:c03cffe402df | 221 | /** \brief Signed Saturate |
slowness | 0:c03cffe402df | 222 | |
slowness | 0:c03cffe402df | 223 | This function saturates a signed value. |
slowness | 0:c03cffe402df | 224 | |
slowness | 0:c03cffe402df | 225 | \param [in] value Value to be saturated |
slowness | 0:c03cffe402df | 226 | \param [in] sat Bit position to saturate to (1..32) |
slowness | 0:c03cffe402df | 227 | \return Saturated value |
slowness | 0:c03cffe402df | 228 | */ |
slowness | 0:c03cffe402df | 229 | #define __SSAT __ssat |
slowness | 0:c03cffe402df | 230 | |
slowness | 0:c03cffe402df | 231 | |
slowness | 0:c03cffe402df | 232 | /** \brief Unsigned Saturate |
slowness | 0:c03cffe402df | 233 | |
slowness | 0:c03cffe402df | 234 | This function saturates an unsigned value. |
slowness | 0:c03cffe402df | 235 | |
slowness | 0:c03cffe402df | 236 | \param [in] value Value to be saturated |
slowness | 0:c03cffe402df | 237 | \param [in] sat Bit position to saturate to (0..31) |
slowness | 0:c03cffe402df | 238 | \return Saturated value |
slowness | 0:c03cffe402df | 239 | */ |
slowness | 0:c03cffe402df | 240 | #define __USAT __usat |
slowness | 0:c03cffe402df | 241 | |
slowness | 0:c03cffe402df | 242 | |
slowness | 0:c03cffe402df | 243 | /** \brief Count leading zeros |
slowness | 0:c03cffe402df | 244 | |
slowness | 0:c03cffe402df | 245 | This function counts the number of leading zeros of a data value. |
slowness | 0:c03cffe402df | 246 | |
slowness | 0:c03cffe402df | 247 | \param [in] value Value to count the leading zeros |
slowness | 0:c03cffe402df | 248 | \return number of leading zeros in value |
slowness | 0:c03cffe402df | 249 | */ |
slowness | 0:c03cffe402df | 250 | #define __CLZ __clz |
slowness | 0:c03cffe402df | 251 | |
slowness | 0:c03cffe402df | 252 | #endif /* (__CORTEX_M >= 0x03) */ |
slowness | 0:c03cffe402df | 253 | |
slowness | 0:c03cffe402df | 254 | |
slowness | 0:c03cffe402df | 255 | |
slowness | 0:c03cffe402df | 256 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
slowness | 0:c03cffe402df | 257 | /* IAR iccarm specific functions */ |
slowness | 0:c03cffe402df | 258 | |
slowness | 0:c03cffe402df | 259 | #include <cmsis_iar.h> |
slowness | 0:c03cffe402df | 260 | |
slowness | 0:c03cffe402df | 261 | |
slowness | 0:c03cffe402df | 262 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
slowness | 0:c03cffe402df | 263 | /* GNU gcc specific functions */ |
slowness | 0:c03cffe402df | 264 | |
slowness | 0:c03cffe402df | 265 | /** \brief No Operation |
slowness | 0:c03cffe402df | 266 | |
slowness | 0:c03cffe402df | 267 | No Operation does nothing. This instruction can be used for code alignment purposes. |
slowness | 0:c03cffe402df | 268 | */ |
slowness | 0:c03cffe402df | 269 | __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) |
slowness | 0:c03cffe402df | 270 | { |
slowness | 0:c03cffe402df | 271 | __ASM volatile ("nop"); |
slowness | 0:c03cffe402df | 272 | } |
slowness | 0:c03cffe402df | 273 | |
slowness | 0:c03cffe402df | 274 | |
slowness | 0:c03cffe402df | 275 | /** \brief Wait For Interrupt |
slowness | 0:c03cffe402df | 276 | |
slowness | 0:c03cffe402df | 277 | Wait For Interrupt is a hint instruction that suspends execution |
slowness | 0:c03cffe402df | 278 | until one of a number of events occurs. |
slowness | 0:c03cffe402df | 279 | */ |
slowness | 0:c03cffe402df | 280 | __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) |
slowness | 0:c03cffe402df | 281 | { |
slowness | 0:c03cffe402df | 282 | __ASM volatile ("wfi"); |
slowness | 0:c03cffe402df | 283 | } |
slowness | 0:c03cffe402df | 284 | |
slowness | 0:c03cffe402df | 285 | |
slowness | 0:c03cffe402df | 286 | /** \brief Wait For Event |
slowness | 0:c03cffe402df | 287 | |
slowness | 0:c03cffe402df | 288 | Wait For Event is a hint instruction that permits the processor to enter |
slowness | 0:c03cffe402df | 289 | a low-power state until one of a number of events occurs. |
slowness | 0:c03cffe402df | 290 | */ |
slowness | 0:c03cffe402df | 291 | __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) |
slowness | 0:c03cffe402df | 292 | { |
slowness | 0:c03cffe402df | 293 | __ASM volatile ("wfe"); |
slowness | 0:c03cffe402df | 294 | } |
slowness | 0:c03cffe402df | 295 | |
slowness | 0:c03cffe402df | 296 | |
slowness | 0:c03cffe402df | 297 | /** \brief Send Event |
slowness | 0:c03cffe402df | 298 | |
slowness | 0:c03cffe402df | 299 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
slowness | 0:c03cffe402df | 300 | */ |
slowness | 0:c03cffe402df | 301 | __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) |
slowness | 0:c03cffe402df | 302 | { |
slowness | 0:c03cffe402df | 303 | __ASM volatile ("sev"); |
slowness | 0:c03cffe402df | 304 | } |
slowness | 0:c03cffe402df | 305 | |
slowness | 0:c03cffe402df | 306 | |
slowness | 0:c03cffe402df | 307 | /** \brief Instruction Synchronization Barrier |
slowness | 0:c03cffe402df | 308 | |
slowness | 0:c03cffe402df | 309 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
slowness | 0:c03cffe402df | 310 | so that all instructions following the ISB are fetched from cache or |
slowness | 0:c03cffe402df | 311 | memory, after the instruction has been completed. |
slowness | 0:c03cffe402df | 312 | */ |
slowness | 0:c03cffe402df | 313 | __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) |
slowness | 0:c03cffe402df | 314 | { |
slowness | 0:c03cffe402df | 315 | __ASM volatile ("isb"); |
slowness | 0:c03cffe402df | 316 | } |
slowness | 0:c03cffe402df | 317 | |
slowness | 0:c03cffe402df | 318 | |
slowness | 0:c03cffe402df | 319 | /** \brief Data Synchronization Barrier |
slowness | 0:c03cffe402df | 320 | |
slowness | 0:c03cffe402df | 321 | This function acts as a special kind of Data Memory Barrier. |
slowness | 0:c03cffe402df | 322 | It completes when all explicit memory accesses before this instruction complete. |
slowness | 0:c03cffe402df | 323 | */ |
slowness | 0:c03cffe402df | 324 | __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) |
slowness | 0:c03cffe402df | 325 | { |
slowness | 0:c03cffe402df | 326 | __ASM volatile ("dsb"); |
slowness | 0:c03cffe402df | 327 | } |
slowness | 0:c03cffe402df | 328 | |
slowness | 0:c03cffe402df | 329 | |
slowness | 0:c03cffe402df | 330 | /** \brief Data Memory Barrier |
slowness | 0:c03cffe402df | 331 | |
slowness | 0:c03cffe402df | 332 | This function ensures the apparent order of the explicit memory operations before |
slowness | 0:c03cffe402df | 333 | and after the instruction, without ensuring their completion. |
slowness | 0:c03cffe402df | 334 | */ |
slowness | 0:c03cffe402df | 335 | __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) |
slowness | 0:c03cffe402df | 336 | { |
slowness | 0:c03cffe402df | 337 | __ASM volatile ("dmb"); |
slowness | 0:c03cffe402df | 338 | } |
slowness | 0:c03cffe402df | 339 | |
slowness | 0:c03cffe402df | 340 | |
slowness | 0:c03cffe402df | 341 | /** \brief Reverse byte order (32 bit) |
slowness | 0:c03cffe402df | 342 | |
slowness | 0:c03cffe402df | 343 | This function reverses the byte order in integer value. |
slowness | 0:c03cffe402df | 344 | |
slowness | 0:c03cffe402df | 345 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 346 | \return Reversed value |
slowness | 0:c03cffe402df | 347 | */ |
slowness | 0:c03cffe402df | 348 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) |
slowness | 0:c03cffe402df | 349 | { |
slowness | 0:c03cffe402df | 350 | uint32_t result; |
slowness | 0:c03cffe402df | 351 | |
slowness | 0:c03cffe402df | 352 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
slowness | 0:c03cffe402df | 353 | return(result); |
slowness | 0:c03cffe402df | 354 | } |
slowness | 0:c03cffe402df | 355 | |
slowness | 0:c03cffe402df | 356 | |
slowness | 0:c03cffe402df | 357 | /** \brief Reverse byte order (16 bit) |
slowness | 0:c03cffe402df | 358 | |
slowness | 0:c03cffe402df | 359 | This function reverses the byte order in two unsigned short values. |
slowness | 0:c03cffe402df | 360 | |
slowness | 0:c03cffe402df | 361 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 362 | \return Reversed value |
slowness | 0:c03cffe402df | 363 | */ |
slowness | 0:c03cffe402df | 364 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) |
slowness | 0:c03cffe402df | 365 | { |
slowness | 0:c03cffe402df | 366 | uint32_t result; |
slowness | 0:c03cffe402df | 367 | |
slowness | 0:c03cffe402df | 368 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
slowness | 0:c03cffe402df | 369 | return(result); |
slowness | 0:c03cffe402df | 370 | } |
slowness | 0:c03cffe402df | 371 | |
slowness | 0:c03cffe402df | 372 | |
slowness | 0:c03cffe402df | 373 | /** \brief Reverse byte order in signed short value |
slowness | 0:c03cffe402df | 374 | |
slowness | 0:c03cffe402df | 375 | This function reverses the byte order in a signed short value with sign extension to integer. |
slowness | 0:c03cffe402df | 376 | |
slowness | 0:c03cffe402df | 377 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 378 | \return Reversed value |
slowness | 0:c03cffe402df | 379 | */ |
slowness | 0:c03cffe402df | 380 | __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) |
slowness | 0:c03cffe402df | 381 | { |
slowness | 0:c03cffe402df | 382 | uint32_t result; |
slowness | 0:c03cffe402df | 383 | |
slowness | 0:c03cffe402df | 384 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
slowness | 0:c03cffe402df | 385 | return(result); |
slowness | 0:c03cffe402df | 386 | } |
slowness | 0:c03cffe402df | 387 | |
slowness | 0:c03cffe402df | 388 | |
slowness | 0:c03cffe402df | 389 | #if (__CORTEX_M >= 0x03) |
slowness | 0:c03cffe402df | 390 | |
slowness | 0:c03cffe402df | 391 | /** \brief Reverse bit order of value |
slowness | 0:c03cffe402df | 392 | |
slowness | 0:c03cffe402df | 393 | This function reverses the bit order of the given value. |
slowness | 0:c03cffe402df | 394 | |
slowness | 0:c03cffe402df | 395 | \param [in] value Value to reverse |
slowness | 0:c03cffe402df | 396 | \return Reversed value |
slowness | 0:c03cffe402df | 397 | */ |
slowness | 0:c03cffe402df | 398 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) |
slowness | 0:c03cffe402df | 399 | { |
slowness | 0:c03cffe402df | 400 | uint32_t result; |
slowness | 0:c03cffe402df | 401 | |
slowness | 0:c03cffe402df | 402 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
slowness | 0:c03cffe402df | 403 | return(result); |
slowness | 0:c03cffe402df | 404 | } |
slowness | 0:c03cffe402df | 405 | |
slowness | 0:c03cffe402df | 406 | |
slowness | 0:c03cffe402df | 407 | /** \brief LDR Exclusive (8 bit) |
slowness | 0:c03cffe402df | 408 | |
slowness | 0:c03cffe402df | 409 | This function performs a exclusive LDR command for 8 bit value. |
slowness | 0:c03cffe402df | 410 | |
slowness | 0:c03cffe402df | 411 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 412 | \return value of type uint8_t at (*ptr) |
slowness | 0:c03cffe402df | 413 | */ |
slowness | 0:c03cffe402df | 414 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) |
slowness | 0:c03cffe402df | 415 | { |
slowness | 0:c03cffe402df | 416 | uint8_t result; |
slowness | 0:c03cffe402df | 417 | |
slowness | 0:c03cffe402df | 418 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
slowness | 0:c03cffe402df | 419 | return(result); |
slowness | 0:c03cffe402df | 420 | } |
slowness | 0:c03cffe402df | 421 | |
slowness | 0:c03cffe402df | 422 | |
slowness | 0:c03cffe402df | 423 | /** \brief LDR Exclusive (16 bit) |
slowness | 0:c03cffe402df | 424 | |
slowness | 0:c03cffe402df | 425 | This function performs a exclusive LDR command for 16 bit values. |
slowness | 0:c03cffe402df | 426 | |
slowness | 0:c03cffe402df | 427 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 428 | \return value of type uint16_t at (*ptr) |
slowness | 0:c03cffe402df | 429 | */ |
slowness | 0:c03cffe402df | 430 | __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) |
slowness | 0:c03cffe402df | 431 | { |
slowness | 0:c03cffe402df | 432 | uint16_t result; |
slowness | 0:c03cffe402df | 433 | |
slowness | 0:c03cffe402df | 434 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
slowness | 0:c03cffe402df | 435 | return(result); |
slowness | 0:c03cffe402df | 436 | } |
slowness | 0:c03cffe402df | 437 | |
slowness | 0:c03cffe402df | 438 | |
slowness | 0:c03cffe402df | 439 | /** \brief LDR Exclusive (32 bit) |
slowness | 0:c03cffe402df | 440 | |
slowness | 0:c03cffe402df | 441 | This function performs a exclusive LDR command for 32 bit values. |
slowness | 0:c03cffe402df | 442 | |
slowness | 0:c03cffe402df | 443 | \param [in] ptr Pointer to data |
slowness | 0:c03cffe402df | 444 | \return value of type uint32_t at (*ptr) |
slowness | 0:c03cffe402df | 445 | */ |
slowness | 0:c03cffe402df | 446 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) |
slowness | 0:c03cffe402df | 447 | { |
slowness | 0:c03cffe402df | 448 | uint32_t result; |
slowness | 0:c03cffe402df | 449 | |
slowness | 0:c03cffe402df | 450 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
slowness | 0:c03cffe402df | 451 | return(result); |
slowness | 0:c03cffe402df | 452 | } |
slowness | 0:c03cffe402df | 453 | |
slowness | 0:c03cffe402df | 454 | |
slowness | 0:c03cffe402df | 455 | /** \brief STR Exclusive (8 bit) |
slowness | 0:c03cffe402df | 456 | |
slowness | 0:c03cffe402df | 457 | This function performs a exclusive STR command for 8 bit values. |
slowness | 0:c03cffe402df | 458 | |
slowness | 0:c03cffe402df | 459 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 460 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 461 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 462 | \return 1 Function failed |
slowness | 0:c03cffe402df | 463 | */ |
slowness | 0:c03cffe402df | 464 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
slowness | 0:c03cffe402df | 465 | { |
slowness | 0:c03cffe402df | 466 | uint32_t result; |
slowness | 0:c03cffe402df | 467 | |
slowness | 0:c03cffe402df | 468 | __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
slowness | 0:c03cffe402df | 469 | return(result); |
slowness | 0:c03cffe402df | 470 | } |
slowness | 0:c03cffe402df | 471 | |
slowness | 0:c03cffe402df | 472 | |
slowness | 0:c03cffe402df | 473 | /** \brief STR Exclusive (16 bit) |
slowness | 0:c03cffe402df | 474 | |
slowness | 0:c03cffe402df | 475 | This function performs a exclusive STR command for 16 bit values. |
slowness | 0:c03cffe402df | 476 | |
slowness | 0:c03cffe402df | 477 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 478 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 479 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 480 | \return 1 Function failed |
slowness | 0:c03cffe402df | 481 | */ |
slowness | 0:c03cffe402df | 482 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
slowness | 0:c03cffe402df | 483 | { |
slowness | 0:c03cffe402df | 484 | uint32_t result; |
slowness | 0:c03cffe402df | 485 | |
slowness | 0:c03cffe402df | 486 | __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
slowness | 0:c03cffe402df | 487 | return(result); |
slowness | 0:c03cffe402df | 488 | } |
slowness | 0:c03cffe402df | 489 | |
slowness | 0:c03cffe402df | 490 | |
slowness | 0:c03cffe402df | 491 | /** \brief STR Exclusive (32 bit) |
slowness | 0:c03cffe402df | 492 | |
slowness | 0:c03cffe402df | 493 | This function performs a exclusive STR command for 32 bit values. |
slowness | 0:c03cffe402df | 494 | |
slowness | 0:c03cffe402df | 495 | \param [in] value Value to store |
slowness | 0:c03cffe402df | 496 | \param [in] ptr Pointer to location |
slowness | 0:c03cffe402df | 497 | \return 0 Function succeeded |
slowness | 0:c03cffe402df | 498 | \return 1 Function failed |
slowness | 0:c03cffe402df | 499 | */ |
slowness | 0:c03cffe402df | 500 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
slowness | 0:c03cffe402df | 501 | { |
slowness | 0:c03cffe402df | 502 | uint32_t result; |
slowness | 0:c03cffe402df | 503 | |
slowness | 0:c03cffe402df | 504 | __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
slowness | 0:c03cffe402df | 505 | return(result); |
slowness | 0:c03cffe402df | 506 | } |
slowness | 0:c03cffe402df | 507 | |
slowness | 0:c03cffe402df | 508 | |
slowness | 0:c03cffe402df | 509 | /** \brief Remove the exclusive lock |
slowness | 0:c03cffe402df | 510 | |
slowness | 0:c03cffe402df | 511 | This function removes the exclusive lock which is created by LDREX. |
slowness | 0:c03cffe402df | 512 | |
slowness | 0:c03cffe402df | 513 | */ |
slowness | 0:c03cffe402df | 514 | __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) |
slowness | 0:c03cffe402df | 515 | { |
slowness | 0:c03cffe402df | 516 | __ASM volatile ("clrex"); |
slowness | 0:c03cffe402df | 517 | } |
slowness | 0:c03cffe402df | 518 | |
slowness | 0:c03cffe402df | 519 | |
slowness | 0:c03cffe402df | 520 | /** \brief Signed Saturate |
slowness | 0:c03cffe402df | 521 | |
slowness | 0:c03cffe402df | 522 | This function saturates a signed value. |
slowness | 0:c03cffe402df | 523 | |
slowness | 0:c03cffe402df | 524 | \param [in] value Value to be saturated |
slowness | 0:c03cffe402df | 525 | \param [in] sat Bit position to saturate to (1..32) |
slowness | 0:c03cffe402df | 526 | \return Saturated value |
slowness | 0:c03cffe402df | 527 | */ |
slowness | 0:c03cffe402df | 528 | #define __SSAT(ARG1,ARG2) \ |
slowness | 0:c03cffe402df | 529 | ({ \ |
slowness | 0:c03cffe402df | 530 | uint32_t __RES, __ARG1 = (ARG1); \ |
slowness | 0:c03cffe402df | 531 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
slowness | 0:c03cffe402df | 532 | __RES; \ |
slowness | 0:c03cffe402df | 533 | }) |
slowness | 0:c03cffe402df | 534 | |
slowness | 0:c03cffe402df | 535 | |
slowness | 0:c03cffe402df | 536 | /** \brief Unsigned Saturate |
slowness | 0:c03cffe402df | 537 | |
slowness | 0:c03cffe402df | 538 | This function saturates an unsigned value. |
slowness | 0:c03cffe402df | 539 | |
slowness | 0:c03cffe402df | 540 | \param [in] value Value to be saturated |
slowness | 0:c03cffe402df | 541 | \param [in] sat Bit position to saturate to (0..31) |
slowness | 0:c03cffe402df | 542 | \return Saturated value |
slowness | 0:c03cffe402df | 543 | */ |
slowness | 0:c03cffe402df | 544 | #define __USAT(ARG1,ARG2) \ |
slowness | 0:c03cffe402df | 545 | ({ \ |
slowness | 0:c03cffe402df | 546 | uint32_t __RES, __ARG1 = (ARG1); \ |
slowness | 0:c03cffe402df | 547 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
slowness | 0:c03cffe402df | 548 | __RES; \ |
slowness | 0:c03cffe402df | 549 | }) |
slowness | 0:c03cffe402df | 550 | |
slowness | 0:c03cffe402df | 551 | |
slowness | 0:c03cffe402df | 552 | /** \brief Count leading zeros |
slowness | 0:c03cffe402df | 553 | |
slowness | 0:c03cffe402df | 554 | This function counts the number of leading zeros of a data value. |
slowness | 0:c03cffe402df | 555 | |
slowness | 0:c03cffe402df | 556 | \param [in] value Value to count the leading zeros |
slowness | 0:c03cffe402df | 557 | \return number of leading zeros in value |
slowness | 0:c03cffe402df | 558 | */ |
slowness | 0:c03cffe402df | 559 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) |
slowness | 0:c03cffe402df | 560 | { |
slowness | 0:c03cffe402df | 561 | uint8_t result; |
slowness | 0:c03cffe402df | 562 | |
slowness | 0:c03cffe402df | 563 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); |
slowness | 0:c03cffe402df | 564 | return(result); |
slowness | 0:c03cffe402df | 565 | } |
slowness | 0:c03cffe402df | 566 | |
slowness | 0:c03cffe402df | 567 | #endif /* (__CORTEX_M >= 0x03) */ |
slowness | 0:c03cffe402df | 568 | |
slowness | 0:c03cffe402df | 569 | |
slowness | 0:c03cffe402df | 570 | |
slowness | 0:c03cffe402df | 571 | |
slowness | 0:c03cffe402df | 572 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
slowness | 0:c03cffe402df | 573 | /* TASKING carm specific functions */ |
slowness | 0:c03cffe402df | 574 | |
slowness | 0:c03cffe402df | 575 | /* |
slowness | 0:c03cffe402df | 576 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
slowness | 0:c03cffe402df | 577 | * Please use "carm -?i" to get an up to date list of all intrinsics, |
slowness | 0:c03cffe402df | 578 | * Including the CMSIS ones. |
slowness | 0:c03cffe402df | 579 | */ |
slowness | 0:c03cffe402df | 580 | |
slowness | 0:c03cffe402df | 581 | #endif |
slowness | 0:c03cffe402df | 582 | |
slowness | 0:c03cffe402df | 583 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
slowness | 0:c03cffe402df | 584 | |
slowness | 0:c03cffe402df | 585 | #endif /* __CORE_CMINSTR_H */ |