Dependents:   sample_collection_for_starboard_orange starboard_orange_samples

Committer:
chris
Date:
Wed May 19 06:31:49 2010 +0000
Revision:
0:f4e330489777

        

Who changed what in which revision?

UserRevisionLine numberNew contents of line
chris 0:f4e330489777 1 /*
chris 0:f4e330489777 2 **************************************************************************************************************
chris 0:f4e330489777 3 * NXP USB Host Stack
chris 0:f4e330489777 4 *
chris 0:f4e330489777 5 * (c) Copyright 2008, NXP SemiConductors
chris 0:f4e330489777 6 * (c) Copyright 2008, OnChip Technologies LLC
chris 0:f4e330489777 7 * All Rights Reserved
chris 0:f4e330489777 8 *
chris 0:f4e330489777 9 * www.nxp.com
chris 0:f4e330489777 10 * www.onchiptech.com
chris 0:f4e330489777 11 *
chris 0:f4e330489777 12 * File : usbhost_lpc17xx.c
chris 0:f4e330489777 13 * Programmer(s) : Ravikanth.P
chris 0:f4e330489777 14 * Version :
chris 0:f4e330489777 15 *
chris 0:f4e330489777 16 **************************************************************************************************************
chris 0:f4e330489777 17 */
chris 0:f4e330489777 18
chris 0:f4e330489777 19 /*
chris 0:f4e330489777 20 **************************************************************************************************************
chris 0:f4e330489777 21 * INCLUDE HEADER FILES
chris 0:f4e330489777 22 **************************************************************************************************************
chris 0:f4e330489777 23 */
chris 0:f4e330489777 24
chris 0:f4e330489777 25 #include "usbhost_lpc17xx.h"
chris 0:f4e330489777 26
chris 0:f4e330489777 27 /*
chris 0:f4e330489777 28 **************************************************************************************************************
chris 0:f4e330489777 29 * GLOBAL VARIABLES
chris 0:f4e330489777 30 **************************************************************************************************************
chris 0:f4e330489777 31 */
chris 0:f4e330489777 32 int gUSBConnected;
chris 0:f4e330489777 33
chris 0:f4e330489777 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
chris 0:f4e330489777 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
chris 0:f4e330489777 36 volatile USB_INT08U HOST_TDControlStatus = 0;
chris 0:f4e330489777 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
chris 0:f4e330489777 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
chris 0:f4e330489777 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
chris 0:f4e330489777 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
chris 0:f4e330489777 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
chris 0:f4e330489777 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
chris 0:f4e330489777 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
chris 0:f4e330489777 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
chris 0:f4e330489777 45
chris 0:f4e330489777 46 // USB host structures
chris 0:f4e330489777 47 // AHB SRAM block 1
chris 0:f4e330489777 48 #define HOSTBASEADDR 0x2007C000
chris 0:f4e330489777 49 // reserve memory for the linker
chris 0:f4e330489777 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
chris 0:f4e330489777 51 /*
chris 0:f4e330489777 52 **************************************************************************************************************
chris 0:f4e330489777 53 * DELAY IN MILLI SECONDS
chris 0:f4e330489777 54 *
chris 0:f4e330489777 55 * Description: This function provides a delay in milli seconds
chris 0:f4e330489777 56 *
chris 0:f4e330489777 57 * Arguments : delay The delay required
chris 0:f4e330489777 58 *
chris 0:f4e330489777 59 * Returns : None
chris 0:f4e330489777 60 *
chris 0:f4e330489777 61 **************************************************************************************************************
chris 0:f4e330489777 62 */
chris 0:f4e330489777 63
chris 0:f4e330489777 64 void Host_DelayMS (USB_INT32U delay)
chris 0:f4e330489777 65 {
chris 0:f4e330489777 66 volatile USB_INT32U i;
chris 0:f4e330489777 67
chris 0:f4e330489777 68
chris 0:f4e330489777 69 for (i = 0; i < delay; i++) {
chris 0:f4e330489777 70 Host_DelayUS(1000);
chris 0:f4e330489777 71 }
chris 0:f4e330489777 72 }
chris 0:f4e330489777 73
chris 0:f4e330489777 74 /*
chris 0:f4e330489777 75 **************************************************************************************************************
chris 0:f4e330489777 76 * DELAY IN MICRO SECONDS
chris 0:f4e330489777 77 *
chris 0:f4e330489777 78 * Description: This function provides a delay in micro seconds
chris 0:f4e330489777 79 *
chris 0:f4e330489777 80 * Arguments : delay The delay required
chris 0:f4e330489777 81 *
chris 0:f4e330489777 82 * Returns : None
chris 0:f4e330489777 83 *
chris 0:f4e330489777 84 **************************************************************************************************************
chris 0:f4e330489777 85 */
chris 0:f4e330489777 86
chris 0:f4e330489777 87 void Host_DelayUS (USB_INT32U delay)
chris 0:f4e330489777 88 {
chris 0:f4e330489777 89 volatile USB_INT32U i;
chris 0:f4e330489777 90
chris 0:f4e330489777 91
chris 0:f4e330489777 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
chris 0:f4e330489777 93 ;
chris 0:f4e330489777 94 }
chris 0:f4e330489777 95 }
chris 0:f4e330489777 96
chris 0:f4e330489777 97 // bits of the USB/OTG clock control register
chris 0:f4e330489777 98 #define HOST_CLK_EN (1<<0)
chris 0:f4e330489777 99 #define DEV_CLK_EN (1<<1)
chris 0:f4e330489777 100 #define PORTSEL_CLK_EN (1<<3)
chris 0:f4e330489777 101 #define AHB_CLK_EN (1<<4)
chris 0:f4e330489777 102
chris 0:f4e330489777 103 // bits of the USB/OTG clock status register
chris 0:f4e330489777 104 #define HOST_CLK_ON (1<<0)
chris 0:f4e330489777 105 #define DEV_CLK_ON (1<<1)
chris 0:f4e330489777 106 #define PORTSEL_CLK_ON (1<<3)
chris 0:f4e330489777 107 #define AHB_CLK_ON (1<<4)
chris 0:f4e330489777 108
chris 0:f4e330489777 109 // we need host clock, OTG/portsel clock and AHB clock
chris 0:f4e330489777 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
chris 0:f4e330489777 111
chris 0:f4e330489777 112 /*
chris 0:f4e330489777 113 **************************************************************************************************************
chris 0:f4e330489777 114 * INITIALIZE THE HOST CONTROLLER
chris 0:f4e330489777 115 *
chris 0:f4e330489777 116 * Description: This function initializes lpc17xx host controller
chris 0:f4e330489777 117 *
chris 0:f4e330489777 118 * Arguments : None
chris 0:f4e330489777 119 *
chris 0:f4e330489777 120 * Returns :
chris 0:f4e330489777 121 *
chris 0:f4e330489777 122 **************************************************************************************************************
chris 0:f4e330489777 123 */
chris 0:f4e330489777 124 void Host_Init (void)
chris 0:f4e330489777 125 {
chris 0:f4e330489777 126 PRINT_Log("In Host_Init\n");
chris 0:f4e330489777 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
chris 0:f4e330489777 128
chris 0:f4e330489777 129 // turn on power for USB
chris 0:f4e330489777 130 LPC_SC->PCONP |= (1UL<<31);
chris 0:f4e330489777 131 // Enable USB host clock, port selection and AHB clock
chris 0:f4e330489777 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
chris 0:f4e330489777 133 // Wait for clocks to become available
chris 0:f4e330489777 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
chris 0:f4e330489777 135 ;
chris 0:f4e330489777 136
chris 0:f4e330489777 137 // it seems the bits[0:1] mean the following
chris 0:f4e330489777 138 // 0: U1=device, U2=host
chris 0:f4e330489777 139 // 1: U1=host, U2=host
chris 0:f4e330489777 140 // 2: reserved
chris 0:f4e330489777 141 // 3: U1=host, U2=device
chris 0:f4e330489777 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
chris 0:f4e330489777 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
chris 0:f4e330489777 144 LPC_USB->OTGStCtrl |= 1;
chris 0:f4e330489777 145
chris 0:f4e330489777 146 // now that we've configured the ports, we can turn off the portsel clock
chris 0:f4e330489777 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
chris 0:f4e330489777 148
chris 0:f4e330489777 149 // power pins are not connected on mbed, so we can skip them
chris 0:f4e330489777 150 /* P1[18] = USB_UP_LED, 01 */
chris 0:f4e330489777 151 /* P1[19] = /USB_PPWR, 10 */
chris 0:f4e330489777 152 /* P1[22] = USB_PWRD, 10 */
chris 0:f4e330489777 153 /* P1[27] = /USB_OVRCR, 10 */
chris 0:f4e330489777 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
chris 0:f4e330489777 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
chris 0:f4e330489777 156 */
chris 0:f4e330489777 157
chris 0:f4e330489777 158 // configure USB D+/D- pins
chris 0:f4e330489777 159 /* P0[29] = USB_D+, 01 */
chris 0:f4e330489777 160 /* P0[30] = USB_D-, 01 */
chris 0:f4e330489777 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
chris 0:f4e330489777 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
chris 0:f4e330489777 163
chris 0:f4e330489777 164 PRINT_Log("Initializing Host Stack\n");
chris 0:f4e330489777 165
chris 0:f4e330489777 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
chris 0:f4e330489777 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
chris 0:f4e330489777 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
chris 0:f4e330489777 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
chris 0:f4e330489777 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
chris 0:f4e330489777 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
chris 0:f4e330489777 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
chris 0:f4e330489777 173
chris 0:f4e330489777 174 /* Initialize all the TDs, EDs and HCCA to 0 */
chris 0:f4e330489777 175 Host_EDInit(EDCtrl);
chris 0:f4e330489777 176 Host_EDInit(EDBulkIn);
chris 0:f4e330489777 177 Host_EDInit(EDBulkOut);
chris 0:f4e330489777 178 Host_TDInit(TDHead);
chris 0:f4e330489777 179 Host_TDInit(TDTail);
chris 0:f4e330489777 180 Host_HCCAInit(Hcca);
chris 0:f4e330489777 181
chris 0:f4e330489777 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
chris 0:f4e330489777 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
chris 0:f4e330489777 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
chris 0:f4e330489777 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
chris 0:f4e330489777 186
chris 0:f4e330489777 187 /* SOFTWARE RESET */
chris 0:f4e330489777 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
chris 0:f4e330489777 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
chris 0:f4e330489777 190
chris 0:f4e330489777 191 /* Put HC in operational state */
chris 0:f4e330489777 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
chris 0:f4e330489777 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
chris 0:f4e330489777 194
chris 0:f4e330489777 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
chris 0:f4e330489777 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
chris 0:f4e330489777 197
chris 0:f4e330489777 198
chris 0:f4e330489777 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
chris 0:f4e330489777 200 OR_INTR_ENABLE_WDH |
chris 0:f4e330489777 201 OR_INTR_ENABLE_RHSC;
chris 0:f4e330489777 202
chris 0:f4e330489777 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
chris 0:f4e330489777 204 /* Enable the USB Interrupt */
chris 0:f4e330489777 205 NVIC_EnableIRQ(USB_IRQn);
chris 0:f4e330489777 206 PRINT_Log("Host Initialized\n");
chris 0:f4e330489777 207 }
chris 0:f4e330489777 208
chris 0:f4e330489777 209 /*
chris 0:f4e330489777 210 **************************************************************************************************************
chris 0:f4e330489777 211 * INTERRUPT SERVICE ROUTINE
chris 0:f4e330489777 212 *
chris 0:f4e330489777 213 * Description: This function services the interrupt caused by host controller
chris 0:f4e330489777 214 *
chris 0:f4e330489777 215 * Arguments : None
chris 0:f4e330489777 216 *
chris 0:f4e330489777 217 * Returns : None
chris 0:f4e330489777 218 *
chris 0:f4e330489777 219 **************************************************************************************************************
chris 0:f4e330489777 220 */
chris 0:f4e330489777 221
chris 0:f4e330489777 222 void USB_IRQHandler (void) __irq
chris 0:f4e330489777 223 {
chris 0:f4e330489777 224 USB_INT32U int_status;
chris 0:f4e330489777 225 USB_INT32U ie_status;
chris 0:f4e330489777 226
chris 0:f4e330489777 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
chris 0:f4e330489777 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
chris 0:f4e330489777 229
chris 0:f4e330489777 230 if (!(int_status & ie_status)) {
chris 0:f4e330489777 231 return;
chris 0:f4e330489777 232 } else {
chris 0:f4e330489777 233
chris 0:f4e330489777 234 int_status = int_status & ie_status;
chris 0:f4e330489777 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
chris 0:f4e330489777 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
chris 0:f4e330489777 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
chris 0:f4e330489777 238 /*
chris 0:f4e330489777 239 * When DRWE is on, Connect Status Change
chris 0:f4e330489777 240 * means a remote wakeup event.
chris 0:f4e330489777 241 */
chris 0:f4e330489777 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
chris 0:f4e330489777 243 }
chris 0:f4e330489777 244 else {
chris 0:f4e330489777 245 /*
chris 0:f4e330489777 246 * When DRWE is off, Connect Status Change
chris 0:f4e330489777 247 * is NOT a remote wakeup event
chris 0:f4e330489777 248 */
chris 0:f4e330489777 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
chris 0:f4e330489777 250 if (!gUSBConnected) {
chris 0:f4e330489777 251 HOST_TDControlStatus = 0;
chris 0:f4e330489777 252 HOST_WdhIntr = 0;
chris 0:f4e330489777 253 HOST_RhscIntr = 1;
chris 0:f4e330489777 254 gUSBConnected = 1;
chris 0:f4e330489777 255 }
chris 0:f4e330489777 256 else
chris 0:f4e330489777 257 PRINT_Log("Spurious status change (connected)?\n");
chris 0:f4e330489777 258 } else {
chris 0:f4e330489777 259 if (gUSBConnected) {
chris 0:f4e330489777 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
chris 0:f4e330489777 261 HOST_RhscIntr = 0;
chris 0:f4e330489777 262 gUSBConnected = 0;
chris 0:f4e330489777 263 }
chris 0:f4e330489777 264 else
chris 0:f4e330489777 265 PRINT_Log("Spurious status change (disconnected)?\n");
chris 0:f4e330489777 266 }
chris 0:f4e330489777 267 }
chris 0:f4e330489777 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
chris 0:f4e330489777 269 }
chris 0:f4e330489777 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
chris 0:f4e330489777 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
chris 0:f4e330489777 272 }
chris 0:f4e330489777 273 }
chris 0:f4e330489777 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
chris 0:f4e330489777 275 HOST_WdhIntr = 1;
chris 0:f4e330489777 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
chris 0:f4e330489777 277 }
chris 0:f4e330489777 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
chris 0:f4e330489777 279 }
chris 0:f4e330489777 280 return;
chris 0:f4e330489777 281 }
chris 0:f4e330489777 282
chris 0:f4e330489777 283 /*
chris 0:f4e330489777 284 **************************************************************************************************************
chris 0:f4e330489777 285 * PROCESS TRANSFER DESCRIPTOR
chris 0:f4e330489777 286 *
chris 0:f4e330489777 287 * Description: This function processes the transfer descriptor
chris 0:f4e330489777 288 *
chris 0:f4e330489777 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
chris 0:f4e330489777 290 * token SETUP, IN, OUT
chris 0:f4e330489777 291 * buffer Current Buffer Pointer of the transfer descriptor
chris 0:f4e330489777 292 * buffer_len Length of the buffer
chris 0:f4e330489777 293 *
chris 0:f4e330489777 294 * Returns : OK if TD submission is successful
chris 0:f4e330489777 295 * ERROR if TD submission fails
chris 0:f4e330489777 296 *
chris 0:f4e330489777 297 **************************************************************************************************************
chris 0:f4e330489777 298 */
chris 0:f4e330489777 299
chris 0:f4e330489777 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
chris 0:f4e330489777 301 volatile USB_INT32U token,
chris 0:f4e330489777 302 volatile USB_INT08U *buffer,
chris 0:f4e330489777 303 USB_INT32U buffer_len)
chris 0:f4e330489777 304 {
chris 0:f4e330489777 305 volatile USB_INT32U td_toggle;
chris 0:f4e330489777 306
chris 0:f4e330489777 307
chris 0:f4e330489777 308 if (ed == EDCtrl) {
chris 0:f4e330489777 309 if (token == TD_SETUP) {
chris 0:f4e330489777 310 td_toggle = TD_TOGGLE_0;
chris 0:f4e330489777 311 } else {
chris 0:f4e330489777 312 td_toggle = TD_TOGGLE_1;
chris 0:f4e330489777 313 }
chris 0:f4e330489777 314 } else {
chris 0:f4e330489777 315 td_toggle = 0;
chris 0:f4e330489777 316 }
chris 0:f4e330489777 317 TDHead->Control = (TD_ROUNDING |
chris 0:f4e330489777 318 token |
chris 0:f4e330489777 319 TD_DELAY_INT(0) |
chris 0:f4e330489777 320 td_toggle |
chris 0:f4e330489777 321 TD_CC);
chris 0:f4e330489777 322 TDTail->Control = 0;
chris 0:f4e330489777 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
chris 0:f4e330489777 324 TDTail->CurrBufPtr = 0;
chris 0:f4e330489777 325 TDHead->Next = (USB_INT32U) TDTail;
chris 0:f4e330489777 326 TDTail->Next = 0;
chris 0:f4e330489777 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
chris 0:f4e330489777 328 TDTail->BufEnd = 0;
chris 0:f4e330489777 329
chris 0:f4e330489777 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
chris 0:f4e330489777 331 ed->TailTd = (USB_INT32U)TDTail;
chris 0:f4e330489777 332 ed->Next = 0;
chris 0:f4e330489777 333
chris 0:f4e330489777 334 if (ed == EDCtrl) {
chris 0:f4e330489777 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
chris 0:f4e330489777 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
chris 0:f4e330489777 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
chris 0:f4e330489777 338 } else {
chris 0:f4e330489777 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
chris 0:f4e330489777 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
chris 0:f4e330489777 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
chris 0:f4e330489777 342 }
chris 0:f4e330489777 343
chris 0:f4e330489777 344 Host_WDHWait();
chris 0:f4e330489777 345
chris 0:f4e330489777 346 // if (!(TDHead->Control & 0xF0000000)) {
chris 0:f4e330489777 347 if (!HOST_TDControlStatus) {
chris 0:f4e330489777 348 return (OK);
chris 0:f4e330489777 349 } else {
chris 0:f4e330489777 350 return (ERR_TD_FAIL);
chris 0:f4e330489777 351 }
chris 0:f4e330489777 352 }
chris 0:f4e330489777 353
chris 0:f4e330489777 354 /*
chris 0:f4e330489777 355 **************************************************************************************************************
chris 0:f4e330489777 356 * ENUMERATE THE DEVICE
chris 0:f4e330489777 357 *
chris 0:f4e330489777 358 * Description: This function is used to enumerate the device connected
chris 0:f4e330489777 359 *
chris 0:f4e330489777 360 * Arguments : None
chris 0:f4e330489777 361 *
chris 0:f4e330489777 362 * Returns : None
chris 0:f4e330489777 363 *
chris 0:f4e330489777 364 **************************************************************************************************************
chris 0:f4e330489777 365 */
chris 0:f4e330489777 366
chris 0:f4e330489777 367 USB_INT32S Host_EnumDev (void)
chris 0:f4e330489777 368 {
chris 0:f4e330489777 369 USB_INT32S rc;
chris 0:f4e330489777 370
chris 0:f4e330489777 371 PRINT_Log("Connect a Mass Storage device\n");
chris 0:f4e330489777 372 while (!HOST_RhscIntr)
chris 0:f4e330489777 373 __WFI();
chris 0:f4e330489777 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
chris 0:f4e330489777 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
chris 0:f4e330489777 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
chris 0:f4e330489777 377 __WFI(); // Wait for port reset to complete...
chris 0:f4e330489777 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
chris 0:f4e330489777 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
chris 0:f4e330489777 380
chris 0:f4e330489777 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
chris 0:f4e330489777 382 /* Read first 8 bytes of device desc */
chris 0:f4e330489777 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
chris 0:f4e330489777 384 if (rc != OK) {
chris 0:f4e330489777 385 PRINT_Err(rc);
chris 0:f4e330489777 386 return (rc);
chris 0:f4e330489777 387 }
chris 0:f4e330489777 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
chris 0:f4e330489777 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
chris 0:f4e330489777 390 if (rc != OK) {
chris 0:f4e330489777 391 PRINT_Err(rc);
chris 0:f4e330489777 392 return (rc);
chris 0:f4e330489777 393 }
chris 0:f4e330489777 394 Host_DelayMS(2);
chris 0:f4e330489777 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
chris 0:f4e330489777 396 /* Get the configuration descriptor */
chris 0:f4e330489777 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
chris 0:f4e330489777 398 if (rc != OK) {
chris 0:f4e330489777 399 PRINT_Err(rc);
chris 0:f4e330489777 400 return (rc);
chris 0:f4e330489777 401 }
chris 0:f4e330489777 402 /* Get the first configuration data */
chris 0:f4e330489777 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
chris 0:f4e330489777 404 if (rc != OK) {
chris 0:f4e330489777 405 PRINT_Err(rc);
chris 0:f4e330489777 406 return (rc);
chris 0:f4e330489777 407 }
chris 0:f4e330489777 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
chris 0:f4e330489777 409 if (rc != OK) {
chris 0:f4e330489777 410 PRINT_Err(rc);
chris 0:f4e330489777 411 return (rc);
chris 0:f4e330489777 412 }
chris 0:f4e330489777 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
chris 0:f4e330489777 414 if (rc != OK) {
chris 0:f4e330489777 415 PRINT_Err(rc);
chris 0:f4e330489777 416 }
chris 0:f4e330489777 417 Host_DelayMS(100); /* Some devices may require this delay */
chris 0:f4e330489777 418 return (rc);
chris 0:f4e330489777 419 }
chris 0:f4e330489777 420
chris 0:f4e330489777 421 /*
chris 0:f4e330489777 422 **************************************************************************************************************
chris 0:f4e330489777 423 * RECEIVE THE CONTROL INFORMATION
chris 0:f4e330489777 424 *
chris 0:f4e330489777 425 * Description: This function is used to receive the control information
chris 0:f4e330489777 426 *
chris 0:f4e330489777 427 * Arguments : bm_request_type
chris 0:f4e330489777 428 * b_request
chris 0:f4e330489777 429 * w_value
chris 0:f4e330489777 430 * w_index
chris 0:f4e330489777 431 * w_length
chris 0:f4e330489777 432 * buffer
chris 0:f4e330489777 433 *
chris 0:f4e330489777 434 * Returns : OK if Success
chris 0:f4e330489777 435 * ERROR if Failed
chris 0:f4e330489777 436 *
chris 0:f4e330489777 437 **************************************************************************************************************
chris 0:f4e330489777 438 */
chris 0:f4e330489777 439
chris 0:f4e330489777 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
chris 0:f4e330489777 441 USB_INT08U b_request,
chris 0:f4e330489777 442 USB_INT16U w_value,
chris 0:f4e330489777 443 USB_INT16U w_index,
chris 0:f4e330489777 444 USB_INT16U w_length,
chris 0:f4e330489777 445 volatile USB_INT08U *buffer)
chris 0:f4e330489777 446 {
chris 0:f4e330489777 447 USB_INT32S rc;
chris 0:f4e330489777 448
chris 0:f4e330489777 449
chris 0:f4e330489777 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris 0:f4e330489777 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris 0:f4e330489777 452 if (rc == OK) {
chris 0:f4e330489777 453 if (w_length) {
chris 0:f4e330489777 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
chris 0:f4e330489777 455 }
chris 0:f4e330489777 456 if (rc == OK) {
chris 0:f4e330489777 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
chris 0:f4e330489777 458 }
chris 0:f4e330489777 459 }
chris 0:f4e330489777 460 return (rc);
chris 0:f4e330489777 461 }
chris 0:f4e330489777 462
chris 0:f4e330489777 463 /*
chris 0:f4e330489777 464 **************************************************************************************************************
chris 0:f4e330489777 465 * SEND THE CONTROL INFORMATION
chris 0:f4e330489777 466 *
chris 0:f4e330489777 467 * Description: This function is used to send the control information
chris 0:f4e330489777 468 *
chris 0:f4e330489777 469 * Arguments : None
chris 0:f4e330489777 470 *
chris 0:f4e330489777 471 * Returns : OK if Success
chris 0:f4e330489777 472 * ERR_INVALID_BOOTSIG if Failed
chris 0:f4e330489777 473 *
chris 0:f4e330489777 474 **************************************************************************************************************
chris 0:f4e330489777 475 */
chris 0:f4e330489777 476
chris 0:f4e330489777 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
chris 0:f4e330489777 478 USB_INT08U b_request,
chris 0:f4e330489777 479 USB_INT16U w_value,
chris 0:f4e330489777 480 USB_INT16U w_index,
chris 0:f4e330489777 481 USB_INT16U w_length,
chris 0:f4e330489777 482 volatile USB_INT08U *buffer)
chris 0:f4e330489777 483 {
chris 0:f4e330489777 484 USB_INT32S rc;
chris 0:f4e330489777 485
chris 0:f4e330489777 486
chris 0:f4e330489777 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris 0:f4e330489777 488
chris 0:f4e330489777 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris 0:f4e330489777 490 if (rc == OK) {
chris 0:f4e330489777 491 if (w_length) {
chris 0:f4e330489777 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
chris 0:f4e330489777 493 }
chris 0:f4e330489777 494 if (rc == OK) {
chris 0:f4e330489777 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
chris 0:f4e330489777 496 }
chris 0:f4e330489777 497 }
chris 0:f4e330489777 498 return (rc);
chris 0:f4e330489777 499 }
chris 0:f4e330489777 500
chris 0:f4e330489777 501 /*
chris 0:f4e330489777 502 **************************************************************************************************************
chris 0:f4e330489777 503 * FILL SETUP PACKET
chris 0:f4e330489777 504 *
chris 0:f4e330489777 505 * Description: This function is used to fill the setup packet
chris 0:f4e330489777 506 *
chris 0:f4e330489777 507 * Arguments : None
chris 0:f4e330489777 508 *
chris 0:f4e330489777 509 * Returns : OK if Success
chris 0:f4e330489777 510 * ERR_INVALID_BOOTSIG if Failed
chris 0:f4e330489777 511 *
chris 0:f4e330489777 512 **************************************************************************************************************
chris 0:f4e330489777 513 */
chris 0:f4e330489777 514
chris 0:f4e330489777 515 void Host_FillSetup (USB_INT08U bm_request_type,
chris 0:f4e330489777 516 USB_INT08U b_request,
chris 0:f4e330489777 517 USB_INT16U w_value,
chris 0:f4e330489777 518 USB_INT16U w_index,
chris 0:f4e330489777 519 USB_INT16U w_length)
chris 0:f4e330489777 520 {
chris 0:f4e330489777 521 int i;
chris 0:f4e330489777 522 for (i=0;i<w_length;i++)
chris 0:f4e330489777 523 TDBuffer[i] = 0;
chris 0:f4e330489777 524
chris 0:f4e330489777 525 TDBuffer[0] = bm_request_type;
chris 0:f4e330489777 526 TDBuffer[1] = b_request;
chris 0:f4e330489777 527 WriteLE16U(&TDBuffer[2], w_value);
chris 0:f4e330489777 528 WriteLE16U(&TDBuffer[4], w_index);
chris 0:f4e330489777 529 WriteLE16U(&TDBuffer[6], w_length);
chris 0:f4e330489777 530 }
chris 0:f4e330489777 531
chris 0:f4e330489777 532
chris 0:f4e330489777 533
chris 0:f4e330489777 534 /*
chris 0:f4e330489777 535 **************************************************************************************************************
chris 0:f4e330489777 536 * INITIALIZE THE TRANSFER DESCRIPTOR
chris 0:f4e330489777 537 *
chris 0:f4e330489777 538 * Description: This function initializes transfer descriptor
chris 0:f4e330489777 539 *
chris 0:f4e330489777 540 * Arguments : Pointer to TD structure
chris 0:f4e330489777 541 *
chris 0:f4e330489777 542 * Returns : None
chris 0:f4e330489777 543 *
chris 0:f4e330489777 544 **************************************************************************************************************
chris 0:f4e330489777 545 */
chris 0:f4e330489777 546
chris 0:f4e330489777 547 void Host_TDInit (volatile HCTD *td)
chris 0:f4e330489777 548 {
chris 0:f4e330489777 549
chris 0:f4e330489777 550 td->Control = 0;
chris 0:f4e330489777 551 td->CurrBufPtr = 0;
chris 0:f4e330489777 552 td->Next = 0;
chris 0:f4e330489777 553 td->BufEnd = 0;
chris 0:f4e330489777 554 }
chris 0:f4e330489777 555
chris 0:f4e330489777 556 /*
chris 0:f4e330489777 557 **************************************************************************************************************
chris 0:f4e330489777 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
chris 0:f4e330489777 559 *
chris 0:f4e330489777 560 * Description: This function initializes endpoint descriptor
chris 0:f4e330489777 561 *
chris 0:f4e330489777 562 * Arguments : Pointer to ED strcuture
chris 0:f4e330489777 563 *
chris 0:f4e330489777 564 * Returns : None
chris 0:f4e330489777 565 *
chris 0:f4e330489777 566 **************************************************************************************************************
chris 0:f4e330489777 567 */
chris 0:f4e330489777 568
chris 0:f4e330489777 569 void Host_EDInit (volatile HCED *ed)
chris 0:f4e330489777 570 {
chris 0:f4e330489777 571
chris 0:f4e330489777 572 ed->Control = 0;
chris 0:f4e330489777 573 ed->TailTd = 0;
chris 0:f4e330489777 574 ed->HeadTd = 0;
chris 0:f4e330489777 575 ed->Next = 0;
chris 0:f4e330489777 576 }
chris 0:f4e330489777 577
chris 0:f4e330489777 578 /*
chris 0:f4e330489777 579 **************************************************************************************************************
chris 0:f4e330489777 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
chris 0:f4e330489777 581 *
chris 0:f4e330489777 582 * Description: This function initializes host controller communications area
chris 0:f4e330489777 583 *
chris 0:f4e330489777 584 * Arguments : Pointer to HCCA
chris 0:f4e330489777 585 *
chris 0:f4e330489777 586 * Returns :
chris 0:f4e330489777 587 *
chris 0:f4e330489777 588 **************************************************************************************************************
chris 0:f4e330489777 589 */
chris 0:f4e330489777 590
chris 0:f4e330489777 591 void Host_HCCAInit (volatile HCCA *hcca)
chris 0:f4e330489777 592 {
chris 0:f4e330489777 593 USB_INT32U i;
chris 0:f4e330489777 594
chris 0:f4e330489777 595
chris 0:f4e330489777 596 for (i = 0; i < 32; i++) {
chris 0:f4e330489777 597
chris 0:f4e330489777 598 hcca->IntTable[i] = 0;
chris 0:f4e330489777 599 hcca->FrameNumber = 0;
chris 0:f4e330489777 600 hcca->DoneHead = 0;
chris 0:f4e330489777 601 }
chris 0:f4e330489777 602
chris 0:f4e330489777 603 }
chris 0:f4e330489777 604
chris 0:f4e330489777 605 /*
chris 0:f4e330489777 606 **************************************************************************************************************
chris 0:f4e330489777 607 * WAIT FOR WDH INTERRUPT
chris 0:f4e330489777 608 *
chris 0:f4e330489777 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
chris 0:f4e330489777 610 *
chris 0:f4e330489777 611 * Arguments : None
chris 0:f4e330489777 612 *
chris 0:f4e330489777 613 * Returns : None
chris 0:f4e330489777 614 *
chris 0:f4e330489777 615 **************************************************************************************************************
chris 0:f4e330489777 616 */
chris 0:f4e330489777 617
chris 0:f4e330489777 618 void Host_WDHWait (void)
chris 0:f4e330489777 619 {
chris 0:f4e330489777 620 while (!HOST_WdhIntr)
chris 0:f4e330489777 621 __WFI();
chris 0:f4e330489777 622
chris 0:f4e330489777 623 HOST_WdhIntr = 0;
chris 0:f4e330489777 624 }
chris 0:f4e330489777 625
chris 0:f4e330489777 626 /*
chris 0:f4e330489777 627 **************************************************************************************************************
chris 0:f4e330489777 628 * READ LE 32U
chris 0:f4e330489777 629 *
chris 0:f4e330489777 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
chris 0:f4e330489777 631 * containing little endian processor
chris 0:f4e330489777 632 *
chris 0:f4e330489777 633 * Arguments : pmem Pointer to the character buffer
chris 0:f4e330489777 634 *
chris 0:f4e330489777 635 * Returns : val Unsigned integer
chris 0:f4e330489777 636 *
chris 0:f4e330489777 637 **************************************************************************************************************
chris 0:f4e330489777 638 */
chris 0:f4e330489777 639
chris 0:f4e330489777 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
chris 0:f4e330489777 641 {
chris 0:f4e330489777 642 USB_INT32U val = *(USB_INT32U*)pmem;
chris 0:f4e330489777 643 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 644 return __REV(val);
chris 0:f4e330489777 645 #else
chris 0:f4e330489777 646 return val;
chris 0:f4e330489777 647 #endif
chris 0:f4e330489777 648 }
chris 0:f4e330489777 649
chris 0:f4e330489777 650 /*
chris 0:f4e330489777 651 **************************************************************************************************************
chris 0:f4e330489777 652 * WRITE LE 32U
chris 0:f4e330489777 653 *
chris 0:f4e330489777 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris 0:f4e330489777 655 * containing little endian processor.
chris 0:f4e330489777 656 *
chris 0:f4e330489777 657 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 658 * val Integer value to be placed in the charecter buffer
chris 0:f4e330489777 659 *
chris 0:f4e330489777 660 * Returns : None
chris 0:f4e330489777 661 *
chris 0:f4e330489777 662 **************************************************************************************************************
chris 0:f4e330489777 663 */
chris 0:f4e330489777 664
chris 0:f4e330489777 665 void WriteLE32U (volatile USB_INT08U *pmem,
chris 0:f4e330489777 666 USB_INT32U val)
chris 0:f4e330489777 667 {
chris 0:f4e330489777 668 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 669 *(USB_INT32U*)pmem = __REV(val);
chris 0:f4e330489777 670 #else
chris 0:f4e330489777 671 *(USB_INT32U*)pmem = val;
chris 0:f4e330489777 672 #endif
chris 0:f4e330489777 673 }
chris 0:f4e330489777 674
chris 0:f4e330489777 675 /*
chris 0:f4e330489777 676 **************************************************************************************************************
chris 0:f4e330489777 677 * READ LE 16U
chris 0:f4e330489777 678 *
chris 0:f4e330489777 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris 0:f4e330489777 680 * containing little endian processor
chris 0:f4e330489777 681 *
chris 0:f4e330489777 682 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 683 *
chris 0:f4e330489777 684 * Returns : val Unsigned short integer
chris 0:f4e330489777 685 *
chris 0:f4e330489777 686 **************************************************************************************************************
chris 0:f4e330489777 687 */
chris 0:f4e330489777 688
chris 0:f4e330489777 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
chris 0:f4e330489777 690 {
chris 0:f4e330489777 691 USB_INT16U val = *(USB_INT16U*)pmem;
chris 0:f4e330489777 692 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 693 return __REV16(val);
chris 0:f4e330489777 694 #else
chris 0:f4e330489777 695 return val;
chris 0:f4e330489777 696 #endif
chris 0:f4e330489777 697 }
chris 0:f4e330489777 698
chris 0:f4e330489777 699 /*
chris 0:f4e330489777 700 **************************************************************************************************************
chris 0:f4e330489777 701 * WRITE LE 16U
chris 0:f4e330489777 702 *
chris 0:f4e330489777 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
chris 0:f4e330489777 704 * platform containing little endian processor
chris 0:f4e330489777 705 *
chris 0:f4e330489777 706 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 707 * val Value to be placed in the charecter buffer
chris 0:f4e330489777 708 *
chris 0:f4e330489777 709 * Returns : None
chris 0:f4e330489777 710 *
chris 0:f4e330489777 711 **************************************************************************************************************
chris 0:f4e330489777 712 */
chris 0:f4e330489777 713
chris 0:f4e330489777 714 void WriteLE16U (volatile USB_INT08U *pmem,
chris 0:f4e330489777 715 USB_INT16U val)
chris 0:f4e330489777 716 {
chris 0:f4e330489777 717 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
chris 0:f4e330489777 719 #else
chris 0:f4e330489777 720 *(USB_INT16U*)pmem = val;
chris 0:f4e330489777 721 #endif
chris 0:f4e330489777 722 }
chris 0:f4e330489777 723
chris 0:f4e330489777 724 /*
chris 0:f4e330489777 725 **************************************************************************************************************
chris 0:f4e330489777 726 * READ BE 32U
chris 0:f4e330489777 727 *
chris 0:f4e330489777 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
chris 0:f4e330489777 729 * containing big endian processor
chris 0:f4e330489777 730 *
chris 0:f4e330489777 731 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 732 *
chris 0:f4e330489777 733 * Returns : val Unsigned integer
chris 0:f4e330489777 734 *
chris 0:f4e330489777 735 **************************************************************************************************************
chris 0:f4e330489777 736 */
chris 0:f4e330489777 737
chris 0:f4e330489777 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
chris 0:f4e330489777 739 {
chris 0:f4e330489777 740 USB_INT32U val = *(USB_INT32U*)pmem;
chris 0:f4e330489777 741 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 742 return val;
chris 0:f4e330489777 743 #else
chris 0:f4e330489777 744 return __REV(val);
chris 0:f4e330489777 745 #endif
chris 0:f4e330489777 746 }
chris 0:f4e330489777 747
chris 0:f4e330489777 748 /*
chris 0:f4e330489777 749 **************************************************************************************************************
chris 0:f4e330489777 750 * WRITE BE 32U
chris 0:f4e330489777 751 *
chris 0:f4e330489777 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris 0:f4e330489777 753 * containing big endian processor
chris 0:f4e330489777 754 *
chris 0:f4e330489777 755 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 756 * val Value to be placed in the charecter buffer
chris 0:f4e330489777 757 *
chris 0:f4e330489777 758 * Returns : None
chris 0:f4e330489777 759 *
chris 0:f4e330489777 760 **************************************************************************************************************
chris 0:f4e330489777 761 */
chris 0:f4e330489777 762
chris 0:f4e330489777 763 void WriteBE32U (volatile USB_INT08U *pmem,
chris 0:f4e330489777 764 USB_INT32U val)
chris 0:f4e330489777 765 {
chris 0:f4e330489777 766 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 767 *(USB_INT32U*)pmem = val;
chris 0:f4e330489777 768 #else
chris 0:f4e330489777 769 *(USB_INT32U*)pmem = __REV(val);
chris 0:f4e330489777 770 #endif
chris 0:f4e330489777 771 }
chris 0:f4e330489777 772
chris 0:f4e330489777 773 /*
chris 0:f4e330489777 774 **************************************************************************************************************
chris 0:f4e330489777 775 * READ BE 16U
chris 0:f4e330489777 776 *
chris 0:f4e330489777 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris 0:f4e330489777 778 * containing big endian processor
chris 0:f4e330489777 779 *
chris 0:f4e330489777 780 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 781 *
chris 0:f4e330489777 782 * Returns : val Unsigned short integer
chris 0:f4e330489777 783 *
chris 0:f4e330489777 784 **************************************************************************************************************
chris 0:f4e330489777 785 */
chris 0:f4e330489777 786
chris 0:f4e330489777 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
chris 0:f4e330489777 788 {
chris 0:f4e330489777 789 USB_INT16U val = *(USB_INT16U*)pmem;
chris 0:f4e330489777 790 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 791 return val;
chris 0:f4e330489777 792 #else
chris 0:f4e330489777 793 return __REV16(val);
chris 0:f4e330489777 794 #endif
chris 0:f4e330489777 795 }
chris 0:f4e330489777 796
chris 0:f4e330489777 797 /*
chris 0:f4e330489777 798 **************************************************************************************************************
chris 0:f4e330489777 799 * WRITE BE 16U
chris 0:f4e330489777 800 *
chris 0:f4e330489777 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
chris 0:f4e330489777 802 * platform containing big endian processor
chris 0:f4e330489777 803 *
chris 0:f4e330489777 804 * Arguments : pmem Pointer to the charecter buffer
chris 0:f4e330489777 805 * val Value to be placed in the charecter buffer
chris 0:f4e330489777 806 *
chris 0:f4e330489777 807 * Returns : None
chris 0:f4e330489777 808 *
chris 0:f4e330489777 809 **************************************************************************************************************
chris 0:f4e330489777 810 */
chris 0:f4e330489777 811
chris 0:f4e330489777 812 void WriteBE16U (volatile USB_INT08U *pmem,
chris 0:f4e330489777 813 USB_INT16U val)
chris 0:f4e330489777 814 {
chris 0:f4e330489777 815 #ifdef __BIG_ENDIAN
chris 0:f4e330489777 816 *(USB_INT16U*)pmem = val;
chris 0:f4e330489777 817 #else
chris 0:f4e330489777 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
chris 0:f4e330489777 819 #endif
chris 0:f4e330489777 820 }