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targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file W7500x.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
bogdanm 0:9b334a45a8ff 4 * Device W7500x
bogdanm 0:9b334a45a8ff 5 * @version V3.01
bogdanm 0:9b334a45a8ff 6 * @date 06. March 2012
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #ifndef W7500x_H
bogdanm 0:9b334a45a8ff 27 #define W7500x_H
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 30 extern "C" {
bogdanm 0:9b334a45a8ff 31 #endif
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /** @addtogroup W7500x_Definitions W7500x Definitions
bogdanm 0:9b334a45a8ff 34 This file defines all structures and symbols for W7500x:
bogdanm 0:9b334a45a8ff 35 - registers and bitfields
bogdanm 0:9b334a45a8ff 36 - peripheral base address
bogdanm 0:9b334a45a8ff 37 - peripheral ID
bogdanm 0:9b334a45a8ff 38 - Peripheral definitions
bogdanm 0:9b334a45a8ff 39 @{
bogdanm 0:9b334a45a8ff 40 */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /******************************************************************************/
bogdanm 0:9b334a45a8ff 44 /* Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 45 /******************************************************************************/
bogdanm 0:9b334a45a8ff 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
bogdanm 0:9b334a45a8ff 47 Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 48 @{
bogdanm 0:9b334a45a8ff 49 */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /*
bogdanm 0:9b334a45a8ff 52 * ==========================================================================
bogdanm 0:9b334a45a8ff 53 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 54 * ==========================================================================
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 typedef enum IRQn
bogdanm 0:9b334a45a8ff 58 {
bogdanm 0:9b334a45a8ff 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
bogdanm 0:9b334a45a8ff 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
bogdanm 0:9b334a45a8ff 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
bogdanm 0:9b334a45a8ff 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
bogdanm 0:9b334a45a8ff 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
bogdanm 0:9b334a45a8ff 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
bogdanm 0:9b334a45a8ff 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
bogdanm 0:9b334a45a8ff 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
bogdanm 0:9b334a45a8ff 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
bogdanm 0:9b334a45a8ff 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
bogdanm 0:9b334a45a8ff 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
bogdanm 0:9b334a45a8ff 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
bogdanm 0:9b334a45a8ff 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
bogdanm 0:9b334a45a8ff 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
bogdanm 0:9b334a45a8ff 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
bogdanm 0:9b334a45a8ff 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
bogdanm 0:9b334a45a8ff 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
bogdanm 0:9b334a45a8ff 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
bogdanm 0:9b334a45a8ff 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
bogdanm 0:9b334a45a8ff 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
bogdanm 0:9b334a45a8ff 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
bogdanm 0:9b334a45a8ff 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
bogdanm 0:9b334a45a8ff 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
bogdanm 0:9b334a45a8ff 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
bogdanm 0:9b334a45a8ff 90 RTC_IRQn = 22, /*!< RTC Interrupt */
bogdanm 0:9b334a45a8ff 91 ADC_IRQn = 23, /*!< ADC Interrupt */
bogdanm 0:9b334a45a8ff 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
bogdanm 0:9b334a45a8ff 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
bogdanm 0:9b334a45a8ff 94 } IRQn_Type;
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /*
bogdanm 0:9b334a45a8ff 97 * ==========================================================================
bogdanm 0:9b334a45a8ff 98 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 99 * ==========================================================================
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
bogdanm 0:9b334a45a8ff 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /*@}*/ /* end of group W7500x_CMSIS */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm 0:9b334a45a8ff 112 #include "system_W7500x.h" /* W7500x System include file */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /** @addtogroup Exported_types
bogdanm 0:9b334a45a8ff 116 * @{
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm 0:9b334a45a8ff 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm 0:9b334a45a8ff 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /**
bogdanm 0:9b334a45a8ff 129 * @}
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @addtogroup Peripheral_registers_structures
bogdanm 0:9b334a45a8ff 136 * @{
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /**
bogdanm 0:9b334a45a8ff 140 * @brief Clock Reset Generator
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142 typedef struct
bogdanm 0:9b334a45a8ff 143 {
bogdanm 0:9b334a45a8ff 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
bogdanm 0:9b334a45a8ff 145 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
bogdanm 0:9b334a45a8ff 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
bogdanm 0:9b334a45a8ff 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
bogdanm 0:9b334a45a8ff 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
bogdanm 0:9b334a45a8ff 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
bogdanm 0:9b334a45a8ff 151 uint32_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
bogdanm 0:9b334a45a8ff 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
bogdanm 0:9b334a45a8ff 154 uint32_t RESERVED2[2];
bogdanm 0:9b334a45a8ff 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
bogdanm 0:9b334a45a8ff 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
bogdanm 0:9b334a45a8ff 157 uint32_t RESERVED3[6];
bogdanm 0:9b334a45a8ff 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
bogdanm 0:9b334a45a8ff 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
bogdanm 0:9b334a45a8ff 160 uint32_t RESERVED4[2];
bogdanm 0:9b334a45a8ff 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
bogdanm 0:9b334a45a8ff 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
bogdanm 0:9b334a45a8ff 163 uint32_t RESERVED5[2];
bogdanm 0:9b334a45a8ff 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
bogdanm 0:9b334a45a8ff 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
bogdanm 0:9b334a45a8ff 166 uint32_t RESERVED6[10];
bogdanm 0:9b334a45a8ff 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
bogdanm 0:9b334a45a8ff 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
bogdanm 0:9b334a45a8ff 169 uint32_t RESERVED7[2];
bogdanm 0:9b334a45a8ff 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
bogdanm 0:9b334a45a8ff 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
bogdanm 0:9b334a45a8ff 172 uint32_t RESERVED8[2];
bogdanm 0:9b334a45a8ff 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
bogdanm 0:9b334a45a8ff 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
bogdanm 0:9b334a45a8ff 175 uint32_t RESERVED9[2];
bogdanm 0:9b334a45a8ff 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
bogdanm 0:9b334a45a8ff 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
bogdanm 0:9b334a45a8ff 178 uint32_t RESERVED10[2];
bogdanm 0:9b334a45a8ff 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
bogdanm 0:9b334a45a8ff 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
bogdanm 0:9b334a45a8ff 181 uint32_t RESERVED11[2];
bogdanm 0:9b334a45a8ff 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
bogdanm 0:9b334a45a8ff 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
bogdanm 0:9b334a45a8ff 184 uint32_t RESERVED12[2];
bogdanm 0:9b334a45a8ff 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
bogdanm 0:9b334a45a8ff 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
bogdanm 0:9b334a45a8ff 187 uint32_t RESERVED13[2];
bogdanm 0:9b334a45a8ff 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
bogdanm 0:9b334a45a8ff 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
bogdanm 0:9b334a45a8ff 190 uint32_t RESERVED14[2];
bogdanm 0:9b334a45a8ff 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
bogdanm 0:9b334a45a8ff 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
bogdanm 0:9b334a45a8ff 193 uint32_t RESERVED15;
bogdanm 0:9b334a45a8ff 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
bogdanm 0:9b334a45a8ff 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
bogdanm 0:9b334a45a8ff 198 uint32_t RESERVED16;
bogdanm 0:9b334a45a8ff 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
bogdanm 0:9b334a45a8ff 203 uint32_t RESERVED17[2];
bogdanm 0:9b334a45a8ff 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
bogdanm 0:9b334a45a8ff 205 uint32_t RESERVED18[3];
bogdanm 0:9b334a45a8ff 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
bogdanm 0:9b334a45a8ff 207 }CRG_TypeDef;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /**
bogdanm 0:9b334a45a8ff 211 * @brief UART
bogdanm 0:9b334a45a8ff 212 */
bogdanm 0:9b334a45a8ff 213 typedef struct
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
bogdanm 0:9b334a45a8ff 216 union {
bogdanm 0:9b334a45a8ff 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
bogdanm 0:9b334a45a8ff 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
bogdanm 0:9b334a45a8ff 219 } STATUS;
bogdanm 0:9b334a45a8ff 220 uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
bogdanm 0:9b334a45a8ff 222 uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
bogdanm 0:9b334a45a8ff 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
bogdanm 0:9b334a45a8ff 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
bogdanm 0:9b334a45a8ff 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
bogdanm 0:9b334a45a8ff 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
bogdanm 0:9b334a45a8ff 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
bogdanm 0:9b334a45a8ff 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
bogdanm 0:9b334a45a8ff 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
bogdanm 0:9b334a45a8ff 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
bogdanm 0:9b334a45a8ff 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
bogdanm 0:9b334a45a8ff 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
bogdanm 0:9b334a45a8ff 234 } UART_TypeDef;
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /**
bogdanm 0:9b334a45a8ff 238 * @brief Simple UART
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 typedef struct
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
bogdanm 0:9b334a45a8ff 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
bogdanm 0:9b334a45a8ff 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
bogdanm 0:9b334a45a8ff 245 union {
bogdanm 0:9b334a45a8ff 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
bogdanm 0:9b334a45a8ff 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
bogdanm 0:9b334a45a8ff 248 }INT;
bogdanm 0:9b334a45a8ff 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 } S_UART_TypeDef;
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /**
bogdanm 0:9b334a45a8ff 254 * @brief Analog Digital Converter
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 typedef struct
bogdanm 0:9b334a45a8ff 258 {
bogdanm 0:9b334a45a8ff 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
bogdanm 0:9b334a45a8ff 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
bogdanm 0:9b334a45a8ff 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
bogdanm 0:9b334a45a8ff 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
bogdanm 0:9b334a45a8ff 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
bogdanm 0:9b334a45a8ff 264 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
bogdanm 0:9b334a45a8ff 266 }ADC_TypeDef;
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /**
bogdanm 0:9b334a45a8ff 269 * @brief dualtimer
bogdanm 0:9b334a45a8ff 270 */
bogdanm 0:9b334a45a8ff 271 typedef struct
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
bogdanm 0:9b334a45a8ff 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
bogdanm 0:9b334a45a8ff 275 __IO uint32_t TimerControl; // <h> Timer Control
bogdanm 0:9b334a45a8ff 276 // <o.7> TimerEn: Timer Enable
bogdanm 0:9b334a45a8ff 277 // <o.6> TimerMode: Timer Mode
bogdanm 0:9b334a45a8ff 278 // <0=> Freerunning-mode
bogdanm 0:9b334a45a8ff 279 // <1=> Periodic mode
bogdanm 0:9b334a45a8ff 280 // <o.5> IntEnable: Interrupt Enable
bogdanm 0:9b334a45a8ff 281 // <o.2..3> TimerPre: Timer Prescale
bogdanm 0:9b334a45a8ff 282 // <0=> / 1
bogdanm 0:9b334a45a8ff 283 // <1=> / 16
bogdanm 0:9b334a45a8ff 284 // <2=> / 256
bogdanm 0:9b334a45a8ff 285 // <3=> Undefined!
bogdanm 0:9b334a45a8ff 286 // <o.1> TimerSize: Timer Size
bogdanm 0:9b334a45a8ff 287 // <0=> 16-bit counter
bogdanm 0:9b334a45a8ff 288 // <1=> 32-bit counter
bogdanm 0:9b334a45a8ff 289 // <o.0> OneShot: One-shoot mode
bogdanm 0:9b334a45a8ff 290 // <0=> Wrapping mode
bogdanm 0:9b334a45a8ff 291 // <1=> One-shot mode
bogdanm 0:9b334a45a8ff 292 // </h>
bogdanm 0:9b334a45a8ff 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
bogdanm 0:9b334a45a8ff 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
bogdanm 0:9b334a45a8ff 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
bogdanm 0:9b334a45a8ff 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
bogdanm 0:9b334a45a8ff 297 } DUALTIMER_TypeDef;
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /**
bogdanm 0:9b334a45a8ff 300 * @brief GPIO
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302 typedef struct
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
bogdanm 0:9b334a45a8ff 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
bogdanm 0:9b334a45a8ff 306 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
bogdanm 0:9b334a45a8ff 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
bogdanm 0:9b334a45a8ff 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
bogdanm 0:9b334a45a8ff 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
bogdanm 0:9b334a45a8ff 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
bogdanm 0:9b334a45a8ff 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
bogdanm 0:9b334a45a8ff 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
bogdanm 0:9b334a45a8ff 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
bogdanm 0:9b334a45a8ff 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
bogdanm 0:9b334a45a8ff 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
bogdanm 0:9b334a45a8ff 317 union {
bogdanm 0:9b334a45a8ff 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
bogdanm 0:9b334a45a8ff 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
bogdanm 0:9b334a45a8ff 320 }Interrupt;
bogdanm 0:9b334a45a8ff 321 uint32_t RESERVED3[241];
bogdanm 0:9b334a45a8ff 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
bogdanm 0:9b334a45a8ff 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
bogdanm 0:9b334a45a8ff 324 } GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 typedef struct
bogdanm 0:9b334a45a8ff 327 {
bogdanm 0:9b334a45a8ff 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
bogdanm 0:9b334a45a8ff 329 /* Port_01, offset : 0x04 */
bogdanm 0:9b334a45a8ff 330 /* Port_02, offset : 0x08 */
bogdanm 0:9b334a45a8ff 331 /* Port_03, offset : 0x0C */
bogdanm 0:9b334a45a8ff 332 /* Port_04, offset : 0x10 */
bogdanm 0:9b334a45a8ff 333 /* Port_05, offset : 0x14 */
bogdanm 0:9b334a45a8ff 334 /* Port_06, offset : 0x18 */
bogdanm 0:9b334a45a8ff 335 /* Port_07, offset : 0x1C */
bogdanm 0:9b334a45a8ff 336 /* Port_08, offset : 0x20 */
bogdanm 0:9b334a45a8ff 337 /* Port_09, offset : 0x24 */
bogdanm 0:9b334a45a8ff 338 /* Port_10, offset : 0x28 */
bogdanm 0:9b334a45a8ff 339 /* Port_11, offset : 0x2C */
bogdanm 0:9b334a45a8ff 340 /* Port_12, offset : 0x30 */
bogdanm 0:9b334a45a8ff 341 /* Port_13, offset : 0x34 */
bogdanm 0:9b334a45a8ff 342 /* Port_14, offset : 0x38 */
bogdanm 0:9b334a45a8ff 343 /* Port_15, offset : 0x3C */
bogdanm 0:9b334a45a8ff 344 } P_Port_Def;
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 typedef struct
bogdanm 0:9b334a45a8ff 347 {
bogdanm 0:9b334a45a8ff 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
bogdanm 0:9b334a45a8ff 349 /* Port_01, offset : 0x04 */
bogdanm 0:9b334a45a8ff 350 /* Port_02, offset : 0x08 */
bogdanm 0:9b334a45a8ff 351 /* Port_03, offset : 0x0C */
bogdanm 0:9b334a45a8ff 352 /* Port_04, offset : 0x10 */
bogdanm 0:9b334a45a8ff 353 } P_Port_D_Def;
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /**
bogdanm 0:9b334a45a8ff 356 * @brief I2C Register structure definition
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358 typedef struct
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 __IO uint32_t PRER; //0x00
bogdanm 0:9b334a45a8ff 361 __IO uint32_t CTR; //0x04
bogdanm 0:9b334a45a8ff 362 __IO uint32_t CMDR; //0x08
bogdanm 0:9b334a45a8ff 363 __I uint32_t SR; //0x0C
bogdanm 0:9b334a45a8ff 364 __IO uint32_t TSR; //0x10
bogdanm 0:9b334a45a8ff 365 __IO uint32_t SADDR; //0x14
bogdanm 0:9b334a45a8ff 366 __IO uint32_t TXR; //0x18
bogdanm 0:9b334a45a8ff 367 __I uint32_t RXR; //0x1C
bogdanm 0:9b334a45a8ff 368 __I uint32_t ISR; //0x20
bogdanm 0:9b334a45a8ff 369 __IO uint32_t ISCR; //0x24
bogdanm 0:9b334a45a8ff 370 __IO uint32_t ISMR; //0x28
bogdanm 0:9b334a45a8ff 371 }I2C_TypeDef;
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @brief PWM Register structure definition
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 typedef struct
bogdanm 0:9b334a45a8ff 377 {
bogdanm 0:9b334a45a8ff 378 __IO uint32_t IER; //Interrupt enable register
bogdanm 0:9b334a45a8ff 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 __IO uint32_t SSR; //Start Stop register
bogdanm 0:9b334a45a8ff 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 __IO uint32_t PSR; //Pause register
bogdanm 0:9b334a45a8ff 399 // <7> PS7 : Channel 7 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 400 // <6> PS6 : Channel 6 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 401 // <5> PS5 : Channel 5 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 402 // <4> PS4 : Channel 4 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 403 // <3> PS3 : Channel 3 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 404 // <2> PS2 : Channel 2 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 405 // <1> PS1 : Channel 1 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 406 // <0> PS0 : Channel 0 TC pasue <R/W>
bogdanm 0:9b334a45a8ff 407 } PWM_TypeDef;
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 typedef struct
bogdanm 0:9b334a45a8ff 410 {
bogdanm 0:9b334a45a8ff 411 __I uint32_t IR; //Interrupt register
bogdanm 0:9b334a45a8ff 412 // <2> CI : Capture interrupt <R>
bogdanm 0:9b334a45a8ff 413 // <1> OI : Overflow interrupt <R>
bogdanm 0:9b334a45a8ff 414 // <0> MI : Match interrupt <R>
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 __IO uint32_t IER; //Interrupt enable register
bogdanm 0:9b334a45a8ff 417 // <2> CIE : Capture interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 418 // <1> OIE : Overflow interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 419 // <0> MIE : Match interrupt enable <R/W>
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 __O uint32_t ICR; //Interrupt clear register
bogdanm 0:9b334a45a8ff 422 // <2> CIC : Capture interrupt clear <W>
bogdanm 0:9b334a45a8ff 423 // <1> OIC : Overflow interrupt clear <W>
bogdanm 0:9b334a45a8ff 424 // <0> MIC : Match interrupt clear <W>
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 __I uint32_t TCR; //Timer/Counter register
bogdanm 0:9b334a45a8ff 427 // <0..31> TCR : Timer/Counter register <R>
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 __I uint32_t PCR; //Prescale counter register
bogdanm 0:9b334a45a8ff 430 // <0..5> PCR : Prescale Counter register <R>
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 __IO uint32_t PR; //Prescale register
bogdanm 0:9b334a45a8ff 433 // <0..5> PR : prescale register <R/W>
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 __IO uint32_t MR; //Match register
bogdanm 0:9b334a45a8ff 436 // <0..31> MR : Match register <R/W>
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 __IO uint32_t LR; //Limit register
bogdanm 0:9b334a45a8ff 439 // <0..31> LR : Limit register <R/W>
bogdanm 0:9b334a45a8ff 440 __IO uint32_t UDMR; //Up-Down mode register
bogdanm 0:9b334a45a8ff 441 // <0> UDM : Up-down mode <R/W>
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 __IO uint32_t TCMR; //Timer/Counter mode register
bogdanm 0:9b334a45a8ff 444 // <0> TCM : Timer/Counter mode <R/W>
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
bogdanm 0:9b334a45a8ff 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 __IO uint32_t CMR; //Capture mode register
bogdanm 0:9b334a45a8ff 450 // <0> CM : Capture mode <R/W>
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 __IO uint32_t CR; //Capture register
bogdanm 0:9b334a45a8ff 453 // <0..31> CR : Capture register <R>
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 __IO uint32_t PDMR; //Periodic mode register
bogdanm 0:9b334a45a8ff 456 // <0> PDM : Periodic mode <R/W>
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 __IO uint32_t DZER; //Dead-zone enable register
bogdanm 0:9b334a45a8ff 459 // <0> DZE : Dead-zone enable <R/W>
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 __IO uint32_t DZCR; //Dead-zone counter register
bogdanm 0:9b334a45a8ff 462 // <0..9> DZC : Dead-zone counter <R/W>
bogdanm 0:9b334a45a8ff 463 } PWM_CHn_TypeDef;
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 typedef struct
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 __IO uint32_t PWM_CHn_PR; //Prescale register
bogdanm 0:9b334a45a8ff 468 // <0..5> PR : prescale register <R/W>
bogdanm 0:9b334a45a8ff 469 __IO uint32_t PWM_CHn_MR; //Match register
bogdanm 0:9b334a45a8ff 470 // <0..31> MR : Match register <R/W>
bogdanm 0:9b334a45a8ff 471 __IO uint32_t PWM_CHn_LR; //Limit register
bogdanm 0:9b334a45a8ff 472 // <0..31> LR : Limit register <R/W>
bogdanm 0:9b334a45a8ff 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
bogdanm 0:9b334a45a8ff 474 // <0> UDM : Up-down mode <R/W>
bogdanm 0:9b334a45a8ff 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
bogdanm 0:9b334a45a8ff 476 // <0> PDM : Periodic mode <R/W>
bogdanm 0:9b334a45a8ff 477 }PWM_TimerModeInitTypeDef;
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 typedef struct
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 __IO uint32_t PWM_CHn_PR; //Prescale register
bogdanm 0:9b334a45a8ff 482 // <0..5> PR : prescale register <R/W>
bogdanm 0:9b334a45a8ff 483 __IO uint32_t PWM_CHn_MR; //Match register
bogdanm 0:9b334a45a8ff 484 // <0..31> MR : Match register <R/W>
bogdanm 0:9b334a45a8ff 485 __IO uint32_t PWM_CHn_LR; //Limit register
bogdanm 0:9b334a45a8ff 486 // <0..31> LR : Limit register <R/W>
bogdanm 0:9b334a45a8ff 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
bogdanm 0:9b334a45a8ff 488 // <0> UDM : Up-down mode <R/W>
bogdanm 0:9b334a45a8ff 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
bogdanm 0:9b334a45a8ff 490 // <0> PDM : Peiodic mode <R/W>
bogdanm 0:9b334a45a8ff 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
bogdanm 0:9b334a45a8ff 492 // <0> CM : Capture mode <R/W>
bogdanm 0:9b334a45a8ff 493 }PWM_CaptureModeInitTypeDef;
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 typedef struct
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 __IO uint32_t PWM_CHn_MR;
bogdanm 0:9b334a45a8ff 498 __IO uint32_t PWM_CHn_LR;
bogdanm 0:9b334a45a8ff 499 __IO uint32_t PWM_CHn_UDMR;
bogdanm 0:9b334a45a8ff 500 __IO uint32_t PWM_CHn_PDMR;
bogdanm 0:9b334a45a8ff 501 __IO uint32_t PWM_CHn_TCMR;
bogdanm 0:9b334a45a8ff 502 }PWM_CounterModeInitTypeDef;
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /**
bogdanm 0:9b334a45a8ff 506 * @brief Random Number generator
bogdanm 0:9b334a45a8ff 507 */
bogdanm 0:9b334a45a8ff 508 typedef struct
bogdanm 0:9b334a45a8ff 509 {
bogdanm 0:9b334a45a8ff 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
bogdanm 0:9b334a45a8ff 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
bogdanm 0:9b334a45a8ff 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
bogdanm 0:9b334a45a8ff 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
bogdanm 0:9b334a45a8ff 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
bogdanm 0:9b334a45a8ff 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
bogdanm 0:9b334a45a8ff 516 }RNG_TypeDef;
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /**
bogdanm 0:9b334a45a8ff 519 * @brief Serial Peripheral Interface
bogdanm 0:9b334a45a8ff 520 */
bogdanm 0:9b334a45a8ff 521 typedef struct
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 __IO uint32_t CR0;
bogdanm 0:9b334a45a8ff 524 __IO uint32_t CR1;
bogdanm 0:9b334a45a8ff 525 __IO uint32_t DR;
bogdanm 0:9b334a45a8ff 526 __IO uint32_t SR;
bogdanm 0:9b334a45a8ff 527 __IO uint32_t CPSR;
bogdanm 0:9b334a45a8ff 528 __IO uint32_t IMSC;
bogdanm 0:9b334a45a8ff 529 __IO uint32_t RIS;
bogdanm 0:9b334a45a8ff 530 __IO uint32_t MIS;
bogdanm 0:9b334a45a8ff 531 __IO uint32_t ICR;
bogdanm 0:9b334a45a8ff 532 __IO uint32_t DMACR;
bogdanm 0:9b334a45a8ff 533 } SSP_TypeDef;
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 typedef struct
bogdanm 0:9b334a45a8ff 536 {
bogdanm 0:9b334a45a8ff 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
bogdanm 0:9b334a45a8ff 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
bogdanm 0:9b334a45a8ff 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
bogdanm 0:9b334a45a8ff 540 // <o.1> RESEN: Reset enable
bogdanm 0:9b334a45a8ff 541 // <o.0> INTEN: Interrupt enable
bogdanm 0:9b334a45a8ff 542 // </h>
bogdanm 0:9b334a45a8ff 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
bogdanm 0:9b334a45a8ff 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
bogdanm 0:9b334a45a8ff 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
bogdanm 0:9b334a45a8ff 546 uint32_t RESERVED[762];
bogdanm 0:9b334a45a8ff 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
bogdanm 0:9b334a45a8ff 548 }WATCHDOG_TypeDef;
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /** @addtogroup Peripheral_memory_map
bogdanm 0:9b334a45a8ff 551 * @{
bogdanm 0:9b334a45a8ff 552 */
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Peripheral and SRAM base address */
bogdanm 0:9b334a45a8ff 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
bogdanm 0:9b334a45a8ff 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
bogdanm 0:9b334a45a8ff 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 #define W7500x_RAM_BASE (0x20000000UL)
bogdanm 0:9b334a45a8ff 560 #define W7500x_APB1_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 561 #define W7500x_APB2_BASE (0x41000000UL)
bogdanm 0:9b334a45a8ff 562 #define W7500x_AHB_BASE (0x42000000UL)
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
bogdanm 0:9b334a45a8ff 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
bogdanm 0:9b334a45a8ff 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
bogdanm 0:9b334a45a8ff 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 #define W7500x_INFO_BGT (0x0003FDB8)
bogdanm 0:9b334a45a8ff 572 #define W7500x_INFO_OSC (0x0003FDBC)
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 #define W7500x_TRIM_BGT (0x41001210)
bogdanm 0:9b334a45a8ff 575 #define W7500x_TRIM_OSC (0x41001004)
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
bogdanm 0:9b334a45a8ff 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
bogdanm 0:9b334a45a8ff 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
bogdanm 0:9b334a45a8ff 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
bogdanm 0:9b334a45a8ff 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
bogdanm 0:9b334a45a8ff 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 #define SSP0_BASE (0x4000A000)
bogdanm 0:9b334a45a8ff 599 #define SSP1_BASE (0x4000B000)
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 /**
bogdanm 0:9b334a45a8ff 604 * @}
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /** @addtogroup Peripheral_declaration
bogdanm 0:9b334a45a8ff 609 * @{
bogdanm 0:9b334a45a8ff 610 */
bogdanm 0:9b334a45a8ff 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
bogdanm 0:9b334a45a8ff 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
bogdanm 0:9b334a45a8ff 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
bogdanm 0:9b334a45a8ff 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
bogdanm 0:9b334a45a8ff 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
bogdanm 0:9b334a45a8ff 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
bogdanm 0:9b334a45a8ff 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
bogdanm 0:9b334a45a8ff 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
bogdanm 0:9b334a45a8ff 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
bogdanm 0:9b334a45a8ff 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
bogdanm 0:9b334a45a8ff 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
bogdanm 0:9b334a45a8ff 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
bogdanm 0:9b334a45a8ff 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
bogdanm 0:9b334a45a8ff 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
bogdanm 0:9b334a45a8ff 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
bogdanm 0:9b334a45a8ff 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
bogdanm 0:9b334a45a8ff 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
bogdanm 0:9b334a45a8ff 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
bogdanm 0:9b334a45a8ff 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
bogdanm 0:9b334a45a8ff 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
bogdanm 0:9b334a45a8ff 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
bogdanm 0:9b334a45a8ff 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
bogdanm 0:9b334a45a8ff 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
bogdanm 0:9b334a45a8ff 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
bogdanm 0:9b334a45a8ff 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
bogdanm 0:9b334a45a8ff 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
bogdanm 0:9b334a45a8ff 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
bogdanm 0:9b334a45a8ff 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
bogdanm 0:9b334a45a8ff 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
bogdanm 0:9b334a45a8ff 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
bogdanm 0:9b334a45a8ff 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
bogdanm 0:9b334a45a8ff 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
bogdanm 0:9b334a45a8ff 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
bogdanm 0:9b334a45a8ff 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
bogdanm 0:9b334a45a8ff 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
bogdanm 0:9b334a45a8ff 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
bogdanm 0:9b334a45a8ff 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
bogdanm 0:9b334a45a8ff 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 /**
bogdanm 0:9b334a45a8ff 680 * @}
bogdanm 0:9b334a45a8ff 681 */
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /******************************************************************************/
bogdanm 0:9b334a45a8ff 686 /* */
bogdanm 0:9b334a45a8ff 687 /* Clock Reset Generator */
bogdanm 0:9b334a45a8ff 688 /* */
bogdanm 0:9b334a45a8ff 689 /******************************************************************************/
bogdanm 0:9b334a45a8ff 690 /**************** Bit definition for CRG_OSC_PDR **************************/
bogdanm 0:9b334a45a8ff 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
bogdanm 0:9b334a45a8ff 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
bogdanm 0:9b334a45a8ff 693 /**************** Bit definition for CRG_PLL_PDR **************************/
bogdanm 0:9b334a45a8ff 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
bogdanm 0:9b334a45a8ff 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
bogdanm 0:9b334a45a8ff 696 /**************** Bit definition for CRG_PLL_FCR **************************/
bogdanm 0:9b334a45a8ff 697 //ToDo
bogdanm 0:9b334a45a8ff 698 /**************** Bit definition for CRG_PLL_OER **************************/
bogdanm 0:9b334a45a8ff 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
bogdanm 0:9b334a45a8ff 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
bogdanm 0:9b334a45a8ff 701 /**************** Bit definition for CRG_PLL_BPR **************************/
bogdanm 0:9b334a45a8ff 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
bogdanm 0:9b334a45a8ff 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
bogdanm 0:9b334a45a8ff 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
bogdanm 0:9b334a45a8ff 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
bogdanm 0:9b334a45a8ff 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
bogdanm 0:9b334a45a8ff 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
bogdanm 0:9b334a45a8ff 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
bogdanm 0:9b334a45a8ff 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
bogdanm 0:9b334a45a8ff 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
bogdanm 0:9b334a45a8ff 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
bogdanm 0:9b334a45a8ff 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
bogdanm 0:9b334a45a8ff 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
bogdanm 0:9b334a45a8ff 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
bogdanm 0:9b334a45a8ff 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
bogdanm 0:9b334a45a8ff 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
bogdanm 0:9b334a45a8ff 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
bogdanm 0:9b334a45a8ff 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
bogdanm 0:9b334a45a8ff 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
bogdanm 0:9b334a45a8ff 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
bogdanm 0:9b334a45a8ff 778 /**************** Bit definition for CRG_RTC_SSR **************************/
bogdanm 0:9b334a45a8ff 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
bogdanm 0:9b334a45a8ff 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
bogdanm 0:9b334a45a8ff 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
bogdanm 0:9b334a45a8ff 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
bogdanm 0:9b334a45a8ff 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
bogdanm 0:9b334a45a8ff 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
bogdanm 0:9b334a45a8ff 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
bogdanm 0:9b334a45a8ff 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
bogdanm 0:9b334a45a8ff 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
bogdanm 0:9b334a45a8ff 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
bogdanm 0:9b334a45a8ff 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
bogdanm 0:9b334a45a8ff 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
bogdanm 0:9b334a45a8ff 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
bogdanm 0:9b334a45a8ff 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
bogdanm 0:9b334a45a8ff 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
bogdanm 0:9b334a45a8ff 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
bogdanm 0:9b334a45a8ff 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
bogdanm 0:9b334a45a8ff 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
bogdanm 0:9b334a45a8ff 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
bogdanm 0:9b334a45a8ff 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
bogdanm 0:9b334a45a8ff 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
bogdanm 0:9b334a45a8ff 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
bogdanm 0:9b334a45a8ff 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
bogdanm 0:9b334a45a8ff 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
bogdanm 0:9b334a45a8ff 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
bogdanm 0:9b334a45a8ff 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
bogdanm 0:9b334a45a8ff 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
bogdanm 0:9b334a45a8ff 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
bogdanm 0:9b334a45a8ff 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
bogdanm 0:9b334a45a8ff 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
bogdanm 0:9b334a45a8ff 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
bogdanm 0:9b334a45a8ff 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
bogdanm 0:9b334a45a8ff 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
bogdanm 0:9b334a45a8ff 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
bogdanm 0:9b334a45a8ff 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
bogdanm 0:9b334a45a8ff 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
bogdanm 0:9b334a45a8ff 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
bogdanm 0:9b334a45a8ff 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
bogdanm 0:9b334a45a8ff 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
bogdanm 0:9b334a45a8ff 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
bogdanm 0:9b334a45a8ff 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /******************************************************************************/
bogdanm 0:9b334a45a8ff 834 /* */
bogdanm 0:9b334a45a8ff 835 /* UART */
bogdanm 0:9b334a45a8ff 836 /* */
bogdanm 0:9b334a45a8ff 837 /******************************************************************************/
bogdanm 0:9b334a45a8ff 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
bogdanm 0:9b334a45a8ff 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
bogdanm 0:9b334a45a8ff 840 #define UART_DR_BE (0x01ul << 10) // Break Error
bogdanm 0:9b334a45a8ff 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
bogdanm 0:9b334a45a8ff 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
bogdanm 0:9b334a45a8ff 843 //#define UART_DR_DR // ToDo
bogdanm 0:9b334a45a8ff 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
bogdanm 0:9b334a45a8ff 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
bogdanm 0:9b334a45a8ff 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
bogdanm 0:9b334a45a8ff 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
bogdanm 0:9b334a45a8ff 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
bogdanm 0:9b334a45a8ff 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
bogdanm 0:9b334a45a8ff 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
bogdanm 0:9b334a45a8ff 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
bogdanm 0:9b334a45a8ff 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
bogdanm 0:9b334a45a8ff 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
bogdanm 0:9b334a45a8ff 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
bogdanm 0:9b334a45a8ff 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
bogdanm 0:9b334a45a8ff 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
bogdanm 0:9b334a45a8ff 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
bogdanm 0:9b334a45a8ff 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
bogdanm 0:9b334a45a8ff 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
bogdanm 0:9b334a45a8ff 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
bogdanm 0:9b334a45a8ff 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
bogdanm 0:9b334a45a8ff 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
bogdanm 0:9b334a45a8ff 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
bogdanm 0:9b334a45a8ff 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
bogdanm 0:9b334a45a8ff 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
bogdanm 0:9b334a45a8ff 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
bogdanm 0:9b334a45a8ff 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
bogdanm 0:9b334a45a8ff 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
bogdanm 0:9b334a45a8ff 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
bogdanm 0:9b334a45a8ff 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
bogdanm 0:9b334a45a8ff 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
bogdanm 0:9b334a45a8ff 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
bogdanm 0:9b334a45a8ff 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
bogdanm 0:9b334a45a8ff 874 /********************* Bit definition for Contro(UARTCR) register *************************/
bogdanm 0:9b334a45a8ff 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
bogdanm 0:9b334a45a8ff 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
bogdanm 0:9b334a45a8ff 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
bogdanm 0:9b334a45a8ff 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
bogdanm 0:9b334a45a8ff 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
bogdanm 0:9b334a45a8ff 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
bogdanm 0:9b334a45a8ff 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
bogdanm 0:9b334a45a8ff 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
bogdanm 0:9b334a45a8ff 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
bogdanm 0:9b334a45a8ff 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
bogdanm 0:9b334a45a8ff 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
bogdanm 0:9b334a45a8ff 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
bogdanm 0:9b334a45a8ff 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
bogdanm 0:9b334a45a8ff 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
bogdanm 0:9b334a45a8ff 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
bogdanm 0:9b334a45a8ff 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
bogdanm 0:9b334a45a8ff 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
bogdanm 0:9b334a45a8ff 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
bogdanm 0:9b334a45a8ff 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
bogdanm 0:9b334a45a8ff 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
bogdanm 0:9b334a45a8ff 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
bogdanm 0:9b334a45a8ff 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
bogdanm 0:9b334a45a8ff 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
bogdanm 0:9b334a45a8ff 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
bogdanm 0:9b334a45a8ff 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
bogdanm 0:9b334a45a8ff 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
bogdanm 0:9b334a45a8ff 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
bogdanm 0:9b334a45a8ff 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
bogdanm 0:9b334a45a8ff 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
bogdanm 0:9b334a45a8ff 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
bogdanm 0:9b334a45a8ff 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
bogdanm 0:9b334a45a8ff 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
bogdanm 0:9b334a45a8ff 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
bogdanm 0:9b334a45a8ff 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
bogdanm 0:9b334a45a8ff 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
bogdanm 0:9b334a45a8ff 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
bogdanm 0:9b334a45a8ff 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
bogdanm 0:9b334a45a8ff 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
bogdanm 0:9b334a45a8ff 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
bogdanm 0:9b334a45a8ff 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
bogdanm 0:9b334a45a8ff 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
bogdanm 0:9b334a45a8ff 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
bogdanm 0:9b334a45a8ff 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
bogdanm 0:9b334a45a8ff 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
bogdanm 0:9b334a45a8ff 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
bogdanm 0:9b334a45a8ff 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
bogdanm 0:9b334a45a8ff 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
bogdanm 0:9b334a45a8ff 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
bogdanm 0:9b334a45a8ff 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
bogdanm 0:9b334a45a8ff 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
bogdanm 0:9b334a45a8ff 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
bogdanm 0:9b334a45a8ff 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
bogdanm 0:9b334a45a8ff 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
bogdanm 0:9b334a45a8ff 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
bogdanm 0:9b334a45a8ff 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
bogdanm 0:9b334a45a8ff 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
bogdanm 0:9b334a45a8ff 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
bogdanm 0:9b334a45a8ff 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
bogdanm 0:9b334a45a8ff 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
bogdanm 0:9b334a45a8ff 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
bogdanm 0:9b334a45a8ff 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
bogdanm 0:9b334a45a8ff 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
bogdanm 0:9b334a45a8ff 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
bogdanm 0:9b334a45a8ff 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
bogdanm 0:9b334a45a8ff 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
bogdanm 0:9b334a45a8ff 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
bogdanm 0:9b334a45a8ff 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
bogdanm 0:9b334a45a8ff 942
bogdanm 0:9b334a45a8ff 943 /******************************************************************************/
bogdanm 0:9b334a45a8ff 944 /* */
bogdanm 0:9b334a45a8ff 945 /* Simple UART */
bogdanm 0:9b334a45a8ff 946 /* */
bogdanm 0:9b334a45a8ff 947 /******************************************************************************/
bogdanm 0:9b334a45a8ff 948 /***************** Bit definition for S_UART Data () register ************************/
bogdanm 0:9b334a45a8ff 949 #define S_UART_DATA (0xFFul << 0)
bogdanm 0:9b334a45a8ff 950 /***************** Bit definition for S_UART State() register ************************/
bogdanm 0:9b334a45a8ff 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
bogdanm 0:9b334a45a8ff 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
bogdanm 0:9b334a45a8ff 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
bogdanm 0:9b334a45a8ff 954 /***************** Bit definition for S_UART Control() register ************************/
bogdanm 0:9b334a45a8ff 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
bogdanm 0:9b334a45a8ff 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
bogdanm 0:9b334a45a8ff 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
bogdanm 0:9b334a45a8ff 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
bogdanm 0:9b334a45a8ff 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
bogdanm 0:9b334a45a8ff 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
bogdanm 0:9b334a45a8ff 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
bogdanm 0:9b334a45a8ff 962 /***************** Bit definition for S_UART Interrupt() register ************************/
bogdanm 0:9b334a45a8ff 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
bogdanm 0:9b334a45a8ff 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
bogdanm 0:9b334a45a8ff 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
bogdanm 0:9b334a45a8ff 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
bogdanm 0:9b334a45a8ff 967
bogdanm 0:9b334a45a8ff 968 /******************************************************************************/
bogdanm 0:9b334a45a8ff 969 /* */
bogdanm 0:9b334a45a8ff 970 /* Analog Digital Register */
bogdanm 0:9b334a45a8ff 971 /* */
bogdanm 0:9b334a45a8ff 972 /******************************************************************************/
bogdanm 0:9b334a45a8ff 973
bogdanm 0:9b334a45a8ff 974 /*********************** Bit definition for ADC_CTR ***********************/
bogdanm 0:9b334a45a8ff 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
bogdanm 0:9b334a45a8ff 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
bogdanm 0:9b334a45a8ff 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
bogdanm 0:9b334a45a8ff 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
bogdanm 0:9b334a45a8ff 979 /*********************** Bit definition for ADC_CHSEL ***********************/
bogdanm 0:9b334a45a8ff 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
bogdanm 0:9b334a45a8ff 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
bogdanm 0:9b334a45a8ff 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
bogdanm 0:9b334a45a8ff 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
bogdanm 0:9b334a45a8ff 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
bogdanm 0:9b334a45a8ff 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
bogdanm 0:9b334a45a8ff 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
bogdanm 0:9b334a45a8ff 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
bogdanm 0:9b334a45a8ff 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
bogdanm 0:9b334a45a8ff 989 /*********************** Bit definition for ADC_START ***********************/
bogdanm 0:9b334a45a8ff 990 #define ADC_START_START (0x1ul) // ADC conversion start
bogdanm 0:9b334a45a8ff 991 /*********************** Bit definition for ADC_DATA ***********************/
bogdanm 0:9b334a45a8ff 992 //ToDo (Readonly)
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /*********************** Bit definition for ADC_INT ***********************/
bogdanm 0:9b334a45a8ff 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
bogdanm 0:9b334a45a8ff 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
bogdanm 0:9b334a45a8ff 997 //ToDo (Readonly)
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 /*********************** Bit definition for ADC_INTCLR ***********************/
bogdanm 0:9b334a45a8ff 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
bogdanm 0:9b334a45a8ff 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
bogdanm 0:9b334a45a8ff 1004
bogdanm 0:9b334a45a8ff 1005 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1006 /* */
bogdanm 0:9b334a45a8ff 1007 /* Dual Timer */
bogdanm 0:9b334a45a8ff 1008 /* */
bogdanm 0:9b334a45a8ff 1009 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1010
bogdanm 0:9b334a45a8ff 1011 /*********************** Bit definition for dualtimer ***********************/
bogdanm 0:9b334a45a8ff 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
bogdanm 0:9b334a45a8ff 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
bogdanm 0:9b334a45a8ff 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
bogdanm 0:9b334a45a8ff 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
bogdanm 0:9b334a45a8ff 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
bogdanm 0:9b334a45a8ff 1019
bogdanm 0:9b334a45a8ff 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
bogdanm 0:9b334a45a8ff 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
bogdanm 0:9b334a45a8ff 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
bogdanm 0:9b334a45a8ff 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
bogdanm 0:9b334a45a8ff 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
bogdanm 0:9b334a45a8ff 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
bogdanm 0:9b334a45a8ff 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
bogdanm 0:9b334a45a8ff 1031 #define DUALTIMER_TimerControl_Size_Pos 1
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
bogdanm 0:9b334a45a8ff 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
bogdanm 0:9b334a45a8ff 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1038 /* */
bogdanm 0:9b334a45a8ff 1039 /* External Interrupt */
bogdanm 0:9b334a45a8ff 1040 /* */
bogdanm 0:9b334a45a8ff 1041 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1042
bogdanm 0:9b334a45a8ff 1043 /**************** Bit definition for Px_IER **************************/
bogdanm 0:9b334a45a8ff 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
bogdanm 0:9b334a45a8ff 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
bogdanm 0:9b334a45a8ff 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
bogdanm 0:9b334a45a8ff 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1050 /* */
bogdanm 0:9b334a45a8ff 1051 /* GPIO */
bogdanm 0:9b334a45a8ff 1052 /* */
bogdanm 0:9b334a45a8ff 1053 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /**************** Bit definition for Px_AFSR **************************/
bogdanm 0:9b334a45a8ff 1056 #define Px_AFSR_AF0 (0x00ul)
bogdanm 0:9b334a45a8ff 1057 #define Px_AFSR_AF1 (0x01ul)
bogdanm 0:9b334a45a8ff 1058 #define Px_AFSR_AF2 (0x02ul)
bogdanm 0:9b334a45a8ff 1059 #define Px_AFSR_AF3 (0x03ul)
bogdanm 0:9b334a45a8ff 1060 /**************** Bit definition for Px_PCR **************************/
bogdanm 0:9b334a45a8ff 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
bogdanm 0:9b334a45a8ff 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
bogdanm 0:9b334a45a8ff 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
bogdanm 0:9b334a45a8ff 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
bogdanm 0:9b334a45a8ff 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
bogdanm 0:9b334a45a8ff 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1069 /* */
bogdanm 0:9b334a45a8ff 1070 /* I2C */
bogdanm 0:9b334a45a8ff 1071 /* */
bogdanm 0:9b334a45a8ff 1072 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /**************** Bit definition for I2C_CTR **************************/
bogdanm 0:9b334a45a8ff 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
bogdanm 0:9b334a45a8ff 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
bogdanm 0:9b334a45a8ff 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
bogdanm 0:9b334a45a8ff 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
bogdanm 0:9b334a45a8ff 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
bogdanm 0:9b334a45a8ff 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 /**************** Bit definition for I2C_CMDR **************************/
bogdanm 0:9b334a45a8ff 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
bogdanm 0:9b334a45a8ff 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
bogdanm 0:9b334a45a8ff 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
bogdanm 0:9b334a45a8ff 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /**************** Bit definition for I2C_ISCR **************************/
bogdanm 0:9b334a45a8ff 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
bogdanm 0:9b334a45a8ff 1090
bogdanm 0:9b334a45a8ff 1091 /**************** Bit definition for I2C_SR **************************/
bogdanm 0:9b334a45a8ff 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
bogdanm 0:9b334a45a8ff 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
bogdanm 0:9b334a45a8ff 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
bogdanm 0:9b334a45a8ff 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
bogdanm 0:9b334a45a8ff 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
bogdanm 0:9b334a45a8ff 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
bogdanm 0:9b334a45a8ff 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
bogdanm 0:9b334a45a8ff 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
bogdanm 0:9b334a45a8ff 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
bogdanm 0:9b334a45a8ff 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 /**************** Bit definition for I2C_ISR **************************/
bogdanm 0:9b334a45a8ff 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
bogdanm 0:9b334a45a8ff 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
bogdanm 0:9b334a45a8ff 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
bogdanm 0:9b334a45a8ff 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
bogdanm 0:9b334a45a8ff 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
bogdanm 0:9b334a45a8ff 1109
bogdanm 0:9b334a45a8ff 1110 /**************** Bit definition for I2C_ISMR **************************/
bogdanm 0:9b334a45a8ff 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
bogdanm 0:9b334a45a8ff 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
bogdanm 0:9b334a45a8ff 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
bogdanm 0:9b334a45a8ff 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
bogdanm 0:9b334a45a8ff 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1118 /* */
bogdanm 0:9b334a45a8ff 1119 /* PWM */
bogdanm 0:9b334a45a8ff 1120 /* */
bogdanm 0:9b334a45a8ff 1121 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1124 /* */
bogdanm 0:9b334a45a8ff 1125 /* Random number generator Register */
bogdanm 0:9b334a45a8ff 1126 /* */
bogdanm 0:9b334a45a8ff 1127 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1128
bogdanm 0:9b334a45a8ff 1129 /*********************** Bit definition for RNG_RUN ***********************/
bogdanm 0:9b334a45a8ff 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
bogdanm 0:9b334a45a8ff 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
bogdanm 0:9b334a45a8ff 1132 /*********************** Bit definition for RNG_SEED ***********************/
bogdanm 0:9b334a45a8ff 1133 //ToDo
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
bogdanm 0:9b334a45a8ff 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
bogdanm 0:9b334a45a8ff 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
bogdanm 0:9b334a45a8ff 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
bogdanm 0:9b334a45a8ff 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
bogdanm 0:9b334a45a8ff 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
bogdanm 0:9b334a45a8ff 1141 /*********************** Bit definition for RNG_RN ***********************/
bogdanm 0:9b334a45a8ff 1142 //ToDo
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 /*********************** Bit definition for RNG_POLY ***********************/
bogdanm 0:9b334a45a8ff 1145 //ToDo
bogdanm 0:9b334a45a8ff 1146
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148
bogdanm 0:9b334a45a8ff 1149 typedef enum
bogdanm 0:9b334a45a8ff 1150 {
bogdanm 0:9b334a45a8ff 1151 PAD_PA = 0,
bogdanm 0:9b334a45a8ff 1152 PAD_PB,
bogdanm 0:9b334a45a8ff 1153 PAD_PC,
bogdanm 0:9b334a45a8ff 1154 PAD_PD
bogdanm 0:9b334a45a8ff 1155 }PAD_Type;
bogdanm 0:9b334a45a8ff 1156
bogdanm 0:9b334a45a8ff 1157 typedef enum
bogdanm 0:9b334a45a8ff 1158 {
bogdanm 0:9b334a45a8ff 1159 PAD_AF0 = Px_AFSR_AF0,
bogdanm 0:9b334a45a8ff 1160 PAD_AF1 = Px_AFSR_AF1,
bogdanm 0:9b334a45a8ff 1161 PAD_AF2 = Px_AFSR_AF2,
bogdanm 0:9b334a45a8ff 1162 PAD_AF3 = Px_AFSR_AF3
bogdanm 0:9b334a45a8ff 1163 }PAD_AF_TypeDef;
bogdanm 0:9b334a45a8ff 1164
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 #if !defined (USE_HAL_DRIVER)
bogdanm 0:9b334a45a8ff 1167 #define USE_HAL_DRIVER
bogdanm 0:9b334a45a8ff 1168 #endif /* USE_HAL_DRIVER */
bogdanm 0:9b334a45a8ff 1169
bogdanm 0:9b334a45a8ff 1170
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 #if defined (USE_HAL_DRIVER)
bogdanm 0:9b334a45a8ff 1173 // #include "system_W7500x.h"
bogdanm 0:9b334a45a8ff 1174 // #include "W7500x_conf.h"
bogdanm 0:9b334a45a8ff 1175 #endif
bogdanm 0:9b334a45a8ff 1176
bogdanm 0:9b334a45a8ff 1177 #ifdef USE_FULL_ASSERT
bogdanm 0:9b334a45a8ff 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
bogdanm 0:9b334a45a8ff 1179 #else
bogdanm 0:9b334a45a8ff 1180 #define assert_param(expr) ((void)0)
bogdanm 0:9b334a45a8ff 1181 #endif /* USE_FULL_ASSERT */
bogdanm 0:9b334a45a8ff 1182
bogdanm 0:9b334a45a8ff 1183 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1184 }
bogdanm 0:9b334a45a8ff 1185 #endif
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 #endif /* W7500x_H */
bogdanm 0:9b334a45a8ff 1188
bogdanm 0:9b334a45a8ff 1189
bogdanm 0:9b334a45a8ff 1190
bogdanm 0:9b334a45a8ff 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/