Yu Jiaqi / Mbed OS API_2x_ECO

TEST_CODE_ApplyTo2V1_API

Dependencies:   SDFileSystem max32630fthr USBDevice

DUT_RegConfig.cpp@3:35b05d91568d, 2020-06-22 (annotated)

Committer:
china_sn0w
Date:
Mon Jun 22 05:27:48 2020 +0000
Revision:
3:35b05d91568d
Parent:
1:7530b7eb757a
Child:
4:217334c3a5b2
1.2Alpha;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
china_sn0w 1:7530b7eb757a 1 #include "mbed.h"
china_sn0w 1:7530b7eb757a 2 #include "cmsis_os.h"
china_sn0w 1:7530b7eb757a 3 #include "max32630fthr.h"
china_sn0w 1:7530b7eb757a 4 #include "USBSerial.h"
china_sn0w 1:7530b7eb757a 5 #include "CmdHandler.h"
china_sn0w 1:7530b7eb757a 6 #include "DUT_RegConfig.h"
china_sn0w 1:7530b7eb757a 7 #include "ServoRun.h"
china_sn0w 1:7530b7eb757a 8 #include "SDFileSystem.h"
china_sn0w 1:7530b7eb757a 9 #include "Firmware.h"
china_sn0w 1:7530b7eb757a 10 #include "RegTable.h"
china_sn0w 1:7530b7eb757a 11 #include "CmdHandler.h"
china_sn0w 1:7530b7eb757a 12
china_sn0w 1:7530b7eb757a 13 DUTREG dut_reg[DUT_REG_NUM];
china_sn0w 1:7530b7eb757a 14 uint8_t Firmware[8192];
china_sn0w 1:7530b7eb757a 15 uint8_t histogram[10][1024];
china_sn0w 1:7530b7eb757a 16 uint8_t dcr_matrix[17][9*2];
china_sn0w 1:7530b7eb757a 17
china_sn0w 1:7530b7eb757a 18 uint8_t int_mark = 0;
china_sn0w 1:7530b7eb757a 19 uint8_t int_enable = 1;
china_sn0w 1:7530b7eb757a 20 uint8_t histogram_mode = 0;
china_sn0w 1:7530b7eb757a 21 uint8_t histogram_tdc = 0;
china_sn0w 1:7530b7eb757a 22
china_sn0w 1:7530b7eb757a 23 Semaphore chip_int_semph(1);
china_sn0w 1:7530b7eb757a 24 extern DigitalOut xSHUT;
china_sn0w 1:7530b7eb757a 25 extern I2C i2c_v;
china_sn0w 3:35b05d91568d 26 extern DigitalOut TRIM_EN;
china_sn0w 1:7530b7eb757a 27
china_sn0w 1:7530b7eb757a 28 uint16_t histogram_pos_num = 0;
china_sn0w 1:7530b7eb757a 29 uint16_t histogram_per_pos = 0;
china_sn0w 1:7530b7eb757a 30
china_sn0w 3:35b05d91568d 31 uint16_t range_step_num = 0;
china_sn0w 3:35b05d91568d 32 uint16_t range_per_step = 0;
china_sn0w 3:35b05d91568d 33
china_sn0w 1:7530b7eb757a 34 extern const uint8_t reg_table[];
china_sn0w 1:7530b7eb757a 35 extern const uint8_t Firmware_Ranging[];
china_sn0w 1:7530b7eb757a 36 extern uint8_t _uart_send_pbuff[CMD_BUF_LEN] ;
china_sn0w 1:7530b7eb757a 37
china_sn0w 1:7530b7eb757a 38 void ChipInitReset(void)
china_sn0w 1:7530b7eb757a 39 {
china_sn0w 1:7530b7eb757a 40 xSHUT = 0;
china_sn0w 1:7530b7eb757a 41 wait_ms(30);
china_sn0w 1:7530b7eb757a 42 xSHUT = 1;
china_sn0w 3:35b05d91568d 43 wait_ms(30);
china_sn0w 1:7530b7eb757a 44 }
china_sn0w 1:7530b7eb757a 45
china_sn0w 3:35b05d91568d 46 void SetBitThree(uint8_t rco, uint8_t tdc, uint8_t dcr)
china_sn0w 3:35b05d91568d 47 {
china_sn0w 3:35b05d91568d 48 WriteOneReg(0x37, rco);
china_sn0w 3:35b05d91568d 49 WriteOneReg(0xE4, tdc);
china_sn0w 3:35b05d91568d 50 WriteOneReg(0xC0, dcr);
china_sn0w 3:35b05d91568d 51 }
china_sn0w 3:35b05d91568d 52
china_sn0w 3:35b05d91568d 53 void DUT_RegInit(uint8_t rco, uint8_t tdc, uint8_t dcr)
china_sn0w 1:7530b7eb757a 54 {
china_sn0w 1:7530b7eb757a 55 LoadRegTable();
china_sn0w 3:35b05d91568d 56 for(uint16_t i = 0; i < 256; i++)
china_sn0w 3:35b05d91568d 57 {
china_sn0w 3:35b05d91568d 58 WriteOneReg(dut_reg[i].addr, dut_reg[i].value);
china_sn0w 1:7530b7eb757a 59 }
china_sn0w 3:35b05d91568d 60
china_sn0w 3:35b05d91568d 61 SetBitThree(rco, tdc, dcr);
china_sn0w 1:7530b7eb757a 62 }
china_sn0w 1:7530b7eb757a 63
china_sn0w 1:7530b7eb757a 64 void DUT_FirmwareInit(void)
china_sn0w 1:7530b7eb757a 65 {
china_sn0w 1:7530b7eb757a 66 WriteFW(LoadFirmware());
china_sn0w 1:7530b7eb757a 67 }
china_sn0w 1:7530b7eb757a 68
china_sn0w 3:35b05d91568d 69 void DeviceAllInit(uint8_t rco, uint8_t tdc, uint8_t dcr)
china_sn0w 3:35b05d91568d 70 {
china_sn0w 3:35b05d91568d 71 ChipInitReset();
china_sn0w 3:35b05d91568d 72 wait_ms(100);
china_sn0w 3:35b05d91568d 73 DUT_RegInit(rco, tdc, dcr);
china_sn0w 3:35b05d91568d 74 wait_ms(100);
china_sn0w 3:35b05d91568d 75 DUT_FirmwareInit();
china_sn0w 3:35b05d91568d 76 wait_ms(100);
china_sn0w 3:35b05d91568d 77 }
china_sn0w 3:35b05d91568d 78
china_sn0w 1:7530b7eb757a 79 void Enable_DUT_Interrupt(void)
china_sn0w 1:7530b7eb757a 80 {
china_sn0w 1:7530b7eb757a 81 int_enable = 1;
china_sn0w 1:7530b7eb757a 82 }
china_sn0w 1:7530b7eb757a 83
china_sn0w 1:7530b7eb757a 84 void Disable_DUT_Interrupt(void)
china_sn0w 1:7530b7eb757a 85 {
china_sn0w 1:7530b7eb757a 86 int_enable = 0;
china_sn0w 1:7530b7eb757a 87 }
china_sn0w 1:7530b7eb757a 88
china_sn0w 1:7530b7eb757a 89 void InterruptHandle(void)
china_sn0w 1:7530b7eb757a 90 {
china_sn0w 1:7530b7eb757a 91 if(int_enable == 0)
china_sn0w 1:7530b7eb757a 92 return;
china_sn0w 1:7530b7eb757a 93
china_sn0w 1:7530b7eb757a 94 if(int_mark == 1) {
china_sn0w 1:7530b7eb757a 95 int_mark = 0;
china_sn0w 1:7530b7eb757a 96 } else if(int_mark == 2) {
china_sn0w 1:7530b7eb757a 97 chip_int_semph.release();
china_sn0w 1:7530b7eb757a 98 //发送信号量
china_sn0w 1:7530b7eb757a 99 }
china_sn0w 1:7530b7eb757a 100 }
china_sn0w 1:7530b7eb757a 101
china_sn0w 3:35b05d91568d 102
china_sn0w 3:35b05d91568d 103
china_sn0w 1:7530b7eb757a 104 void HistogramReport()
china_sn0w 1:7530b7eb757a 105 {
china_sn0w 1:7530b7eb757a 106 uint8_t ret = 0;
china_sn0w 3:35b05d91568d 107 uint16_t lsb, mili, noise_level;
china_sn0w 3:35b05d91568d 108 uint32_t peak;
china_sn0w 1:7530b7eb757a 109
china_sn0w 1:7530b7eb757a 110
china_sn0w 1:7530b7eb757a 111 uint16_t histogram_pos = 0;
china_sn0w 1:7530b7eb757a 112 uint16_t histogram_num = 0;
china_sn0w 3:35b05d91568d 113 uint16_t range_step = 0;
china_sn0w 1:7530b7eb757a 114 while(1) {
china_sn0w 1:7530b7eb757a 115 if(histogram_mode == 1) {
china_sn0w 1:7530b7eb757a 116 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 117 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 3:35b05d91568d 118 ret = OneTimeMeasure(&lsb, &mili, &peak, &noise_level);
china_sn0w 1:7530b7eb757a 119 if(ret != 0) {
china_sn0w 1:7530b7eb757a 120 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 121 } else {
china_sn0w 1:7530b7eb757a 122 ret = vangogh_ram_rd(histogram_tdc);
china_sn0w 1:7530b7eb757a 123 if(ret != 0) {
china_sn0w 1:7530b7eb757a 124 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 125 } else {
china_sn0w 1:7530b7eb757a 126 HandleReadHistogram(histogram_tdc);
china_sn0w 1:7530b7eb757a 127 }
china_sn0w 1:7530b7eb757a 128 }
china_sn0w 1:7530b7eb757a 129 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 130 } else if(histogram_mode == 2) {
china_sn0w 1:7530b7eb757a 131 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 132 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 3:35b05d91568d 133 ret = OneTimeMeasure(&lsb, &mili, &peak, &noise_level);
china_sn0w 1:7530b7eb757a 134 if(ret != 0) {
china_sn0w 1:7530b7eb757a 135 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 136 } else {
china_sn0w 1:7530b7eb757a 137 for(uint8_t i = 0; i < 10; i++) {
china_sn0w 1:7530b7eb757a 138 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 139 if(ret != 0) {
china_sn0w 1:7530b7eb757a 140 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 141 break;
china_sn0w 1:7530b7eb757a 142 } else {
china_sn0w 1:7530b7eb757a 143 HandleReadHistogram(i);
china_sn0w 1:7530b7eb757a 144 wait_ms(1);
china_sn0w 1:7530b7eb757a 145 }
china_sn0w 1:7530b7eb757a 146 }
china_sn0w 1:7530b7eb757a 147 }
china_sn0w 1:7530b7eb757a 148 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 149 } else if(histogram_mode == 3) {
china_sn0w 1:7530b7eb757a 150
china_sn0w 1:7530b7eb757a 151
china_sn0w 1:7530b7eb757a 152 if(histogram_num >= histogram_per_pos) {
china_sn0w 1:7530b7eb757a 153 histogram_num = 0;
china_sn0w 1:7530b7eb757a 154 histogram_pos++;
china_sn0w 1:7530b7eb757a 155 if(histogram_pos >= histogram_pos_num) {
china_sn0w 1:7530b7eb757a 156 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 157 }
china_sn0w 1:7530b7eb757a 158 ServoRun(1, 10);
china_sn0w 1:7530b7eb757a 159 while(CheckUntil()) wait_ms(100);
china_sn0w 1:7530b7eb757a 160 }
china_sn0w 1:7530b7eb757a 161 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 162 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 3:35b05d91568d 163 ret = OneTimeMeasure(&lsb, &mili, &peak, &noise_level);
china_sn0w 1:7530b7eb757a 164 if(ret != 0) {
china_sn0w 1:7530b7eb757a 165 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 166 } else {
china_sn0w 1:7530b7eb757a 167 for(uint8_t i = 0; i < 10; i++) {
china_sn0w 1:7530b7eb757a 168 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 169 if(ret != 0) {
china_sn0w 1:7530b7eb757a 170 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 171 break;
china_sn0w 1:7530b7eb757a 172 } else {
china_sn0w 1:7530b7eb757a 173 StoreHistogram(histogram_pos, histogram_num, i);
china_sn0w 1:7530b7eb757a 174 wait_ms(100);
china_sn0w 1:7530b7eb757a 175 }
china_sn0w 1:7530b7eb757a 176 }
china_sn0w 1:7530b7eb757a 177 }
china_sn0w 1:7530b7eb757a 178 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 179 histogram_num++;
china_sn0w 1:7530b7eb757a 180 } else if(histogram_mode == 4) {
china_sn0w 1:7530b7eb757a 181 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 182 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 3:35b05d91568d 183 ret = OneTimeMeasure(&lsb, &mili, &peak, &noise_level);
china_sn0w 1:7530b7eb757a 184 if(ret != 0) {
china_sn0w 1:7530b7eb757a 185 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 186 } else {
china_sn0w 1:7530b7eb757a 187 for(uint8_t i = 0; i < 9; i++) {
china_sn0w 1:7530b7eb757a 188 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 189 if(ret != 0) {
china_sn0w 1:7530b7eb757a 190 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 191 break;
china_sn0w 1:7530b7eb757a 192 } else {
china_sn0w 1:7530b7eb757a 193 HandleReadHistogram(i);
china_sn0w 1:7530b7eb757a 194 wait_ms(1);
china_sn0w 1:7530b7eb757a 195 }
china_sn0w 1:7530b7eb757a 196 }
china_sn0w 1:7530b7eb757a 197 }
china_sn0w 1:7530b7eb757a 198 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 3:35b05d91568d 199 } else if(histogram_mode == 5) {
china_sn0w 3:35b05d91568d 200
china_sn0w 3:35b05d91568d 201 if(range_per_step == 0) {
china_sn0w 3:35b05d91568d 202 range_step++;
china_sn0w 3:35b05d91568d 203 if(range_step >= range_step_num) {
china_sn0w 3:35b05d91568d 204 histogram_mode = 0;
china_sn0w 3:35b05d91568d 205 }
china_sn0w 3:35b05d91568d 206 ServoRun(1, 10);
china_sn0w 3:35b05d91568d 207 while(CheckUntil()) wait_ms(100);
china_sn0w 3:35b05d91568d 208
china_sn0w 3:35b05d91568d 209 range_per_step = 0;
china_sn0w 3:35b05d91568d 210 ret = ContinuousMeasure();
china_sn0w 3:35b05d91568d 211 if(ret != 0) {
china_sn0w 3:35b05d91568d 212 histogram_mode = 0;
china_sn0w 3:35b05d91568d 213 } else {
china_sn0w 3:35b05d91568d 214 while(range_per_step<256 && histogram_mode == 5) {
china_sn0w 3:35b05d91568d 215 wait_ms(100);
china_sn0w 3:35b05d91568d 216 }
china_sn0w 3:35b05d91568d 217 StoreHistogram(range_step, 0, 0);
china_sn0w 3:35b05d91568d 218 wait_ms(5);
china_sn0w 3:35b05d91568d 219 StoreHistogram(range_step, 0, 1);
china_sn0w 3:35b05d91568d 220 wait_ms(5);
china_sn0w 3:35b05d91568d 221 StoreHistogram(range_step, 0, 2);
china_sn0w 3:35b05d91568d 222 wait_ms(5);
china_sn0w 3:35b05d91568d 223 StoreHistogram(range_step, 0, 3);
china_sn0w 3:35b05d91568d 224 wait_ms(5);
china_sn0w 3:35b05d91568d 225 range_per_step = 0;
china_sn0w 3:35b05d91568d 226
china_sn0w 3:35b05d91568d 227 }
china_sn0w 3:35b05d91568d 228 }
china_sn0w 3:35b05d91568d 229
china_sn0w 3:35b05d91568d 230
china_sn0w 3:35b05d91568d 231
china_sn0w 3:35b05d91568d 232 } else {
china_sn0w 1:7530b7eb757a 233 histogram_num = 0;
china_sn0w 1:7530b7eb757a 234 histogram_pos = 0;
china_sn0w 3:35b05d91568d 235 range_step = 0;
china_sn0w 1:7530b7eb757a 236 histogram_pos_num = 0;
china_sn0w 1:7530b7eb757a 237 histogram_per_pos = 0;
china_sn0w 1:7530b7eb757a 238 }
china_sn0w 1:7530b7eb757a 239 wait(1);
china_sn0w 1:7530b7eb757a 240 }
china_sn0w 1:7530b7eb757a 241 }
china_sn0w 1:7530b7eb757a 242
china_sn0w 3:35b05d91568d 243 void StoreMeasureData(uint16_t lsb, uint16_t milimeter, uint32_t peak, uint16_t noise_level, uint16_t i)
china_sn0w 3:35b05d91568d 244 {
china_sn0w 3:35b05d91568d 245 histogram[0][4*i] = 0;
china_sn0w 3:35b05d91568d 246 histogram[0][4*i+1] = 0;
china_sn0w 3:35b05d91568d 247 histogram[0][4*i+2] = lsb >> 8;
china_sn0w 3:35b05d91568d 248 histogram[0][4*i+3] = lsb ;
china_sn0w 3:35b05d91568d 249
china_sn0w 3:35b05d91568d 250 histogram[1][4*i] = 0;
china_sn0w 3:35b05d91568d 251 histogram[1][4*i+1] = 0;
china_sn0w 3:35b05d91568d 252 histogram[1][4*i+2] = milimeter >> 8;
china_sn0w 3:35b05d91568d 253 histogram[1][4*i+3] = milimeter ;
china_sn0w 3:35b05d91568d 254
china_sn0w 3:35b05d91568d 255 histogram[2][4*i] = peak >> 24;
china_sn0w 3:35b05d91568d 256 histogram[2][4*i+1] = peak >> 16;
china_sn0w 3:35b05d91568d 257 histogram[2][4*i+2] = peak >> 8;
china_sn0w 3:35b05d91568d 258 histogram[2][4*i+3] = peak ;
china_sn0w 3:35b05d91568d 259
china_sn0w 3:35b05d91568d 260 histogram[3][4*i] = 0;
china_sn0w 3:35b05d91568d 261 histogram[3][4*i+1] = 0;
china_sn0w 3:35b05d91568d 262 histogram[3][4*i+2] = noise_level >> 8;
china_sn0w 3:35b05d91568d 263 histogram[3][4*i+3] = noise_level ;
china_sn0w 3:35b05d91568d 264
china_sn0w 3:35b05d91568d 265 }
china_sn0w 3:35b05d91568d 266
china_sn0w 1:7530b7eb757a 267 void ContinuousMeasureReport()
china_sn0w 1:7530b7eb757a 268 {
china_sn0w 3:35b05d91568d 269 uint16_t lsb, milimeter, noise_level;
china_sn0w 3:35b05d91568d 270 uint32_t peak;
china_sn0w 1:7530b7eb757a 271 uint8_t int_flag = 0;
china_sn0w 1:7530b7eb757a 272 uint16_t time_out = 0;
china_sn0w 1:7530b7eb757a 273
china_sn0w 1:7530b7eb757a 274 while(1) {
china_sn0w 1:7530b7eb757a 275
china_sn0w 1:7530b7eb757a 276 chip_int_semph.wait();
china_sn0w 3:35b05d91568d 277 if(histogram_mode == 5) {
china_sn0w 3:35b05d91568d 278 if(RaadContinuousMeasure(&lsb, &milimeter, &peak, &noise_level) == 0) {
china_sn0w 3:35b05d91568d 279 StoreMeasureData(lsb, milimeter, peak, noise_level, range_per_step++);
china_sn0w 3:35b05d91568d 280 if(range_per_step == 256) {
china_sn0w 3:35b05d91568d 281 StopContinuousMeasure();
china_sn0w 3:35b05d91568d 282 }
china_sn0w 3:35b05d91568d 283 }
china_sn0w 3:35b05d91568d 284 } else {
china_sn0w 3:35b05d91568d 285 if(RaadContinuousMeasure(&lsb, &milimeter, &peak, &noise_level) == 0) {
china_sn0w 3:35b05d91568d 286 HandleContinuousMeasureReport(lsb, milimeter, peak, noise_level);
china_sn0w 3:35b05d91568d 287 }
china_sn0w 1:7530b7eb757a 288 }
china_sn0w 1:7530b7eb757a 289
china_sn0w 1:7530b7eb757a 290 }
china_sn0w 1:7530b7eb757a 291 }
china_sn0w 1:7530b7eb757a 292
china_sn0w 1:7530b7eb757a 293 uint8_t WriteOneReg(uint8_t addr, uint8_t data)
china_sn0w 1:7530b7eb757a 294 {
china_sn0w 1:7530b7eb757a 295 uint8_t buf[2];
china_sn0w 1:7530b7eb757a 296 buf[0] = addr;
china_sn0w 1:7530b7eb757a 297 buf[1] = data;
china_sn0w 1:7530b7eb757a 298
china_sn0w 1:7530b7eb757a 299 i2c_v.write(DUT_DEV_ADDR, (char*)buf, 2);
china_sn0w 1:7530b7eb757a 300
china_sn0w 1:7530b7eb757a 301 return 0;
china_sn0w 1:7530b7eb757a 302 }
china_sn0w 1:7530b7eb757a 303
china_sn0w 1:7530b7eb757a 304 uint8_t ReadOneReg(uint8_t addr, uint8_t *data)
china_sn0w 1:7530b7eb757a 305 {
china_sn0w 1:7530b7eb757a 306 uint8_t buf[2];
china_sn0w 1:7530b7eb757a 307 buf[0] = addr;
china_sn0w 1:7530b7eb757a 308
china_sn0w 1:7530b7eb757a 309 i2c_v.write(DUT_DEV_ADDR, (char*)buf, 1);
china_sn0w 1:7530b7eb757a 310 i2c_v.read (DUT_DEV_ADDR, (char*)data, 1);
china_sn0w 1:7530b7eb757a 311
china_sn0w 1:7530b7eb757a 312 return 0;
china_sn0w 1:7530b7eb757a 313 }
china_sn0w 1:7530b7eb757a 314
china_sn0w 1:7530b7eb757a 315
china_sn0w 1:7530b7eb757a 316 uint8_t ReadAllRegToTable(void)
china_sn0w 1:7530b7eb757a 317 {
china_sn0w 1:7530b7eb757a 318 for(uint16_t i = 0; i < DUT_REG_NUM; i++) {
china_sn0w 1:7530b7eb757a 319 ReadOneReg(dut_reg[i].addr, &(dut_reg[i].value));
china_sn0w 1:7530b7eb757a 320 }
china_sn0w 1:7530b7eb757a 321
china_sn0w 1:7530b7eb757a 322 return 0;
china_sn0w 1:7530b7eb757a 323 }
china_sn0w 1:7530b7eb757a 324
china_sn0w 1:7530b7eb757a 325 uint8_t WriteFW(uint16_t size)
china_sn0w 1:7530b7eb757a 326 {
china_sn0w 1:7530b7eb757a 327 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 328 uint8_t i;
china_sn0w 1:7530b7eb757a 329 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 330 uint8_t uart_rx_data;
china_sn0w 1:7530b7eb757a 331 uint16_t fw_size = size;
china_sn0w 1:7530b7eb757a 332 uint16_t fw_send = 0;
china_sn0w 1:7530b7eb757a 333
china_sn0w 1:7530b7eb757a 334 ret = WriteOneReg(REG_PW_CTRL, 0x08);
china_sn0w 1:7530b7eb757a 335 ret = WriteOneReg(REG_PW_CTRL, 0x0a);
china_sn0w 1:7530b7eb757a 336 ret = WriteOneReg(REG_MCU_CFG, 0x02);
china_sn0w 1:7530b7eb757a 337 ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg);
china_sn0w 1:7530b7eb757a 338 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 339 ret = WriteOneReg(REG_CMD, 0x01);
china_sn0w 1:7530b7eb757a 340 ret = WriteOneReg(REG_SIZE, 0x02);
china_sn0w 1:7530b7eb757a 341 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x00, 0x00);
china_sn0w 1:7530b7eb757a 342 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x01, 0x00);
china_sn0w 1:7530b7eb757a 343
china_sn0w 1:7530b7eb757a 344 while(fw_size >= 32) {
china_sn0w 1:7530b7eb757a 345 ret = WriteOneReg(REG_CMD,0x03);
china_sn0w 1:7530b7eb757a 346 ret = WriteOneReg(REG_SIZE,0x20);
china_sn0w 1:7530b7eb757a 347 for(i=0; i<32; i++) {
china_sn0w 1:7530b7eb757a 348 uart_rx_data = Firmware[fw_send++];
china_sn0w 1:7530b7eb757a 349 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+i, uart_rx_data);
china_sn0w 1:7530b7eb757a 350 wait_us(5);
china_sn0w 1:7530b7eb757a 351 }
china_sn0w 1:7530b7eb757a 352 fw_size -= 32;
china_sn0w 1:7530b7eb757a 353 }
china_sn0w 1:7530b7eb757a 354 if(fw_size > 0) {
china_sn0w 1:7530b7eb757a 355 ret = WriteOneReg(REG_CMD,0x03);
china_sn0w 1:7530b7eb757a 356 ret = WriteOneReg(REG_SIZE,(uint8_t)fw_size);
china_sn0w 1:7530b7eb757a 357 for(i=0; i<fw_size; i++) {
china_sn0w 1:7530b7eb757a 358 uart_rx_data = Firmware[fw_send++];
china_sn0w 1:7530b7eb757a 359 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+i, uart_rx_data);
china_sn0w 1:7530b7eb757a 360 wait_us(5);
china_sn0w 1:7530b7eb757a 361 }
china_sn0w 1:7530b7eb757a 362 }
china_sn0w 1:7530b7eb757a 363 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0));
china_sn0w 1:7530b7eb757a 364 ret = WriteOneReg(REG_MCU_CFG, 0x03);
china_sn0w 1:7530b7eb757a 365 ret = WriteOneReg(REG_PW_CTRL, 0x02); //reset r_otp_ld_done, is a must
china_sn0w 1:7530b7eb757a 366 ret = WriteOneReg(REG_PW_CTRL, 0x00); //reset r_otp_ld_done, exit low power mode
china_sn0w 1:7530b7eb757a 367
china_sn0w 1:7530b7eb757a 368 return ret;
china_sn0w 1:7530b7eb757a 369 }
china_sn0w 1:7530b7eb757a 370
china_sn0w 1:7530b7eb757a 371 uint8_t vangogh_ram_rd(uint8_t tdc) //UART CMD foramt: CMD-1-byte|TDC-index-1-byte
china_sn0w 1:7530b7eb757a 372 {
china_sn0w 1:7530b7eb757a 373 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 374 uint8_t i;
china_sn0w 1:7530b7eb757a 375 uint8_t j;
china_sn0w 1:7530b7eb757a 376 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 377 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 378 uint8_t tdc_index = tdc;
china_sn0w 1:7530b7eb757a 379 uint16_t ram_addr_base = 0x1000 + 0x0400 * tdc_index;
china_sn0w 1:7530b7eb757a 380
china_sn0w 1:7530b7eb757a 381 ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 382 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 383 ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 384 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 385 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3) | (0x01<<1)); //set otp_ld_done, pw_ctrl_lp
china_sn0w 3:35b05d91568d 386 ret = WriteOneReg(REG_MCU_CFG, 0x01);
china_sn0w 1:7530b7eb757a 387 ret = WriteOneReg(REG_CMD, 0x01);
china_sn0w 1:7530b7eb757a 388 ret = WriteOneReg(REG_SIZE, 0x02);
china_sn0w 1:7530b7eb757a 389 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x00, *((uint8_t*)(&ram_addr_base) ));
china_sn0w 1:7530b7eb757a 390 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x01, *((uint8_t*)(&ram_addr_base)+1));
china_sn0w 1:7530b7eb757a 391 wait_us(100);
china_sn0w 1:7530b7eb757a 392 for(j=0; j<32; j++) {
china_sn0w 1:7530b7eb757a 393 ret = WriteOneReg(REG_CMD,0x05); //Issue RAM read command
china_sn0w 1:7530b7eb757a 394 ret = WriteOneReg(REG_SIZE,0x20); //Issue RAM read command
china_sn0w 1:7530b7eb757a 395 wait_us(100);
china_sn0w 1:7530b7eb757a 396 for(i=0; i<32; i++) {
china_sn0w 1:7530b7eb757a 397 ret = ReadOneReg(0x0c+i, &histogram[tdc_index][32*j + i]);
china_sn0w 1:7530b7eb757a 398 }
china_sn0w 1:7530b7eb757a 399 }
china_sn0w 3:35b05d91568d 400 ret = WriteOneReg(REG_MCU_CFG, 0x03);
china_sn0w 1:7530b7eb757a 401 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 402 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 3:35b05d91568d 403 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 404
china_sn0w 1:7530b7eb757a 405 return ret;
china_sn0w 1:7530b7eb757a 406 }
china_sn0w 1:7530b7eb757a 407
china_sn0w 3:35b05d91568d 408 uint8_t OneTimeMeasure(uint16_t *lsb, uint16_t *milimeter, uint32_t *peak, uint16_t *noise_level)
china_sn0w 1:7530b7eb757a 409 {
china_sn0w 1:7530b7eb757a 410 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 411 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 412 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 413 uint32_t timeout = 0;
china_sn0w 3:35b05d91568d 414 uint8_t flag = 0;
china_sn0w 1:7530b7eb757a 415
china_sn0w 1:7530b7eb757a 416 int_mark = 1;//One Time Measure
china_sn0w 1:7530b7eb757a 417
china_sn0w 1:7530b7eb757a 418 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 419 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 420 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 421 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 422 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 3:35b05d91568d 423 //ret = WriteOneReg(0x08, 0x00);
china_sn0w 1:7530b7eb757a 424 ret = WriteOneReg(REG_CMD, 0x0E);
china_sn0w 1:7530b7eb757a 425 //ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 426
china_sn0w 1:7530b7eb757a 427 timeout = 1000;
china_sn0w 1:7530b7eb757a 428 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 429 timeout--;
china_sn0w 1:7530b7eb757a 430 wait_ms(5);
china_sn0w 3:35b05d91568d 431 //ReadOneReg(0x08, &flag);
china_sn0w 3:35b05d91568d 432 // if(flag == 0xFF)
china_sn0w 3:35b05d91568d 433 //{
china_sn0w 3:35b05d91568d 434 // int_mark = 0;
china_sn0w 3:35b05d91568d 435 // }
china_sn0w 1:7530b7eb757a 436 }
china_sn0w 1:7530b7eb757a 437
china_sn0w 1:7530b7eb757a 438 if(timeout == 0) {
china_sn0w 1:7530b7eb757a 439 return 1;
china_sn0w 1:7530b7eb757a 440
china_sn0w 1:7530b7eb757a 441 } else {
china_sn0w 1:7530b7eb757a 442
china_sn0w 1:7530b7eb757a 443 ret = ReadOneReg(0x0d, (uint8_t*)lsb);
china_sn0w 1:7530b7eb757a 444 ret = ReadOneReg(0x0e, (uint8_t*)lsb + 1);
china_sn0w 1:7530b7eb757a 445
china_sn0w 1:7530b7eb757a 446 ret = ReadOneReg(0x18, (uint8_t*)milimeter);
china_sn0w 1:7530b7eb757a 447 ret = ReadOneReg(0x19, (uint8_t*)milimeter + 1);
china_sn0w 1:7530b7eb757a 448
china_sn0w 3:35b05d91568d 449 ret = ReadOneReg(0x26, (uint8_t*)noise_level);
china_sn0w 3:35b05d91568d 450 ret = ReadOneReg(0x27, (uint8_t*)noise_level + 1);
china_sn0w 3:35b05d91568d 451
china_sn0w 3:35b05d91568d 452 ret = ReadOneReg(0x28, (uint8_t*)peak );
china_sn0w 3:35b05d91568d 453 ret = ReadOneReg(0x29, (uint8_t*)peak + 1);
china_sn0w 3:35b05d91568d 454 ret = ReadOneReg(0x2a, (uint8_t*)peak + 2);
china_sn0w 3:35b05d91568d 455 ret = ReadOneReg(0x2b, (uint8_t*)peak + 3);
china_sn0w 3:35b05d91568d 456
china_sn0w 1:7530b7eb757a 457 }
china_sn0w 1:7530b7eb757a 458
china_sn0w 1:7530b7eb757a 459 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 460 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 1:7530b7eb757a 461 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl & ~(0x01<<1)); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 462
china_sn0w 1:7530b7eb757a 463 return ret;
china_sn0w 1:7530b7eb757a 464 }
china_sn0w 1:7530b7eb757a 465
china_sn0w 1:7530b7eb757a 466 uint8_t ContinuousMeasure(void)
china_sn0w 1:7530b7eb757a 467 {
china_sn0w 1:7530b7eb757a 468 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 469 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 470 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 471
china_sn0w 1:7530b7eb757a 472 int_mark = 2;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 473
china_sn0w 1:7530b7eb757a 474 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 475 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 476 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 477 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 478 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 479 ret = WriteOneReg(REG_CMD, 0x0F);
china_sn0w 1:7530b7eb757a 480 //ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 481
china_sn0w 1:7530b7eb757a 482 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 483
china_sn0w 1:7530b7eb757a 484 return ret;
china_sn0w 1:7530b7eb757a 485 }
china_sn0w 1:7530b7eb757a 486
china_sn0w 3:35b05d91568d 487 uint8_t RaadContinuousMeasure(uint16_t *lsb, uint16_t *milimeter, uint32_t *peak, uint16_t *noise_level)
china_sn0w 1:7530b7eb757a 488 {
china_sn0w 1:7530b7eb757a 489 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 490 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 491 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 492
china_sn0w 1:7530b7eb757a 493 int_mark = 2;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 494
china_sn0w 1:7530b7eb757a 495 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 496 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 497 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 498 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 499 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 500
china_sn0w 1:7530b7eb757a 501 ret = ReadOneReg(0x0d, (uint8_t*)lsb);
china_sn0w 1:7530b7eb757a 502 ret = ReadOneReg(0x0e, (uint8_t*)lsb + 1);
china_sn0w 1:7530b7eb757a 503
china_sn0w 1:7530b7eb757a 504 ret = ReadOneReg(0x18, (uint8_t*)milimeter);
china_sn0w 1:7530b7eb757a 505 ret = ReadOneReg(0x19, (uint8_t*)milimeter + 1);
china_sn0w 1:7530b7eb757a 506
china_sn0w 3:35b05d91568d 507 ret = ReadOneReg(0x26, (uint8_t*)noise_level);
china_sn0w 3:35b05d91568d 508 ret = ReadOneReg(0x27, (uint8_t*)noise_level + 1);
china_sn0w 3:35b05d91568d 509
china_sn0w 3:35b05d91568d 510 ret = ReadOneReg(0x28, (uint8_t*)peak );
china_sn0w 3:35b05d91568d 511 ret = ReadOneReg(0x29, (uint8_t*)peak + 1);
china_sn0w 3:35b05d91568d 512 ret = ReadOneReg(0x2a, (uint8_t*)peak + 2);
china_sn0w 3:35b05d91568d 513 ret = ReadOneReg(0x2b, (uint8_t*)peak + 3);
china_sn0w 3:35b05d91568d 514
china_sn0w 1:7530b7eb757a 515 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 516
china_sn0w 1:7530b7eb757a 517 return ret;
china_sn0w 1:7530b7eb757a 518 }
china_sn0w 1:7530b7eb757a 519
china_sn0w 1:7530b7eb757a 520 uint8_t StopContinuousMeasure()
china_sn0w 1:7530b7eb757a 521 {
china_sn0w 1:7530b7eb757a 522 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 523 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 524 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 525
china_sn0w 1:7530b7eb757a 526 int_mark = 0;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 527
china_sn0w 1:7530b7eb757a 528 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 529 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 530 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 531 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 532 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 533 ret = WriteOneReg(REG_CMD, 0x00);
china_sn0w 1:7530b7eb757a 534 ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 535
china_sn0w 1:7530b7eb757a 536 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 537 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 1:7530b7eb757a 538 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl & ~(0x01<<1)); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 539
china_sn0w 1:7530b7eb757a 540 return ret;
china_sn0w 1:7530b7eb757a 541 }
china_sn0w 1:7530b7eb757a 542
china_sn0w 1:7530b7eb757a 543 void StoreHistogram(uint16_t histogram_pos, uint16_t histogram_num, uint8_t tdc)
china_sn0w 1:7530b7eb757a 544 {
china_sn0w 1:7530b7eb757a 545 /*
china_sn0w 1:7530b7eb757a 546 char file_name[20];
china_sn0w 1:7530b7eb757a 547
china_sn0w 1:7530b7eb757a 548 //sprintf(file_name, "/sd/hist_%d_%d_tdc%d", histogram_pos, histogram_num, tdc);
china_sn0w 1:7530b7eb757a 549 sprintf(file_name, "/sd/hello.txt");
china_sn0w 1:7530b7eb757a 550
china_sn0w 1:7530b7eb757a 551 FILE *fp = fopen(file_name, "w");
china_sn0w 1:7530b7eb757a 552 //for(uint32_t i = 0; i < 1024; i++) {
china_sn0w 1:7530b7eb757a 553 // fseek(fp,0,SEEK_END);
china_sn0w 1:7530b7eb757a 554 // fprintf(fp, "%02X ", histogram[tdc][i]);
china_sn0w 1:7530b7eb757a 555 //}
china_sn0w 1:7530b7eb757a 556 fprintf(fp, "hello ");
china_sn0w 1:7530b7eb757a 557
china_sn0w 1:7530b7eb757a 558 fflush(fp);
china_sn0w 1:7530b7eb757a 559 fclose(fp);
china_sn0w 1:7530b7eb757a 560 */
china_sn0w 1:7530b7eb757a 561
china_sn0w 1:7530b7eb757a 562 _uart_send_pbuff[0] = histogram_pos;
china_sn0w 1:7530b7eb757a 563 _uart_send_pbuff[1] = histogram_pos >> 8;
china_sn0w 1:7530b7eb757a 564
china_sn0w 1:7530b7eb757a 565 _uart_send_pbuff[2] = tdc;
china_sn0w 1:7530b7eb757a 566
china_sn0w 1:7530b7eb757a 567 _uart_send_pbuff[3] = histogram_num;
china_sn0w 1:7530b7eb757a 568 _uart_send_pbuff[4] = histogram_num >> 8;
china_sn0w 1:7530b7eb757a 569
china_sn0w 1:7530b7eb757a 570 memcpy(&_uart_send_pbuff[5], histogram[tdc], 1024);
china_sn0w 1:7530b7eb757a 571
china_sn0w 1:7530b7eb757a 572 UART_CmdAckSend(READ_CMD | 0x80, VAN_STEP_HISTOGRAM_CMD, _uart_send_pbuff, 1024 + 1 + 2 + 2);
china_sn0w 1:7530b7eb757a 573 //return 0;
china_sn0w 1:7530b7eb757a 574 }
china_sn0w 1:7530b7eb757a 575
china_sn0w 1:7530b7eb757a 576 uint8_t DCRTest(uint8_t vspad, uint8_t test_time)
china_sn0w 1:7530b7eb757a 577 {
china_sn0w 1:7530b7eb757a 578 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 579 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 580 memset(dcr_matrix, 0x00, 17*9*2);
china_sn0w 3:35b05d91568d 581 //WriteOneReg(0x50, 0x01);
china_sn0w 3:35b05d91568d 582 //WriteOneReg(0xBD, 0x01);
china_sn0w 3:35b05d91568d 583 //wait_ms(100);
china_sn0w 3:35b05d91568d 584 //WriteOneReg(0xD8, 0xF0);
china_sn0w 3:35b05d91568d 585 WriteOneReg(0xC0, vspad);
china_sn0w 1:7530b7eb757a 586
china_sn0w 1:7530b7eb757a 587 for(uint8_t group = 0; group < 9; group++) {
china_sn0w 1:7530b7eb757a 588 WriteOneReg(0x0C, group);
china_sn0w 1:7530b7eb757a 589 wait_ms(1);
china_sn0w 1:7530b7eb757a 590 WriteOneReg(0x0D, test_time);
china_sn0w 1:7530b7eb757a 591 wait_ms(1);
china_sn0w 1:7530b7eb757a 592
china_sn0w 1:7530b7eb757a 593 timeout = 25;
china_sn0w 1:7530b7eb757a 594 int_mark = 1;
china_sn0w 1:7530b7eb757a 595 WriteOneReg(0x0A, 0x0C);
china_sn0w 1:7530b7eb757a 596 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 597 timeout--;
china_sn0w 1:7530b7eb757a 598 wait_ms(100);
china_sn0w 1:7530b7eb757a 599 }
china_sn0w 1:7530b7eb757a 600 //osDelay(80);
china_sn0w 1:7530b7eb757a 601 for(uint8_t pix = 0; pix < 17; pix++) {
china_sn0w 1:7530b7eb757a 602 ret = ReadOneReg(0x82 + pix*2, &dcr_matrix[pix][group*2 + 1]);
china_sn0w 1:7530b7eb757a 603 ret = ReadOneReg(0x82 + pix*2 + 1, &dcr_matrix[pix][group*2]);
china_sn0w 1:7530b7eb757a 604 //osDelay(1);
china_sn0w 1:7530b7eb757a 605 if(ret != 0)
china_sn0w 1:7530b7eb757a 606 return ret;
china_sn0w 1:7530b7eb757a 607 }
china_sn0w 1:7530b7eb757a 608
china_sn0w 1:7530b7eb757a 609 }
china_sn0w 1:7530b7eb757a 610
china_sn0w 1:7530b7eb757a 611 return 0;
china_sn0w 1:7530b7eb757a 612 }
china_sn0w 1:7530b7eb757a 613
china_sn0w 1:7530b7eb757a 614 uint8_t DelayLineTest(uint8_t phase, uint8_t* buf)
china_sn0w 1:7530b7eb757a 615 {
china_sn0w 1:7530b7eb757a 616 uint8_t ret = 0;
china_sn0w 3:35b05d91568d 617 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 618
china_sn0w 1:7530b7eb757a 619 WriteOneReg(0xE4, phase);
china_sn0w 1:7530b7eb757a 620 wait_ms(10);
china_sn0w 1:7530b7eb757a 621
china_sn0w 1:7530b7eb757a 622 for(uint8_t step = 0; step < 8; step++) {
china_sn0w 1:7530b7eb757a 623 WriteOneReg(0xE1, 0x61 | (step << 1));
china_sn0w 1:7530b7eb757a 624 wait_ms(10);
china_sn0w 1:7530b7eb757a 625
china_sn0w 1:7530b7eb757a 626 timeout = 50;
china_sn0w 1:7530b7eb757a 627 int_mark = 1;
china_sn0w 1:7530b7eb757a 628 WriteOneReg(0x0A, 0x0B);
china_sn0w 1:7530b7eb757a 629 wait_ms(10);
china_sn0w 1:7530b7eb757a 630 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 631 timeout--;
china_sn0w 1:7530b7eb757a 632 wait_ms(100);
china_sn0w 3:35b05d91568d 633 }
china_sn0w 1:7530b7eb757a 634 for(uint8_t tdc = 0; tdc < 9; tdc++) {
china_sn0w 1:7530b7eb757a 635 ret = ReadOneReg(0x0c + tdc*2, buf + step*18 + tdc*2 + 1);
china_sn0w 1:7530b7eb757a 636 wait_ms(1);
china_sn0w 3:35b05d91568d 637 ret = ReadOneReg(0x0c + tdc*2 + 1, buf + step*18 + tdc*2);
china_sn0w 3:35b05d91568d 638 wait_ms(1);
china_sn0w 1:7530b7eb757a 639 }
china_sn0w 1:7530b7eb757a 640
china_sn0w 1:7530b7eb757a 641 }
china_sn0w 1:7530b7eb757a 642
china_sn0w 1:7530b7eb757a 643 return 0;
china_sn0w 1:7530b7eb757a 644 }
china_sn0w 1:7530b7eb757a 645
china_sn0w 1:7530b7eb757a 646 uint8_t GetTdcPhase(uint8_t* buf)
china_sn0w 1:7530b7eb757a 647 {
china_sn0w 1:7530b7eb757a 648 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 649 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 650 memset(buf, 0x00, 10);
china_sn0w 1:7530b7eb757a 651
china_sn0w 1:7530b7eb757a 652 WriteOneReg(0x0C, 0x0C);
china_sn0w 1:7530b7eb757a 653 WriteOneReg(0x0A, 0x0A);
china_sn0w 1:7530b7eb757a 654 wait_ms(1);
china_sn0w 1:7530b7eb757a 655
china_sn0w 1:7530b7eb757a 656 timeout = 10;
china_sn0w 1:7530b7eb757a 657 int_mark = 1;
china_sn0w 1:7530b7eb757a 658 WriteOneReg(0x0A, 0x0B);
china_sn0w 1:7530b7eb757a 659 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 660 timeout--;
china_sn0w 1:7530b7eb757a 661 wait_ms(100);
china_sn0w 1:7530b7eb757a 662 }
china_sn0w 1:7530b7eb757a 663 //osDelay(80);
china_sn0w 1:7530b7eb757a 664
china_sn0w 1:7530b7eb757a 665 ret = ReadOneReg(0x0D, buf);
china_sn0w 1:7530b7eb757a 666 ret = ReadOneReg(0xE4, buf + 1);
china_sn0w 1:7530b7eb757a 667
china_sn0w 1:7530b7eb757a 668 if(ret != 0)
china_sn0w 1:7530b7eb757a 669 return ret;
china_sn0w 1:7530b7eb757a 670
china_sn0w 1:7530b7eb757a 671 return 0;
china_sn0w 1:7530b7eb757a 672 }
china_sn0w 1:7530b7eb757a 673
china_sn0w 3:35b05d91568d 674 uint8_t SetWindow(uint8_t* pd)
china_sn0w 3:35b05d91568d 675 {
china_sn0w 3:35b05d91568d 676 uint8_t ret = 0;
china_sn0w 3:35b05d91568d 677 uint8_t buf[14];
china_sn0w 3:35b05d91568d 678
china_sn0w 3:35b05d91568d 679 memset(buf, 0x00, 14);
china_sn0w 3:35b05d91568d 680
china_sn0w 3:35b05d91568d 681 buf[0] |= (pd[5]&0xF);
china_sn0w 3:35b05d91568d 682 buf[0] |= ((pd[6] << 4)&0xF0);
china_sn0w 3:35b05d91568d 683
china_sn0w 3:35b05d91568d 684 buf[1] |= (pd[7]&0xF);
china_sn0w 3:35b05d91568d 685 buf[1] |= ((pd[8] << 4)&0xF0);
china_sn0w 3:35b05d91568d 686
china_sn0w 3:35b05d91568d 687 buf[2] |= (pd[9]&0xF);
china_sn0w 3:35b05d91568d 688 buf[2] |= ((pd[10] << 4)&0xF0);
china_sn0w 3:35b05d91568d 689
china_sn0w 3:35b05d91568d 690 buf[3] |= (pd[11]&0xF);
china_sn0w 3:35b05d91568d 691 buf[3] |= ((pd[12] << 4)&0xF0);
china_sn0w 3:35b05d91568d 692
china_sn0w 3:35b05d91568d 693 buf[4] |= (pd[13]&0xF);
china_sn0w 3:35b05d91568d 694 buf[4] |= ((pd[14] << 4)&0xF0);
china_sn0w 3:35b05d91568d 695
china_sn0w 3:35b05d91568d 696 buf[5] |= (pd[15]&0xF);
china_sn0w 3:35b05d91568d 697 buf[5] |= ((pd[16] << 4)&0xF0);
china_sn0w 3:35b05d91568d 698
china_sn0w 3:35b05d91568d 699 buf[6] |= (pd[17]&0xF);
china_sn0w 3:35b05d91568d 700 buf[6] |= ((pd[18] << 4)&0xF0);
china_sn0w 3:35b05d91568d 701
china_sn0w 3:35b05d91568d 702 buf[7] |= (pd[19]&0xF);
china_sn0w 3:35b05d91568d 703 buf[7] |= ((pd[20] << 4)&0xF0);
china_sn0w 3:35b05d91568d 704
china_sn0w 3:35b05d91568d 705 buf[8] = 0x00;// Fisrt 16LSB cut off
china_sn0w 3:35b05d91568d 706 buf[9] = 0xFF;
china_sn0w 3:35b05d91568d 707
china_sn0w 3:35b05d91568d 708 buf[10] = 0x01;// Ref PAD switch
china_sn0w 3:35b05d91568d 709
china_sn0w 3:35b05d91568d 710 buf[11] = 0x1F;// TDC Resolution 1F = 31
china_sn0w 3:35b05d91568d 711
china_sn0w 3:35b05d91568d 712 buf[12] = 0x0C;// Length
china_sn0w 3:35b05d91568d 713 buf[13] = 0x09;//CMD
china_sn0w 3:35b05d91568d 714
china_sn0w 3:35b05d91568d 715 for(uint8_t i = 0; i < 12; i++)
china_sn0w 3:35b05d91568d 716 {
china_sn0w 3:35b05d91568d 717 WriteOneReg(0x0C + i, buf[i]);
china_sn0w 3:35b05d91568d 718 }
china_sn0w 3:35b05d91568d 719
china_sn0w 3:35b05d91568d 720 WriteOneReg(0x0B, 0x0C);
china_sn0w 3:35b05d91568d 721 WriteOneReg(0x0A, 0x09);
china_sn0w 3:35b05d91568d 722
china_sn0w 3:35b05d91568d 723 return 0;
china_sn0w 3:35b05d91568d 724 }
china_sn0w 1:7530b7eb757a 725
china_sn0w 3:35b05d91568d 726 uint8_t RCO_Trim(uint8_t *rco)
china_sn0w 3:35b05d91568d 727 {
china_sn0w 3:35b05d91568d 728 uint8_t ret = 0;
china_sn0w 3:35b05d91568d 729 uint8_t value = 0, result = 0;
china_sn0w 3:35b05d91568d 730
china_sn0w 3:35b05d91568d 731 TRIM_EN = 1;
china_sn0w 3:35b05d91568d 732
china_sn0w 3:35b05d91568d 733 //==================First BAND=====================//
china_sn0w 3:35b05d91568d 734 ChipInitReset();
china_sn0w 3:35b05d91568d 735 ret = WriteOneReg(0xED , 0x03);
china_sn0w 3:35b05d91568d 736 ret = WriteOneReg(0xEC , 0x36);
china_sn0w 3:35b05d91568d 737 ret = WriteOneReg(0x3D , 0xC0);
china_sn0w 3:35b05d91568d 738 ret = WriteOneReg(0xE8 , 0x00);
china_sn0w 3:35b05d91568d 739 ret = WriteOneReg(0xEA , 0x3F);
china_sn0w 3:35b05d91568d 740 ret = WriteOneReg(0x3D , 0xC8);
china_sn0w 3:35b05d91568d 741 ret = WriteOneReg(0xED , 0x83);
china_sn0w 3:35b05d91568d 742
china_sn0w 3:35b05d91568d 743 wait_ms(1000);
china_sn0w 3:35b05d91568d 744
china_sn0w 3:35b05d91568d 745 ret = ReadOneReg(0xFA, &value);
china_sn0w 3:35b05d91568d 746 ret = ReadOneReg(0xFB, &result);
china_sn0w 3:35b05d91568d 747
china_sn0w 3:35b05d91568d 748 if((result&0xC0) == 0xC0)
china_sn0w 3:35b05d91568d 749 {
china_sn0w 3:35b05d91568d 750 *rco = value;
china_sn0w 3:35b05d91568d 751 ChipInitReset();
china_sn0w 3:35b05d91568d 752 TRIM_EN = 0;
china_sn0w 3:35b05d91568d 753 return 0;
china_sn0w 3:35b05d91568d 754 }
china_sn0w 3:35b05d91568d 755
china_sn0w 3:35b05d91568d 756 //==================Second BAND=====================//
china_sn0w 3:35b05d91568d 757 ChipInitReset();
china_sn0w 3:35b05d91568d 758 ret = WriteOneReg(0xED , 0x03);
china_sn0w 3:35b05d91568d 759 ret = WriteOneReg(0xEC , 0x36);
china_sn0w 3:35b05d91568d 760 ret = WriteOneReg(0x3D , 0xC0);
china_sn0w 3:35b05d91568d 761 ret = WriteOneReg(0xE8 , 0x00);
china_sn0w 3:35b05d91568d 762 ret = WriteOneReg(0xEA , 0x7F);
china_sn0w 3:35b05d91568d 763 ret = WriteOneReg(0xEB , 0x40);
china_sn0w 3:35b05d91568d 764 ret = WriteOneReg(0x3D , 0xC8);
china_sn0w 3:35b05d91568d 765 ret = WriteOneReg(0xED , 0x83);
china_sn0w 3:35b05d91568d 766
china_sn0w 3:35b05d91568d 767 wait_ms(1000);
china_sn0w 3:35b05d91568d 768
china_sn0w 3:35b05d91568d 769 ret = ReadOneReg(0xFA, &value);
china_sn0w 3:35b05d91568d 770 ret = ReadOneReg(0xFB, &result);
china_sn0w 3:35b05d91568d 771
china_sn0w 3:35b05d91568d 772 if((result&0xC0) == 0xC0)
china_sn0w 3:35b05d91568d 773 {
china_sn0w 3:35b05d91568d 774 *rco = value;
china_sn0w 3:35b05d91568d 775 ChipInitReset();
china_sn0w 3:35b05d91568d 776 TRIM_EN = 0;
china_sn0w 3:35b05d91568d 777 return 0;
china_sn0w 3:35b05d91568d 778 }
china_sn0w 3:35b05d91568d 779
china_sn0w 3:35b05d91568d 780 //==================Third BAND=====================//
china_sn0w 3:35b05d91568d 781 ChipInitReset();
china_sn0w 3:35b05d91568d 782 ret = WriteOneReg(0xED , 0x03);
china_sn0w 3:35b05d91568d 783 ret = WriteOneReg(0xEC , 0x36);
china_sn0w 3:35b05d91568d 784 ret = WriteOneReg(0x3D , 0xC0);
china_sn0w 3:35b05d91568d 785 ret = WriteOneReg(0xE8 , 0x00);
china_sn0w 3:35b05d91568d 786 ret = WriteOneReg(0xEA , 0xBF);
china_sn0w 3:35b05d91568d 787 ret = WriteOneReg(0xEB , 0x80);
china_sn0w 3:35b05d91568d 788 ret = WriteOneReg(0x3D , 0xC8);
china_sn0w 3:35b05d91568d 789 ret = WriteOneReg(0xED , 0x83);
china_sn0w 3:35b05d91568d 790
china_sn0w 3:35b05d91568d 791 wait_ms(1000);
china_sn0w 3:35b05d91568d 792
china_sn0w 3:35b05d91568d 793 ret = ReadOneReg(0xFA, &value);
china_sn0w 3:35b05d91568d 794 ret = ReadOneReg(0xFB, &result);
china_sn0w 3:35b05d91568d 795
china_sn0w 3:35b05d91568d 796 if((result&0xC0) == 0xC0)
china_sn0w 3:35b05d91568d 797 {
china_sn0w 3:35b05d91568d 798 *rco = value;
china_sn0w 3:35b05d91568d 799 ChipInitReset();
china_sn0w 3:35b05d91568d 800 TRIM_EN = 0;
china_sn0w 3:35b05d91568d 801 return 0;
china_sn0w 3:35b05d91568d 802 }
china_sn0w 3:35b05d91568d 803
china_sn0w 3:35b05d91568d 804 //==================Fourth BAND=====================//
china_sn0w 3:35b05d91568d 805 ChipInitReset();
china_sn0w 3:35b05d91568d 806 ret = WriteOneReg(0xED , 0x03);
china_sn0w 3:35b05d91568d 807 ret = WriteOneReg(0xEC , 0x36);
china_sn0w 3:35b05d91568d 808 ret = WriteOneReg(0x3D , 0xC0);
china_sn0w 3:35b05d91568d 809 ret = WriteOneReg(0xE8 , 0x00);
china_sn0w 3:35b05d91568d 810 ret = WriteOneReg(0xEA , 0xFF);
china_sn0w 3:35b05d91568d 811 ret = WriteOneReg(0xEB , 0xC0);
china_sn0w 3:35b05d91568d 812 ret = WriteOneReg(0x3D , 0xC8);
china_sn0w 3:35b05d91568d 813 ret = WriteOneReg(0xED , 0x83);
china_sn0w 3:35b05d91568d 814
china_sn0w 3:35b05d91568d 815 wait_ms(1000);
china_sn0w 3:35b05d91568d 816
china_sn0w 3:35b05d91568d 817 ret = ReadOneReg(0xFA, &value);
china_sn0w 3:35b05d91568d 818 ret = ReadOneReg(0xFB, &result);
china_sn0w 3:35b05d91568d 819
china_sn0w 3:35b05d91568d 820 if((result&0xC0) == 0xC0)
china_sn0w 3:35b05d91568d 821 {
china_sn0w 3:35b05d91568d 822 *rco = value;
china_sn0w 3:35b05d91568d 823 ChipInitReset();
china_sn0w 3:35b05d91568d 824 TRIM_EN = 0;
china_sn0w 3:35b05d91568d 825 return 0;
china_sn0w 3:35b05d91568d 826 }
china_sn0w 3:35b05d91568d 827
china_sn0w 3:35b05d91568d 828 ChipInitReset();
china_sn0w 3:35b05d91568d 829 TRIM_EN = 0;
china_sn0w 3:35b05d91568d 830 return 1;
china_sn0w 3:35b05d91568d 831 }
china_sn0w 3:35b05d91568d 832
china_sn0w 3:35b05d91568d 833 uint8_t BVD_Trim(uint8_t *bvd)
china_sn0w 3:35b05d91568d 834 {
china_sn0w 3:35b05d91568d 835 uint8_t ret = 0;
china_sn0w 3:35b05d91568d 836 uint32_t timeout = 0;
china_sn0w 3:35b05d91568d 837
china_sn0w 3:35b05d91568d 838 WriteOneReg(0xC0, 0x00);
china_sn0w 3:35b05d91568d 839 wait_ms(1);
china_sn0w 3:35b05d91568d 840
china_sn0w 3:35b05d91568d 841 timeout = 600;
china_sn0w 3:35b05d91568d 842 int_mark = 1;
china_sn0w 3:35b05d91568d 843 WriteOneReg(0x0A, 0x08);
china_sn0w 3:35b05d91568d 844 while(int_mark == 1 && timeout != 0) {
china_sn0w 3:35b05d91568d 845 timeout--;
china_sn0w 3:35b05d91568d 846 wait_ms(100);
china_sn0w 3:35b05d91568d 847 }
china_sn0w 3:35b05d91568d 848 //osDelay(80);
china_sn0w 3:35b05d91568d 849
china_sn0w 3:35b05d91568d 850 ret = ReadOneReg(0xC0, bvd);
china_sn0w 3:35b05d91568d 851
china_sn0w 3:35b05d91568d 852 if(timeout == 0)
china_sn0w 3:35b05d91568d 853 return 1;
china_sn0w 3:35b05d91568d 854
china_sn0w 3:35b05d91568d 855 return 0;
china_sn0w 3:35b05d91568d 856 }
china_sn0w 3:35b05d91568d 857
china_sn0w 3:35b05d91568d 858 uint8_t Pixel_Enable(uint8_t *buf)
china_sn0w 3:35b05d91568d 859 {
china_sn0w 3:35b05d91568d 860 for(uint8_t i = 0; i < 18; i++)
china_sn0w 3:35b05d91568d 861 {
china_sn0w 3:35b05d91568d 862 WriteOneReg(0xC2 + i, buf[i]);
china_sn0w 3:35b05d91568d 863 }
china_sn0w 3:35b05d91568d 864
china_sn0w 3:35b05d91568d 865 return 0;
china_sn0w 3:35b05d91568d 866 }
china_sn0w 3:35b05d91568d 867
china_sn0w 3:35b05d91568d 868