charles macneill
Initial release. Mbed library for VL53L1CB
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vl53l1_register_structs.h
00001 00002 /******************************************************************************* 00003 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00004 00005 This file is part of VL53L1 Core and is dual licensed, 00006 either 'STMicroelectronics 00007 Proprietary license' 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 00010 ******************************************************************************** 00011 00012 'STMicroelectronics Proprietary license' 00013 00014 ******************************************************************************** 00015 00016 License terms: STMicroelectronics Proprietary in accordance with licensing 00017 terms at www.st.com/sla0081 00018 00019 STMicroelectronics confidential 00020 Reproduction and Communication of this document is strictly prohibited unless 00021 specifically authorized in writing by STMicroelectronics. 00022 00023 00024 ******************************************************************************** 00025 00026 Alternatively, VL53L1 Core may be distributed under the terms of 00027 'BSD 3-clause "New" or "Revised" License', in which case the following 00028 provisions apply instead of the ones 00029 mentioned above : 00030 00031 ******************************************************************************** 00032 00033 License terms: BSD 3-clause "New" or "Revised" License. 00034 00035 Redistribution and use in source and binary forms, with or without 00036 modification, are permitted provided that the following conditions are met: 00037 00038 1. Redistributions of source code must retain the above copyright notice, this 00039 list of conditions and the following disclaimer. 00040 00041 2. Redistributions in binary form must reproduce the above copyright notice, 00042 this list of conditions and the following disclaimer in the documentation 00043 and/or other materials provided with the distribution. 00044 00045 3. Neither the name of the copyright holder nor the names of its contributors 00046 may be used to endorse or promote products derived from this software 00047 without specific prior written permission. 00048 00049 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00050 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00051 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00052 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00053 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00054 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00055 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00056 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00057 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00058 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00059 00060 00061 ******************************************************************************** 00062 00063 */ 00064 00065 00066 00067 00068 #ifndef _VL53L1_REGISTER_STRUCTS_H_ 00069 #define _VL53L1_REGISTER_STRUCTS_H_ 00070 00071 #include "vl53l1_types.h" 00072 #include "vl53l1_register_map.h" 00073 00074 #define VL53L1_STATIC_NVM_MANAGED_I2C_INDEX \ 00075 VL53L1_I2C_SLAVE__DEVICE_ADDRESS 00076 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_INDEX \ 00077 VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 00078 #define VL53L1_STATIC_CONFIG_I2C_INDEX \ 00079 VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 00080 #define VL53L1_GENERAL_CONFIG_I2C_INDEX \ 00081 VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 00082 #define VL53L1_TIMING_CONFIG_I2C_INDEX \ 00083 VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI 00084 #define VL53L1_DYNAMIC_CONFIG_I2C_INDEX \ 00085 VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 00086 #define VL53L1_SYSTEM_CONTROL_I2C_INDEX \ 00087 VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE 00088 #define VL53L1_SYSTEM_RESULTS_I2C_INDEX \ 00089 VL53L1_RESULT__INTERRUPT_STATUS 00090 #define VL53L1_CORE_RESULTS_I2C_INDEX \ 00091 VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 00092 #define VL53L1_DEBUG_RESULTS_I2C_INDEX \ 00093 VL53L1_PHASECAL_RESULT__REFERENCE_PHASE 00094 #define VL53L1_NVM_COPY_DATA_I2C_INDEX \ 00095 VL53L1_IDENTIFICATION__MODEL_ID 00096 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ 00097 VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS 00098 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \ 00099 VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 00100 #define VL53L1_PATCH_DEBUG_I2C_INDEX \ 00101 VL53L1_RESULT__DEBUG_STATUS 00102 #define VL53L1_GPH_GENERAL_CONFIG_I2C_INDEX \ 00103 VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH 00104 #define VL53L1_GPH_STATIC_CONFIG_I2C_INDEX \ 00105 VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL 00106 #define VL53L1_GPH_TIMING_CONFIG_I2C_INDEX \ 00107 VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 00108 #define VL53L1_FW_INTERNAL_I2C_INDEX \ 00109 VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 00110 #define VL53L1_PATCH_RESULTS_I2C_INDEX \ 00111 VL53L1_DSS_CALC__ROI_CTRL 00112 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ 00113 VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START 00114 #define VL53L1_SHADOW_CORE_RESULTS_I2C_INDEX \ 00115 VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 00116 00117 #define VL53L1_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11 00118 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23 00119 #define VL53L1_STATIC_CONFIG_I2C_SIZE_BYTES 32 00120 #define VL53L1_GENERAL_CONFIG_I2C_SIZE_BYTES 22 00121 #define VL53L1_TIMING_CONFIG_I2C_SIZE_BYTES 23 00122 #define VL53L1_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18 00123 #define VL53L1_SYSTEM_CONTROL_I2C_SIZE_BYTES 5 00124 #define VL53L1_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 00125 #define VL53L1_CORE_RESULTS_I2C_SIZE_BYTES 33 00126 #define VL53L1_DEBUG_RESULTS_I2C_SIZE_BYTES 56 00127 #define VL53L1_NVM_COPY_DATA_I2C_SIZE_BYTES 49 00128 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 00129 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 00130 #define VL53L1_PATCH_DEBUG_I2C_SIZE_BYTES 2 00131 #define VL53L1_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5 00132 #define VL53L1_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6 00133 #define VL53L1_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16 00134 #define VL53L1_FW_INTERNAL_I2C_SIZE_BYTES 2 00135 #define VL53L1_PATCH_RESULTS_I2C_SIZE_BYTES 90 00136 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82 00137 #define VL53L1_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 00138 00139 00140 00141 00142 typedef struct { 00143 uint8_t i2c_slave__device_address; 00144 00145 uint8_t ana_config__vhv_ref_sel_vddpix; 00146 00147 uint8_t ana_config__vhv_ref_sel_vquench; 00148 00149 uint8_t ana_config__reg_avdd1v2_sel; 00150 00151 uint8_t ana_config__fast_osc__trim; 00152 00153 uint16_t osc_measured__fast_osc__frequency; 00154 00155 uint8_t vhv_config__timeout_macrop_loop_bound; 00156 00157 uint8_t vhv_config__count_thresh; 00158 00159 uint8_t vhv_config__offset; 00160 00161 uint8_t vhv_config__init; 00162 00163 } VL53L1_static_nvm_managed_t; 00164 00165 00166 00167 00168 typedef struct { 00169 uint8_t global_config__spad_enables_ref_0; 00170 00171 uint8_t global_config__spad_enables_ref_1; 00172 00173 uint8_t global_config__spad_enables_ref_2; 00174 00175 uint8_t global_config__spad_enables_ref_3; 00176 00177 uint8_t global_config__spad_enables_ref_4; 00178 00179 uint8_t global_config__spad_enables_ref_5; 00180 00181 uint8_t global_config__ref_en_start_select; 00182 00183 uint8_t ref_spad_man__num_requested_ref_spads; 00184 00185 uint8_t ref_spad_man__ref_location; 00186 00187 uint16_t algo__crosstalk_compensation_plane_offset_kcps; 00188 00189 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 00190 00191 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 00192 00193 uint16_t ref_spad_char__total_rate_target_mcps; 00194 00195 int16_t algo__part_to_part_range_offset_mm; 00196 00197 int16_t mm_config__inner_offset_mm; 00198 00199 int16_t mm_config__outer_offset_mm; 00200 00201 } VL53L1_customer_nvm_managed_t; 00202 00203 00204 00205 00206 typedef struct { 00207 uint16_t dss_config__target_total_rate_mcps; 00208 00209 uint8_t debug__ctrl; 00210 00211 uint8_t test_mode__ctrl; 00212 00213 uint8_t clk_gating__ctrl; 00214 00215 uint8_t nvm_bist__ctrl; 00216 00217 uint8_t nvm_bist__num_nvm_words; 00218 00219 uint8_t nvm_bist__start_address; 00220 00221 uint8_t host_if__status; 00222 00223 uint8_t pad_i2c_hv__config; 00224 00225 uint8_t pad_i2c_hv__extsup_config; 00226 00227 uint8_t gpio_hv_pad__ctrl; 00228 00229 uint8_t gpio_hv_mux__ctrl; 00230 00231 uint8_t gpio__tio_hv_status; 00232 00233 uint8_t gpio__fio_hv_status; 00234 00235 uint8_t ana_config__spad_sel_pswidth; 00236 00237 uint8_t ana_config__vcsel_pulse_width_offset; 00238 00239 uint8_t ana_config__fast_osc__config_ctrl; 00240 00241 uint8_t sigma_estimator__effective_pulse_width_ns; 00242 00243 uint8_t sigma_estimator__effective_ambient_width_ns; 00244 00245 uint8_t sigma_estimator__sigma_ref_mm; 00246 00247 uint8_t algo__crosstalk_compensation_valid_height_mm; 00248 00249 uint8_t spare_host_config__static_config_spare_0; 00250 00251 uint8_t spare_host_config__static_config_spare_1; 00252 00253 uint16_t algo__range_ignore_threshold_mcps; 00254 00255 uint8_t algo__range_ignore_valid_height_mm; 00256 00257 uint8_t algo__range_min_clip; 00258 00259 uint8_t algo__consistency_check__tolerance; 00260 00261 uint8_t spare_host_config__static_config_spare_2; 00262 00263 uint8_t sd_config__reset_stages_msb; 00264 00265 uint8_t sd_config__reset_stages_lsb; 00266 00267 } VL53L1_static_config_t; 00268 00269 00270 00271 00272 typedef struct { 00273 uint8_t gph_config__stream_count_update_value; 00274 00275 uint8_t global_config__stream_divider; 00276 00277 uint8_t system__interrupt_config_gpio; 00278 00279 uint8_t cal_config__vcsel_start; 00280 00281 uint16_t cal_config__repeat_rate; 00282 00283 uint8_t global_config__vcsel_width; 00284 00285 uint8_t phasecal_config__timeout_macrop; 00286 00287 uint8_t phasecal_config__target; 00288 00289 uint8_t phasecal_config__override; 00290 00291 uint8_t dss_config__roi_mode_control; 00292 00293 uint16_t system__thresh_rate_high; 00294 00295 uint16_t system__thresh_rate_low; 00296 00297 uint16_t dss_config__manual_effective_spads_select; 00298 00299 uint8_t dss_config__manual_block_select; 00300 00301 uint8_t dss_config__aperture_attenuation; 00302 00303 uint8_t dss_config__max_spads_limit; 00304 00305 uint8_t dss_config__min_spads_limit; 00306 00307 } VL53L1_general_config_t; 00308 00309 00310 00311 00312 typedef struct { 00313 uint8_t mm_config__timeout_macrop_a_hi; 00314 00315 uint8_t mm_config__timeout_macrop_a_lo; 00316 00317 uint8_t mm_config__timeout_macrop_b_hi; 00318 00319 uint8_t mm_config__timeout_macrop_b_lo; 00320 00321 uint8_t range_config__timeout_macrop_a_hi; 00322 00323 uint8_t range_config__timeout_macrop_a_lo; 00324 00325 uint8_t range_config__vcsel_period_a; 00326 00327 uint8_t range_config__timeout_macrop_b_hi; 00328 00329 uint8_t range_config__timeout_macrop_b_lo; 00330 00331 uint8_t range_config__vcsel_period_b; 00332 00333 uint16_t range_config__sigma_thresh; 00334 00335 uint16_t range_config__min_count_rate_rtn_limit_mcps; 00336 00337 uint8_t range_config__valid_phase_low; 00338 00339 uint8_t range_config__valid_phase_high; 00340 00341 uint32_t system__intermeasurement_period; 00342 00343 uint8_t system__fractional_enable; 00344 00345 } VL53L1_timing_config_t; 00346 00347 00348 00349 00350 typedef struct { 00351 uint8_t system__grouped_parameter_hold_0; 00352 00353 uint16_t system__thresh_high; 00354 00355 uint16_t system__thresh_low; 00356 00357 uint8_t system__enable_xtalk_per_quadrant; 00358 00359 uint8_t system__seed_config; 00360 00361 uint8_t sd_config__woi_sd0; 00362 00363 uint8_t sd_config__woi_sd1; 00364 00365 uint8_t sd_config__initial_phase_sd0; 00366 00367 uint8_t sd_config__initial_phase_sd1; 00368 00369 uint8_t system__grouped_parameter_hold_1; 00370 00371 uint8_t sd_config__first_order_select; 00372 00373 uint8_t sd_config__quantifier; 00374 00375 uint8_t roi_config__user_roi_centre_spad; 00376 00377 uint8_t roi_config__user_roi_requested_global_xy_size; 00378 00379 uint8_t system__sequence_config; 00380 00381 uint8_t system__grouped_parameter_hold; 00382 00383 } VL53L1_dynamic_config_t; 00384 00385 00386 00387 00388 typedef struct { 00389 uint8_t power_management__go1_power_force; 00390 00391 uint8_t system__stream_count_ctrl; 00392 00393 uint8_t firmware__enable; 00394 00395 uint8_t system__interrupt_clear; 00396 00397 uint8_t system__mode_start; 00398 00399 } VL53L1_system_control_t; 00400 00401 00402 00403 00404 typedef struct { 00405 uint8_t result__interrupt_status; 00406 00407 uint8_t result__range_status; 00408 00409 uint8_t result__report_status; 00410 00411 uint8_t result__stream_count; 00412 00413 uint16_t result__dss_actual_effective_spads_sd0; 00414 00415 uint16_t result__peak_signal_count_rate_mcps_sd0; 00416 00417 uint16_t result__ambient_count_rate_mcps_sd0; 00418 00419 uint16_t result__sigma_sd0; 00420 00421 uint16_t result__phase_sd0; 00422 00423 uint16_t result__final_crosstalk_corrected_range_mm_sd0; 00424 00425 uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 00426 00427 uint16_t result__mm_inner_actual_effective_spads_sd0; 00428 00429 uint16_t result__mm_outer_actual_effective_spads_sd0; 00430 00431 uint16_t result__avg_signal_count_rate_mcps_sd0; 00432 00433 uint16_t result__dss_actual_effective_spads_sd1; 00434 00435 uint16_t result__peak_signal_count_rate_mcps_sd1; 00436 00437 uint16_t result__ambient_count_rate_mcps_sd1; 00438 00439 uint16_t result__sigma_sd1; 00440 00441 uint16_t result__phase_sd1; 00442 00443 uint16_t result__final_crosstalk_corrected_range_mm_sd1; 00444 00445 uint16_t result__spare_0_sd1; 00446 00447 uint16_t result__spare_1_sd1; 00448 00449 uint16_t result__spare_2_sd1; 00450 00451 uint8_t result__spare_3_sd1; 00452 00453 uint8_t result__thresh_info; 00454 00455 } VL53L1_system_results_t; 00456 00457 00458 00459 00460 typedef struct { 00461 uint32_t result_core__ambient_window_events_sd0; 00462 00463 uint32_t result_core__ranging_total_events_sd0; 00464 00465 int32_t result_core__signal_total_events_sd0; 00466 00467 uint32_t result_core__total_periods_elapsed_sd0; 00468 00469 uint32_t result_core__ambient_window_events_sd1; 00470 00471 uint32_t result_core__ranging_total_events_sd1; 00472 00473 int32_t result_core__signal_total_events_sd1; 00474 00475 uint32_t result_core__total_periods_elapsed_sd1; 00476 00477 uint8_t result_core__spare_0; 00478 00479 } VL53L1_core_results_t; 00480 00481 00482 00483 00484 typedef struct { 00485 uint16_t phasecal_result__reference_phase; 00486 00487 uint8_t phasecal_result__vcsel_start; 00488 00489 uint8_t ref_spad_char_result__num_actual_ref_spads; 00490 00491 uint8_t ref_spad_char_result__ref_location; 00492 00493 uint8_t vhv_result__coldboot_status; 00494 00495 uint8_t vhv_result__search_result; 00496 00497 uint8_t vhv_result__latest_setting; 00498 00499 uint16_t result__osc_calibrate_val; 00500 00501 uint8_t ana_config__powerdown_go1; 00502 00503 uint8_t ana_config__ref_bg_ctrl; 00504 00505 uint8_t ana_config__regdvdd1v2_ctrl; 00506 00507 uint8_t ana_config__osc_slow_ctrl; 00508 00509 uint8_t test_mode__status; 00510 00511 uint8_t firmware__system_status; 00512 00513 uint8_t firmware__mode_status; 00514 00515 uint8_t firmware__secondary_mode_status; 00516 00517 uint16_t firmware__cal_repeat_rate_counter; 00518 00519 uint16_t gph__system__thresh_high; 00520 00521 uint16_t gph__system__thresh_low; 00522 00523 uint8_t gph__system__enable_xtalk_per_quadrant; 00524 00525 uint8_t gph__spare_0; 00526 00527 uint8_t gph__sd_config__woi_sd0; 00528 00529 uint8_t gph__sd_config__woi_sd1; 00530 00531 uint8_t gph__sd_config__initial_phase_sd0; 00532 00533 uint8_t gph__sd_config__initial_phase_sd1; 00534 00535 uint8_t gph__sd_config__first_order_select; 00536 00537 uint8_t gph__sd_config__quantifier; 00538 00539 uint8_t gph__roi_config__user_roi_centre_spad; 00540 00541 uint8_t gph__roi_config__user_roi_requested_global_xy_size; 00542 00543 uint8_t gph__system__sequence_config; 00544 00545 uint8_t gph__gph_id; 00546 00547 uint8_t system__interrupt_set; 00548 00549 uint8_t interrupt_manager__enables; 00550 00551 uint8_t interrupt_manager__clear; 00552 00553 uint8_t interrupt_manager__status; 00554 00555 uint8_t mcu_to_host_bank__wr_access_en; 00556 00557 uint8_t power_management__go1_reset_status; 00558 00559 uint8_t pad_startup_mode__value_ro; 00560 00561 uint8_t pad_startup_mode__value_ctrl; 00562 00563 uint32_t pll_period_us; 00564 00565 uint32_t interrupt_scheduler__data_out; 00566 00567 uint8_t nvm_bist__complete; 00568 00569 uint8_t nvm_bist__status; 00570 00571 } VL53L1_debug_results_t; 00572 00573 00574 00575 00576 typedef struct { 00577 uint8_t identification__model_id; 00578 00579 uint8_t identification__module_type; 00580 00581 uint8_t identification__revision_id; 00582 00583 uint16_t identification__module_id; 00584 00585 uint8_t ana_config__fast_osc__trim_max; 00586 00587 uint8_t ana_config__fast_osc__freq_set; 00588 00589 uint8_t ana_config__vcsel_trim; 00590 00591 uint8_t ana_config__vcsel_selion; 00592 00593 uint8_t ana_config__vcsel_selion_max; 00594 00595 uint8_t protected_laser_safety__lock_bit; 00596 00597 uint8_t laser_safety__key; 00598 00599 uint8_t laser_safety__key_ro; 00600 00601 uint8_t laser_safety__clip; 00602 00603 uint8_t laser_safety__mult; 00604 00605 uint8_t global_config__spad_enables_rtn_0; 00606 00607 uint8_t global_config__spad_enables_rtn_1; 00608 00609 uint8_t global_config__spad_enables_rtn_2; 00610 00611 uint8_t global_config__spad_enables_rtn_3; 00612 00613 uint8_t global_config__spad_enables_rtn_4; 00614 00615 uint8_t global_config__spad_enables_rtn_5; 00616 00617 uint8_t global_config__spad_enables_rtn_6; 00618 00619 uint8_t global_config__spad_enables_rtn_7; 00620 00621 uint8_t global_config__spad_enables_rtn_8; 00622 00623 uint8_t global_config__spad_enables_rtn_9; 00624 00625 uint8_t global_config__spad_enables_rtn_10; 00626 00627 uint8_t global_config__spad_enables_rtn_11; 00628 00629 uint8_t global_config__spad_enables_rtn_12; 00630 00631 uint8_t global_config__spad_enables_rtn_13; 00632 00633 uint8_t global_config__spad_enables_rtn_14; 00634 00635 uint8_t global_config__spad_enables_rtn_15; 00636 00637 uint8_t global_config__spad_enables_rtn_16; 00638 00639 uint8_t global_config__spad_enables_rtn_17; 00640 00641 uint8_t global_config__spad_enables_rtn_18; 00642 00643 uint8_t global_config__spad_enables_rtn_19; 00644 00645 uint8_t global_config__spad_enables_rtn_20; 00646 00647 uint8_t global_config__spad_enables_rtn_21; 00648 00649 uint8_t global_config__spad_enables_rtn_22; 00650 00651 uint8_t global_config__spad_enables_rtn_23; 00652 00653 uint8_t global_config__spad_enables_rtn_24; 00654 00655 uint8_t global_config__spad_enables_rtn_25; 00656 00657 uint8_t global_config__spad_enables_rtn_26; 00658 00659 uint8_t global_config__spad_enables_rtn_27; 00660 00661 uint8_t global_config__spad_enables_rtn_28; 00662 00663 uint8_t global_config__spad_enables_rtn_29; 00664 00665 uint8_t global_config__spad_enables_rtn_30; 00666 00667 uint8_t global_config__spad_enables_rtn_31; 00668 00669 uint8_t roi_config__mode_roi_centre_spad; 00670 00671 uint8_t roi_config__mode_roi_xy_size; 00672 00673 } VL53L1_nvm_copy_data_t; 00674 00675 00676 00677 00678 typedef struct { 00679 uint8_t prev_shadow_result__interrupt_status; 00680 00681 uint8_t prev_shadow_result__range_status; 00682 00683 uint8_t prev_shadow_result__report_status; 00684 00685 uint8_t prev_shadow_result__stream_count; 00686 00687 uint16_t prev_shadow_result__dss_actual_effective_spads_sd0; 00688 00689 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0; 00690 00691 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0; 00692 00693 uint16_t prev_shadow_result__sigma_sd0; 00694 00695 uint16_t prev_shadow_result__phase_sd0; 00696 00697 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0; 00698 00699 uint16_t 00700 psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 00701 00702 uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0; 00703 00704 uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0; 00705 00706 uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0; 00707 00708 uint16_t prev_shadow_result__dss_actual_effective_spads_sd1; 00709 00710 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1; 00711 00712 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1; 00713 00714 uint16_t prev_shadow_result__sigma_sd1; 00715 00716 uint16_t prev_shadow_result__phase_sd1; 00717 00718 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1; 00719 00720 uint16_t prev_shadow_result__spare_0_sd1; 00721 00722 uint16_t prev_shadow_result__spare_1_sd1; 00723 00724 uint16_t prev_shadow_result__spare_2_sd1; 00725 00726 uint16_t prev_shadow_result__spare_3_sd1; 00727 00728 } VL53L1_prev_shadow_system_results_t; 00729 00730 00731 00732 00733 typedef struct { 00734 uint32_t prev_shadow_result_core__ambient_window_events_sd0; 00735 00736 uint32_t prev_shadow_result_core__ranging_total_events_sd0; 00737 00738 int32_t prev_shadow_result_core__signal_total_events_sd0; 00739 00740 uint32_t prev_shadow_result_core__total_periods_elapsed_sd0; 00741 00742 uint32_t prev_shadow_result_core__ambient_window_events_sd1; 00743 00744 uint32_t prev_shadow_result_core__ranging_total_events_sd1; 00745 00746 int32_t prev_shadow_result_core__signal_total_events_sd1; 00747 00748 uint32_t prev_shadow_result_core__total_periods_elapsed_sd1; 00749 00750 uint8_t prev_shadow_result_core__spare_0; 00751 00752 } VL53L1_prev_shadow_core_results_t; 00753 00754 00755 00756 00757 typedef struct { 00758 uint8_t result__debug_status; 00759 00760 uint8_t result__debug_stage; 00761 00762 } VL53L1_patch_debug_t; 00763 00764 00765 00766 00767 typedef struct { 00768 uint16_t gph__system__thresh_rate_high; 00769 00770 uint16_t gph__system__thresh_rate_low; 00771 00772 uint8_t gph__system__interrupt_config_gpio; 00773 00774 } VL53L1_gph_general_config_t; 00775 00776 00777 00778 00779 typedef struct { 00780 uint8_t gph__dss_config__roi_mode_control; 00781 00782 uint16_t gph__dss_config__manual_effective_spads_select; 00783 00784 uint8_t gph__dss_config__manual_block_select; 00785 00786 uint8_t gph__dss_config__max_spads_limit; 00787 00788 uint8_t gph__dss_config__min_spads_limit; 00789 00790 } VL53L1_gph_static_config_t; 00791 00792 00793 00794 00795 typedef struct { 00796 uint8_t gph__mm_config__timeout_macrop_a_hi; 00797 00798 uint8_t gph__mm_config__timeout_macrop_a_lo; 00799 00800 uint8_t gph__mm_config__timeout_macrop_b_hi; 00801 00802 uint8_t gph__mm_config__timeout_macrop_b_lo; 00803 00804 uint8_t gph__range_config__timeout_macrop_a_hi; 00805 00806 uint8_t gph__range_config__timeout_macrop_a_lo; 00807 00808 uint8_t gph__range_config__vcsel_period_a; 00809 00810 uint8_t gph__range_config__vcsel_period_b; 00811 00812 uint8_t gph__range_config__timeout_macrop_b_hi; 00813 00814 uint8_t gph__range_config__timeout_macrop_b_lo; 00815 00816 uint16_t gph__range_config__sigma_thresh; 00817 00818 uint16_t gph__range_config__min_count_rate_rtn_limit_mcps; 00819 00820 uint8_t gph__range_config__valid_phase_low; 00821 00822 uint8_t gph__range_config__valid_phase_high; 00823 00824 } VL53L1_gph_timing_config_t; 00825 00826 00827 00828 00829 typedef struct { 00830 uint8_t firmware__internal_stream_count_div; 00831 00832 uint8_t firmware__internal_stream_counter_val; 00833 00834 } VL53L1_fw_internal_t; 00835 00836 00837 00838 00839 typedef struct { 00840 uint8_t dss_calc__roi_ctrl; 00841 00842 uint8_t dss_calc__spare_1; 00843 00844 uint8_t dss_calc__spare_2; 00845 00846 uint8_t dss_calc__spare_3; 00847 00848 uint8_t dss_calc__spare_4; 00849 00850 uint8_t dss_calc__spare_5; 00851 00852 uint8_t dss_calc__spare_6; 00853 00854 uint8_t dss_calc__spare_7; 00855 00856 uint8_t dss_calc__user_roi_spad_en_0; 00857 00858 uint8_t dss_calc__user_roi_spad_en_1; 00859 00860 uint8_t dss_calc__user_roi_spad_en_2; 00861 00862 uint8_t dss_calc__user_roi_spad_en_3; 00863 00864 uint8_t dss_calc__user_roi_spad_en_4; 00865 00866 uint8_t dss_calc__user_roi_spad_en_5; 00867 00868 uint8_t dss_calc__user_roi_spad_en_6; 00869 00870 uint8_t dss_calc__user_roi_spad_en_7; 00871 00872 uint8_t dss_calc__user_roi_spad_en_8; 00873 00874 uint8_t dss_calc__user_roi_spad_en_9; 00875 00876 uint8_t dss_calc__user_roi_spad_en_10; 00877 00878 uint8_t dss_calc__user_roi_spad_en_11; 00879 00880 uint8_t dss_calc__user_roi_spad_en_12; 00881 00882 uint8_t dss_calc__user_roi_spad_en_13; 00883 00884 uint8_t dss_calc__user_roi_spad_en_14; 00885 00886 uint8_t dss_calc__user_roi_spad_en_15; 00887 00888 uint8_t dss_calc__user_roi_spad_en_16; 00889 00890 uint8_t dss_calc__user_roi_spad_en_17; 00891 00892 uint8_t dss_calc__user_roi_spad_en_18; 00893 00894 uint8_t dss_calc__user_roi_spad_en_19; 00895 00896 uint8_t dss_calc__user_roi_spad_en_20; 00897 00898 uint8_t dss_calc__user_roi_spad_en_21; 00899 00900 uint8_t dss_calc__user_roi_spad_en_22; 00901 00902 uint8_t dss_calc__user_roi_spad_en_23; 00903 00904 uint8_t dss_calc__user_roi_spad_en_24; 00905 00906 uint8_t dss_calc__user_roi_spad_en_25; 00907 00908 uint8_t dss_calc__user_roi_spad_en_26; 00909 00910 uint8_t dss_calc__user_roi_spad_en_27; 00911 00912 uint8_t dss_calc__user_roi_spad_en_28; 00913 00914 uint8_t dss_calc__user_roi_spad_en_29; 00915 00916 uint8_t dss_calc__user_roi_spad_en_30; 00917 00918 uint8_t dss_calc__user_roi_spad_en_31; 00919 00920 uint8_t dss_calc__user_roi_0; 00921 00922 uint8_t dss_calc__user_roi_1; 00923 00924 uint8_t dss_calc__mode_roi_0; 00925 00926 uint8_t dss_calc__mode_roi_1; 00927 00928 uint8_t sigma_estimator_calc__spare_0; 00929 00930 uint16_t vhv_result__peak_signal_rate_mcps; 00931 00932 uint32_t vhv_result__signal_total_events_ref; 00933 00934 uint16_t phasecal_result__phase_output_ref; 00935 00936 uint16_t dss_result__total_rate_per_spad; 00937 00938 uint8_t dss_result__enabled_blocks; 00939 00940 uint16_t dss_result__num_requested_spads; 00941 00942 uint16_t mm_result__inner_intersection_rate; 00943 00944 uint16_t mm_result__outer_complement_rate; 00945 00946 uint16_t mm_result__total_offset; 00947 00948 uint32_t xtalk_calc__xtalk_for_enabled_spads; 00949 00950 uint32_t xtalk_result__avg_xtalk_user_roi_kcps; 00951 00952 uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps; 00953 00954 uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps; 00955 00956 uint32_t range_result__accum_phase; 00957 00958 uint16_t range_result__offset_corrected_range; 00959 00960 } VL53L1_patch_results_t; 00961 00962 00963 00964 00965 typedef struct { 00966 uint8_t shadow_phasecal_result__vcsel_start; 00967 00968 uint8_t shadow_result__interrupt_status; 00969 00970 uint8_t shadow_result__range_status; 00971 00972 uint8_t shadow_result__report_status; 00973 00974 uint8_t shadow_result__stream_count; 00975 00976 uint16_t shadow_result__dss_actual_effective_spads_sd0; 00977 00978 uint16_t shadow_result__peak_signal_count_rate_mcps_sd0; 00979 00980 uint16_t shadow_result__ambient_count_rate_mcps_sd0; 00981 00982 uint16_t shadow_result__sigma_sd0; 00983 00984 uint16_t shadow_result__phase_sd0; 00985 00986 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0; 00987 00988 uint16_t 00989 shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 00990 00991 uint16_t shadow_result__mm_inner_actual_effective_spads_sd0; 00992 00993 uint16_t shadow_result__mm_outer_actual_effective_spads_sd0; 00994 00995 uint16_t shadow_result__avg_signal_count_rate_mcps_sd0; 00996 00997 uint16_t shadow_result__dss_actual_effective_spads_sd1; 00998 00999 uint16_t shadow_result__peak_signal_count_rate_mcps_sd1; 01000 01001 uint16_t shadow_result__ambient_count_rate_mcps_sd1; 01002 01003 uint16_t shadow_result__sigma_sd1; 01004 01005 uint16_t shadow_result__phase_sd1; 01006 01007 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1; 01008 01009 uint16_t shadow_result__spare_0_sd1; 01010 01011 uint16_t shadow_result__spare_1_sd1; 01012 01013 uint16_t shadow_result__spare_2_sd1; 01014 01015 uint8_t shadow_result__spare_3_sd1; 01016 01017 uint8_t shadow_result__thresh_info; 01018 01019 uint8_t shadow_phasecal_result__reference_phase_hi; 01020 01021 uint8_t shadow_phasecal_result__reference_phase_lo; 01022 01023 } VL53L1_shadow_system_results_t; 01024 01025 01026 01027 01028 typedef struct { 01029 uint32_t shadow_result_core__ambient_window_events_sd0; 01030 01031 uint32_t shadow_result_core__ranging_total_events_sd0; 01032 01033 int32_t shadow_result_core__signal_total_events_sd0; 01034 01035 uint32_t shadow_result_core__total_periods_elapsed_sd0; 01036 01037 uint32_t shadow_result_core__ambient_window_events_sd1; 01038 01039 uint32_t shadow_result_core__ranging_total_events_sd1; 01040 01041 int32_t shadow_result_core__signal_total_events_sd1; 01042 01043 uint32_t shadow_result_core__total_periods_elapsed_sd1; 01044 01045 uint8_t shadow_result_core__spare_0; 01046 01047 } VL53L1_shadow_core_results_t; 01048 01049 01050 #endif 01051 01052 01053
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